UNIT-1 INTRODUCTION TO EMBEDDED SYSTEMS TWO MARK QUESTIONS AND ANSWERS

1. Define Embedded System. W !t !"e t e #$m%$nents $f embedded system& An Embedded system is one that has computer hardware with software embedded in it as one of its most important component. The three main components of an embedded system are 1. Hardware 2. Main application software 3. RTO '. W !t is !n embedded #$m%(tin) system& !t is a de"ice that includes a pro#rammable computer but is not itself intended to be a #eneral purpose computer. *. Define system $n # i% +SOC, -it !n e.!m%/e Embedded systems are bein# desi#ned on a sin#le silicon chip called system on chip. O$ is a new desi#n inno"ation for embedded system E%. Mobile phone. &. 0i1e !ny t-$ (ses $f 23SI desi)ned #i"#(its A '( ! chip can embed !)s for the specific application besides the A !) or a *)) core. A system on a '( ! chip that has all of needed analo# as well as di#ital circuits. E#. Mobile phone. 4. 3ist t e im%$"t!nt #$nside"!ti$ns - en se/e#tin) ! %"$#ess$". !nstruction set Ma%imum bits in an operand $loc+ fre,uency )rocessor ability 5. W !t !"e t e ty%es $f embedded system& mall scale embedded systems Medium scale embedded systems ophisticated embedded systems 6. C/!ssify t e %"$#ess$"s in embedded system& 1. *eneral purpose processor Microprocessor Microcontroller Embedded processor -i#ital si#nal processor

Media processor 2. Application specific system processor 3. Multiprocessor system usin# *)) and A ) *)) core or A !) core inte#rated into either an A !$ or a '( ! circuit or an .)*A core inte#rated with processor unit in a '( ! chip.

7. W !t !"e t e im%$"t!nt embedded %"$#ess$" # i%s& ARM / and ARM 0 i 012 AM- 20232 8. N!me s$me DS9 (sed in embedded systems& TM 322$%% HAR$ 3122%% 1:. N!me s$me $f t e !"d-!"e %!"ts $f embedded systems& )ower source $loc+ oscillator circuit Timers Memory units -A$ and A-$ ($- and (E- displays 4eyboard54eypad 11. W !t !"e t e 1!"i$(s ty%es $f mem$"y in embedded systems& RAM 6internal E%ternal7 ROM5)ROM5EE)ROM5.lash $ache memory 1'. W !t !"e t e %$ints t$ be #$nside"ed - i/e #$nne#tin) %$-e" s(%%/y "!i/s -it embedded system& A processor may ha"e more than two pins of 'dd and 'ss upply should separately power the e%ternal !5O dri"in# ports8 timers8 and cloc+ .rom the supply there should be separate interconnections for pairs of 'dd and 'ss pins analo# #round analo# reference and analo# input "olta#e lines. 1*. W !t is -!t# d$) time"& 9atch do# timer is a timin# de"ice that resets after a predefined timeout. 1;. W !t !"e t e t-$ essenti!/ (nits $f ! %"$#ess$" $n ! embedded system&

)ro#ram .low control :nit E%ecution :nit 14. W !t d$es t e e.e#(ti$n (nit $f ! %"$#ess$" in !n embedded system d$& The E: includes the A(: and also the circuits that e%ecute instructions for a pro#ram control tas+. The E: has circuits that implement the instructions pertainin# to data transfer operations and data con"ersion from one form to another. 15. 0i1e e.!m%/es f$" )ene"!/ %("%$se %"$#ess$". Microcontroller Microprocessor 16. Define mi#"$%"$#ess$". A microprocessor is a sin#le '( ! chip that has a $): and may also ha"e some other units for e%ample floatin# point processin# arithmetic unit pipelinin# and super scalin# units for faster processin# of instruction. 17.W en is A%%/i#!ti$n S%e#ifi# System %"$#ess$"s +ASS9s, (sed in !n embedded system& An A ) is used as an additional processin# unit for runnin# the application specific tas+s in place of processin# usin# embedded software. 18. Define ROM im!)e. .inal sta#e software is also called as ROM ima#e .The final implement able software for a product embeds in the ROM as an ima#e at a frame. ;ytes at each address must be defined for creatin# the ima#e. ':. Define de1i#e d"i1e". A de"ice dri"er is software for controllin#8 recei"in# and sendin# byte or a stream of bytes from or to a de"ice. '1. N!me s$me $f t e s$ft-!"e<s (sed f$" t e det!i/ed desi)nin) $f !n embedded system. .inal machine implement able software for a product Assembly lan#ua#e Hi#h le"el lan#ua#e Machine codes oftware for de"ice dri"ers and de"ice mana#ement. ''. W !t !"e t e 1!"i$(s m$de/s (sed in t e desi)n $f !n embedded system& .inite state machine )etri net $ontrol and dataflow #raph Acti"ity dia#ram based :M( model ynchronous data flow #raph

 Timed )etri net and e%tended predicate5transition net Multithreaded #raph '*. 0i1e s$me e.!m%/es f$" medi(m s#!/e embedded systems Router8 a hub and a #ateway Entertainment systems ;an+in# systems i#nal trac+in# systems ';. 0i1e s$me e.!m%/es f$" s$% isti#!ted embedded systems Embedded system for wireless (A< Embedded systems for real time "ideo ecurity products E for space lifeboat.

'4. W !t !"e t e "e=(i"ements $f embedded system& Reliability (ow power consumption $ost effecti"eness Efficient use of processin# power '5. 0i1e t e # !"!#te"isti#s $f embedded system& a7 in#le=functioned b7 Ti#htly constrained c7 Reacti"e and real time '6. W !t !"e t e desi)n met"i#s& )ower i>e <RE cost )erformance '7. W !t !"e t e # !//en)es $f embedded systems& Hardware needed Meetin# the deadlines Minimi>in# the power consumption -esi#n for up#radeability '8. 0i1e t e ste%s in embedded system desi)n&

Re,uirements pecifications Architecture $omponents ystem inte#ration *:.W !t !"e t e "e=(i"ements& ;efore desi#nin# a system8 it must to understand what has to be desi#ned. This can be +nown from the startin# steps of a desi#n process. *1. 0i1e t e ty%es $f "e=(i"ements& .unctional re,uirements <on functional re,uirements *;. W y is t e m(/tit!s>in) im%$"t!nt f$" embedded systems& Embedded software is most often desi#ned for performin# multiple actions and controllin# multiple de"ices and their ! Rs. Multitas+in# software is therefore essential in embedded systems. **. 0i1e s$me e.!m%/es $f f(n#ti$n!/ "e=(i"ements& 1. )erformance 2. $ost 3. physical si>e and wei#ht &. power *;. W !t is t e (se $f "e=(i"ements f$"m& !t is used as a chec+list in the re,uirements analysis. .rom this the fundamental properties of a system came to be +nown. *4. W !t !"e t e ent"ies $f ! "e=(i"ement f$"m& <ame )urpose !nputs and outputs .unctions )erformance Manufacturin# cost )ower )hysical si>e and wei#ht *5. W !t is me!nt by s%e#ifi#!ti$n&

This is a brid#e between $ustomer and Architect. !t con"eys the customer?s needs. These needs are properly used in the desi#n process. *6. W !t is !"# ite#t("e desi)n& !t says the way of implementin# functions by a system. Actually architecture is a plan for whole structure of a system. 9hile will brin# the desi#n of components later. *7. Define system inte)"!ti$n& !t is a processor of combinin# the components into one system. *8. W !t !"e t e f(n#ti$ns $f mem$"y& The memory functions are To pro"ide stora#e for the software that it will run. To store pro#ram "ariables and the intermediate results :sed for stora#e of information ;:. Define RAM& RAM refers Random Access Memory. !t is a memory location that can be accessed without touchin# the other locations. ;1. W !t is d!t! mem$"y& 9hen the pro#ram is e%ecutin#8 to sa"e the "ariable and pro#ram stac+8 this type of memory is used ;'. W !t is #$de mem$"y& The pro#ram code can be stored by usin# this area. The ROM is used for this purpose. ;*. W !t !"e t e (ses $f time"s& The time inter"als can be completed )recise hardware delays can be calculated The timeout facilities are #enerated ;;. 0i1e s $"t n$tes $n RAM %"$#ess$"& !t is said to be the family of R! $ architecture. The ARM instructions are written one per line8 startin# after the first column. ;4. W !t !"e t e d!t! ty%es s(%%$"ted by RAM& tandard ARM word is 32 bit lon# 9ord is splitted into & @ bit bytes

;5. W !t !"e t e * ty%es $f $%e"!tin) m$des& <ormal mode !dle mode )ower down mode

;6. ?$- is "eset !#ti1!ted& a7 An e%ternal reset b7 oftware instruction c7 Time=out by a pro#rammed timer +nown as watch do# timer. d7 A cloc+ timer. ;7. W !t !"e t e 1!"i$(s %"$)"!ms t !t !"e %$ssib/y "(n $n "esettin) t e embedded system & a7 A system pro#ram that e%ecutes from be#innin# b7 A system boot=up pro#ram c7 A system initiali>ation pro#ram. ;8. W !t is t e need f$" 3CD !nd 3ED dis%/!ys& A system re,uires an interfacin# circuit and software to display the status or messa#e for a line8 for multi=line of flashin# displays. 4:. Define de1i#e d"i1e". A de"ice dri"er is software for controllin#8 recei"in# and sendin# a byte or a stream of bytes from or to a de"ice. 41. W !t !"e t e 1!"i$(s f(n#ti$ns #$nt"$//ed by t e de1i#e d"i1e"& )lacin# appropriate bits in the control re#ister acti"ates initiali>in# that. $allin# an ! R on an interrupt or on settin# a status fla# in the status re#ister and run the ! R. Resettin# the status fla# after interrupt ser"ice. 4'. W"ite t e "e!/ time #$nst"!ints $f embedded systems. The real time constraints are performance8 <RE cost8 si>e and power. 4*. Menti$n t e m!@$" !"d-!"e #$m%$nents (sed f$" t e desi)n $f !n embedded system. RAM8 processor8 address latch8 ROM8 A-$5-A$8 interfaces are the hardware components used in the desi#n of an embedded system. 4;. 0i1e t e si)nifi#!n#e $f embedded system. An embedded system performs a well defined tas+. (i+e any other computin# system it has hardware and software. Howe"er it is used for well defined tas+.

44. N!me !ny f$(" %"$#ess$"s (sed in embedded system desi)n. Microprocessor8 microcontroller8 embedded processor8 media processor8 di#ital si#nal processor 8 ARM8 Atmel are the processor used in embedded system desi#n.

UNIT II DE2ICES AND BUSES AOR DE2ICES NETWORK TWO MARKS 1. Diffe"enti!te syn# "$n$(s #$mm(ni#!ti$n !nd is$-syn# "$n$(s #$mm(ni#!ti$n. Syn# "$n$(s #$mm(ni#!ti$n 9hen a byte or a frame of the data is recei"ed or transmitted at constant time inter"als with uniform phase difference8 the communication is called synchronous communication. Is$-syn# "$n$(s #$mm(ni#!ti$n !so=synchronous communication is a special case when the ma%imum time inter"al can be "aried. '. W !t !"e t e t-$ # !"!#te"isti#s $f syn# "$n$(s #$mm(ni#!ti$n& ;ytes maintain a constant phase difference The cloc+ is not always implicit to the synchronous data recei"er. *. W !t !"e t e t "ee -!ys $f #$mm(ni#!ti$n f$" ! de1i#e& !so=synchronous communication synchronous communication Asynchronous communication ;. E.%!nd !, S9I b, SCI )!Aserial )eripheral !nterface $!A erial $ommunication !nterface 4. Define s$ft-!"e time". This is software that e%ecutes and increases or decreases a count "ariable on an interrupt from a timer output or form a real time cloc+ interrupt. A software timer can also #enerate interrupt on o"erflow of count "alue or on finishin# "alue of the count "ariable. *. W !t is I'C& !2$ is a serial bus for interconnectin# !$s .!t has a start bit and a stop bit li+e an :ART. !t has se"en fields for start8/ bit address8 definin# a read or a write8 definin# byte as ac+nowled#in# byte8 data byte8 <A$4 and end.

;. W !t !"e t e bits in I'C #$""es%$ndin) t$& !t has se"en fields for start8/ bit address8 definin# a read or a write8 definin# byte as ac+nowled#in# byte8 data byte8 <A$4 and end. 4. W !t is ! CAN b(s& W e"e is it (sed& $A< is a serial bus for interconnectin# a central $ontrol networ+. !t is mostly used in automobiles. !t has fields for bus arbitration bits8 control bits for address and data len#th data bits8 $R$ chec+ bits8 ac+nowled#ement bits and endin# bits. 5. W !t is USB& W e"e is it (sed& : ; is a serial bus for interconnectin# a system. !t attaches and detaches a de"ice from the networ+. !t uses a root hub. <odes containin# the de"ices can be or#ani>ed li+e a tree structure. !t is mostly used in networ+in# the !O de"ices li+e scanner in a computer system. 6. W !t !"e t e fe!t("es $f t e USB %"$t$#$/& A de"ice can be attached8 confi#ured and used8 reset8 reconfi#ured and used8 share the bandwidth with other de"ices8 detached and reattached. 7. E.%/!in b"ief/y !b$(t 9CI !nd 9CIBC b(ses. )$! and )$!5B buses are independent from the !;M architecture .)$!5B is an e%tension of )$! and support 1&5122 MHC transfers. (ately8 new "ersions ha"e been introduced for the )$! bus architecture. 8. W y !"e S9CI %!"!//e/ b(ses im%$"t!nt& )$! serial buses are important for distributed de"ices. The latest hi#h speed sophisticated systems use new sophisticated buses. 1:. W !t is me!nt by UART& :ART stands for uni"ersal Asynchronous Recei"er5Transmitter. :ART is a hardware component for translatin# the data between parallel and serial interfaces. :ART does con"ert bytes of data to and from asynchronous start stop bit. :ART is normally used in MO-EM. 11. W !t d$es UART #$nt!in& A cloc+ #enerator. !nput and Output start Re#isters ;uffers. Transmitter5Recei"er control.

1'. W !t is me!nt by ?D3C& H-($ stands for DHi#h (e"el -ata (in+ $ontrolE. H-($ is a bit oriented protocol. H-($ is a synchronous data (in+ layer.

1*. N!me t e ?D3C<s f"!me st"(#t("e& .la# Address $ontrol -ata .$ .la# 1;. 3ist $(t t e st!tes $f time"& There are ele"en states as follows Reset state !dle state )resent state O"er flow state O"er run state Runnin# state Reset enabled state 5 disabled .inished state (oad enabled 5 disabled Auto reload enabled 5 disabled er"ice routine e%ecution enabled 5 disabled 14. N!me s$me #$nt"$/ bit $f time"& Timer Enable Timer start :p count Enable Timer !nterrupt Enable 15. W !t is me!nt by st!t(s f/!)& tatus fla# is the hardware si#nal to be set when the timer reaches >eros. 16. 3ist $(t s$me !%%/i#!ti$ns $f time" de1i#es& Real Time cloc+ 9atchdo# timer !nput pulse countin# T-M

 chedulin# of "arious tas+s 17. St!te t e s%e#i!/ fe!t("es $n I'C& (ow cost Easy implementation Moderate speed 6upto 122 +bps7.

18. W !t !"e dis!d1!nt!)es $f I'C& la"e hardware does not pro"ide much support Open collector dri"ers at the master leads to be confused ':.W !t !"e t e t-$ st!nd!"ds $f USB& : ; 1.1 : ; 2.2 '1. W !t is t e need $f Ad1!n#ed Se"i!/ ?i) S%eed B(ses& !f the speed in the rate of F*i#abits per second? then there is a need of Ad"anced erial Hi#h peed ;uses. ''. W !t is me!nt by ISA& ! A stands for !ndustry standard Architecture. :sed for connectin# de"ices followin# !O addresses and interrupts "ectors as per !;M pc architecture. '*. W !t is me!nt by 9CI-C& )$! B offers more speed o"er )$!. 32 times more speed than )$!. '4. Define C9CI& $)$! stands for $ompact peripheral component !nterfaces. $)$! is to be connected "ia a )$!. $)$! is used in the areas of Telecommunication !nstrumentation abd data communication applications. '5. Define !/f-d(%/e. #$mm(ni#!ti$n. Transmission occurs in both the direction8 but not simultaneously. '6. Define f(// d(%/e. #$mm(ni#!ti$n.

Transmission occurs in both the direction8 simultaneously '7. Define Re!/ Time C/$#> +RTC,& Real time cloc+ is a cloc+ which once the system stats does not stop and cant be reset and its count "alue cant be reloaded. '8. Define Time-$(t $" Time O1e"f/$-& A state in which the number of count inputs e%ceeded the last ac,uirable "alue and on reachin# that state8 an interrupt can be #enerated. *:. W y d$ -e need !t /e!st $ne time" in !n ES& The embedded system needs at least on timer de"ice. !t is used as a system cloc+. *1. W !t !"e t e diffe"ent ty%es $f #$nt"$/ bits (sed in ! !"d-!"e time" #$nt"$/ "e)iste"& 1. Timer 2. Timer start 3. Timer stop &. )re=scalin# bits 3. :p count enable 1. -own count enable /. Timer interrupt enable @. (oad enable *'. Define %"$t$#$/. A way of transmittin# messa#es on a networ+ by usin# a software for addin# the additional bits li+e startin# bits8 header addresses of source destination8 error control bits and endin# bits. Each layer or sub layer uses its protocol before a messa#e transmits as a networ+. **. Define b(s. ;usesG The e%chan#e of information. !nformation is transferred between units of the microcomputer by collections of conductors called buses. There will be one conductor for each bit of information to be passed8 e.#.8 11 lines for a 11 bit address bus. There will be address8 control8 and data buses *;. W !t !"e t e #/!ssifi#!ti$ns $f IBO de1i#es& i. ynchronous serial input and output ii. Asynchronous serial :ART input and output iii. )arallel one bit input and output i". )arallel port input and output

*4. W !t !"e t e t-$ # !"!#te"isti#s $f syn# "$n$(s #$mm(ni#!ti$n& H ;ytes5frames maintain constant phase difference and should not be sent at random time inter"als. <o handsha+in# si#nals are pro"ided durin# the communication. H $loc+ pulse is re,uired to transmit a byte or frame serially. $loc+ rate information is transmitted by the transmitter. *5. W !t !"e t e t "ee -!ys $f #$mm(ni#!ti$n f$" ! de1i#e& i. eparate cloc+ pulse alon# with data bits ii. -ata bits modulated with cloc+ information iii. Embedded cloc+ information with data bits before transmittin# *6. W !t !"e t e fe!t("es $f S9I& H )! has pro#rammable cloc+ rates H .ull=duple% mode H $rystal cloc+ fre,uency is @MH> H Open drain or totempole output from master to sla"e *7. W !t !"e t e f$(" ty%es $f d!t! t"!nsfe" (sed in USB& H $ontrolled transfer H ;ul+ transfer H !nterrupt dri"en data transfer *8. 0i1e ! b"ief #$mment $n t e fe!t("es $f I'C b(s. !2$ is a two wire serial bus protocol which enables peripherals to communicate with each other8 it has data rates up to 1222+bps and / bit addressin#. ;:. S%e#ify t e s%e#i!/ !%%/i#!ti$ns s#$%e $f CAN. $an bus has "arious applications in automoti"e electronics. As di#ital electronics were introduced into automoti"e components8 not only did the indi"idual components #et smarter8 but also the need for them to communicate in order to e%ecute their functions #rew. ;1. W !t !"e t e #$m%$nents %"esent in de1i#e net-$">. ;inary outputs8 serial outputs8 analo#ue "alues8 displays8 time deri"ed outputs are some of the components present in de"ice networ+. ;'. W"ite t e f(n#ti$ns $f time" se#ti$n in !n embedded system. !t +eeps trac+ of the system time8 it controls tas+ schedulin#8 restarts "arious cloc+s8 sends si#nals to tas+s based on timin# considerations8 pro"ides statistical information.

UNIT-III 9RO0RAMMIN0 CONCE9TS AND EMBEDDED 9RO0RAMMIN0 IN CD CEE

1. W !t !"e t e !d1!nt!)es $f Assemb/y /!n)(!)e& H !t #i"es the precise control of the processor internal de"ices and full use of processor specific features in its instruction sets and addressin# modes. H The machine codes are compact8 which re,uires only small memory. H -e"ice dri"ers need only few assembly instructions. '. W !t !"e !d1!nt!)es $f i) /e1e/ /!n)(!)es& H -ata type declaration H Type chec+in# H $ontrol structures H )robability of non=processor specific codes *. Define In -/ine !ssemb/y !nsertin# an assembly code in between is said to be in=line assembly. ;. Menti$n t e e/ements $f C %"$)"!m. 1. .ilesG 1. Header files 2. ource files 3. $onfi#uration files &. )reprocessor directi"es 2. .unctionsG 1. Macro function 2. Main function 3. !nterrupt ser"ice routines or de"ice dri"ers 3. OthersG 1. -ata types 2. -ata structures 3. Modifiers &. tatements

3. (oops and pointers 4. W !t is t e (se $f MACRO f(n#ti$n& H A macro function e%ecutes a named small collection of codes8 with the "alues passed by the callin# function throu#h its ar#uments. H !t has constant sa"in# and retrie"in# o"erheads. 5. W !t is t e (se $f inte""(%t se"1i#e "$(tines $" de1i#e d"i1e"s& H !t is used for the declaration of functions and datatypes8 typedef and e%ecutes named set of codes. H ! R must be small 6short78 reentrant or must ha"e solution for shared data problem. 6. W !t !"e t e d!t!ty%es !1!i/!b/e in C /!n)(!)e& $har I @ bitJ byte I @ bitJ short I 11 bitJ unsi#ned short I 11 bitJ unsi#ned int I 32 bitJ int I 32 bitJ lon# double I 1& bitJ float I 32 bitJ double I 1& 7. Menti$n t e d!t! st"(#t("es !1!i/!b/e in C /!n)(!)e. 1. Kueue 2. tac+ 3. Array 61=dimentional and multi=dimentional7 &. (ist 3. Tree 1. ;inary=tree 8. W"ite t e synt!. f$" de#/!"!ti$n $f %$inte" !nd N(//-%$inte". ynta% for pointerG "oid LportAdata ynta% for <ull=pointerG Mdefine <:(( 6"oidL7 2%2222 1:. E.%/!in %!ss by 1!/(es. H The "alues are copied into the ar#uments of the function. H $alled pro#rams does not chan#e the "alues of the "ariables 11. W !t !"e t e t "ee #$nditi$ns t !t m(st be s!tisfied by t e "e-ent"!nt f(n#ti$n& 1. All the ar#uments pass the "alues and none of the ar#ument is a pointer. 2. 9hen a non=atomic operation8 that function should not operate on the function declared outside. 3. A function does does not call a function by itself when it is not reentrant. 1'. E.%/!in %!ss by "efe"en#e. H 9hen an ar#ument "alue to a function is passed throu#h a pointer8 then the "alue can

be chan#ed. H <ew "alue in the callin# function will be returned from the called function.

1*. W"ite t e synt!. f$" f(n#ti$n %$inte". ynta%G "oid LNfunctionOnameP 6function ar#uments7 1;. Define =(e(e. H A structure with a series of elements. H :ses .!.O mode. H !t is used when an element is not directly accessed usin# pointer and inde% but only throu#h .!.O. H Two pointers are used for insertion and deletion. 14. Define st!#>. H A structure with a series of elements which uses (!.O mode. H An element can be pushed only at the top and only one pointer is used for )O). H :sed when an element is not accessible throu#h pointer and inde%8 but only throu#h (!.O. 15. Define 3ist. H Each element has a pointer to its ne%t element. H Only the first element is identifiable and it is done usin# list=top pointer 6header7. H Other element has no direct access and is accessed throu#h the first element. 16. W !t is Ob@e#t $"iented %"$)"!mmin)& An obQect=oriented pro#rammin# lan#ua#e is used when there is a need for re=usability of defined obQects or a set of obQects that are common for many applications. 17. W !t !"e t e !d1!nt!)es $f OO9s& H -ata encapsulation H Reusable software components H inheritance 18. W !t !"e t e # !"!#te"isti#s $f OO9s& H An identity I reference to a memory bloc+ H A state I data8 field and attributes

H A beha"ior I methods to manipulate the state of the obQect ':. Define C/!ss. A class declaration defines a new type that lin+s code and data. !t is then used to declare obQects of that class. Thus a class is an lo#ical abstraction but an obQect has physical e%istence. '1. Define NU33 f(n#ti$n <:(( defines empty stac+ or no content in the stac+5,ueue5list. ''. W !t is M(/ti%/e In e"it!n#e& !nheritance is the process by which obQects of one class ac,uire the properties of obQects of another class. !n OO)8 the concept of inheritance pro"ides the idea of reusability. '*. Define E.#e%ti$n !nd/in) E%ceptions are used to report error conditions. E%ception handlin# is built upon three +eywordsG 1. try 2. catch 3. throw ';. W !t is ! 9"e%"$#ess$" Di"e#ti1e& A preprocessor directi"e starts with FM? si#n. The followin# are the types of preprocessor directi"esG 1. )reprocessor #lobal "ariables 2. )reprocessor constants '4. Menti$n t e f/!)s !1!i/!b/e f$" =(e(e. 1. Kerrror .la# 2. Header .la# 3. Trailin# .la# &. cirKu .la# 3. )olyKu .la# '5. St!te t e (se $f NU33 %$inte"s. <:(( means nothin#8 which is e,ui"alent to >ero. !t is used in "arious applications such as differentiatin# nodes8 declaration8 address usa#e etc. '6. W !t !"e t e s%e#i!/ fe!t("es $f $b@e#t $"iented %"$)"!mmin)& The features include data encapsulation8 desi#n of reusable software components and inheritance.

'7. 0i1e t e synt!. !nd e.!m%/e f$" M!#"$ in C /!n)(!)e. The Macro is pro"ided for short codes only. The function is utili>ed when T o"erhead NN Te%ec and a Macro is used when To"erhead R S P Te%ec.

UNIT-I2 REA3 TIME O9ERATIN0 SYSTEMS 9ART I 1. Define %"$#ess. A process is a pro#ram that performs a specific function. '. Define t!s> !nd T!s> st!te. A tas+ is a pro#ram that is within a process. !t has the followin# statesG 1. Ready 2. Runnin# 3. ;loc+ed &. !dle *. Define +TCB, The T$; stands for Tas+ $ontrol ;loc+ which holds the control of all the tas+s within the bloc+. !t has separate stac+ and pro#ram counter for each tas+. ;. W !t is ! t "e!d& A thread otherwise called a li#htwei#ht process 6(9)7 is a basic unit of $): utili>ation8 it comprises of a thread id8 a pro#ram counter8 a re#ister set and a stac+. !t shares with other threads belon#in# to the same process its code section8 data section8 and operatin# system resources such as open files and si#nals. 4. W !t !"e t e benefits $f m(/tit "e!ded %"$)"!mmin)& The benefits of multithreaded pro#rammin# can be bro+en down into four maQor cate#oriesG T Responsi"eness T Resource sharin# T Economy T :tili>ation of multiprocessor architectures 5. C$m%!"e (se" t "e!ds !nd >e"ne/ t "e!ds. :ser threads 4ernel threads :ser threads are supported abo"e the +ernel and are implemented by a thread library at the user le"el 4ernel threads are supported directly by the operatin# system Thread creation U schedulin# are done in the user space8 without +ernel inter"ention. Therefore they are fast to create and mana#e Thread creation8 schedulin# and mana#ement are done by the operatin# system. Therefore they are slower to create U mana#e compared to

user threads ;loc+in# system call will cause the entire process to bloc+ !f the thread performs a bloc+in# system call8 the +ernel can schedule another thread in the application for e%ecution 6. Define RTOS. A real=time operatin# system 6RTO 7 is an operatin# system that has been de"eloped for real=time applications. !t is typically used for embedded applications8 such as mobile telephones8 industrial robots8 or scientific research e,uipment. 7. Define t!s> !nd t!s> "!tes. An RTO facilitates the creation of real=time systems8 but does not #uarantee that they are real=timeJ this re,uires correct de"elopment of the system le"el software. <or does an RTO necessarily ha"e hi#h throu#hput A rather they allow8 throu#h speciali>ed schedulin# al#orithms and deterministic beha"ior8 the #uarantee that system deadlines can be met. That is8 an RTO is "alued more for how ,uic+ly it can respond to an e"ent than for the total amount of wor+ it can do. 4ey factors in e"aluatin# an RTO are therefore ma%imal interrupt and thread latency 8. Define C9U s# ed(/in). $): schedulin# is the process of switchin# the $): amon# "arious processes. $): schedulin# is the basis of multi=pro#rammed operatin# systems. ;y switchin# the $): amon# processes8 the operatin# system can ma+e the computer more producti"e. 1:. Define Syn# "$niF!ti$n. Messa#e passin# can be either bloc+in# or non=bloc+in#. ;loc+in# is considered to be synchronous and non=bloc+in# is considered to be asynchronous. 11. Define Inte" %"$#ess #$mm(ni#!ti$n. !nter=process communication 6!)$7 is a set of techni,ues for the e%chan#e of data amon# multiple threads in one or more processes. )rocesses may be runnin# on one or more computers connected by a networ+. !)$ techni,ues are di"ided into methods for messa#e passin#8 synchroni>ation8 shared memory8 and remote procedure calls 6R)$7. The method of !)$ used may "ary based on the bandwidth and latency of communication between the threads8 and the type of data bein# communicated. 1'. Define Sem!% $"e. A semaphore F ? is a synchroni>ation tool which is an inte#er "alue that8 apart from initiali>ation8 is accessed only throu#h two standard atomic operationsJ wait and si#nal. emaphores can be used to deal with the n=process critical section problem. !t can be also used to sol"e "arious synchroni>ation problems. The classic definition of Fwait?

wait 6 7V while 6 NS27 J ==JW The classic definition of Fsi#nal? si#nal 6 7V XXJ W 1*. W !t is ! sem!% $"e& emaphores == software8 bloc+in#8 O assistance solution to the mutual e%clusion problem basically a non=ne#ati"e inte#er "ariable that sa"es the number of wa+eup si#nals sent so they are not lost if the process is not sleepin# another interpretation we will see is that the semaphore "alue represents the number of resources a"ailable 14. 0i1e t e sem!% $"e "e/!ted f(n#ti$ns. A semaphore enforces mutual e%clusion and controls access to the process critical sections. Only one process at a time can call the function fn. R )ro#ramG A emaphore )re"ents the Race $ondition. R )ro#ramG A emaphore )re"ents Another Race $ondition. 15. W en t e e""$" -i// $##(" - en -e (se t e sem!% $"e& i. 9hen the process interchan#es the order in which the wait and si#nal operations on the semaphore mute%. ii. 9hen a process replaces a si#nal 6mute%7 with wait 6mute%7. iii. 9hen a process omits the wait 6mute%78 or the si#nal 6mute%78 or both. 16. Diffe"enti!te #$(ntin) sem!% $"e !nd bin!"y sem!% $"e. ;inary emaphoreG The #eneral=purpose binary semaphore is capable of addressin# the re,uirements of both forms of tas+ coordinationG mutual e%clusion and synchroni>ation. A binary semaphore can be "iewed as a fla# that is a"ailable 6full7 or una"ailable 6empty7. $ountin# semaphores are another means to implement tas+ synchroni>ation and mutual e%clusion. $ountin# emaphoreG The countin# semaphore wor+s li+e the binary semaphore e%cept that it +eeps trac+ of the number of times a semaphore is #i"en. E"ery time a semaphore is #i"en8 the count is incrementedJ e"ery time a semaphore is ta+en8 the count is decremented. 9hen the count reaches >ero8 a tas+ that tries to ta+e the semaphore is bloc+ed. As with the binary semaphore8 if a semaphore is #i"en and a tas+ is bloc+ed8 it becomes unbloc+ed. Howe"er8 unli+e the binary semaphore8 if a semaphore is #i"en and no tas+s are bloc+ed8 then the count is

incremented. This means that a semaphore that is #i"en twice can be ta+en twice without bloc+in#. 17. W !t is %"i$"ity in e"it!n#e& )riority inheritance is a method for eliminatin# priority in"ersion problems. :sin# this pro#rammin# method8 a process schedulin# al#orithm will increase the priority of a process to the ma%imum priority of any process waitin# for any resource on which the process has a resource loc+. 18. Define Mess!)e Q(e(e. A messa#e ,ueue is a buffer mana#ed by the operatin# system. Messa#e ,ueues allow a "ariable number of messa#es8 each of "ariable len#th8 to be ,ueued. Tas+s and ! Rs cansend messa#es to a messa#e ,ueue8 and tas+s can recei"e messa#es from a messa#e ,ueue 6if it is nonempty7. Kueues can use a .!.O 6.irst !n8 .irst Out7 policy or it can be based on priorities. Messa#e ,ueues pro"ide an asynchronous communications protocol. ':. Define M!i/b$. !nd 9i%e. A mailbo%es are software=en#ineerin# components used for interprocess communication8 or for inter=thread communication within the same process. A mailbo% is a combination of a semaphore and a messa#e ,ueue 6or pipe7. Messa#e ,ueue is same as pipe with the only difference that pipe is byte oriented while ,ueue can be of any si>e. '1. Define S$#>et. A soc+et is an endpoint for communications between tas+sJ data is sent from one soc+et to another. ''. Define Rem$te 9"$#ed("e C!//. Remote )rocedure $alls 6R)$7 is a facility that allows a process on one machine to call a procedure that is e%ecuted by another process on either the same machine or a remote machine. !nternally8 R)$ uses soc+ets as the underlyin# communication mechanism. Other !mportant Kuestions '*. Define t "e!d #!n#e//!ti$n G t!")et t "e!d. The thread cancellation is the tas+ of terminatin# a thread before it has completed. A thread that is to be cancelled is often referred to as the tar#et thread. .or e%ample8 if multiple threads are concurrently searchin# throu#h a database and one thread returns the result8 the remainin# threads mi#ht be cancelled. '6. W !t !"e t e diffe"ent -!ys in - i# ! t "e!d #!n be #!n#e//ed& $ancellation of a tar#et thread may occur in two different scenariosG

T Asynchronous cancellationG One thread immediately terminates the tar#et thread is called asynchronous cancellation. T -eferred cancellationG The tar#et thread can periodically chec+ if it should terminate8 allowin# the tar#et thread an opportunity to terminate itself in an orderly fashion. '7. W !t is %"eem%ti1e !nd n$n-%"eem%ti1e s# ed(/in)& H :nder non=preempti"e schedulin# once the $): has been allocated to a process8 the process +eeps the $): until it releases the $): either by terminatin# or switchin# to the waitin# state. H )reempti"e schedulin# can preempt a process which is utili>in# the $): in between its e%ecution and #i"e the $): to another process. '8. W !t is ! Dis%!t# e"& The dispatcher is the module that #i"es control of the $): to the process selected by the short=term scheduler. This function in"ol"esG T witchin# conte%t T witchin# to user mode T Yumpin# to the proper location in the user pro#ram to restart that pro#ram. *:. W !t is dis%!t# /!ten#y& The time ta+en by the dispatcher to stop one process and start another runnin# is +nown as dispatch latency. *1. W !t !"e t e 1!"i$(s s# ed(/in) #"ite"i! f$" C9U s# ed(/in)& The "arious schedulin# criteria are T $): utili>ation T Throu#hput T Turnaround time T 9aitin# time T Response time *'. Define t "$() %(t& Throu#hput in $): schedulin# is the number of processes that are completed per unit time. .or lon# processes8 this rate may be one process per hourJ for short transactions8 throu#hput mi#ht be 12 processes per second. **. W !t is t("n!"$(nd time& Turnaround time is the inter"al from the time of submission to the time of completion of a process. !t is the sum of the periods spent waitin# to #et into memory8 waitin# in the ready ,ueue8 e%ecutin# on the $):8 and doin# !5O.

*;. Define "!#e #$nditi$n. 9hen se"eral process access and manipulate same data concurrently8 then the outcome of the e%ecution depends on particular order in which the access ta+es place is called race condition. To a"oid race condition8 only one process at a time can manipulate the shared "ariable. *4. W !t is #"iti#!/ se#ti$n %"$b/em& $onsider a system consists of FnF processes. Each process has se#ment of code called a critical section8 in which the process may be chan#in# common "ariables8 updatin# a table8 writin# a file. 9hen one process is e%ecutin# in its critical section8 no other process can allowed e%ecutin# in its critical section. 31. 9hat are the re,uirements that a solution to the critical section problem must satisfyZ The three re,uirements are T Mutual e%clusion T )ro#ress T ;ounded waitin# *6. Define de!d/$#>. A process re,uests resourcesJ if the resources are not a"ailable at that time8 the process enters a wait state. 9aitin# processes may ne"er a#ain chan#e state8 because the resources they ha"e re,uested are held by other waitin# processes. This situation is called a deadloc+. *7. W !t !"e #$nditi$ns (nde" - i# ! de!d/$#> sit(!ti$n m!y !"ise& A deadloc+ situation can arise if the followin# four conditions hold simultaneously in a systemG 1. Mutual e%clusion 2. Hold and wait 3. <o pre=emption &. $ircular wait *8. W !t !"e t e 1!"i$(s s !"ed d!t! $%e"!tin) system se"1i#es& H e%plain how operatin# systems pro"ide abstraction from the computer hardware. H describe the meanin# of processes8 threads and schedulin# in a multitas+in# operatin# system. H describe the role of memory mana#ement e%plainin# the terms memory swappin#8 memory pa#in#8 and "irtual memory. H contrast the way that M =-O and uni% implement file systems compare the desi#n of some real operatin# systems.

;:. W !t is #"iti#!/ se#ti$n&

The primary use is for protection of shared resources. !t is used to limit access to such a resources to one tas+ at a time. ;1. ?$- d$ %i%es im%"$1e t e %e"f$"m!n#e $f RTOS& )ipes performs similar functions li+e mailbo%8 creation8 writin#8 readin#. The only difference is pipes may be ;yte= oriented in some RTO . ;'. Menti$n t e )$!/s $f RTOS. Resource sharin# and allocatrion .acilitates easy implementation Memory mana#ement )rocess mana#ement -e"ice mana#ement Yob se,uencin#

;*. W !t is 1i"t(!/ s$#>et& A "irtual soc+et is an endpoint for communications between tas+sJ data is sent from one soc+et to another.

UNIT-2

REA3 TIME O9ERATIN0 SYSTEMS 9ART II 1. N!me !ny t-$ im%$"t!nt RTOS. 1. Micro$5O !! 2. '%9or+s '. W !t is s$% isti#!ted m(/tit!s>in) embedded system& Multitas+in# pro"ides the fundamental mechanism for an application to control and react to multiple8 discrete real=world e"ents. Multitas+in# creates the appearance of many threads of e%ecution runnin# concurrently when8 in fact8 the +ernel interlea"es their e%ecution on the basis of a schedulin# al#orithm. *. E.%/!in m(/ti t!s> !nd t ei" f(n#ti$ns in embedded system. This system implements cooperati"e and time=sliced multitas+in#8 pro"ides resource loc+in# and mailbo% ser"ices8 implements an efficient pa#ed memory mana#er8 traps and reports errors8 handles interrupts8 and auto starts your application at system startup. ;y followin# some simple codin# practices as shown in the documented codin# e%amples8 you can ta+e ad"anta#e of these sophisticated features without ha"in# to worry about the implementation details. ;. N!me !ny t-$ =(e(e "e/!ted f(n#ti$ns f$" t e inte" t!s> #$mm(ni#!ti$ns. Kueue related functions includes $reatin# a ,ueue for an !)$8 9aitin# for an !)$ messa#ea t a ,ueue8 Emptyin# the Kueue and Eliminatin# All the Messa#e pointers8 endin#a messa#e=pointetor the Kueue8 endin# a messa#e pointer and insertin# at the Kueue .ront and Kueryin# to .ind the Messa#e and Enor !nformation for the Kueue E$;. To connect a messa#e ,ueue8 or create it if it doesn[t e%ist. 4. W !t !"e t e t-$ s$("#e !1!i/!b/e f$" HCOS I II& )rocessor I dependent source files8 )rocessor I independent source files. 5. 0i1e t e f(n#ti$n f$" sendin) ! =(e(e. Each messa#e is made up of two parts8 which are defined in the template structure struct ms#buf8 as defined in sys5ms#.hG struct ms#buf V lon# mtypeJ char mte%t\1]J WJ The field mtype is used later when retrie"in# messa#es from the ,ueue8 and can be set to any

positi"e number. mte%t is the data this will be added to the ,ueue 6. 0i1e ! f(n#ti$n f$" "e#ei1in) ! mess!)e f"$m ! =(e(e A call to ms#rc"67 that would do it loo+s somethin# li+e thisG Minclude +eyOt +eyJ int ms,idJ struct pirateOms#buf pmbJ 5L where (^[Olonais is to be +ept L5 +ey S fto+6^_5home5beeQ5somefile^_8 ^[b^[7J ms,id S ms##et6+ey8 2111 ` !)$O$REAT7J ms#rc"6ms,id8 Upmb8 si>eof6pmb78 28 27J 5L #et him off the ,ueuea L5 7. 0i1e t e ste%s t$ dest"$y ! mess!)e =(e(e. There are two waysG 1. :se the :ni% command ipcs to #et a list of defined messa#e ,ueues8 then use the command ipcrm to delete the ,ueue. 2. 9rite a pro#ram to do it for you 8. 0i1e t e needs f$" mem$"y m!n!)ement. Each new model of computer seems to come with more main memory than the last8 but8 since the memory re,uirements of the software rise Qust as fast8 memory is always a precious commodity8 hence the need for memory mana#ement . H Memory is allocated to a process when needed H Memory is deallocated when no lon#er in use H wappin# allows the total memory used by all the runnin# processes to e%ceed main memory H 'irtual memory ma+es it possible to run a sin#le pro#ram that uses more memory than the main memory 6normally RAM7 a"ailable on the system. 'irtual memory is normally di"ided into pa#es. H )ro#rams refer to parts of memory usin# addresses. !n a "irtual memory system8 these are "irtual addresses The "irtual address is mapped onto physical addresses by a memory mana#ement unit 6MM:7 1:. N!me s$me !%%/i#!ti$n f$" t e 2.W$">s RTOS. 1. Automobiles 2. A"ionics 3. $onsumer electronics &. Medical de"ices 3. Military 1. Aerospace

/. <etwor+in# 11. W !t !"e t e 1!"i$(s fe!t("es $f 2.W$">s& 1. Hi#h performance 2. Host and tar#et based de"elopment approach 3. upports ad"anced processor architecture &. Hard real=time applications 1'. W !t !"e t e b!si# f(n#ti$ns $f 2.W$">s& 1. ystem le"el functions 2. Tas+ ser"ice functions 3. Tas+ control functions &. !)$s 3. <etwor+ and !O functions 1*. W !t !"e t e t!s> se"1i#e f(n#ti$ns s(%%$"ted by 2.W$">s& 1. Tas+ creation and acti"ation distinct states. 2. .unctions for the tas+ creatin#8 runnin#8 waitin#8 suspendin# and resumin#8 tas+ pendin# cum suspendin# with and without timeouts. 1;. W !t !"e t e diffe"ent ty%es $f sem!% $"es in 1.-$">s& W i# is t e f!stest& '%9or+s supports three types of semaphores. ;inary8 mutual e%clusion8 and countin# semaphores. ;inary is the fastest semaphore. 14. 3ist $(t !ny )$!/s $f HCOS I II& 17 :se messa#e and ,ueues for tas+ communication8 27 :se e"ent fla# for tas+ synchroni>ation8 37 Handlin# interrupt and shared resources8 &7 limit priority in"ersion8 37 )re"ent deadloc+ 15. W !t !"e 2.W$">s %i%es& )ipes pro"ide an alternati"e interface to the messa#e ,ueue facility that #oes throu#h the '%9or+s !5O system. )ipes are "irtual !5O de"ices mana#ed by the dri"er pipe-r". The routine pipe-e"$reate6 7 creates a pipe de"ice and the underlyin# messa#e ,ueue associated with that pipe. The call specifies the name of the created pipe8 the ma%imum number of messa#es that can be ,ueued to it8 and the ma%imum len#th of each messa#eG status S pipe-e"$reate 6_5pipe5name_8 ma%Oms#s8 ma%Olen#th7J The created pipe is a normally named !5O de"ice. Tas+s can use the standard !5O routines to open8 read8 and write pipes8 and in"o+e ioctl routines.

16. W !t is si)n!/ se"1i#in) f(n#ti$n& '%9or+s supports a software si#nal facility. i#nals asynchronously alter the control flow of a tas+. Any tas+ or ! R can raise a si#nal for a particular tas+. The tas+ bein# si#naled immediately suspends its current thread of e%ecution and e%ecutes the tas+specified si#nal handler routine the ne%t time it is scheduled to run. The si#nal handler e%ecutes in the recei"in# tas+[s conte%t and ma+es use of that tas+[s stac+. The si#nal handler is in"o+ed e"en if the tas+ is bloc+ed. 17. Define Mi#"$ CBOSII. Micro $5O !! 6commonly termed u$5O !! or m$5O =!l78i s a low=cost priorty=based preempti"e real time multitas+in# operatin# system +emel for microprocessors8 mainly in the $ pro#rammin# lan#ua#e. !t is mainly intended for use in embedded systems. 18. W !t !"e t e t!s> st!tes in MICRO CBOS-II& Tas+ statesG m$5O =\ is a multitas+in# operatin# system. Each tas+ is an infinite loop and can be in any one of the followin# 3 statesG 1. -ormant 2. Ready 3. Runnin# &. 9aitin# 3. ! R ':. W !t !"e t e ' s$("#e fi/es in Mi#"$ CBOS-II& 1. )reprocessor dependent source file 2. )reprocessor independent source file '1. W !t !"e t e b!si# f(n#ti$ns $f MUCOS& H ystem le"elG O initiate8 start8 system timer set8 ! R enter and e%it H Tas+ ser"ice functionG create8 run8 suspend8 resume H Tas+ delay H Memory allocation and partitionin# H !)$s8 mailbo% and ,ueues

''. W !t is RTOS& RTO has the basic functions of the os plus functions for Real time tas+ schedulin# and interrupt latency control. RTO uses the timers and system cloc+s8 time allocation and de = allocation to attain best utili>ation of the $): time.

'*.W !t !"e t e t-$ s$("#e !1!i/!b/e f$" HCOS I II& )rocessor I dependent source files8 )rocessor I independent source files ';. 3ist $(t !ny 5 fe!t("es $f HCOS I II& calable )ortable !nterrupt mana#ement Romable !nterrupt ser"ices -eterministic '4. A(n#ti$ns $f si)n!/ ISR& 17 $all tas+ restart 678 27 $all e%it 678 37 $all lon# Qump 67 '5. W !t is #/!ss di!)"!m& A class dia#rams shows how the classes and obQects of a class relate8 and also hierarchical associations and obQect interaction between the class and obQect. '6. W !t is st!te di!)"!m& A state dia#ram shows a model of a structure for its start8 end8 in I between associations throu#h the transactions and shows e"ent labels with associated transitions. '7. W !t is >e"ne/& The +ernel is the essential center of a compute os8 the code that pro"ides basic ser"ices for all other parts of the os. '8. Menti$n !ny f$(" mem$"y "e/!ted f(n#ti$ns. $reatin# memory bloc+s at a memory address *ettin# a memory bloc+ at a memory address Kueryin# a memory bloc+

*:. W !t is t e ne#essity f$" I9C in RTOS& !t is used in semaphore release8 chec+in# the a"ailability8 sendin# an !)$8 retrie"in# the error information for a semaphore. *1. W !t !"e RTOS system /e1e/ f(n#ti$ns&

'oid O 6"oid78 'oid O !ntEnter6"oid78 'oidO !ntE%it6"oid7. *'. Menti$n t e %"$b/ems "e/!ted -it mem$"y !//$#!ti$n in RTOS. .or more comple% systems8 allocation of memory is not efficient8 in that memory may be reser"ed or allocated to a tas+ yet.