MH Datasheet LCD12864ZW
MH Datasheet LCD12864ZW
MH Datasheet LCD12864ZW
Main Features
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Operation Voltage Range: 4.5V to 5.5V Support 8-bit, 4-bit and serial bus MPU interface 64 x 16-bit display RAM (DDRAM) Supports 16 words x 4 lines (Max) LCD display range 16 words x 2 lines 64 x 256-bit Graphic Display RAM (GDRAM) 2M-bits Character Generation ROM (CGROM): Support 8192 Chinese words (16x16 dot matrix) 16K-bit half-width Character Generation ROM (HCGROM): Supports 126 characters (16x8 dot matrix) 32-common x 64-segment (2 lines of character) LCD drivers Automatic power on reset (POR) External reset pin (XRESET) With the extension segment drivers, the display area can up to 16x2 lines Built-in RC oscillator: Frequency is adjusted by an external resistor
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Function Description
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ST7920 LCD controller/driver IC can display alphabets, numbers, Chinese fonts and self-defined characters. It supports 3 kinds of bus interface, namely 8-bit, 4-bit and serial. All functions, including display RAM, Character Generation ROM, LCD display drivers and control circuits are all in a one-chip solution. With a minimum system configuration, a Chinese character display system can be easily achieved. ST7920 includes character ROM with 8192 16x16 dots Chinese fonts and 126 16x8 dots half-width alphanumerical fonts. Besides, it supports 64x256 dots graphic display area for graphic display (GDRAM). Mix-mode display with both character and graphic data is possible. ST7920 has built-in CGRAM and provide 4 sets software programmable 16x16 fonts. ST7920 has wide operating voltage range (2.7V to 5.5V). It also has low power consumption. So ST7920 is suitable for battery-powered portable device. ST7920 LCD driver consists of 32-common and 64-segment. Company with the extension segment driver (ST7921) ST7920 can support up to 32-common x 256-segment display. Part Number ST7920-0A ST7920-0B ST7920-0C ST7920-0F Font Code BIG-5 Code Set (Traditional Chinese) GB Code Set (Simplified Chinese) Chinese (Traditional/Simplified) & Japanese Chinese (Traditional/Simplified), Japanese & Korean
RESO
CLK
RS RW E
SEG1 to SEG64 64-bit shift register 64-bit latch circuit Segment Signal Driver
DB4 to DB7 Input/ Output Buffer Data Register (DR) Busy Flag
Address Counter
DB0 to DB3
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Character Generator RAM (CGRAM) 1024 bits Character Generator ROM (CGROM) 2M bits Cursor Blink Scroll Controller Parallel/Serial converter and Attribute Circuit V0 V1 V2 V3 V4
Vss
No.
17
I/O
I I
Connects to
! !
Function
System reset input (low active). Interface selection: 0: serial mode; 1: 8/4-bit parallel bus mode. Parallel Mode: Register select. 0: Select instruction register (write) or busy flag, address counter (read); 1: Select data register (write/read). Serial mode: Chip select. 1: chip enabled; 0: chip disabled. When chip is disabled, SID and SCLK should be set as "H# or "L#. Transcient of SID and SCLK is not allowed. Parallel Mode: Read/Write control. 0: Write; 1: Read. Serial Mode: Sserial data input. Parallel Mode: 1: Enable trigger. Serial Mode: Serial clock. Higher nibble data bus of 8-bit interface and data bus for 4-bit interface Lower nibble data bus of 8-bit interface. VDD : 4.5V to 5.5V. VSS: 0V. LCD voltage doubler output. VOUT " 7V.
RS(CS*)
MPU
RW(SID*)
MPU
6 11~14 7~10 2 1 18
I/O I/O I I
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MPU MPU Power Power Resistors
MPU
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Address Counter (AC) is used as the address pointer of DDRAM, CGRAM and GDRAM. (AC) can be set by instruction. After that, accesses (Read/Write operations) to the memories, such as DDRAM, CGRAM or GDRAM, (AC) will be increased or decreased by 1 (according to the setting in "Entry Mode Set# Register). When RS=#0#, RW=#1# and E=#1# the value of (AC) will be output to DB6~DB0. Character Generation ROM (CGROM) and Half-width Character Generation ROM (HCGROM) ST7920 is built in a Character Generation ROM (CGROM) to provide 8192 16x16 character fonts and a Half-width Character Generation ROM to provide 126 8x16 alphanumeric characters. It is easy to support multi-language applications such as Chinese and English. Two consecutive bytes are used to specify one 16x16 character or two 8x16 half-width characters. Character codes are written into DDRAM and the corresponding fonts are mapped from CGROM or HCGROM to the display drivers. Character Generation RAM (CGRAM) ST7920 is built in a Character Generation RAM (CGRAM) to support user-defined fonts. Four sets of 16x16 bit-maped RAM spaces are available. These user-defined fonts are displayed the same ways as CGROM fonts by writing the related character code into the DDRAM.
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Table 6 16x8 half-width characters
0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
...........
15
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b15 b14 b13
...........
b0
Table 7
Code
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 I/D 1 X S to "00H".
Description
Fill DDRAM with "20H" and set DDRAM address counter (AC) Set DDRAM address counter (AC) to "00H", and put cursor to origin #the content of DDRAM are not changed Set cursor position and display shift when doing write or read operation D=1: Display ON C=1: Cursor ON B=1: Character Blink ON Cursor position and display shift control; the content of DDRAM are not changed DL=1 8-bit interface
72 us
72 us
DL
AC5 AC4 AC3 AC2 AC1 AC0 Make sure that in extended instruction SR=0 (scroll or RAM address select)
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RE=0: basic instruction AC6 is fixed to 0 Write data to internal RAM (DDRAM/CGRAM/GDRAM) Read data from internal RAM (DDRAM/CGRAM/GDRAM)
72 us
72 us
Read busy flag (BF) for completion of internal operation, also Read out the value of address counter (AC)
0 us
72 us 72 us
Code
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 0 1 COM1!32 are halted.
Description
Enter standby mode, any other instruction can terminate.
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AC3 AC2 AC1 AC0
72 us
Note: 1. 2. Make sure that ST7920 is not in busy state by reading the busy flag before sending instruction or data. If using delay loop instead, please make sure the delay time is enough. Please refer to the instruction execution time. "RE# is the selection bit of basic and extended instruction set. After setting the RE bit, the value will be kept. So that the software doesn t have to set RE every time when using the same instruction set.
Code
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 1 I/D 1 C 0 X S 0 B
Description
Cursor move to right ,DDRAM address counter (AC) plus 1
Display, cursor and blink are ALL OFF 0 X No cursor or display shift operation
Code
0 0 0 0 0
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0 1 R1 R0 Graphic display OFF
Description
Code
This instruction will change the following items: 1. Fill DDRAM with "20H"(space code). 2. Set DDRAM address counter (AC) to"00H". 3. Set Entry Mode I/D bit to be "1". Cursor moves right and AC adds 1 after write or read operation. Return Home
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Code
Set address counter (AC) to "00H". Cursor moves to origin. Then content of DDRAM is not changed. Enry Mode Set
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Code
I/D
Set the cursor movement and display shift direction when doing write or read operation. I/D: Address Counter Control: (Increase/Decrease) When I/D = "1", cursor moves right, address counter (AC) is increased by 1. When I/D = "0", cursor moves left, address counter (AC) is decreased by 1. S: Display Shift Control: (Shift Left/Right) S I/D DESCRIPTION H H Entire display shift left by 1 H L Entire display shift right by 1
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Code
Controls display, cursor and blink ON/OFF. D: Display ON/OFF control bit When D = "1", display ON When D = "0", display OFF, the content of DDRAM is not changed C: Cursor ON/OFF control bit When C = "1", cursor ON. When C = "0", cursor OFF. B: Character Blink ON/OFF control bit When B = "1", cursor position blink ON. Then display data (character) in cursor position will blink. When B = "0", cursor position blink OFF l Cursor/Display Shift Control
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Code
S/C R/L
This instruction configures the cursor moving direction or the display shifting direction. The content of DDRAM is not changed. S/C R/L Description AC Value L L Cursor moves left by 1 position AC=AC-1 L H Cursor moves right by 1 position AC=AC+1 H L Display shift left by 1, cursor also follows to shift. AC=AC H H Display shift right by 1, cursor also follows to shift. AC=AC
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Code
DL
RE
DL: 4/8-bit interface control bit When DL = "1", 8-bit MPU bus interface When DL = "0", 4-bit MPU bus interface RE: extended instruction set control bit When RE = "1", extended instruction set When RE = "0", basic instruction set In same instruction cannot alter DL and RE at once. Make sure that change DL first then RE. l Set CGRAM Address
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Code
Set CGRAM address into address counter (AC) AC range is 00H!3FH Make sure that in extended instruction SR=0 (scroll address or RAM address select) l Set DDRAM Address
RS
Code
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RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Set DDRAM address into address counter (AC). First line AC range is 80H!8FH Second line AC range is 90H!9FH Third line AC range is A0H!AFH Fourth line AC range is B0H!BFH Please note that only 2 lines can be display with one ST7920. l Read Busy Flag (BF) and Address
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Code
BF
Read busy flag (BF) can check whether the internal operation is finished or not. At the same time, the value of address counter (AC) is also read. When BF = "1#, further instruction(s) will not be accepted until BF = "0#.
Code
D7 D6 D5 D4 D3 D2 D1 D0
Write data to the internal RAM and increase/decrease the (AC) by 1 Each RAM address (CGRAM, DDRAM and GDRAM!) must write 2 consecutive bytes for 16-bit data. After receiving the second byte, the address counter will increase or decrease by 1 according to the entry mode set control bit. l Read RAM Data
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Code
D7 D6 D5 D4 D3 D2 D1 D0
Read data from the internal RAM and increase/decrease the (AC) by 1 After the operation mode changed to Read (CGRAM, DDRAM and GDRAM!), a "Dummy Read# is required. There is no need to add a "Dummy Read# for the following bytes unless a new address set instruction is issued.
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Code
This Instruction will set ST7920 entering the standby mode. Any other instruction follows this instruction will terminate the standby mode. The content of DDRAM remains the same. l Vertical Scroll or RAM Address Select
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Code
SR
When SR = "1", the Vertical Scroll mode is enabled. When SR = "0", "Set CGRAM Address# instruction (basic instruction) is enabled. l Reverse
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Code
R1 R0
Select 1 out of 4 lines to reverse the display and to toggle the reverse condition by repeating this instruction. R1, R0 initial vale is 00. The first time issuing this instruction, the display will be reversed while the second time will return the display become normal. R1 L L H H R0 L H L H Description
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First line normal or reverse Second line normal or reverse Third line normal or reverse Fourth line normal or reverse
Please note that only 2 lines out of 4 lines of display data can be displayed with one ST7920.
Code
DL
RE
DL: 4/8-bit interface control bit When DL = "1", 8-bit MPU interface. When DL = "0", 4-bit MPU interface. RE: extended instruction set control bit When RE = "1", extended instruction set When RE = "0", basic instruction set G: Graphic display control bit When G = "1", Graphic Display ON When G = "0", Graphic Display OFF In same instruction cannot alter DL, RE and G at once. Make sure that change DL or G first and then RE. l Set Scroll Address
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 Code
SR=1: AC5~AC0 is vertical scroll displacement address l Set Graphic RAM Address
RS
RW
0 Code
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DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
RS
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0 Code
Set GDRAM address into address counter (AC). This is a 2-byte instruction. The first instruction sets the vertical address while the second one sets the horizontal address (write 2 consecutive bytes to complete the vertical and horizontal address setting). Vertical address range is AC5...AC0 Horizontal address range is AC3!AC0 The address counter (AC) of graphic RAM (GRAM) will be increased automatically after the vertical and horizontal addresses are set. After horizontal address is increased upto 0FH, it will automatically return to 00H. However, the vertical address will not increase as the result of the same action.
RS RW E DB0-DB7
Instruction write
RS RW E
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Lower Upper Lower 4-bit 4-bit 4-bit 4-bit
Upper
Upper
Lower
DB0-DB7
4-bit
4-bit
Instruction write
Dummy read
RAM read
CS
1 2 3 4 5
SCLK SID
1 1 1 1
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6 7 8 0 0 Higher data 1st byte
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
1 RW RS 0 D7 D6 D5 D4 0
0 D3 D2 D1 D0 0
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CGROM Last four bytes Y0 38 9D FD Y1 88 81 6F Y2 CC 79 B5 Y3 F1 29 85
The table below is a comparing table of CGROM for different versions. Version (Font) 1 2 3 Big5 (0A) GB (0B) 0C
The table below is a comparing table of HCGROM for different versions. Version (Font) 1 2 3 Big5 (0A) GB (0B) 0C
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HCGROM last four bytes Y0 B5 B5 B5 Y1 11 11 11 Y2 B5 B5 B5 Y3 11 11 11
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STACK FUNC
RESET:
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CGROM:
CN5: CN6:
;Counter 655360 ; ;A=Y3 ;COMPARE Y3 DATA ; ;IF OK CLR TT3 ; ERRORC: ; CLR TT5 ;IF CGROM CHECK ERROR CLR TT5 ;---------------------------------------; ;*******************************; ;* CHECK_HCGROM *; ;*******************************; ;*******************************; ;* Initial setting *; ;*******************************; HCGROM: SETB TT1 ; SETB TT2 ;TT1,TT2 SET HIGH (RESET) CALL DELAY_100US ;Wait Reset 100us CLR TT2 ;TT2=LOW TT1=HIGH ( CHECK HCGROM) SETB CLK ; CALL DELAY_100US ; ;*******************************; ;* start counter *; ;*******************************; MOV R3,#9 ; N4: MOV R2,#32 ;<---N3: MOV R1,#32 ; | N2: CLR CLK ; | SETB CLK ; | DJNZ R1,N2 ; | DJNZ R2,N3 ; | DJNZ R3,N4 ; | ; | MOV R3,#32 ; | N5: MOV R2,#31 ; | N6: CLR CLK ; | SETB CLK ; | DJNZ R2,N6 ; | DJNZ R3,N5 ; | ; | MOV R2,#30 ; |
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XRESET
HIGH
Function set RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 1 X 0 X X
Wait time >100uS Function set RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 1 X 0 X X
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Display ON/OFF control Wait time >100uS Display clear 0 0 0 0 0 0 0 0 Wait time >10mS Entry mode set 0 0 0 0 0 0 1 I/D Initialization end
POWER ON
Wait time > 40mS (for VDD stable) XRESET: LOW HIGH
RS 0 0
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 1 0 X X X X 0 X 0 X X X X X X Wait time > 100 S
Function set
RS 0 0
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 1 0 X X X X 0 X 0 X X X X X X Wait time > 100 S
Function set
RS 0 0
RS 0 0
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Wait time > 100 S
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 X X X X 0 0 0 0 1 X X X X Wait time > 10mS
Display Clear
RS 0 0
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 X X X X 0 0 1 I/D S X X X X
INITIALIZATION END
VD2
VD2
VSS
VOUT
VOUT
VDD
XRESET
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Tres Trw
Trw Tres
10us 50ns
V0 V1 V2 COM1 V3 V4 VSS
V0 V1 V2 COM2 V3 V4 VSS
V0 V1 V2 COM33 V3 V4 VSS
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SEGx off
V0 V1 V2 V3 V4 VSS
SEGx on
V0 V1 V2 V3 V4 VSS
1 frame
DC Characteristics (TA = -30- ~ 85-, VDD = 2.7 V - 4.5 V) Symbol VDD VLCD ICC VIH1 VIL1 VIH2 VIL2 VOH1 VOL1 VOH2 VOL2 ILEAK IPUP Characteristics Operating Voltage LCD Voltage Test Condition Min. 2.7 3.0 0.7VDD - 0.3 VDD % 1 Typ. 0.20 27 Max. 5.5 7 0.45 VDD 0.6 VDD 1.0 VDD 0.1 VDD 0.1VDD 1 32 Unit V V mA V V V V V V V V A A
V0-VSS fOSC = 530KHz, VDD=3.0V Power Supply Current Rf=18K% Input High Voltage (Except OSC1) Input Low Voltage (Except OSC1) Input High Voltage (OSC1) Input Low Voltage (OSC1) Output High Voltage (DB0 - DB7) Output Low Voltage (DB0 - DB7) Output High Voltage (Except DB0 - DB7) Output Low Voltage (Except DB0 - DB7) Input Leakage Current Pull Up MOS Current -
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IOH = -0.1mA IOL = 0.1mA 0.8VDD IOH = -0.04mA IOL = 0.04mA VIN = 0V to VDD VDD = 3V 0.8VDD -1 22
V0-VSS fOSC = 540KHz, VDD=5V Power Supply Current Rf=33K% Input High Voltage (Except OSC1) Input Low Voltage (Except OSC1) Input High Voltage (OSC1) Input Low Voltage (OSC1) Output High Voltage (DB0 - DB7) Output Low Voltage (DB0 - DB7) Output High Voltage (Except DB0 - DB7) Output Low Voltage (Except DB0 - DB7) Input Leakage Current Pull Up MOS Current IOH = -0.1mA IOL = 0.1mA IOH = -0.04mA IOL = 0.04mA
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VIN = 0V to VDD VDD = 5V -1 75
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RS
R/W
TPW TAH
E
TR TDSW TH
DB0-DB7
Valid data
TC
RS
R/W
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VIH1 VIL1 TAS TAH TPW TR TAH TDDR TH
DB0-DB7
Valid data
TC
AC Characteristics (TA = -30- ~ 85-, VDD = 2.7V) Serial Mode Interface Symbol fOSC fEX TR,TF TSCYC TSHW TSLW TSDS TSDH TCSS TCSH Characteristics OSC Frequency
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Test Condition R = 18K Min. 470 Internal Clock Operation External Clock Operation 470 45 600 300 300 40 40 60 60 Pin E Pin E Pin E Pins RW Pins RW Pins RS Pins RS
Typ. 530
530 50 -
Serial clock cycle SCLK high pulse width SCLK low pulse width SID data setup time SID data hold time CS setup time CS hold time
TCSH
TSHW Tr TSDH
Valid data
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Enable DATA
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