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Microprocessors Lecture Slides

1. The x86 ISA evolved from the 8086 processor in 1974 to increasingly more powerful processors over time, growing from 8-bit to 16-bit to 32-bit and beyond. 2. The x86 family uses a CISC instruction set with complex instruction decoding. It has general purpose registers and segment registers that interface with memory through a Bus Interface Unit (BIU) and executes instructions in the Execution Unit (EU). 3. The 80x86 architecture introduced segmentation to access memory beyond 1MB using segment registers and offsets, allowing relocation of programs in memory.

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145 views30 pages

Microprocessors Lecture Slides

1. The x86 ISA evolved from the 8086 processor in 1974 to increasingly more powerful processors over time, growing from 8-bit to 16-bit to 32-bit and beyond. 2. The x86 family uses a CISC instruction set with complex instruction decoding. It has general purpose registers and segment registers that interface with memory through a Bus Interface Unit (BIU) and executes instructions in the Execution Unit (EU). 3. The 80x86 architecture introduced segmentation to access memory beyond 1MB using segment registers and offsets, allowing relocation of programs in memory.

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tourist101
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© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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X86 - ISA

The 80x86 Family

Name 8080 8086 80286 80386

Date Trans istors 1974 1978 1982 1985 6K 29K 134K

Clock speed 2MHz 5MHz 12 MHz

Data width 8 16 16 32

275K 16-33 MHz

80486
Pentium Pentium II Pentium III Pentium 4

1989
1993

1.2 M
3.1M

20 -100 MHz
60-200 MHz 233-450 MHz 450 -933 MHz 1.5 GHz

32
32 /64 32/ 64 32 /64 32/ 64

1997 7.5 M 1999 2000 9.5M 42 M

The Evolution of Microprocessors

The 16-bit Processors


8086 20 Address lines 220 1 MB 2.5 MIPS 80286 24 Address lines 224 16 MB 4 MIPS

The 32-bit Processors


80386 32 Address lines 232 4GB 80486 32 Address lines 232 4GB Floating Pt Unit Internal Cache 50 MIPS

Characteristics of the X86 Family


CISC Instructions broken up into ops Complex Instruction Decoder

Memory Interface

2
3

ES CS SS DS IP

Instruction Queue

4 5 6

BIU

Control & Timing EU

AH BH CH

AL BL CL

ALU

DH
BP SP SI DI

DL

Operands Flags

Block Diagram of 8086

8086 - Buses
A0 A19 D0
Add Bus

8086

D15

Data Bus

Control signals

Memory Address Space


A19A0 0.0
00000H FFFFFH 00000H

1.1

Memory Address Space


FFFFFH

Microprocessor
Fetches Instruction Executes Instruction

BIU EU

Address bus

BIU
ROM RAM
I/o Ports

Discs Video

Data Bus

ALU

CLK
Control & Timing

EU

Variation of 8086 - 8088


External Data Bus 8-bits Inst Queue 4 bytes

X86 - ISA
8086-80486 Programmers Model BIU

Memory Addressing
Real
Access only 1 MB of Memory Only 20 Address Lines Required

Protected

Programmers Model - BIU


EIP IP

CS DS ES SS FS GS

Code Segment

Data Segment

Extra Segment

Stack Segment

CS = 2000H IP = 3000H

Base address

Offset address
CS

2000H : 3000H

DS ES

Physical address = 20000H + 3000H 23000H

SS

2000

0000

3000 Code Segment

FFFF

Advantage of Segmentation
Relocation Program Specify only offset Program F0000H 10000H Program contents need not be change only Segment needs to change from F000H 0000H

58FFFH
Extra

49000H 43FFFH
Stack

4900 ES 3400 SS
Code

34000H 2FFFFH

20000H 1FFFFH
10000H 00000H

2000 CS
Data

1000

DS

High Memory
HIMEM.SYS A20 Segment Address FFFFH Offset Address 4000H 103FF0H 03FF0H

X86 - ISA

8086-80486 Programmers Model EU

Programmers Model
AX BX

Accumulator
Base Index Count Data Stack Pointer Base Pointer Source Index Destination Index

CX
DX SP

BP
SI DI

Registers
MULTIPURPOSE REGISTERS
AX, BX, CX, DX, BP, DI, SI

SPECIAL PURPOSE REGISTERS


IP, SP, FLAGS CS, DS, SS, ES ( Segment Registers )

Registers - MPR
AH (8 bit) (Accumulator) AX BH BX (Base Register) CH CX (Used as a counter) DX DH AL (8 bit) BL CL DL

(Used to point to data in I/O operations)

Programmers Model-MPR
EAX AH AL

EBX ECX EDX


EBP ESI EDI ESP

BH CH DH
BP SI DI SP

BL CL DL

Default 16 bit segment and offset address combinations

Segment offset special purpose


CS SS DS IP SP (or) BP BX,DI,SI an 8-bit number 16 bit number DI for string Instructions Instruction Address Stack address Data address String destination address

ES

Programmers Model -SFR


EFLAGS FLAGS

Flags
Status Control

Flag Register
A V R C M F N IOPL O D I T S Z T A P C

80x86-Summary
BIU (Bus Interface Unit) provides hardware funcns for generation of the memory and I/O addresses for the transfer of data between itself and the outside world
EU (Execution Unit) receives program instruction codes and data from the BIU executes these instructions and stores the results in the general- purpose registers

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