SINGLE EVENT EFFECTS

RADIATION TEST REPORT

Part Type : BUK7508-55

Package : TO-220AB

N-Channel Power MOSFET

Philips

Report Reference : ESA_QCA9909013S_C

Issue : 01

Date : July 2nd 1999

ESA Contract No 13413/98/NL/MV dated 25/01/99

European Space Agency Contract Report

The work described in this report was done under ESA contract.
Responsibility for the contents resides in the author or organization that prepared it

ESTEC Technical Officer : R. Harboe Sorensen

Hirex reference : HRX/99.4605 Issue : 01 Date : July 2, 1999

Prepared by : H. CONSTANS/FX GUERRE Date :

Approved by : F.X GUERRE Date :

HIREX Engineering SA au capital de 1 000 000 F - RCS Toulouse B 389 715 525
Siège social: 117, Rue de la Providence - 31500 Toulouse
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TABLE OF CHANGES

Issue 1 July 2, 1999

Original Issue
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TABLE OF CONTENTS

I. ABSTRACT 4

II. INTRODUCTION 5

III. DOCUMENTS 5
III.1 APPLICABLE DOCUMENTS 5
III.2 REFERENCE DOCUMENTS 5
IV. DEVICE INFORMATION 6
IV.1 DEVICE DESCRIPTION 6
IV.2 PROCUREMENT OF TEST SAMPLES 6
IV.3 PREPARATION OF SAMPLES 6
IV.4 SAMPLES CHECK OUT 6
IV.5 DEVICE MARKING 6
V. DEVICE TEST DEFINITION 7
V.1 PREPARATION OF TEST HARDWARE AND PROGRAM 7
V.2 GENERIC TEST SET-UP 7
V.2.1 Mother board description (Ref. IL140A) 7
V.2.2 DUT Test board description 10
V.3 TEST CONFIGURATION 10
V.3.1 Single Event burnout (SEB) 10
V.3.2 Single Event Gate Rupture (SEGR) 11
VI. TEST FACILITIES 12
VI.1 HEAVY I ONS 12
VI.1.1 Beam Source 12
VI.1.2 Beam Set-up 12
VII. HEAVY IONS RESULTS 13
VII.1 BUK7508-55 TEST RESULTS 13
VII.2 TYPICAL SEB WAVEFORM 13
VIII. CONCLUSION 14
FIGURES

Figure 1 – Device marking 6

Figure 2 - Generic Test Set-up 8
Figure 3 – Functional diagram for SEE Test 9
Figure 4 – Equivalent circuit for SEB including the parasitic capacitor of the MOSFET. 10
Figure 5 – Example of non destructive SEBs observed on a 100V transistor at 60V and 70V Vds ratings 13

TABLES

Table 1 – Test circuit resistor values 10

Table 2 – Heavy Ion Test results on BUK7508-55 N-Channel Power MOSFET from Philips : 15
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I. ABSTRACT

Under ESA/ESTEC contract n° 13413/98/NL/MV covering "Radiation Evaluation of Power MOSFET

Devices from Different European Manufacturers", a large number of commercial Power MOSFET
device types were radiation assessed. Results from these assessments, primarily focused on the radiation
sensitivity of the MOSFETs to Total Ionizing Dose (TID) and Single Event Effects (SEE), are reported
in individual TID and SEE reports. Below summary table list manufacturer and evaluated types, and
give references to the various reports issued.

Manufacturer Type TID Report SEE Report

Philips PHP50N06T ESA_QCA990901T_C ESA_QCA990901S_C
Philips BUK456-200A ESA_QCA990902T_C ESA_QCA990902S_C
Motorola MTP50N06VL ESA_QCA990903T_C
Motorola MTW32N20E ESA_QCA990904T_C
Motorola MTP50N06V ESA_QCA990905T_C
Siemens BUZ100S ESA_QCA990906T_C ESA_QCA990906S_C
Siemens BUZ100SL ESA_QCA990907T_C ESA_QCA990907S_C
Siemens BUZ341 ESA_QCA990908T_C ESA_QCA990908S_C
SGS-Thomson SP60 ESA_QCA990909T_C ESA_QCA990909S_C
SGS-Thomson SP100V ESA_QCA9909010T_C ESA_QCA9909010S_C
SGS-Thomson SP200V ESA_QCA9909011T_C ESA_QCA9909011S_C
Siemens SPP1N60S5 ESA_QCA9909012T_C ESA_QCA9909012S_C
Philips BUK7508-55 ESA_QCA9909013T_C ESA_QCA9909013S_C
Harris HUF75639P3 ESA_QCA9909014T_C ESA_QCA9909014S_C
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II. INTRODUCTION

This report presents the results of a heavy ion Single Event Effects (SEEs) test program carried out on
BUK7508-55 N-Channel Power MOSFET from Philips
Devices were tested at the European Heavy Ion Irradiation Facility (HIF) at Cyclone, Université
Catholique de Louvain, Belgium.

This work was performed for ESA/ESTEC under ESA Contract No 13413/98/NL/MV dated 25/01/99

III. DOCUMENTS

III.1 APPLICABLE DOCUMENTS

AD1. Hirex Engineering proposal ref. HRX/98.3475 Issue 1, "Radiation Evaluation of Power MOS
Devices from Different European Manufacturers"
AD2. ESA memorandum Appendix 1 to ESTEC/Contract No 13413/NL/MV

III.2 REFERENCE DOCUMENTS

RD1. Philips data sheet

RD2. Single Event Effects Test method and Guidelines ESA/SCC basic specification No 25100
RD3. The Heavy Ion Irradiation Facility at CYCLONE, UCL document, Centre de Recherches du
Cyclotron (IEEE NSREC'96, Workshop Record, Indian Wells, California, 1996)
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IV. DEVICE INFORMATION

IV.1 DEVICE DESCRIPTION

N-Channel Power MOSFET, 55 Volts, 75 A encapsulated in TO-220AB package

IV.2 PROCUREMENT OF TEST SAMPLES

Procured by Hirex through AVNET distributor

IV.3 PREPARATION OF SAMPLES

Devices have been opened by chemical etch by Hirex Lab.

IV.4 SAMPLES CHECK OUT

A functional test sequence has been performed on opened samples to check that devices have not
been degraded by the opening operation.

IV.5 DEVICE MARKING

Device marking is provided in Figure 1

Figure 1 – Device marking

Technology : TrenchMOS

Die metallization : Aluminum

Die dimensions (approximately, mm²) : 5,4 x 4 ,4

Further details on die description are provided in "Comparative Description and Analysis of Various
Power MOSFETs", ESA document ref. ESA_QCA9909015_C (Hirex ref. HRX/99.4775) / ESA
Contract No 13413/98/NL/MV dated 25/01/99.
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V. DEVICE TEST DEFINITION

V.1 PREPARATION OF TEST HARDWARE AND PROGRAM

Overall device emulation, SEE, data storage and processing were implemented using an in-house test
hardware and application specific test boards.

The generic in-house test equipment is driven by a PC computer through a RS232 line. All power
supplies and input signals are delivered and monitored by the in-house equipment which also stores in
its memory the output data from the device throughout the specific test board.

The application specific test board allowed to interface the standard test hardware with the device
under test, in order to correctly emulate the relevant part, to record all the different type of errors
during the irradiation and to set output signal for processing and storage by the standard test
equipment.

At the end of each test run, data are transferred to the PC computer through the RS232 link for storage
on hard disk or floppies.

V.2 GENERIC TEST SET-UP

Generic device test set-up is presented in Figure 2.

This set-up is constituted of the following units:
• A PC computer (to configure and interface with the test system and store the data),
• An electronic rack with the instrumentation functions provided by a set of electronic modules,
• A mother board under vacuum which allows for the sequential test of up to 10 devices.
• A digital oscilloscope to store analog SEE waveform

SEE Test functional diagram is shown in Figure 3.

V.2.1 Mother board description (Ref. IL140A)
The motherboard acts as a standard interface between each DUT test board and the control unit :
For each slot, the following signals can be considered:
− 4 inputs signals
− Drain Source programmable power supply
− Gate Source programmable power supply
− Simulation signal
− Heater control signal
− 1 output signal
− 1 fast analog output signal

- IL140 board has been designed to comply with both PSI and Louvain test facilities .
- Each device needs a dedicated plug-in test board compatible with IL140 mother board.
- The number of slots is limited to 10: Up to 10 TO220 DUT test boards can be attached or up to5
TO3 DUT test boards.
- Operation is multiplexed and only one slot is powered at one time.
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… … … … …

Slot 1 Slot 2 Slot 10

IL140A
Generic test board
Vacuum chamber

Supplies, switches
commands Count pulses

24 modular instruments
Control unit 50 Ω lines

16 Bit RISC µControleur

Modular DC sources

RS232 to
Digital Scope
control PC
Fast trigger counters

Near Vacuum
chamber

ÿ
Control Room

Figure 2 - Generic Test Set-up

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Figure 3 – Functional diagram for SEE Test

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V.2.2 DUT Test board description

The device under test is mounted on a specific PCB board which again is connected to the
motherboard.
Two different DUT boards have been designed which can be fitted with either a TO2xx plastic
package device or with TO3 metal package device.
On each individual DUT board, a limiting current serie resistance and a shunt resistor are mounted for
SEB pulse measurement.
To prevent the destructive burn-out of the DUT when the parasitic Bipolar Junction Transistor (BJT)
is triggered on by a strike, the DUT Drain is biased with a capacitor and a limiting current resistor
mounted on each DUT board. This is to limit the amount of energy available as well as the maximum
transient current value.
For testing at elevated temperature, each board is equipped with surface mount heating resistors plus a
CTN thermistor for temperature control.

V.3 TEST CONFIGURATION

Test set-up which has been used for the present test report, allows for the detection of both Single
Event Burn-out (SEB) and Single Event Gate Rupture (SEGR) effects
V.3.1 Single Event burnout (SEB)
SEB can be observed with the MOSFET in the off mode.
To get non destructive SEBs, selected test principle was to limit as much as possible the energy which
could flow into the DUT when the parasitic bipolar transistor enters second breakdown.
To achieve this goal, a resistor Rload (see Figure 3) in serie with the DUT drain limits the current
which can flow from the bias circuit (capacitor of 100nF, see Figure 3). In that case the only available
energy which can flow into the DUT without any external current limitation is the one stored into the
output DUT capacitance CDS.
The equivalent circuit when an SEB is triggered is shown in Figure 4.
Observation of VDS transients is done at Rshunt which form a resistor divider with Rload.

R LOAD

DUT C DS Scope

R SHUNT

Figure 4 – Equivalent circuit for SEB

including the parasitic capacitor of the MOSFET.

Actual resistor values for the test results presented in this report are shown in the Table 1 here below.

Symbol Value
Rload 1,6 kohms
RShunt 25 ohms

Table 1 – Test circuit resistor values

Events are counted thanks to a programmable threshold comparator of 50MHz bandwidth. Moreover
the monitoring of changes in the leakage dc current Idss will allow to check for eventual permanent
degradation.

Temperature effect may be evaluated as each DUT single board is provided with surface mount
heating resistors and a thermistor mounted on the back side of the board, which give the ability of
testing at elevated temperature.
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V.3.2 Single Event Gate Rupture (SEGR)

SEGR is a destructive effect which can be observed with the MOSFET in the off mode. Monitoring of
the IGSS current allows for the detection of a SEGR which corresponds to a permanent degradation
of the gate current.
This requires the measurement of µamp current amplitude under high impedance. Test board design is
compatible with the accelerator environment by the use of a complete guard ring.
Fluence is recorded during each run by monitoring with a modular counter, the TTL signal delivered
by an on-line Beam Detector. Information on the reached fluence at the time of an eventual SEGR
occurrence can then be retrieved by analysis of the run data.
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VI. TEST FACILITIES

VI.1 HEAVY IONS

Test at the cyclotron accelerator was performed at Université de Louvain (UCL) in Louvain la neuve
(Belgium) under HIREX Engineering responsibility.
VI.1.1 Beam Source
In collaboration with the European Space Agency (ESA), the needed equipment for single events
studies using heavy ions has been built and installed on the HIF beam line in the experimental hall of
Louvain-la-Neuve cyclotron.
CYCLONE is a multi particle, variable energy, cyclotron capable of accelerating protons (up to 75
MeV), alpha particles and heavy ions. For the heavy ions, the covered energy range is between 0.6
MeV/AMU and 27.5 MeV/AMU. For these ions, the maximal energy can be determined by the
formula :
110 Q2/M
where Q is the ion charge state, and M is the mass in Atomic Mass Units.

The heavy ions are produced in a double stage Electron Cyclotron Resonance (ECR) source. Such a
source allows to produce highly charged ions and ion "cocktails". These are composed of ions with
the same or very close M/Q ratios. The cocktail ions are injected in the cyclotron, accelerated at the
same time and extracted separately by a fine tuning of the magnetic field or a slight changing of the
RF frequency. This method is very convenient for a quick change of ion (in a few minutes) which is
equivalent to a LET variation.
VI.1.2 Beam Set-up

VI.1.2.1 Ion Beam Selection

The LET range was obtained by changing the ion species and incident energy and changing the angle
of incidence between the beam and the chip.
For each run, information on the beam characteristics is provided in Table 2.
VI.1.2.2 Flux Range
For each run, the averaged flux value is provided in Table 2.
VI.1.2.3 Particle Fluence Levels
Fluence level was comprised between few x10E4 and 5 x10E5 ions/cm²
VI.1.2.4 Dosimetry
The current UCL Cyclotron dosimetry system and procedures were used.
VI.1.2.5 Accumulated Total Dose
For each run, the computed equivalent cumulated doses received by the DUT sample, is provided
here below :
S/N Dose (rads)
#003 6,38 E 2
#004 4,22 E 2
VI.1.2.6 Test Temperature Range
All the tests performed were conducted at ambient temperature.
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VII. HEAVY IONS RESULTS

VII.1 BUK7508-55 TEST RESULTS

Krypton and Argon ions have been used with respective LETs of 34 and 14.1 MeV/mg/cm².
All test have been performed at ambient temperature.
Results per run are presented in Table 2.

Main outcomes can then be summarized as follows :

With Krypton (34 MeV/mg/cm²) and device biased with a fixed Gate Source Voltage (VGS) of –2V :
− Devices are SEB free when VDSS. does not exceed 40 % of maximum rating.
− Devices are not sensitive to SEGR (limit of the present test was 60% of VDSS)

With Argon (14.1 MeV/mg/cm²) and device biased with a fixed Gate Source Voltage (VGS) of –2V :
− Devices are SEB free when VDSS. does not exceed 55% of maximum rating.
− Devices are not sensitive to SEGR (limit of the present test was 70% of VDSS)

With Argon, when devices are tested at a VDSS rating (50%) such that no SEB is expected, the
maximum gate source voltage which can be applied without occurrence of SEGR event is -15V.

VII.2 TYPICAL SEB WAVEFORM

Figure 5 show a typical example obtained with a 100V transistor. In this figure, voltage variation
across Rshunt can be observed for a SEB pulse waveform at two rated VDS conditions, 60V and 70V.
The superposition of the simulation pulse (observed at Rshunt) which consist to turn on the DUT
allows to compare in each case, which part of the circuit is involved:

− In the SEB case, it can be seen that drain source voltage drops to zero in a very short time, then
once the energy stored in the output DUT capacitance is dissipated, the current limitation
provided by Rload allows for leaving the burn-out sustaining condition and DUT output
capacitance start to reload with a current limited by Rload.
The very high dV/dt (> 10 000V/µs)induce a peak current greater than 2 A, which discharge the
internal CDS DUT capacitor in a few ns.
− In the case of simulation pulse, once the DUT is switched on, the supply current which flows
into the DUT is limited by Rload.

60V rating

70V rating

Simulation pulse

100mV corresponds to 10V

Figure 5 – Example of non destructive SEBs observed

on a 100V transistor at 60V and 70V Vds ratings
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VIII. CONCLUSION

SEU test have been conducted on BUK7508-55 N-channel Power MOSFET from SGS Thomson
Semiconductor, using the heavy ions available at the European Heavy Ion Irradiation Facility (HIF),
at Cyclone, Université Catholique de Louvain, Belgium.

With Krypton (34 MeV/mg/cm²) and device biased with a fixed Gate Source Voltage (VGS) of –2V :
− Devices are SEB free when VDSS. does not exceed 40 % of maximum rating.
− Devices are not sensitive to SEGR (limit of the present test was 60% of VDSS)

With Argon (14.1 MeV/mg/cm²) and device biased with a fixed Gate Source Voltage (VGS) of –2V :
− Devices are SEB free when VDSS. does not exceed 55% of maximum rating.
− Devices are not sensitive to SEGR (limit of the present test was 70% of VDSS)

With Argon, when devices are tested at a VDSS rating (50%) such that no SEB is expected, the
maximum gate source voltage which can be applied without occurrence of SEGR event is -15V.
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Table 2 – Heavy Ion Test results on BUK7508-55 N-Channel Power MOSFET from Philips :
SEB SEGR
Run Date S/N Ion LETeff Angle T(°C) VDS VGS %VDSS Fluence Flux Time Nbr Sigma Nbr Sigma Comparator Equivalent
Threshold Pulse height
# - - (MeV/mg/cm²) (°) (°C) (V) (V) (%) (p/cm²) (p/cm²/s) (s) (-) cm² (-) cm² mV V

VGS=-2V, Ion Krypton, LET =34 MeV/mg/cm²

A116 09/01/99 4 84-Kr 34 0 25 22 -2 40% 101067 1148 88 0 -152 -10
A117 09/01/99 3 84-Kr 34 0 25 22 -2 40% 100279 1700 59 0 -152 -10
A114 09/01/99 4 84-Kr 34 0 25 27,5 -2 50% 100663 1736 58 295 2,93E-03 -152 -10
A118 09/01/99 3 84-Kr 34 0 25 27,5 -2 50% 101219 1511 67 36 3,56E-04 -152 -10
A115 09/01/99 4 84-Kr 34 0 25 33 -2 60% 22184 1305 17 1370 6,18E-02 -152 -10
A119 09/01/99 3 84-Kr 34 0 25 33 -2 60% 20950 1612 13 1147 5,47E-02 -152 -10
VGS=-2V, Ion Argon, LET =14,1 MeV/mg/cm²
A144 10/01/99 4 40-Ar 14,1 0 25 27,5 -2 50% 101400 3900 26 0 -152 -10
A150 10/01/99 3 40-Ar 14,1 0 25 27,5 -2 50% 103145 4688 22 0 -152 -10
A151 10/01/99 3 40-Ar 14,1 0 25 30 -2 55% 542720 5025 108 0 -152 -10
A145 10/01/99 4 40-Ar 14,1 0 25 33 -2 60% 103973 5472 19 277 2,66E-03 -152 -10
A152 10/01/99 3 40-Ar 14,1 0 25 33 -2 60% 102397 4876 21 28 2,73E-04 -152 -10
A146 10/01/99 4 40-Ar 14,1 0 25 38,5 -2 70% 30792 3849 8 674 2,19E-02 -152 -10
A153 10/01/99 3 40-Ar 14,1 0 25 38,5 -2 70% 33446 4778 7 463 1,38E-02 -152 -10
VGS=-5V, Ion Argon, LET =14,1 MeV/mg/cm²
A147 10/01/99 4 40-Ar 14,1 0 25 27,5 -5 50% 502532 4527 111 0 -152 -10
VGS=-10V, Ion Argon, LET =14,1 MeV/mg/cm²
A148 10/01/99 4 40-Ar 14,1 0 25 27,5 -10 50% 501207 4556 110 0 -152 -10
A154 10/01/99 3 40-Ar 14,1 0 25 27,5 -10 50% 503076 3699 136 0 -152 -10
VGS=-12,5V, Ion Argon, LET =14,1 MeV/mg/cm²
A155 10/01/99 3 40-Ar 14,1 0 25 27,5 -12,5 50% 504140 3848 131 0 -152 -10
VGS=-15V, Ion Argon, LET =14,1 MeV/mg/cm²
A149 10/01/99 4 40-Ar 14,1 0 25 27,5 -15 50% 92071 7673 12 0 -152 -10
A156 10/01/99 3 40-Ar 14,1 0 25 27,5 -15 50% 502920 3309 152 0 -152 -10