Introduction to Digital Logic

EE 101
Course Syllabus - Spring 2014
University of Southern California
Welcome to INTRODUCTION TO DIGITAL LOGIC, a course designed to
introduce digital logic design basics which are fundamental to all computers
and other digital hardware. Number systems, Boolean algebra, and analysis
and design of combinational and sequential circuits are covered. Practical
design techniques along with theory and principles will be taught. While
focus will be put on paper-pencil design techniques, basic computer aided
design tools and FPGAs will be introduced in several lab modules.
Course Administration
Prerequisite: None.
Credit: 3 units.
Lectures: Mondays and Wednesdays 14:00 - 15:20 in VHE205.
Tuesdays and Thursdays 12:00 - 13:20 in VHE205.
Discussions: Fridays 10:00 - 11:50 or
14:00 - 15:50 or 16:00 - 17:50 in VHE205.
Quizzes: Fridays 12:00 - 13:50 in TBA.
Students should enroll in a lecture section, a discussion section and the quiz
section.
Website: http://blackboard.usc.edu
The last day to drop the class without a mark of W is 31 January, and the
last day to drop the class with a mark of W is 11 April. Incomplete grades
(IN) are rarely assigned. The IN grade may be justied only in exceptional
cases.
The EE 101 grade is based on the following components:
Midterm Exam (28 Mar 2014 12:00 - 13:50) 25%
Homeworks (due on due date at the beginning of lecture) 10%
Labs 20%
Two Quizzes 20%
Final Exam 25%
Mo/We Class: 12 May 2014, 14:00 - 16:00
Tu/Th Class: 14 May 2014, 14:00 - 16:00
All exams will be closed book. There will be no calculators allowed, just bring
a few pencils and an eraser. You must show how you arrived at your answers
to receive full credit. Any cheating may result in an F in the course and will
be referred to Student Aairs for other penalties. Make up exams will only
be given for valid medical or family emergency excuses (proof required).
Homeworks are your key to learning. Only by doing problems on your own
will you develop the logic skills and understanding to perform well on exams.
You are expected to present your work with your own creative solutions.
Experience has shown that those students who put in the eort on
these homeworks, struggled with problems, asking questions when
they did not understand a porblem did the best in this course.
Homework should be stapled together at the beginning of class. All circuit
drawings should be neat. There will be approximately 8 homework assign-
ments which are to be turned in at the beginning of class on the due date.
Late homework will be accepted with a 15% deduction per day.
Homework will not be accepted after solutions are posted (2 days
after the due date.) You will be expected to have read the listed sections of
the class notes and textbook before each lecture.
Textbook
Required:
Class Notes available at the Bookstore.
Wakerly, J. F., Digital Design Principles and Practices, 4th Ed., New Jersey:
Prentice Hall, 2005.
Discussion/Lab
Discussion sections will be a mix of review/example problems and small lab
exercises. Lab exercises will consist of small logic designs using a digital
training board, FPGA boards, and logic simulators. These lab exercises
are meant to give students an opportunity to work with actual hardware
and provide concrete examples to the pencil and paper designs discussed in
lecture. FPGA boards will be checked out to every pair of students. You are
responsible for keeping these safe and undamaged. Lost or damaged boards
will need to be paid for by the student(s) to whom it was checked out.
Quizzes
There will be 2 quizzes given throughout the semester during the Quiz sec-
tion. Quiz 1 and Quiz 2 dates are shown on the schedule. These are meant to
track the level of understanding of the class material. Make-up quizzes will
only be given for valid medical or family emergency excuses (proof required)
or if arranged ahead of time with the instructor.
Instructor Information
Satsuki Takahashi
Oce: PHE 506
Tel: (213) 740 - 0194
Email: satsukit@usc.edu
Oce Hours: Tuesdays and Thursdays, 10:00 - 11:30
Teaching Assistants
Rebecca Lee
leerk@usc.edu
Oce Hours: Mondays 16:00-18:00
Location: VHE205
Graders
Hari Prasanth Govindaraju
hgovinda@usc.edu
Shobhit Agrawal
shobhita@usc.edu
Statement for Students with Disabilities
Any student requesting academic accommodations based on a disability is re-
quired to register with Disability Services and Programs (DSP) each semester.
A letter of verication for approved accommodations can be obtained from
DSP. Please be sure the letter is delivered to me (or to a TA) as early in the
semester as possible. DSP is located in STU 301 and is open 8:30 a.m. -
5:00 p.m., Monday through Friday. The phone number for DSP is (213) 740
- 0776.
Statement on Academic Integrity
USC seeks to maintain an optimal learning environment. General principles
of academic honesty include the concept of respect for the intellectual prop-
erty of others, the expectation that individual work will be submitted unless
otherwise allowed by an instructor, and the obligations both to protect ones
own academic work from misuse by others as well as to avoid using anothers
work as ones own. All students are expected to understand and abide by these
principles. Scampus, the Student Guidebook, contains the Student Conduct
Code in Section 11.00, while the recommended sanctions are located in Ap-
pendix A: http://www.usc.edu/dept/publications/SCAMPUS/gov/. Stu-
dents will be referred to the Oce of Student Judicial Aairs and Community
Standards for further review, should there be any suspicion of academic dis-
honesty. The Review process can be found at: http://www.usc.edu/student-
aairs/SJACS/.


EE 101 Tentative Schedule and Topics
Wk. Readings
1 Analog vs. Digital
Positional # Systems
Logic Functions &
Visualization
Logic Function Examples
Number Conversion
Binary, Octal, Hex
Binary Codes: ASCII, BCD
Binary Arithmetic
Wakerly: Ch. 1, 2.1-2.4,
2.10, 2.12
Notes: 1-28
2 Signed Magnitude
2s complement System
Sign Extension


The Basics: Logic
Functions & Representation
Minterms / Maxterms
Canonical Sums/Products
Wakerly: 2.5,4.1
Notes: 29-51
3 The Tools: Boolean Algebra
(T1-T5)
Boolean Algebra (T6-T11)
DeMorgans Theorem
Circuit Analysis
Waveforms (maybe timing)
Conversion to Canonical
Form
Wakerly: 4.1,4.2
Notes: 51-82
4 Design Goals
Circuit Design, Manipulations,
2-Level Implementations
Circuit Synthesis
Canonical Implementation
Simplified 2-Level Impl.
Karnaugh Maps
Dont Cares
Decoders & Muxes & ROMs

Wakerly: 4.3, 9.1
Notes: 83-125
5 More Circuit Design

Decoders (Enables, Active
Levels, Composition)
Wakerly: 6.1, 6.4
Notes: 126-140
6 Encoders
Multiplexers (Composition,
Width)
Multiplexers
Demultiplexers
Adders
Wakerly: 6.5, 6.7, 6.10
Notes: 140-156
Quiz 1: 21/Feb/2014
7 Adders
Multipliers

Addition/Subtraction
Overflow

Wakerly: 6.10-6.11, 2.5-
2.6
Notes: 157-182
8 Comparators
XORs & Parity

Sequential Logic
Bistables

Wakerly: 6.9, 6.8,6.6,7.1
Notes: 183-195
9 Latches
Flip-Flops
Master/Slave FFs

Wakerly: 7.1, 7.2
Notes: 195-222
10 Spring Recess
11 State Machine Overview
State Machine Analysis

State Machine Design
State Machine Analysis
Review
Wakerly: 7.2-7.3
Notes: 223-233
Midterm 28/Mar/2014
12 State Machine Design
Registers
Registers W/ Enables
Counters
Digital System Design

Wakerly: 7.3-7.5
Notes: 234-255
13 Datapath & ALU design

System Design
(Vending Machine)

Wakerly: 8.2, 8.4, 8.5
Notes: 255-280
Quiz 2: 11/Apr/2014
14 CPU Design CPU Design
15 Final Review Final Review
16 Final Review Final Review
Final Exam (Cumulative): Please see Final Schedule


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