A T M E L A P P L I C A T I O N S Number 6 Winter 2006

R
Everywhere You Are
In This Issue:
Using ARM Core- based Flash
MCUs as a Platform for Custom
Systems- on- Chip
The Explosive World of Serial Flash
Networked Networks and
Embedded Microcontroller
Architectures
Polybot Board: A Robot
Controller Board Using the Atmel
ATMega32
Integration and Low Current
Consumption: A Reality Today for
License- free Wireless Applications
SiGe BiCMOS or RF CMOS for
Your Next Wireless Application?
Lighting: Ballast Controller
Combined with RISC Processor
Yields an Efficient Lamp
Automotive Bus Systems
Atmels Complete Chipset for
DAB Reception in Automotive
Environments
Areascan Cameras: How to
Choose Between Global and
Rolling Shutter
Simple VGA/ Video Adapter Using
the Atmel AVR
A 10- bit 2.2 Gsps ADC Operating
Over First and Second Nyquist Zones
Graham Turner, Vi ce Presi dent
and General Manager,
Mi crocont rol l ers Busi ness Uni t ,
At mel
www. at mel. com
page 1
Int roduct ion
Welcome to Atmel Applications Journal Volume 6.
I would like to thank all of you for your dedication to the AVR microcontroller family. 2005 has been anoth-
er great year for us and the AVR product family has enjoyed high double- digit growth, both in revenue and
units shipped. Design wins continue to go from strength to strength and we are all very excited about our
prospects for 2006.
In 2006 we will celebrate the 10th anniversary of the AVR. It all started in 1996 in Norway and with the
continuous efforts of everyone who has joined the team, we have grown the AVR to be the most exciting
8- bit microcontroller family in the market place.
In 2005 we increased the family of products by 24 to over 50. We entered the automotive market with the
AVR and already have received great customer acceptance for these products. We have also introduced
products for motor control applications and are able to offer solutions for the PC fan market below 50
cents. The TinyAVR family has been expanded with several new parts including 14- pin devices, and final-
ly, we have introduced many parts with increased pin counts and larger memories.
Looking forward to 2006, we have many exciting new products to announce. The first of which is as a result
of our considerable R&D efforts to set new standards in the power consumption of our microcontrollers.
We will launch a new range of ultra low power products which will significantly extend the lifetime of the
battery in the system. This new development combined with the efficiency of our AVR core will allow us to
continue as the leader in the 8- bit microcontroller market.
Along with our great products we have continued our advances in software tools and hardware develop-
ment systems. There are hundreds of thousands of AVR Studio users out there who will continue to bene-
fit from our high quality, low- cost tools. The latest AVR Studio version has enabled third party suppliers to
plug their software directly into it for complete integration, which will allow for increases in functionality in
debug software and hardware designs. Our continued focus on the AVR Studio, combined with our low-
cost starter kits and emulators will ensure that we have the best offering in the market.
In 2006 we will further develop our plan to reduce our lead- times for these popular products so that our
customers can get their hands on the AVR quicker than before.
I would like to thank you all for your continued support of the AVR products. We will continue to bring you
the products that you need to develop your own exciting and world- beating products.
www. at mel. com
page 2
A T M E L A P P L I C A T I O N S Number 6 Winter 2006
T A B L E O F C O N T E N T S
Introduction Graham Turner, At mel
Automotive Bus Systems
by Markus Schmid, At mel
The Explosive World of
Serial Flash
by Richard De Caro, At mel
Using ARMCore-based Flash
MCUs as a Platformfor Custom
Systems-on-Chip
by Pet er Bishop, At mel
Atmel News New Product Releases
page 37
R
page 10
Integration and LowCurrent
Consumption: A Reality Today for
License-free Wireless Applications
by Eric Mercier, At mel
Networked Networks and
Embedded Microcontroller
Architectures
by Jacko Wilbrink, Dany Nat ivel and
Tim Morin, At mel
Lighting: Ballast Controller
Combined with RISCProcessor
Yields an Efficient Lamp
by Jean-Florent Helie, Elect ronique Magazine
SiGe BiCMOSor RF CMOSfor
Your Next Wireless Application?
by David Hess, At mel
1
3
8
13
16
20
22
25
27
29
33
37
40
46
Areascan Cameras: Howto
Choose Between Global and
Rolling Shutter
by Jacques Lecont e, At mel
A 10-bit 2.2 Gsps ADCOperating
Over First and Second Nyquist Zones
by Francois Bore, Sandrine Bruel and Marc Wingender
Everywhere You Are

page 32
page 41
Polybot Board: A Robot
Controller Board Using the Atmel
ATMega32
by Dr. John Seng, Cal Poly St at e Universit y
Simple VGA/ Video Adapter
Using the Atmel AVR
by Ibragimov Maksim, Developer, Russia
page 20
Atmels Complete Chipset for
DABReception in Automotive
Environments
by Dr. Mart in Alles, At mel
www. at mel. com
page 3
BCDMOS Fail-saf e Syst em I C, ATA6814,
Designed f or Saf et y-crit ical
Aut omot ive Applicat ions
Atmel has released a new monolithically integrated
fail- safe system IC, the ATA6814, manufactured
using Atmel' s state- of- the- art 0.8- m BCDMOS
technology. With its built- in driver functions and
complete monitoring system, the ATA6814 is a
unique solution beneficial for all safety- relevant
automotive electronics, such as DC motor controls
that can be found in electric parking brake systems,
power steering, chassis and powertrains. The
ATA6814 combines various functions into one sin-
gle IC, an improvement over competing solutions
requiring the addition of several standard compo-
nents such as stand- alone voltage regulators and
watchdogs. This leads to significant board space
reduction and smaller, more cost- efficient designs.
The ATA6814 is ideally suited to safety- critical auto-
motive applications, since the watchdog is com-
pletely separate from the system microcontroller
and operates with its own dedicated oscillator,
which in turn is monitored by a second oscillator.
The fail- safe system IC ATA6814 is highly integrat-
ed, including voltage regulators, driver stages, an
SPI interface, as well as watchdog and monitoring
functional blocks. Two separate voltage regulators
and band gaps enable high flexibility, while still
maintaining a high safety level, thanks to the mutu-
al monitoring. Power consumption reduction down
At mel News: More informat ion on t he product s and services in t hese art icles can be found at www.at mel.com
to 80 uA in standby mode is achieved since one of
the voltage regulators can be switched off. The fully
integrated, 250 mA low- side relay drivers do not
need any additional external circuitry and thus help
to further save cost and space on the PC board.
The independent watchdog circuitry the heart of
the fail- safe concept monitors the microcon-
troller' s operation. In addition, the monitoring func-
tion covers the battery voltage, all internally gener-
ated voltages, and the chip temperature in two
stages, and it can disable the different IC blocks.
Samples of the new fail- safe system IC ATA6814 in
RoHS- compatible QFN48 (7 mm x 7 mm) packages
are available now. Pricing starts at US $2.70 (10 k)
Product information on Atmel' s new BCDMOS Fail-
safe System IC ATA6814 may be retrieved at:
http:/ / www.atmel.com/ dyn/ products/ product_card.
asp?part_id= 3770
BCDMOS = Mixed- signal technology with Bipolar, CMOS and
DMOS components
DC = Direct Current
PC board = Printed Circuit board
SPI = Serial Peripheral Interface
RoHS = Restriction of the Use of Certain Hazardous Substances
I ndust rys First Mult iple
Smart Card Reader
I nt erf ace I C f or POS
and Healt h Card Reader
The AT83C26 is the industrys first multiple analog
smart card interface which can physically handle up to
5 smart cards. It powers the smart cards with the
appropriate supply voltage and enables data transfer
between the host controller and the smart cards.
System designers can use a single chip to develop
readers requiring multiple cards, thus reducing system
size and cost. The AT83C26 is the ideal solution for
Point of Sales (POS) Terminals that typically involve one
user card and up to 4 SAM cards, and Health Card
Readers that require 2 user cards and 1 SAM card.
The device can interface with any host controller fea-
turing an ISO7816 UART such as Atmels ARM7, ARM9
and ARM SecurCore (AT91SO100) devices.
Featuring two DC/ DC converters and low drop out reg-
ulators to power independently each smart card, the
AT83C26 is compliant with the EMV and ISO7816
standards.
It is clear that the need to handle multiple smart cards
during various forms of secure transaction will become
the norm in the future and the AT83C26 has already
been adopted by a major POS manufacturer for its new
applications, said Manish Vadher, Marketing Director
for Microcontroller products with Atmel.
Samples are available now in VQFP48 and QFN48
packages. Full production will start in January 2006
with pricing starting at $1.95 each for 10K units.
Atmel' s AT83C26 product information may be retrieved
at: http:/ / www.atmel.com/ dyn/ products/ product_card.
asp?PN= AT83C26
www. at mel. com
page 4
Highly I nt egrat ed RoHS-compliant SiGe Front -end I C
f or Privat e Mobile Radios (PMR)
A new Silicon Germanium (SiGe) based front- end IC,
ATR0981, from Atmel, makes the new device easy to
use, highly efficient, and extremely flexible The use of
SiGe technology, the simple yet flexible application cir-
cuit, and the devices wide operating frequency range
(300 MHz to 500 MHz) make possible a broad range of
applications, from hand- held family radios (private
mobile radios, PMR) to meter readers. It is easy to
design applications with low external component
counts using this front- end device because of its high
level of integration, including a very efficient power
amplifier (PA) and a low- noise amplifier (LNA) for the
receive path.
In contrast to most competitors family- radio front- end
solutions, which are designed as discrete solutions, this
device is an integrated circuit manufactured using
Atmels innovative Silicon Germanium (SiGe) technolo-
gy, providing many advantages over discrete or non-
SiGe solutions. SiGe ensures high reliability and robust-
ness due to low temperature dependency; plus, the
cost savings of using the ATR0981 IC go beyond sim-
ply the component cost lower component count also
equals decreased design effort, failure risk and assem-
bly cost.
What is more, SiGe offers increased efficiency the
PAE value is as high as 55%, typically, helping to
ensure the low current consumption of the PA. The
overall current consumption can be reduced even fur-
ther by shutting down the PA, providing extended bat-
tery life. The output power can reach 29 dBm and the
PA has a power gain of 34 dB, controllable within a
range of 3 dB. ATR0981s LNA offers excellent noise
performance, with a noise figure of 1.5 dB and a power
gain of 19 dB. Samples of the ATR0981 are available
now in PSSO20 packages, which are both Pb- free and
green. Atmel is the one of very few suppliers offering
this type of product as an RoHS- compliant device.
Pricing for the ATR0981 starts at 1.20 US$ in quanti-
ties of 10k.
Atmels front- end IC ATR0981 product information may
be retrieved at: http:/ / www.atmel.com/ dyn/ products/
product_card.asp?part_id= 3765
LNA = Low Noise Amplifier
PA = Power Amplifier
PAE = Power Added Efficiency
PMR = Private Mobile Radio
RoHS = Restriction of the Use of Certain Hazardous Substances
SiGe = Silicon Germanium
At mel' s FingerChip Feat ured in FingerGear' s
Comput er-On-a-St ick Biomet ric Edit ion
Atmel, and FingerGear, the consumer products divi-
sion of biometrics leader Bionopoly LLC, announced
today the release of its groundbreaking Bio
Computer- On- a- Stick USB Flash Drive now with
fingerprint security. The Computer- On- a- Stick is the
world' s first bootable USB flash drive. The OS and all
Desktop Software applications come preinstalled
and occupy as little as 200Mb of flash memory. The
device also features Atmel' s FingerChip

sensor for
convenient and accurate one- swipe secure data
access, and a large font LCD display for the ultimate
user- friendly experience.
The FingerGear Computer- On- a- Stick also includes
an Office Productivity Suite, along with many of the
most commonly used home and office applications.
The Office Suite, developed by OpenOffice.org, is
compatible with Microsoft Office applications,
including Word , Excel

, PowerPoint

, and
Outlook

. The Computer- On- a- Stick also bundles the

increasingly popular Mozilla FireFox

web browser,
now at a 25% market share*, as well as a PDF
Creator, a zip compression utility, and an Instant
Messenger which communicates with Yahoo

IM,
MSN

Messenger, AIM, and Napster

, among others.
The Bio Computer- On- a- Stick includes a USB 2.0
extension cable, a neck lanyard, and a mini boot CD.
The device is bootable from any PC using an x86
processor, which can be found on nearly every
Windows and Linux desktop shipped over the past 5
years. Recent PCs allow the user to configure their
system to boot directly from a USB Flash Drive with-
out the need for a CD. The Computer- On- a- Stick
Standard and Biometric Editions are currently in
stock and shipping now. The Computer- On- a- Stick
pricing starts at only $99, and the Biometric Edition
starts at $149.
The USB standard has experienced one of the
fastest adoption rates in the history of consumer
electronics, said Bionopoly C.E.O. Jon Louis, The
next wave of USB devices, led by FingerGear, now
allows you to carry not only your files, but also your
entire Desktop Software Environment as well, essen-
tially replacing your hard drive. The Computer- On- a-
Stick, and now the Biometric edition, offer the ulti-
mate combination of desktop portability and
advanced security.
For further information on Atmel' s FingerChip

, go
to: http:/ / www.atmel.com/ products/ Biometrics/ .
*According to W3Schools.com.
www. at mel. com
page 5
Cont act less Credit Card Market s Target ed
wit h SecureAVR C
Atmels secureAVR 8- / 16- bit RISC microcontroller
provides 16- bit CPU performance while offering
state of the art security features. It is now available
as a contactless only product, optimizing perform-
ance with smaller die size for price sensitive con-
tactless applications. These features include
DFA/ DPA/ SPA resistant, DES/ TDES processor, true
RNG (Random Number Generator), firewalls, and
environmental protections. The AT90SC6404RFT,
comprising of 64K ROM, 4K EEPROM and 1.2K RAM
is a derivative of the popular AT90SC12872RCFT
dual- interface chip targeted at e- Passport and ID
applications, but having only a single RF ISO- 14443
contactless interface. It is ideally suited to the
emerging USA Contactless Card Payment market
based on the standard Credit/ Debit magnetic stripe
profile offerings from American Express
(ExpressPay) , MasterCard

(PayPass ) and Visa

.
The ROM/ EEPROM mem-
ory sizes provide sufficient
capacity to allow addition-
al applications, such as
Loyalty or Mass Transit or
alternatively as a Physical
or Logical Access contact-
less card.
Ian Duthie, Atmels Smart
Card IC Marketing
Manager, commented
The success of our first
PayPass product, which
established Atmel as a
leading IC vendor in the
USA Contactless Card
Payment market, convinced us of the potential
growth and need for further product development to
serve the USA payment industry. The customer inter-
est in the AT90SC6404RFT bears this out; we are
sampling now and planning volume production
capability for 1Q 2006. Preliminary estimates from
our customers indicate that the USA Contactless
Card Payment market will grow from several million
cards this year to 25M+ next year and 40M+ by end
2007.
For further information on Atmels secureAVR
family: http:/ / www.atmel.com/ products/ Secure AVR
At mel Achieves Higher Resolut ions wit h
2.5M Pixel CMOS I ndust rial Camera
Atmel has announced the introduction of a new mem-
ber of the ATMOS area scan CMOS camera family
dedicated to industrial machine- vision applications.
The additional members ATMOS 2M30 and ATMOS
2M60 are fast CMOS area scan cameras able to work
in 8, 10 or 12 bits that offers an excellent dynamic
range. Specific CommCam software, also developed by
Atmel, renders camera configuration easy.
ATMOS 2M30 and 2M60 are composed of a 2.5 mil-
lion pixels CMOS sensor featuring high sensitivity and
high quality even at maximal speed. The region of
interest (R.O.I.) allows the end- user to implement infi-
nite resolutions and to increase frame rate such as: 48
fps full resolution at 2.5M pixels, 60 fps at 2M pixels
and 160 fps in VGA format (640X480 pixels) for the
2M60 model (half- speed for the 2M30). Furthermore,
the ATMOS 2M30 and ATMOS 2M60 cameras com-
prises an electronic shutter and Camera Link

inter-
face suitable for those wanting to upgrade from analog
to digital modes while offering cost effective solutions.
The two ATMOS cameras are delivered in a 44 mm
square section design with a C- mount adapter, among
the smallest in the market. The performance, versatili-
ty and adaptability of the compact mechanical body
give OEM and integrators an optimum solution to space
saving in systems. It also allows an implementation into
multiple configurations. The camera can be uploaded
remotely.
With these new members, ATMOS camera family
offers an exciting alternative to CCD base cameras,
said Christophe Robinet, Camera Marketing Manager
of Atmels Professional Imaging. These cameras allow
for customized solutions on request.
The ATMOS 2M30 and 2M60 cameras are at sample
stage now and will enter their production phase in April
2006. Pricing starts at $2500 and $3000 respectively
for a quantity of 100 pieces.
Atmels product ATMOS 2M30 may be retrieved at:
http:/ / atmel.com/ dyn/ products/ product_card.asp?part
_id= 3802
Atmels product ATMOS 2M60 may be retrieved at:
http:/ / atmel.com/ dyn/ products/ product_card.asp?part
_id= 3803
For further information on Atmels Camera products, go
to: http:/ / atmel.com/ products/ Cameras/
www. at mel. com
page 6
New Generat ion of Secure Microcont rollers Released f or Trust ed
Elect ronic Transact ion Terminals
The AT91SO100, a new high- end 32- bit secure
microcontroller for electronic transaction terminals
improves security and level of integration for POS,
PINPads and health card reader applications.
Based on the ARM

SecurCore SC100 CPU core,

the AT91SO100 achieves an outstanding level of
integration. This chip featuring 256 Kbytes EEPROM
for program and data, 32 Kbytes ROM and 100
Kbytes RAM, provides also USB, SPI, USARTs, I/ O
ports, magnetic stripe card interfaces plus a secured
external bus interface. In addition, Atmel offers a
smart card interface integration through a single
package solution in BGA 256 embedding two chips,
the AT91SO100 and the AT83C26, which physically
interface with up to 5 smart cards.
Herve Roche, Atmels Smart Card IC Marketing
Manager stated, To comply with EMV standard,
VISA

PED and others, terminals and readers indus-

try require higher security and more performance.
Atmel leverages its design expertise in highly secure
smart card ICs by providing to its customers the
most efficient secure product for EMV migration.
The AT91SO100 hosts strong security mechanics,
including intrusion sensors, dedicated hardware pro-
tections, real- time clock and battery backup. It also
has an impressive set of cryptography features,
hardware DES/ TDES, hardware AES, hardware SHA-
n, hardware cryptography accelerator for asymmet-
ric algorithms (RSA, Elliptic curves, Key generation)
and a true random number generator. Implemented
in 0.18- micron embedded technology, this secure
chip runs a RSA 2048- bit decryption in less than
150 ms. It is targeted to achieve Common Criteria
EAL4+ certification. Complete sets of documenta-
tion and development tools are available.
For further information on Atmels ARM
SecurCore family, go to: http:/ / www.atmel.com/
products/ SecureARM
Avnet , At mel Supercharge Bat t ery Technology I nc.' s Design Process
When Battery Technology Inc. (aka Battery Tech) began
working on its next- generation of batteries, it enlisted
engineering aid from the silicon chip expertise of Avnet
Electronics Marketing, a division of Avnet, Inc.
(NYSE:AVT) and Atmel

Corporation (Nasdaq: ATML).

Together, Avnet and Atmel field application engineers
(FAEs), in conjuction with Battery Techs internal engi-
neering department, created a new line of batteries for
laptop computers that rely on Atmels AVR

line of
microcontrollers. The AVR features an award winning
RISC- based processor core and is the worlds highest
performance, low power 8- bit Flash memory micro-
controller.
With help from Avnet and Atmel, we brought engi-
neering in- house and now we control our own design
destiny, says Andy Tong, Battery Tech, vice president
of research and development.
The collaborative group effort also resulted in a design
that uses fewer components, has a smaller form fac-
tor, and features improved performance. We created a
total team effort between Atmel, Avnet and Battery
Tech, says Andy Barbosa, Avnet account manager.
Rodney McCray, Atmels field application engineer,
added, All of this was done to make Battery Tech more
competitive. We looked at everything to help them
become more competitive from performance and
power consumption to cost and flexibility.
Tapping Avnets supply chain expertise, Battery Tech
was also able to speed the products time- to- market.
By using Avnets Point of Use Replenishment System
(POURS), Battery Tech is assured of the right amount of
inventory at exactly the time its needed on the pro-
duction floor. Today, Battery Tech has plans to migrate
additional products to the same microcontroller plat-
form, and it continues to rely on its relationship with
Avnet and Atmel in bringing new products to life.
STAFF BOX
Publisher:
Glenn ImObersteg
Gl enn@convergencepromoti ons.com
Technical Editor:
Markus Levy
Markus@convergencepromoti ons.com
Sales Manager:
Mike Miller
Mi ke@convergencepromoti ons.com
Production Manager:
Dave Ramos
dbyd@garl i c.com
Thi s i ssue of the Atmel Appl i cati ons Journal i s publ i shed by
Convergence Promoti ons. No porti on of thi s publ i cati on may be
reproduced i n part or i n whol e wi thout express permi ssi on, i n wri t-
i ng, from the publ i sher. The contents of thi s publ i cati on are
Copyri ght Atmel Corporati on 2006. Al l ri ghts reserved. Atmel

,
l ogo and combi nati ons thereof are regi stered trademarks, and
Everywhere You Are i s the trademark of Atmel Corporati on or i ts
subsi di ari es. Other terms and product names may be trademarks of
others. Al l product names, speci fi cati ons, pri ces and other i nforma-
ti on are subj ect to change wi thout noti ce. The publ i sher takes no
responsi bi l i ty for fal se or mi sl eadi ng i nformati on or errors or omi s-
si ons. Any comments may be addressed to the publ i sher, Gl enn
ImObersteg at gl enn@convergencepromoti ons.com,
or +1 (925) 516- 6227.
At mel' s New 200 MI PS ARM9 MCU Draws Only 2.5 A St andby, and
350 A/ MHz at Maximum Perf ormance
Atmel has announced the industrys first ultra low-
power, deterministic microcontroller, the AT91SAM
9261 Smart ARM Microcontroller (SAM), based on
the ARM926EJ- S processor.
Targeted at low power, high throughput wireless
handheld applications, such as wireless PoS devices,
the AT91SAM9261 consumes only 2.5 A
in standby mode. Operating
at 500 Hz it draws 400
A. In industrial temper-
ature range, its current
consumption at 200 MIPS
with all peripherals turned
on is just 65 mA. The
AT91SAM9261' s through-
put and its extended instruction set with DSP exten-
sions allow complex DSP functions, such as biomet-
rics, voice recognition, software modems, or encryp-
tion/ decryption algorithms like RSA, to be executed
very quickly in burst mode, so the system can be shut
down much of the time.
In a typical PoS application with a four- hour battery
life, such as a rental car- return processing module,
these new MCUs can extend battery life by as much
as a factor of 4 to 16 hours.
Packaging and Availability: The AT91SAM9261 is
available now in a 217- ball LFBGA RoHS- compliant
package and is priced at sub $10 in high volume.
Atmels AT91SAM9261 product information is avail-
able at http:/ / www.atmel.com/ products/ AT91/ or by
email from at91support@atmel.com.
At mel I nt roduces First Power Management I C
f or Handset Add-on Modules
Add- on modules are a key factor in the marketing
strategy of handset manufacturers. Mobile phones,
music players, digital still cameras, PDAs and multi-
media devices can add GSM/ GPRS, 3G, WLAN,
Bluetooth

, GPS, image capture, music playback and

other features by simply adding plug- in modules to
existing devices. These modules require a specific reg-
ulated power supply interface from the main supply.
Manufactured using Atmels low- cost mainstream
CMOS process, the AT73C211 is designed to supply
the digital, analog, interface, and, if required, the Radio
Frequency (RF) and backup sections of add- on mod-
ules used in hand- held products such as PDAs and
mobile phones. The AT73C211 integrates a high- per-
formance DC to DC converter with integrated switches
to supply digital cores at 1.9V, delivering up to 300mA.
Additionally, three high- current Low Drop Out (LDO) lin-
ear voltage regulators supply analog, interface andRF
portions of typical multimedia or wireless communica-
tion applications, with voltage from 2.7 to 2.8V and
current up to 130 mA. An ultra low- power LDO and a
back- up battery or supercap charger are also provided
to supply the Real- Time Clock (RTC) section that is
usually present inside the application processor core.
This achieves the lowest current consumption possible
in standby mode. A reset generator and a voltage
supervision function complete the integration of the
AT73C211.
Our AT73C211 is a first in its market, said Michele
Casetta, Marketing Manager for Atmels Power
Management and Audio Analog Companion PMAAC
Product Line. The integration of various power supply
www. at mel. com
page 7
channels and an ultra- low- power backup supply chan-
nel with a power controller circuit for startup and shut-
down, it makes it an ideal companion for every appli-
cation where power consumption, cost and space are
key.
Atmel offers the AT73C211 in a 5 x 5 mm, 25- ball
ultra- thin BGA package in order to satisfy portable
device manufacturers minimum space requirements.
It is available now mounted on a reference design
board or as engineering samples. Production quantities
are also available, with a reference price below $1.00
in large quantities.
Atmels Power Management product information may
be retrieved at: http:/ / www.atmel.com/ products/
PowerManage/
For more information about AT73C211 go to:
http:/ / www.atmel.com/ dyn/ products/ datasheets.asp?f
amily_id= 639
By: Peter Bishop, Communications Manager,
Atmel Rousset
The Big Picture: System- on- Chip Challenges
There is a consensus in the semiconductor industry
that the challenges facing designers of systems- on-
chip (SoC) are electronic system level (ESL) design,
design for manufacturing (DFM)/ design for test (DFT),
power management, and the cost, time and risk asso-
ciated with SoC development. As a consequence of
these challenges, there has been a decrease in recent
years in the number of systems- on- chip being
designed, offset by the increase in revenue derived
from a successful system- on- chip.
Electronic System Level Design
A system- on- chip is almost always built around one or
more microcontroller(s) (MCUs), digital signal process-
ing (DSP) core(s) or other software programmable ele-
ment. Accordingly, the software that drives the system
must be developed concurrently with the hardware,
and is at least as costly and time- consuming.
Numerous attempts are being made to develop a uni-
fied language to specify the entire SoC (both hardware
and software) at the outset of the design cycle. These
electronic system level (ESL) design projects are most-
ly based on System Verilog or System C, but to date
neither has been widely adopted in practice. In reality
most SoC hardware and software is developed concur-
rently but separately. This causes a number of prob-
lems, originating from the differences in culture, train-
ing and methodology between hardware and software
developers. Combined hardware/ software testing only
occurs late in the design cycle, and the hardware/ soft-
ware interface is a major source of errors. In addition
architectural limitations or design errors are often
detected late in the cycle.
www. at mel. com
page 8
Using ARM Core-based Flash MCUs as a
Plat f orm f or Cust om Syst ems-on-Chip
ADVANCES IN PROCESS TECHNOLOGY
ARE MAKING IT POSSIBLE TO FABRICATE
SYSTEMS- ON- CHIP (SOCS) CONTAINING
HUNDREDS OF MILLIONS OF TRANSIS-
TORS OPERATING AT GIGAHERTZ CLOCK
FREQUENCIES IN A FEW TENS OF SQUARE
MILLIMETERS. HOWEVER, THESE SAME
ADVANCES ARE MAKING IT INCREASINGLY
DIFFICULT TO DEVELOP SUCH COMPLEX
SOCS ECONOMICALLY IN AN ACCEPTABLE
TIMESCALE, AND MAKING POWER
CONSUMPTION A CRITICAL ISSUE. YIELD
AND TESTABILITY ISSUES ARE BECOMING
A MAJOR CONCERN. SOCS INCORPORATE
PROGRAMMABLE ELEMENTS
(MICROCONTROLLERS AND DIGITAL
SIGNAL PROCESSORS) MAKING THEIR
SOFTWARE CONTENT AS EXPENSIVE
AND TIME- CONSUMING TO DEVELOP
AS THEIR HARDWARE.
USING A FLASH MCU BASED ON THE
INDUSTRY- STANDARD ARM PROCESSOR
AS A PLATFORM REPRESENTS A
PRACTICAL APPROACH TO SOC
DEVELOPMENT THAT ADDRESSES ALL
THESE ISSUES. INCORPORATING AN FPGA
(FIELD PROGRAMMABLE GATE ARRAY)
PROTOTYPING STEP INTO THE DESIGN
FLOW ENABLES PARALLEL HARDWARE/
SOFTWARE TESTING AND INCREASES THE
CHANCES OF RIGHT- FIRST- TIME SILICON.
ARM
Processor
JTAG
Scan
Voltage
Regulator
System Controller
Advanced Int Ctrl
Power Mgt Ctrl
Reset Ctrl
Prog Int Timer
Watchdog Timer
Real Time Timer
Debug Unit
PIO Ctrl
PLL
Osc
Brownout Dtr
Power On Reset
RCOsc
Peripheral
Bridge
SRAM
Flash
Flash
Programmer
M
e
m
o
r
y

C
o
n
t
r
o
l
l
e
r
Peripheral
Data Ctrl
USART0-1
SPI
Two Wire Interface
ADC0-7
USB Device
PWM Ctrl
Synchro Serial Ctrl
Timer/Counter 0-2
P
I
O
P
I
O
P
I
O
ASB/AHB
APB
EBI
Fi gure 1: ARM- based Fl ash MCU Pl at f orm Archi t ect ure
reduce once a process becomes stable), design times
are lengthening in proportion to the transistor count,
and increasing design complexity makes errors more
difficult to detect during the design flow.
Hardware/ software interaction is an increasing source
of error, and difficult to identify until late in the design
flow.
The delay and cost over- run induced by a re- spin can
kill a product. Often the market window has closed,
particularly for a consumer product, and client dissatis-
faction can lead to cancelled orders or worse.
An ARM- based Flash Microcontroller
as an Architecture Platform
Using an ARM- based Flash microcontroller as an archi-
tecture platform for the development of a custom
(application- specific) SoC is a practical approach that
addresses all the challenges outlined in the previous
sections. It takes advantage of available design
methodologies and fabrication technologies, while giv-
ing a higher performance than the previous approach
of testchips- plus- FPGA for dedicated logic. It enables
parallel hardware and software development, with the
additional advantage of software implementation on
embedded Flash (as opposed to ROM) that facilitates
bug fixes and upgrades to meet evolving interface
standards. The design cycle is short (months instead of
years for an SoC designed from scratch) and the exten-
sive re- use of IP blocks makes it cost- effective. It is an
approach based on years of experience and multiple
successful SoC products.
ARM- based Flash MCU Platform Architecture
The general- purpose architecture of an ARM- based
MCU platform (Figure 1) is characterized by a high level
of system integration. It embeds an ARM processor
core together with Flash memory for program and ref-
erence data storage and an SRAM workspace. An
external bus interface (EBI) provides high- speed access
to external memories or memory- mapped devices such
as FPGAs to emulate custom logic.
The system controller includes a number of elements
that until recently were off- chip, notably oscillator/ PLL,
voltage regulator, reset controller, brownout detector
and power- on- reset. An advanced interrupt controller
(AIC) reduces interrupt latency, enhancing the real- time
performance of the system. The system controller also
includes the power management controller that is the
central clock source to the entire device.
www. at mel. com
page 9
It is recognized that ESL design is essential in reducing
the time- to- market of the end- user product.
Design for Manufacturing
Design for manufacturing (DFM) implies taking into
account issues that influence yield and device charac-
teristics during the logical and physical phases of the
design cycle. It involves feeding forward process
issues into design steps that have traditionally been
process- independent. The first area to be impacted has
been timing closure and the identification of critical sig-
nal paths. Physical synthesis has been helpful in
addressing this, but is not a panacea.
Analog characterization is a major area of difficulty, as
is that of embedded Flash memory. The process com-
promises required in embedding Flash into mainstream
CMOS technology give rise to problems of
endurance/ data retention. There is also the practical
issue of the time taken for Flash programming, often
carried out as an integral part of the test cycle.
Yield optimization is generally carried out by process
refinement after successive iterations of a product once
it is in volume production. This can be expensive unless
an acceptable yield level is achieved reasonably rapidly.
Design for Test
Design for test (DFT) is well understood for digital logic,
where scan insertion/ automatic test pattern generation
(ATPG) is the norm. Built- in self- test (BIST) for embed-
ded memories is less common now than a decade ago.
Accordingly, the time taken in testing of embedded
Flash memory can be a major issue unless adequate
provisions such as parallel testing are made.
Power Management
Wasted power drains supplies by generating heat, both
of which are undesirable. The problem is becoming
more significant with smaller transistor geometries, in
particular static leakage current due to reduced gate
thickness. Higher clock speeds lead to a proportional
increase in dynamic power consumption.
A number of approaches to power management are in
vogue, including partitioning the device into separate
voltage islands and clock domains. These enable the
clock to be slowed or stopped in under- or unused
blocks (to reduce dynamic power consumption), and
unused blocks to be powered down (to reduce static
power consumption). In extreme cases the entire SoC
can be put in power- down mode except for its real- time
clock, but the time taken to wake up from low- power
mode can be an issue.
It is essential to integrate a device- wide power man-
agement methodology into the design of an SoC from
the outset; it cannot be grafted on as an afterthought.
Development Cost, Time and Risk
These are all becoming more significant with smaller
geometries: mask costs are escalating (although they
ARM
Processor
JTAG
Scan
Voltage
Regulator
System Controller
Advanced Int Ctrl
Power Mgt Ctrl
Reset Ctrl
Prog Int Timer
Watchdog Timer
Real Time Timer
Debug Unit
PIO Ctrl
PLL
Osc
Brownout Dtr
Power On Reset
RCOsc
Peripheral
Bridge
SRAM
Flash
Flash
Programmer
M
e
m
o
r
y

C
o
n
t
r
o
l
l
e
r
Peripheral
Data Ctrl
USART0-1
SPI
Two Wire Interface
ADC0-7
USB Device
PWM Ctrl
Synchro Serial Ctrl
Timer/Counter 0-2
Ethernet MAC CAN
P
I
O
P
I
O
P
I
O
ASB/AHB
APB
EBI
Application-Specific
Logic
Fi gure 2: Appl i cat i on- speci f i c SoC Deri ved f rom ARM- based Fl ash MCU Pl at f orm
www. at mel. com
page 10
External communication is via industry- standard inter-
faces such as USB, SPI, etc. Data throughput is
enhanced by peripheral DMA controller (PDC) channels
that link each external interface directly with the mem-
ory, enabling data transfers to take place with no
processor intervention. A multi- channel ADC enables
sensors and other analog devices to be directly con-
nected. A parallel I/ O controller multiplexes the
input/ outputs from the communications interfaces with
a number of general- purpose I/ O lines, significantly
reducing the device pin count.
Modular AMBA- compliant IP Blocks
The intellectual property (IP) blocks that make up the
ARM- based SoC are all separately designed, validated
and documented. They are designed for re- use, either
in- house or externally by qualified sub- contractors.
They are characterized on- silicon, in particular the
characteristics of the analog and Flash memory blocks
are determined. Software device drivers, real- time
operating systems and communications protocol
stacks are developed and tested in parallel. The indus-
try- standard ARM core facilitates software develop-
ment via the re- use of legacy code and the availability
of a wide range of software development tools, ported
operating systems and support.
Synthesized, Fabricated and Characterized
Platform
The ARM- based Flash MCU platform is created by inte-
grating the qualified IP blocks around the ARM core.
The platform is synthesized, timing closure is achieved,
critical paths are dealt with and power consumption is
optimized by fabricating the device and marketing it as
a standard product, with successive silicon iterations
for yield enhancement. The device is validated in mul-
tiple applications by diverse clients.
Transformation to Application- specific
System- on- Chip
The generic ARM- based Flash MCU platform is trans-
formed into an application- specific device (Figure 2) by
adding or removing communications interfaces, and by
building in an application- specific logic block. The EBI
or one of the high- speed serial interfaces is used to
connect external memor y- mapped devices. Data
throughput is enhanced by the DMA capability that
reduces processor performance loss to a few percent
during bulk data transfers. The application- specific SoC
is emulated on an FPGA- based development platform
before fabrication, as described in a later section.
SoC Design Flow Based on Architecture and
Emulation Platforms
The System- on- Chip design flow shown in Figure 4 is
based on parallel hardware and software development.
Its starting point is the architecture platform pre- built
from generic hardware and software IP blocks that
have already been characterized and debugged, as
described in previous sections.
The key steps are to partition the hardware and soft-
ware of the application- specific system, using the
existing hardware/ software IP blocks as a guide. Then
follows the development of any application- specific
hardware and software IP blocks that are required.
These are integrated, together with an operating sys-
tem if needed, into the architecture platform and asso-
ciated software. After synthesis and simulation, the
hardware and software of the application- specific sys-
tem are emulated on an FPGA- based emulation plat-
form.
Emulation Platform Architecture
The central feature of the emulation platform (Figures 5
and Figure 6) is a high- density FPGA onto which are
mapped the application- specific logic and any non-
standard communications interfaces. An on- board
clock generator provides all the required timing
Fi gure 3: Syst em- on- Chi p wi t h embedded MCU and
Memor y Bl ocks
Operating
System
Specify
System-on-Chip
Partition
Hardware/
Software
Hardware/Software
Verification on
Application Prototype
or Development Board
Integrate Application-
specific IP Blocks
into Architecture
Platform
Integrate
Software
IP Modules
Hardware and Low-level
Software Emulation on FPGA-based
Emulation Platform
Hardware/Software
Co-simulation
Prototype
IC Fabrication
Physical
Design
Application
Software
Development
Volume
IC Fabrication
Software
Test
Functional
Simulation
Software
Simulation
Generic
Hardware
IP Blocks
Generic
Software
IP Modules
Parallel Development of
Hardware IP Blocks
Parallel Development of
Software IP Modules
Ship ICs and Software to Clients
Architecture
Platform
Select
Architecture
Platform
Application-
specific
Hardware
IP Blocks
Application-
specific
Software
Modules
Select
Software IP
Modules
Fi gure 4: SoC Desi gn Fl ow
www. at mel. com
page 11
sources. There are connections to mezzanine board(s)
that host the architecture platform(s), and both on-
board and external memories. There are also connec-
tions to custom interface boards, and an extensive set
of user switches, displays, LEDs and buttons. There are
interfaces (including PHYs) for USB, Ethernet, RS232
and other standards, as well as external user I/ O pins.
Emulation Key Steps
The first step is to map the Verilog or VHDL code of the
application- specific IP block and any non- standard
communications interfaces onto the FPGA. The archi-
tecture platform(s) are available on plug- in mezzanine
boards (Figure 7). These, and any custom interface
boards are connected to the emulation platform, which
is in turn linked to the development PC.
The development software, comprising at least the low-
level device drivers, operating system and basic func-
tional modules, is loaded on the PC, from where it is
run and debugged using an industry- standard develop-
ment system. Although the emulation board cannot
generally achieve the full operational speed of the tar-
get device, it is orders of magnitude faster than a sim-
ulation, and enables functional behavior to be investi-
gated, rather than just simulation test patterns.
Should any errors be detected, they are corrected
either by modifications to the Verilog/ VHDL code of the
IP blocks, or by modifications to the device drivers or
higher- level software. The sequence of test/ correction
continues until all errors have been identified and elim-
inated.
Emulation Benefits
Emulation provides many benefits. The most important
is to be able to use the software to drive the hardware
at close to operational speed. This tests real- time
behavior such as interrupt handling that is almost
impossible to simulate. For the first time in the design
cycle, the hardware/ software interface can be thor-
oughly tested.
Errors are corrected and re- tested rapidly and at mini-
mal cost. There are no masks to re- make or fabrication
re- spins to correct prototypes. The savings in time and
cost are significant.
Finally, the debugged emulation system corresponds to
the fabricated devices. It can be used as the starting
point for upgraded versions of the system- on- chip
(both hardware and software).
Platform- based SoC Design: How Does it Rate?
How does the use of an ARM- based Flash microcon-
troller platform measure up to the challenges of SoC
development listed at the start of this article?
Electronic System Level Design
Platform- based SoC design does not use a unified
electronic system- level design language, but it does
address the key issue of hardware/ software design
partitioning. The use of pre- qualified hardware/ soft-
ware IP blocks guides and simplifies design partition-
ing, and the architecture platform provides a system-
level starting point. The emulation of the entire hard-
ware/ software system relatively early in the design
cycle resolves many ESL design issues before fabrica-
tion. The use of Flash memory ensures that software
modifications can be incorporated late in the design
cycle, or even as field upgrades.
Design for Manufacture/ Test
The architecture platform is implemented on silicon as
a standard product, which means that timing closure
and critical path issues are already addressed. Analog
and embedded Flash characterization is already
achieved. Yield enhancement by process optimization is
already accomplished, or yield data from the platform
can be taken into account in the fabrication of the
application- specific device. The major test issues, gen-
erally concerning the analog and embedded Flash, are
already resolved in the test regime for the architecture
platform. All these factors increase the probability of a
right- first time application- specific SoC with an accept-
able yield starting from the first production batch.
Power Management
The principles of power management, including an
integrated power management controller, are incorpo-
rated in the architecture platform. The IP blocks are all
designed for compatibility with the power management
controller, and these design principles are easily
extended to the application- specific logic and any ded-
icated interfaces. These include the provision of clock
and voltage domains, and the establishment of stand-
by or power- down modes where appropriate. The result
is an application- specific device with optimal power
consumption in all modes of use.
Mezzanine 1
Connectors
Mezzanine 2
Connectors
High-Speed/
LVDS Edge
Connectors
PCI
Extension
Slot
DIN41612
Extension
Connector (VME)
Power Cycle
Push-button
PC-ATX
Power
Input
Warm Reset
Push-button
JTAG
JTAG
External
Clock Input
User
Push-buttons
User
DIP Switches
User Rotary
Selectors
Extension Connectors
System Memory
RJ45
RJ45
USB Host
USB Device
USB On-the-Go
CAN 1
CAN 2
Serial Full
Serial Minimal
TWI
QWI
Speaker Output
Mic/Line Input
S
t
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n
d
a
r
d

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P
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k
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g
U
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e
r

I
n
p
u
t
s
Voltage
Regulators
Reset Gen
System ACE
(Embedded Flash &
Config Ctrl)
User Clock
Programmable
Triple Digital
PLL
TCXO
Debouncer
Debouncer
12V
5V
3.3V
2.5V
1.8V
1.5V
Reset
NReset
Xilinx Virtex II
XC2V8000 FPGA
500K Gate
Asic Equivalent
67584 Flip-flops
16 Global
Clock Paths
2.5 Mbit SSRAM
12 Digital Clock
Managers (PLL)
12 18x18 Multipliers
1104 User I/O Ports
Ethernet PHY
USB 1.0/2.0
PHY
USB 1.0 PHY
X
Matrix
CAN PHY
CAN PHY
RS232 Level
Shifters
Amplifier
Line Adapter
4-digit
LED Display
LED Bar
Free
User I/O
512K x 32
ZBT
SSRAM
32-bit DDR-SDRAM Slot
32-bit SDRAM Slot
Xtal
(Dual Mounting)
50 MHz
1 to 200 MHz
U
s
e
r

O
u
t
p
u
t
s
/
C
o
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n
e
c
t
i
o
n
s
DAC
ADC
Fi gure 5: Emul at i on Pl at f orm Archi t ect ure
www. at mel. com
page 12
Design Cost, Time and Risk
These are all significantly reduced by starting from an
already- fabricated architecture platform with re- use of
qualified hardware/ software IP blocks. The emulation
phase enables the custom hardware and software driv-
ers to be thoroughly debugged at minimal cost. The
embedded Flash memory enables software upgrades
at minimal cost, even in the field.
Conclusion
An ARM- based Flash microcontroller can serve as an
architecture platform for the development of an appli-
cation- specific system- on- chip. The design flow based
on its use addresses all of the issues of system- on- chip
design, contributing to lower development cost and
risk, and increasing the chances of right- first- time sili-
con with an acceptable yield.
Fi gure 6: At mel s Mi st ral Emul at i on Pl at f orm
Fi gure 7: Mezzani ne Board f or ARM- based
Archi t ect ure Pl at f orm
March 21 -23 2006,
Santa Clara Convention Center
I n t he 3 days of t his conf erence, delegat es will learn about :
I
New mul t i core hardware and sof t ware devel opment t echni ques
I
Hot product s t o f aci l i t at e your devel opment of mul t i core-enhanced appl i cat i ons
I
Pract i cal , hands-on approaches t o desi gni ng mul t i core sol ut i ons
I
Key devel opment s and roadmap of t he Mul t i core Associ at i on, an i ndust ry organi zat i on
sponsor of t he Mul t i core Expo
Don t mi ss t he Mul t i core Expo! Regi st rat i on opens February 1.
www.multicore-expo.com
T h e F a s t T r a c k t o M u lt ic o r e S o lu t io n s
Mul t i core t echnol ogi es have become key f act ors i n t he success of many embedded product s.
Thi s t rend i s becomi ng exponent i al l y more i mport ant as desi gns grow i n compl exi t y and
pl ace great er demands on perf ormance, pow er, and pri ce requi rement s.
The chal l enges of i mpl ement i ng a successf ul mul t i core-based syst em are al so i ncreasi ng
exponent i al l y.
Joi n t he i ndust rys t op expert s i n a uni que conf erence
t hat del i vers real devel oper sol ut i ons f or mul t i core and
mul t i processi ng desi gns.
ply selects the serial Flash, sends it one command to
start reading the memory, and then continues to clock
the serial Flash until all of the necessary code has been
output. The serial Flash is designed to be read sequen-
tially and incorporates an internal address counter so
that every clock cycle will output the next bit of data.
In order to minimize boot time, shadowing code into
RAM requires relatively fast transfers from the Flash,
especially as code densities increase. A common mis-
conception in the industry is that serial equates to slow
performance, but that simply isn t true anymore.
Todays PCs, for example, incorporate a host of some
ver y high- speed serial interfaces such as PCI
Express , serial ATA, USB 2.0, and IEEE1394/
FireWire
TM
.
Atmel Corporation, with its AT26 and AT45 series
DataFlash

family of serial Flash, currently offers the

industrys highest speeds at 66 MHz. These devices
are capable of sustaining read throughputs at a very
fast 66 Mbps, or 8.25 MB per second, which is equiv-
alent to a 120 ns 8- bit parallel Flash. With such high
throughputs, an entire 64 Mbit device can be read in
less than one second. A lower density device, such as
an 8 Mbit can output the entire contents of its memo-
ry in a mere 127 ms.
Increasing Performance
The performance requirements of todays applications
continue to increase, despite the seemingly simplistic
nature of some of these applications. The performance
increases generally arise from the incorporation of
additional and improved features in the applications or
improved data transfer rates and processing through-
put. As the performance requirements increase, the
access times (45 ns+ ) of traditional XiP parallel Flash
simply aren t fast enough to directly execute the pro-
gram code. In such instances, either external RAM or
embedded RAM in the ASIC or processor must be used
to execute the code since the RAM access times are
much faster than Flash, especially when considering
DDR type SDRAM.
With embedded SRAM technology, sub- 10 ns access
times can be achieved, and the data paths from the
SRAM array to the processor core in an embedded
design are, of course, very short. With external DDR
SDRAM, read throughputs of 400 MB per second are
easily achievable, which are faster than what any type
of XiP parallel Flash in production today can offer, even
the fastest burst- mode type Flash.
Saving Cost by Shadowing
In a code shadowing application, the code can be
stored compressed in the Flash and decompressed
during the shadowing process. With todays algo-
rithms, compression rates as high as 2.5- to- 1 can be
achieved, thereby effectively halving the density of
By: Richard De Caro, Atmel Corporation
Since its inception in 1997, the serial Flash market has
grown at an incredible rate and is rapidly becoming the
Flash memory of choice in many applications once
dominated by parallel NOR Flash. Developed initially
for the nonvolatile data storage segment, serial Flash
has since found its way into the much more lucrative
and high volume code storage market.
As applications evolve, the code storage landscape
continues to change, driving more and more appli-
cations away from traditional parallel Flash and
towards code shadowing with serial Flash. Three
very important factors are fueling this migration:
the need to increase system performance
beyond what execute- in- place (XiP) parallel
Flash can accommodate, the need to reduce
total system cost, and of course the need to
reduce system pin counts.
Applications that shadow code from serial
Flash are not extravagant, high- end, or one- off
designs. They are, on the contrary, high- volume,
everyday consumer applications that can be found
everywhere. Listed below are just some of the appli-
cations currently code shadowing with serial Flash:
Desktop and notebook PCs
Hard disk drives
CD- ROM/ CD- RW drives
DVD- ROM/ DVD RW drives
Video graphics cards
Gigabit Ethernet (GbE) LAN controllers
DSL modems
Wireless LAN (WLAN) routers/ access points
Inkjet and laser printers (including all- in- one multi
function units)
DVD players and recorders
Video game system remote controls
Radar detectors
Household alarm systems
Shadowing Code is Fast and Easy
The concept of shadowing code into RAM is not a new
one. PCs, for example, have been shadowing code
practically since their beginning. Aside from increases
in device density, the only thing that has changed over
time is the type of nonvolatile memory that the code is
shadowed from, whether it be EPROM, parallel Flash,
Firmware Hub/ Low Pin Count Flash, or serial Flash.
Shadowing code from serial Flash is extremely simple,
and it can be effortless since native boot support is
being added to more and more third- party chipsets.
With native boot support, the downloading of code from
the serial Flash to RAM is automatically handled at sys-
tem power- up. In applications being developed with
custom ASICs, implementing the shadow process is
very easy. After the system powers up, the ASIC sim-
www. at mel. com
page 13
The Explosive World of Serial Flash
Designers
Corner
Designers
Corner
www. at mel. com
page 14
Flash needed to store the code compared to what
would be needed for direct code execution. In an XiP
scenario, it is generally not possible to store the code
compressed because it would have to be decom-
pressed on the fly while being executed, which would
severely degrade system performance.
In many applications, a portion of the system SDRAM
may not be used as work/ scratchpad memory and can
be used to store uncompressed shadowed program
code. Therefore, the total system cost can be reduced
by compressing the code, halving the Flash density, and
keeping the SDRAM density the same as what would be
used in an XiP scenario. Dynamic shadowing, in which
specific subroutines are pre- fetched and shadowed
only when needed, can also be incorporated to reduce
the amount of SDRAM needed to store the shadowed
code.
If the uncompressed code cannot fit into unused
SDRAM space, then in many instances, it is still more
cost effective to double the SDRAM density rather than
double the Flash density because of SDRAMs lower
cost per bit factor. This is especially true when consid-
ering high density parallel NOR Flash such as a 128-
Mbit and the cost increase that would be incurred if
forced to jump to a 256 Mbit device.
Serial Flash Reduces System
Pin Counts and Cost
Looked at any way, pins aren t free, whether its leads
on a package, traces on a PCB, I/ O buffers and logic in
an ASIC, or bond pads on a die. The desire of every
system designer, and for that matter every ASIC and
controller designer, is to keep the number of used pins
to a minimum. Using serial Flash for code shadowing
can significantly help in this area. For example, in a
system with 32 Mbits of code, 36 pins can be trimmed
off the ASIC/ controller by using serial Flash and elimi-
nating the 16- bit parallel Flash bus.
A savings of 36 pins translates into cost reductions in
many areas. Many ASIC/ controller designs are pad
limited in that the number of bond pads dictates how
large the die is rather than the amount of gates used
for the core and logic. Eliminating 36 bond pads allows
for a much more compact ASIC/ controller design that
results in a reduced die size which lowers the die cost
and increases the die per wafer count. In addition,
reducing the number of active pins allows the use of
lower pin count packages and reductions in assembly
and package costs. For example, a $0.30 to $0.50
assembly and package cost savings per unit can easi-
ly be realized by going from a high pin- count BGA to a
lower pin- count QFP. With smaller and lower pin- count
packages comes reduced PCB areas and simplified
routing, both of which help lower system costs.
Of course, the package size of the Flash device itself
also drastically changes when going from large 40- ,
48- , or 56- lead TSOPs used for parallel Flash to 8- lead
SOICs used for serial Flash. A 48- lead TSOP, which is
used for 32M (x16) parallel Flash, uses 240 mm
2
of
PCB area. A 32 Mbit serial Flash in an 8- lead pack-
age, on the other hand, uses a very small 48 mm
2
of
board area. This savings in board space again helps
lower the system cost and allows for a more compact
PCB design.
Is the Future Serial Flash?
Increased system performance by code shadowing, the
positives of storing code compressed, reduced ASIC
and controller pin counts, less board space the list
goes on. Serial Flash brings a number of advantages
over parallel Flash, so its no wonder designers are
making the migration to serial Flash. In todays com-
petitive environment, designers must investigate and
implement new technologies and architectures to
reduce their time to market and give them a cost com-
petitive product. Is serial Flash that new technology?
Most definitely, and one thing is for sure, serial Flash is
here to stay and is already changing the landscape of
code storage.
Richard De Caro is the Director of Strategic Marketing
for Nonvolatile Memory Products at Atmel Corporation
in San Jose, California. For more information on
Atmels serial DataFlash products, go to
www.atmel.com.
Pad limited when
using Parallel Flash
Optimized by using
Serial Flash
ASIC/Controller Die
sensor to a PC via the Internet), and greatly reduces
network complexity, while increasing device interoper-
ability.
As the Ethernet protocol reaches deeper into the
embedded world, it will become a mandatory compo-
nent of embedded systems networks. Controllers, such
as Atmels SAM7X Smart Advanced Microcontroller,
include a 10/ 100- Mbps IEEE 802.3- compliant Ether-
net media- access controller (MAC) on chip, as well as
CAN, USB, SPI, TWI, UART and USART interfaces. The
Ethernet MAC can be configured in full- or half- duplex
modes and has a dedicated DMA controller that
ensures maximum 100 Mbps throughout. The Ethernet
MAC also offers programmable interpacket gap, sup-
port for virtual- LAN tagged frames and automatic-
pause frame generation and termination. A dual mode
interface allows the device to connect seamlessly
through either a Media Independent Interface (MII) or a
Reduced Media Independent Interface (RMII) interface,
allowing a large selection of PHYs in Fast Ethernet
applications. The MII offers a wider choice of PHYs,
while the RMII frees I/ Os on the microcontroller for the
application. These MCUs can be interfaced directly with
POS- PHY Level 2/ SPI- 3- compliant devices, including
standard network processors. On- chip system buffers
offer lossless flow- control, eliminating the need for
external memory and a flow- control mechanism
reduces port congestion and traffic loss. Jumbo frames
of up to 10240 bytes are supported.
A dedicated DMA controller connects the Ethernet
MAC to the MCU memories via the SAM7X Advanced
System Bus (ASB) bus interface. The DMA controller
contains 28 byte receive and transmit FIFOs for buffer-
ing frame data. It loads the transmit FIFO and empties
By: Jacko Wilbrink, Dany Nativel, and
Tim Morin, Atmel Corporation
Trends in Embedded Connectivity
The evolution of embedded systems to embedded net-
works radically changes the architectural requirements
of embedded microcontrollers. The MCU must inter-
face to multiple networking protocols. It must be able
to transfer and verify large amounts of data. It must
provide security. It must have sufficient memory den-
sity and processing power to accommodate all the var-
ious protocol stacks and, in many cases, it must do
these tasks while consuming a minimal amount of
power. And, it must do all these things while providing
the determinism required for real- time applications.
In environments where the number of networked
devices is increasing rapidly, cable lengths and band-
width requirements increase exponentially. Lower
bandwidth networks, such as CAN, which has a maxi-
mum bandwidth of 1Mbps, are facing their limits and
are beginning to be replaced by higher bandwidth 100
Mbps Ethernet networks. CAN will remain a factor in
embedded networks for sometime, and ZigBee is
expected to make substantial inroads into low data rate
control applications. For communication with a PC,
USB has become the standard.
Ethernet is the most widely used and best understood
networking protocol around. Extending it into the
embedded space offers a great opportunity to provide
seamless communications within the local network and
with the Internet. Since both Ethernet and the Internet
use the TCP/ IP communication protocol, implementing
Ethernet in the local network eliminates the need for
protocol conversions (e.g. when connecting a remote
www. at mel. com
page 16
Net worked Net works and Embedded
Microcont roller Archit ect ures
Fi gure 1: Embedded Net works
EMBEDDED SYSTEMS USED TO BE DEEPLY
EMBEDDED INSIDE END PRODUCTS. THEY
WERE ONLY RARELY CONNECTED TO THE
OUTSIDE WORLD. THE MICROCONTROLLER
WORKED IN A FAIRLY CLOSED SYSTEM
POLLING PERIPHERALS, COLLECTING
DATA, PERFORMING SIMPLE PROCESSING
AND TURNING SWITCHES AND LEDS ON
AND OFF. THERE WAS LIMITED DATA
MANIPULATION OR DATA TRANSFER. THEY
WERE NOT CONNECTED TO A LAN OR THE
INTERNET. SECURITY WAS NOT AN ISSUE.
THATS CHANGED. TODAY, EMBEDDED
SYSTEMS ARE FREQUENTLY NETWORKED
USING CAN, 802.15.4 OR EVEN ETHERNET
PROTOCOLS. THESE LOCAL NETWORKS
ARE IN TURN CONNECTED TO OTHER
NETWORKS AND TO THE REST OF THE
WORLD VIA THE INTERNET. AS EMBEDDED
CONTROL SYSTEMS BECOME MORE NET-
WORKED, EMBEDDED MICROCONTROLLER
ARCHITECTURES WILL HAVE TO ADAPT TO
PROVIDE THE BANDWIDTH, CONNECTIVITY
AND SECURITY MANDATED BY ANY
EXTENSIVELY CONNECTED SYSTEM.
THIS ARTICLE TAKES A CLOSER LOOK
AT TODAYS NETWORKED EMBEDDED
SYSTEM AND THE CRITICAL ROLE
THE MICROCONTROLLER ARCHITECTURE
PLAYS IN CONNECTIVITY, POWER
MANAGEMENT AND SECURITY.
Local Control
andMonitoring
Ethernet
PLC PLC
Control Server
Firewall
Internet
Remote
Access
Servo-Drive
Servo-Drive Servo-Drive
Servo-Drive
Actuator Actuator
Actuator Actuator
Bring TCP/IP
Down to the Node
Secure Remote
Access over Internet
Communication
Bandwidth
www. at mel. com
page 17
the receive FIFO using ASB bus master operations.
Receive data is not sent to memory until the address
checking logic has determined that the frame should be
copied. Receive or transmit frames are stored in one or
more buffers. Receive buffers have a fixed length of
128 bytes. Transmit buffers range in length between 0
and 2047 bytes, and up to 128 buffers are permitted
per frame. The DMA block manages the transmit and
receive frame buffer queues. These queues can hold
multiple frames.
Frame data is transferred to and from the Ethernet MAC
through the DMA interface. All transfers are 32- bit
words and may be single accesses or bursts of 2, 3 or
4 words. Burst accesses do not cross 16- byte bound-
aries. Bursts of 4 words are the default data transfer;
single accesses or bursts of less than four words may
be used to transfer data at the beginning or the end of
a buffer.
At 100 Mbps, it takes 960 ns to transmit or receive 12
bytes of data. In addition, six master clock cycles should
be allowed for data to be loaded from the bus and to
propagate through the FIFOs. For a 60 MHz master
clock this takes 100 ns, making the bus latency
requirement 860 ns.
The only wrinkle is that, using a public communication
network, such as the Internet radically increases the
need for security. Advanced encryption algorithms and
secure keys are mandatory.
Networking Mandates Data Security
Transferring megabits of control data over the Internet
or any other open network poses serious security prob-
lems because it opens up access to those embedded
systems. You wouldn t want an outsider messing with
your building security or HVAC systems. And you really
wouldn t want anyone to get into the utility system and
shut down the power grid, or release all the water from
a dam on short notice, or open a valve on a gas
pipeline.
Therefore, access to embedded networks must be
controlled and data must be encrypted. Encryption is
computationally intensive. The Advanced Encryption
Standard (AES), Data Encryption Standard (DES), and
Triple Data Encryption Standard (TDES) are Federal
Information Processing Standard (FIPS)- approved
cryptographic algorithms that can be used to protect
electronic data. AES supports five confidentiality modes
of operation for symmetrical key block cipher algo-
rithms (ECB, CBC, OFB, CFB and CTR), as specified in
the NIST Special Publication 800- 38A Recommen-
dation. TDES supports four different confidentiality
modes of operation (ECB, CBC, OFB and CFB), as spec-
ified in the FIPS Publication 81.
AES Encryption
The AES algorithm is a symmetric block cipher capable
of using cryptographic keys of 128 bits to encrypt and
decrypt data in blocks of 128 bits. Encryption converts
data to an unintelligible form called cipher text.
Decrypting the cipher text converts the data back into
its original form, called plain text. The CIPHER bit in the
AES Mode Register allows selection between the
encryption and the decryption processes. This 128- bit
key is defined in the Key Registers. The input to the
encryption processes of the CBC, CFB, and OFB modes
includes, in addition to the plaintext, a 128- bit data
block called the initialization vector. The initialization
vector is used in an initial step in the encryption of a
message and in the corresponding decryption of the
message. The Initialization Vector Registers are also
used by the CTR mode to set the counter value.
The AES supports Electronic Code Book (ECB), Cipher
Block Chaining (CBC), Output Feedback (OFB), Cipher
Feedback (CFB), with 8- , 16- , 32- , 64- or 128- bit data
segments, and Counter (CTR). The data pre- process-
ing, post- processing and data chaining for the con-
cerned modes are performed automatically. These
modes and the encryption/ decryption start modes are
selected by setting fields in the AES Mode register.
DES/ Triple DES
The DES standard uses a 64- bit encryption/ decryption
key to operate on 64- bit blocks of data. Triple DES uses
three DES keys, referred to as a key bundle. These
three 64- bit keys are defined, respectively, in the Key
1, 2 and 3 Word Registers In Triple DES mode a bit in
the TDES Mode Register is used to choose between a
two- and a three- key algorithm. In three key triple DES
the data is first encrypted with Key 1, then decrypted
using Key 2 and then encrypted with Key 3, then de-
/ encrypted in reverse order. In two- key mode, the data
are first encrypted with Key 1, then decrypted using
Key 2 and then encrypted with Key 1.
The input to the encryption processes of the CBC, CFB,
and OFB modes includes, in addition to the plain text,
a 64- bit data block called the initialization vector (IV),
which must be set in a register. The initialization vector
is used in an initial step in the encryption of a message
and in the corresponding decryption of the message.
TDES supports the similar modes to AES, except it has
no 128- bit CFB mode.
Software or Hardware Security?
Based on the number or encryption steps and/ or the
size of the keys, encryption can be a particularly com-
pute- intensive activity, frequently overwhelming the
resources of even 32- bit processors. For example, an
ARM7 Family processor can execute software AES
encryption at 4.7 Mbps. This is not nearly fast enough
to keep up with even a 12 Mbps full- speed USB con-
nection, much less that 25 Mbps data rates of SPI and
TWI. Even at 4.7 Mbps, the ARM7TDMI

processor
ends up becoming a dedicated encryption processor,
limiting its ability to do anything else.
Clearly, the optimal solution is to embed the encryption
engine directly on the processor itself. This solution not
only speeds up encryption. It also frees up the CPU to
do its embedded control job. For example the embed-
ded encryption engine on Atmels SAM7X executes
AES encryption at 20 Mbps, DES at 11.2 Mbps and
Embedded
ICE
ARM7TDMI
Core
Memory
Controller
32bitFlash
128K- 256KB
32bitSRAM
32K- 64KB
ASB
APB
POR/
BOD
1.8V
LDO
SPI SPI TWI Debug
UART
USART USART
USB
Device
SSC CAN Ethernet
MAC
10/100
AES
3DES
AIC
Timer
x3
PWM
x4
PIO
10-bit
ADC
x8
SAM-BA FFPI
XTAL
OSC
RC
OSC
PLL WDT
PMC
RTT
PIT
Peripheral
DMA
Controller
AT91SAM7X
AMBA Bridge
1
Refer to the NIST Special Publication 800-38A Recommendation for more complete information.
Fi gure 2: SAM7X Bl ock Di agram
that directly transfers data between the peripherals
and the chips internal and external memories. Most
SAM7X peripherals have two dedicated PDC channels,
one each for receiving and transmitting data. The user
interface of a PDC channel is integrated in the memo-
ry space of each peripheral, and contains a 32- bit
memory pointer register, a 16- bit transfer count regis-
ter, a 32- bit register for next memory pointer, and a
16- bit register for next transfer count. The peripherals
trigger PDC transfers using transmit and receive sig-
nals. When the first programmed data block is trans-
ferred, an end- of- transfer interrupt is generated by the
corresponding peripheral. The second block data
transfer is started automatically and the processing of
the first block can be
performed in parallel
by the ARM proces-
sor, thereby remov-
ing heavy real- time
interrupt constraints
to updating the DMA
memory pointers on
the processor, and
sustaining high-
speed data transfers
on any peripheral.
It is possible, at any
moment, to read the
location in memory
of the next transfer
and the number of
remaining transfers.
The PDC has dedicated status registers which indicate
if the transfer is enabled or disabled for each channel.
When the peripheral receives an external character, it
sends a Receive Ready signal to the PDC which then
requests access to the system bus. When access is
granted, the PDC starts a read of the peripheral
Receive Holding Register (RHR) and then triggers a
write in the memory. After each transfer, the relevant
PDC memory pointer is incremented and the number
of transfers left is decremented. When the memory
block size is reached, the next block transfer is auto-
matically started or a signal is sent to the
peripheral and the transfer stops. The same
procedure is followed, in reverse, for trans-
mit transfers.
If simultaneous requests of the same type
(receiver or transmitter) occur on identical
peripherals, the priority is determined by
the numbering of the peripherals. If transfer
requests are not simultaneous, they are
treated in the order they occurred.
Requests from the receivers are handled
first and then followed by transmitter
requests.
To ensure that the DMA transfers operate
continuously, at speed, the PDC is config-
www. at mel. com
page 18
triple DES at 12.8 Mbps, pretty much independently of
the CPU, while leaving 99% of the processors
resources free for other things.
Moving the Data Around.
Embedded MCU applications linked to a network must
be able to deal with both communications and control
chores and give the programmer as much control as
possible over those operations. They also must be able
to provide seamless and endless transmission between
memory and the peripheral devices with no interrup-
tions. You don t want a transmission counter to expire.
Direct the processor to do something else while it
resends and then comes back to the stack.
DMA is not native to the ARM7TDMI

processor. The
CPU itself transfers data one byte at a time. Thus, data
rates can be very slow and they consume processing
resources that are needed for the embedded control
function. This is fine, as long as the quantity of data
being transferred is relatively small. However, as data
rates exceed one million bits per second (Mbps), even
fast processors start to bog down. For example, at 50
MHz, a one Mbps data transfer uses 28% of an
ARM7TDMI processor resources. A 2 Mbps data trans-
fer uses more than half the ARM7 processor
resources, and at 4 Mbps, the processor is not avail-
able for any other activity.
When you consider that the data rate for full speed
USB 2.0 is 12 Mbps, the CAN data rate is 1 Mbps,
Ethernet at 100 Mbps and SAM7 SPI and USART
peripherals can run at 25 Mbps, it becomes quite clear
that the issue of data transfer must be dealt with in any
extensively connected embedded control system. In
applications where there is a lot of data to move
around, can the microcontroller act as both a gateway
AND a controller?
Atmel has augmented the ARM7 Family processor
architecture with a peripheral DMA controller (PDC)
Peripheral Peripheral DMA Controller
THR
RHR
Control
PDC Channel 0
PDC Channel 1
Status & Control
Control
Memory
Controller
Fi gure 3: PDC
ured so that when one counter expires, the PDC down-
loads the next counter into the current register, gener-
ates an interrupt and updates the next counter. One
counter- register set is used for the initial transfer and
the other set for the next transfer, allowing the pro-
grammer to ping pong the DMA count and simulate an
endless DMA transfer of data to the peripherals with-
out interruption.
Unlike traditional DMA structures, PDC transfers are
not measured in terms of 8- , 16- , 32- bits or bytes,
words or halfwords. The transfer counter transfers
cycles over a 32- bit bus, with the PDC defining
whether the transfer is byte, word or halfword. If the
peripheral is programmed to transfer eight bit data, the
PDC can transfer 64 kbytes of data per block transfer.
If programmed for 16- bit transfers, it moves 128
kbytes of data per block transfer. If programmed for
32- bit data, it transfers, four times as much or 256
kbytes per block transfer. This gives the programmer
considerable leeway over the DMA transfer character-
istics.
To simplify programming, the PDC programming struc-
tures are embedded into each supported peripheral
device. The register and counter locations are in the
peripheral control map so the programmer sees a list
of registers and pointers: addresses and counts for the
current and next counter and a controller register to
enable or disable it.
The PDC avoids processor intervention and removes
the processor interrupt- handling overhead, thereby
significantly reducing the number of clock cycles
required for a data transfer and freeing up the MCU to
do its embedded control job. The DMA schemes in the
SAM7X architecture enable it to simultaneously serve
as both a gateway AND a controller, even at high data
rates. When transferring just 4 Mbps, a conventional
ARM7TDMI processor effectively ties up all its pro-
cessing resources. In contrast, Atmel SAM7X proces-
sor uses only 2% of its processing capacity to transfer
4 Mbps. The device easily supports 25 Mbps SPI or
TWI transfers, and still has 96% of it resources avail-
able to execute embedded control functions.
Fi gure 4: TX Rat e Tabl e
www. at mel. com
page 19
Encryption and the Peripheral Data Controller
Any embedded control system that needs an Ethernet
connection is going to have to be able to
encrypt/ decrypt data at or near Ethernet speeds. This
means that even the relatively fast 20 Mbps AES
encryption/ decryption throughput achieved by the
SAM7X hardware encryption engine may not be suffi-
cient in some applications.
The same bandwidth increases achieved by the PDC in
data transfers can also be applied to encr yp-
tion/ decryption. Encryption requires that data be fed
continuously to the peripheral devices at the data rate
they need so they can perform control operations while
simultaneously servicing the compute- and memory-
intensive encryption blocks.
Data may be encrypted and decrypted directly through
the peripheral data controller (PDC) channels, without
out the aid of the ARM7 processor. This capability
increases encryption throughput by a factor of 300%
to 400%. And frees up the ARM7 processor for other
functions. For example, AES encryption that runs at 4
Mbps in software and 20 Mbps using a hardware
encryption engine, executes at 80 Mbps when aug-
mented by the SAM7X PDC. DES and triple DES require
too much computation and memory to be done in soft-
ware on the ARM7TDMI processor. However, the PDC
increases hardware DES encryption from 11.2 to Mbps
to 20 Mbps and triple DES from 12.8 Mbps to 32.8
Mbps.
Support for Real- time Applications
With all the glamour of 10/ 100 Ethernet MACs and
CAN and USB and advanced encryption, it is all too
easy to lose site of the fact that, even when connected
by vast arrays of networks, embedded systems are still
real time systems. Processing must be deterministic
and instructions and data must arrive in the right place
at a precisely predictable clock cycle. Unfortunately,
the vast majority of 32- bit controllers that have the
horsepower to handle a networked are ill- equipped for
real- time applications.
High- speed 25 ns flash memory on SAM7X microcon-
trollers allows single- cycle fetches of code directly
from memory, eliminating the need for code shadow-
ing and guaranteeing deterministic processing. The
SAM7X can achieve 38 MIPS of raw performance with-
out using cache running out of the Flash and 50 MIPS
when running out of the on- chip SRAM.
Real- time systems are inherently interrupt driven. The
SAM7X has a set of individually maskable, vectored
interrupt sources and an 8- level priority interrupt con-
troller, permanently stored in SRAM that resolves inter-
rupt priorities.
Read/ Modify/ Write (RMW) sequences that individually
set or clear a bit in I/ O space are all too common in real
time systems, but not well supported by 32- bit MCUs
which typically require 15 instructions to execute.
Every peripheral on the SAM7X has its own set con-
trol register and a clear control register. This allows a
six cycle load/ move/ store sequence to handle all inter-
rupt masking and bit set and reset operations, reduc-
ing the processing overhead and code required for this
operation by 60 percent.
Another weakness of 32- bit processors is their lack of
supervisory functions to anticipate and prevent unex-
pected system crashes due to power failures (brown-
out) memory and registers with old values, and
unforeseen loops The SAM7X includes a full set of
supervisory functions and on- chip RC clocks the
watchdog timer guarantees the system can be reset
using the RC to put the system into a safe state in the
event the mechanical crystal fails.
Conclusion
Todays embedded control systems are rapidly morph-
ing into embedded networks that are themselves fre-
quently networked via the Internet. This trend changes
the criteria for selecting microcontroller for many
embedded applications. Microcontrollers must offer
extensive connectivity, based on industry standards,
such as USB, CAN and Ethernet, is paramount. MCU
architectures must be capable of moving large
amounts of data, without compromising processor per-
formance. The exposure of these systems to public
networks mandates that MCUs include advanced
encryption algorithms and secure key storage.
Designers should not, however, allow high perform-
ance networking requirements to trivalize the fact that
embedded systems are still real- time systems and
need features that support real- time performance,
whether or not they are networked. When evaluating
MCUs designers should verify the level on- chip support
for real- time applications. At a minimum MCUs should
provide deterministic processing, single- supply volt-
age, an RC clock and supervisory functions, such as
power on reset, brown out detection, and watchdog
timers.
Fi gure 5: Sof t ware V. Hardware and PDC Encr ypt i on Tabl e
SAM7X@50MHz
Without
PDC
With
PDC
DES 12.8Mb/s 32.8Mb/s
TDES 11.2Mb/s 20Mb/s
AES 20Mb/s 80Mb/s
AES softemulated 4.3Mb/s n/a
By: Dr. John Seng
Computer Science Department
Cal Poly State University San Luis Obispo
Cal Poly State University, San Luis Obispo recently
introduced an undergraduate- level robotics course in
its computer engineering program. I was responsible
for designing and teaching this course. In the class, I
wanted the students to assemble their robots from the
ground up, starting with the controller board. I looked
at a number of controller boards available on the mar-
ket, but none met all of the requirements I was looking
for in a board design: availability as an unassembled
kit, sufficient number of inputs and outputs, powerful
software tools, and overall low- cost. As a result, I set
out to design a board with these requirements and
ended up with a design I called the PolyBot board.
For the design of the PolyBot board, I wanted to sup-
port a number of features. The board was going to be
assembled by students with limited soldering experi-
ence, so all the chips for the board had to be available
in a DIP package and seated in sockets on the board
itself. Chip packages are moving to smaller and small-
er sizes, but I needed one that was both available in a
DIP package and powerful enough for my application.
The board was going to be used in a classroom envi-
ronment, so input power protection was important. The
board needed to support both over- current and reverse
polarity power protection. In addition, it would be use-
ful to have the ability to use different voltages to power
the board. For example, the ability to disable and
enable a 7805 voltage regulator was desirable. If
someone wanted to power a robot with a voltage high-
er than the logic supports, then they could use the reg-
ulator; otherwise, they could disable it.
As for sensor inputs, the controller board needed to
have multiple digital inputs along with analog inputs for
the various sensors that are needed on a robot. In
terms of outputs, robots need several motor outputs. I
decided that 8 hobby servo output connectors and 4
DC motors would satisfy the requirements.
Hardware design
The microcontroller I chose was the AVR ATMega32.
This chip provides more than enough capability for our
application. It has a RISC core that allows for good per-
formance for our application (many of the instructions
execute in a single cycle). In addition, the 16 MHz
clock rate was more than adequate for the robots in our
class. This chip was the most powerful microcontroller
I could find in a DIP package, and fortunately, the chip
was also available at a low cost. This microcontroller
had all of the features I needed for my application.
The over- current and reverse- polarity power protection
is achieved by using a PPTC fuse coupled with a
1N5401 diode. A PPTC fuse greatly increases in
resistance when the fuse current rating is exceeded.
This resistance increases to the point that the fuse
effectively becomes an open connection. In the case of
the PolyBot board, I selected a PPTC fuse with a rating
of 1.85A. This is sufficient to provide over- current pro-
tection in the cases of stalled motors and accidental
shorts. For the reverse current protection, a 1N5401
diode is connected in a crow- bar configuration. When
the power is connected with reverse polarity, the
1N5401 diode conducts, and the current causes the
fuse to trip.
For the voltage regulator, I added a 3- pin male header
that uses a 2- pin jumper to enable or disable the volt-
age regulator. If 2 of the pins are shorted, then the volt-
age sent to the logic is + 5 volts. This voltage
comes from the output of the 7805 voltage
regulator. If the other set of 2 pins are short-
ed, then the voltage sent to the logic is taken
directly from the battery voltage.
For the hobby servo outputs, I used 0.1
spaced male headers as connectors. They
match the female connectors available on
hobby servos. Hobby servos require 3 pins for
operation: signal input, + 5 volts, and ground.
The 8 servo signals come from the ATMega32
microcontroller.
For the DC motor outputs, I used 2 SN754410
H- bridge chips. These chips are commonly
used to control motors in small robots. Each
chip provides 2 DC motor H- bridges. Each H-
bridge allows bi- directional control of a DC
motor with up to 1- amp of current draw. This
www. at mel. com
page 20
PolyBot Board: A Robot Cont roller Board
Using t he At mel ATMega32
Fi gure 1: Sampl e Robot
THIS ARTICLE DEALS WITH DESIGNING
A ROBOT CONTROLLER BOARD USING
THE ATMEGA32 FROM ATMEL.
boards successfully. I have found that 4 AA NiMH bat-
teries provide an excellent power source. The voltage
of fully charged batteries is sometimes a little higher
than the 5.5V maximum voltage for the ATMega32, so
I recommend using a Schottky barrier diode to drop the
voltage by approximately .3 volts.
Conclusion
The PolyBot board has worked well at Cal Poly. Using
the ATMega32 microcontroller on the PolyBot board
has provided ample computing horsepower for our
robot applications. More information about the PolyBot
board and full schematics can be found here:
www.csc.calpoly.edu/ ~ jseng/ PolyBot_Board.html
www. at mel. com
page 21
provided sufficient current for our applications, and the
outputs can be bridged to obtain 2- amps of current if
needed.
As for other features on the board, I included: an LCD
connection port, a jumper for the LCD backlight,
jumpers to allow the use of different voltages for the DC
motors and servos, a relay control port, and a software-
controlled LED. The backlight jumper was quite useful
because disabling the backlight allowed the robots to
run longer on a single charge.
Software
The ATMega32 has a number of open source tools
available that make this chip a practical choice for a
university environment. For software development, we
use the WinAVR software suite that provides a C com-
piler (based on GCC), a download utility (AVRdude), and
an editing environment (Programmer' s Notepad). The
GCC compiler and download utility are also available for
Linux and Mac OS X. In our lab environment, we used
both Windows and Linux and found the experience to be
similar on both platforms.
For the PolyBot board, I wrote a set of library routines
that allowed easy reading of the analog and digital
inputs, servo control, DC motor control, and LCD display
control.
Board design
I designed the PolyBot board using the Eagle CAD pro-
gram. This is an excellent PCB design program and is
free for limited size applications. Fortunately, the
PolyBot board design fit into the freely available version.
The board itself measures 3 x4 and required only 2
layers of routing.
In addition to the PolyBot board, I designed a compan-
ion download board that mates a parallel port download
cable with an RJ- 45 download cable. Preparing for a
download to the microcontroller becomes just a matter
of clicking the RJ- 45 cable into the PolyBot board.
Experience
The board has been well received by the students at Cal
Poly and has been successful as a controller in small
robots as well as in other student projects. All of the
students in the robot class were able to assemble their
Fi gure 2: Pol yBot board.
Fi gure 3: Downl oad board
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It's hard to compete without the right tools!
a ballast inductance that is suitable for the voltage and
the frequency of use. An electromagnetic ballast is
specific to an electricity supply and a type of tube. It
must be suited to the starting technique, adapted to the
size of the tube (which governs the consumption of
electrical power), and wired in accordance with the lay-
out and the number of tubes concerned.
Optimal consumption
Over time, ballast systems have taken advantage of
power- switching conversion techniques, and incorpo-
rate not only the starting function but also a power fac-
tor correction stage, which is necessary so that the
switching at high frequency does not disrupt the elec-
tricity supply. In fact, tubes can now be controlled using
variable- frequency half- bridge inverters, based on a
rectified voltage, irrespective of the voltage and fre-
quency of the supply network, and efficiency increases
of approximately 10% are possible.
More recently, the integration of microcontrollers in
ballast control circuits marked the beginning of pro-
grammable ballasts, offering even greater flexibility,
and opening the door to new applications such as light-
ing network management, automatic luminosity con-
trol, inventory control, and even contrast optimization
for video projection in the case of high- intensity dis-
charge lamps (HID). Such lamps, which are also used
in vehicles and for street lighting, will benefit from a
luminosity intensity control which can be automatically
adjusted to a minimal dormancy level, because they
are particularly refractory to hot starting.
By: Jean- Florent Helie, Electronique Magazine
Unlike incandescent lamps, which convert almost 90%
of consumed energy into heat, fluorescent lamps (LFL
in the case of linear tubes) are significantly more effi-
cient at converting electrical energy into luminous
energy. While the former use a resistant filament that
provides incandescence, the latter make use of an
electric arc that passes through the lamp between two
electrodes located at either end.
This arc is conducted by a vapor mixture of mercury
and noble gases (neon, krypton or argon) enclosed in a
tube with a phosphorous coating. The excited gas
reacts by means of photoelectric emissions, mainly in
the ultraviolet wavelength. The phosphorus in turn
reacts by emitting a visible light.
In order to start the LFL, it is necessary to create an
electrical arc in a gas that is relatively cold and in tubes
of varying lengths. A high initial resistance must be
overcome and this is achieved using one of the follow-
ing three techniques: ionization of the gas by applying
a high electrical potential; application of a high voltage
at the electrodes; and the simplest is based on pre-
heating with the aid of filaments.
Each lamp is designed for a particular technique
depending on the required speed of operation. In each
case, the excitation causes the heating of the gas and
facilitates current conduction, thereby giving the fluo-
rescent tubes a negative resistance characteristic. This
requires a current- limiting device, the most basic being
www. at mel. com
page 22
Light ing: Ballast Cont roller Combined wit h
RI SC Processor Yields an Ef f icient Lamp
MICROCONTROLLERS HAVE BEEN USED IN
THE CONTROL OF FLUORESCENT LAMPS
FOR A NUMBER OF YEARS, PROVIDING
LOGISTICS AND ENERGY MANAGEMENT.
ATMEL OFFERS COMMUNICATION AND
LUMINOSITY CONTROL FUNCTIONS FOR
LIGHTING, BY INCORPORATING AN 8/ 16-
BIT AVR AT THE HEART OF ITS MOST
RECENT CIRCUITS.
Reprinted with permission
from Electronique Magazine,
Issue 158, May 2005.
Fi gure 1: From st reet l i ght i ng t o vi deo proj ect i on, bal l ast s can now be programmed.
www. at mel. com
page 23
In addition to the control functions, an obvious area of
interest to end- users is energy consumption. A ballast
that is more efficient, with a good power factor and a
degree of intelligence, will allow a lamp to consume
less energy over a longer service life. It is also advanta-
geous that faults can be detected by means of intelli-
gent control: some lamps are able to see that their con-
sumption increases when a ballast is trying to start a
tube that is missing or faulty.
Logistical benefits
Atmel now offers two microcontroller categories that
are particularly suitable for ballast applications. The first
category was developed to meet the needs of a fluo-
rescent lamp manufacturer, who had exclusive use of it
up until now. With an 80C51 at its heart, the circuit
with the reference number AT83EB5114 is used for
electronic ballasts that do not include an attenuation
function.
With a 256- byte serial EEPROM stacked on the chip,
this component is able to store utilization parameters
for different tubes and adapt to the detected type. This
clearly simplifies inventory control for the manufactur-
er, since a single ballast model suits numerous tube
references.
This circuit has four PWM channels for controlling the
power factor and the ballast circuit. Control accuracy is
ensured by the high resolution of the pulse width mod-
ulation modules (16 bits). In addition to an amplifier for
conditioning a shunt voltage, reflecting the current in
the tubes, it includes six 10- bit analog- digital conver-
sion channels. A triple clocking system is also provid-
ed: one oscillator for a 24 MHz quartz or ceramic res-
onator, or two oscillators for an external RC network,
one of which is optimized for accuracy and the other
for low consumption. Based on cost, the RC solution is
preferred, but it sacrifices the performance by limiting
the operating frequency to 12 MHz. Performance lev-
els off at 2 MIPS with such a frequency, because the
80C51 core is not really monocyclic.
The circuit has three reduced activity modes in order to
manage the consumption of energy. An idle mode sus-
pends the functioning of the core but keeps its periph-
erals active; a deeper dormancy mode retains only the
A/ D conversion activity. When it is completely isolated
from the circuit, the microcontroller saves the contents
of its RAM and all its functions are deactivated. Since
this microcontroller is intended for low- cost, high- vol-
ume applications, it has 4 Kbytes of hidden ROM, but
a flash equivalent is also available for development
purposes (AT89EB5114). With a power supply between
3 V and 3.6 V, these circuits in 0.35 m technology are
compatible across the industrial temperature range
and available in a SO20 or SO24 casing.
Variable luminosity control
In order to enhance performance, provide luminosity
control functions, and accommodate the protocols
required for a communication bus, Atmel has
increased the processing power by using its mega AVR
core. This virtually monocyclic 8/ 16- bit RISC architec-
ture effectively offers an execution speed of 16 MIPS
without an external cr ystal. The circuits in the
AT90PWMx range have also been enhanced in terms
of PWM channels so that more sophisticated controls
can be generated, particularly for HID lamps which will
benefit from a step- down stage after the PFC module
and full- bridge type control (see figure). The manu-
facturer has also been quick to extend the range of
operating temperatures.
Better pulse modulation
In response to experiments carried out with microcon-
troller ballasts, Atmel has improved the PWM for light-
ing applications. Known as the PSC (Power Stage
Controller) or 12- bit PWM, this module offers two com-
plementary outputs with programmable dead time. Its
main feature is to offer an improved modulation mode,
making it possible to obtain a high average resolution,
while maintaining an acceptable counter speed.
The anticipated applications actually involve relatively
high switching frequencies, extending from 50 to 100
kHz. The 16- bit resolution available on standard mod-
ules is therefore never used in practice, and a resolu-
tion of 12 bits already implies an extremely fast time
Fi gure 2: Di f f erent l evel s of appl i cat i on: Dependi ng on t he t ype of l amp and t he cont rol accuracy requi red, t he
energy conversi on st ages can ut i l i ze 6 t o 10 PWM channel s. The schemat i c di agram at (b) based on t he
AT90PWM3 i s part i cul arl y sui t abl e f or HID l amps.
www. at mel. com
page 24
base. The resolution enhancement mode allows the
PSC module to spread a resolution step over 16 cycles,
thereby gaining 4 bits compared with the average res-
olution. The modulation step is therefore less than 25
Hz for a switching frequency of 150 kHz controlled by
an on- board PLL providing a time base of 64 MHz. It is
also the integration of this phase locked loop which
allows the core to function at 16 MHz, based on a sim-
ple RC oscillator running at 8 MHz, allowing it to devel-
op its computing power of 1 MIPS per MHz.
The PSC module also has a control input, coming from
one of the synchronous analog comparators (8 MHz),
in order to allow the detection of any excessive inten-
sity. Provision is also made to synchronize the analog-
digital acquisition (8 or 11 channels on 10 bits in 8 s).
The acquisition module benefits from the association of
one or two switched- capacitor amplifiers. The 10- bit
digital- analog converter provided on the AT90PWM3
circuit will make it possible to set a comparison thresh-
old. It will also be used for debugging in some cases,
to supervise the digital values by means of an analog
signal. In fact, it is not always possible to set a stop
point with this type of system.
For the purpose of storing advanced control software,
the programmer will have access to 8 Kbytes of flash
memory, 512 bytes of EEPROM and the same amount
of RAM. Furthermore, the two circuits AT90PWM2 and
AT90PWM3 include a two- mode UART for communi-
cation functions. In addition to the standard applica-
tion, this interface has a two- phase mode for use on a
DALI bus. Therefore, it manages Manchester encoding
and decoding, 16- bit or 17- bit data frames, and the
auto- synchronization function characteristic of this
protocol. With the help of these hardware aids, full
DALI functionality will require less than 4 Kbytes of
code.
Implemented in a 0.35 m technology that is different
to previous circuits, the three AVR- based microcon-
trollers will be supplied with a wider voltage range
extending from 2.7 V to 5.5 V. The supply to the micro-
controller is a relatively critical function for correct
starting of the system. Atmel is proposing a reference
design, developed with Ixys who will provide the rec-
ommended power semiconductors. The ballast is
designed to operate two 18- W linear fluorescent tubes
on the basis of a universal 90- 265 VAC 50/ 60 Hz or
90- 250 VDC input. It ensures correct operation when
there is only one tube as well as attenuation control via
a DALI or Swiss- type protocol, or a signal of 0- 10 V,
which is detected automatically.
Atmel AT90PWMx Microcontroller
Family Overview
AT90PWM2 Specially designed for Lamp bal-
last and Motor Control applications, the
AT90PWM2 AVR microcontroller features 8
KBytes Flash memory, 7- channel advanced
PWM, 8- channel 8- bit ADC, two or three 12- bit
High Speed PSC (Power Stage Controllers) with
4- bit Resolution Enhancement and DALI protocol
support.
AT90PWM3 Specially designed for Lamp bal-
last and Motor Control applications, the
AT90PWM3 AVR microcontroller features 8
Kbytes Flash memory, 10- channel advanced
PWM, 11- channel 8- bit ADC, a 10- bit DAC, two
or three 12- bit High Speed PSC (Power Stage
Controllers) with 4- bit Resolution Enhancement
and DALI protocol support.
The received RF signal is processed through the RX
chain without any need to go outside the device. The
filtering stages have been integrated on- chip including
the Image Rejection Mixer, which allows the elimination
of a SAW filter, and the IF filter, requiring no external
component. This has been made possible using a Low-
IF architecture in relation with an integrated filter. The
incoming signal is down converted from the RF to IF =
226 kHz, keeping the same modulation scheme. Then,
the filtering is applied and the signal is demodulated
either in Frequency (FSK) or in Amplitude (ASK).
Thereafter, the data can be retrieved on the
SDO_TMDO pin or directly in the buffer, readable on
the SPI port.
On the transmitter side, the data is processed feed-
ing through SDI_TDMI the internal buffer or direct-
ly the RF in transparent mode. In both cases, the
data straightly modulates the RF signal, directed
to the antenna. Again, no external
modulation/ calibration/ control is required and
whatever the chosen modulation is, the pro-
cessing is applied internally. The software
developer work is focused on processing the
information data and not supporting the RF
requirements.
Moreover, the production of application
modules populate with such an RF device becomes
easy and cost- effective: less components and no cali-
bration means time and money saving.
High Performance Level
Several points should be considered in a RF applica-
tion. Among them are :
Sensitivity: ability to receive a very low signal, having
gone through a long air path
Output power: ability to transmit a high power,
compliant with regulations, being able to go through
a long air path.
Selectivity: ability to reject other RF signals, close in
the RF spectrum
Blocking: ability to reject other RF signals, far in the
RF spectrum
All these listed points relate to the ability to communi-
cate through a long- distance range signal. In a quiet
world, the sensitivity and the output power predict the
distance range which could be reached by ones appli-
cation. In a real world, it is important to be able to keep
safe from other applications, which might disturb ones
receiver chain, on the LNA stage (wide band), on the IF
stage ( medium- band ) and on the demodulation stage
(narrow- band). The ATA542x was designed to balance
all these specifications.
By: Eric Mercier, Atmel
In the license- free RF ISM world, a new step ahead has
recently been announced, representing a major step in
the integration of RF transceivers.
The ATA542x family targeting 315/ 345/ 433/ 868/ 915
MHz bands provides a high- level of performance for
ISM band applications, with a significant lowering in
current consumption and a cut in the bill- of- materials.
More Simple Outside/ More Complex Inside
The new family of RF transceivers is provided in a small
7x7 mm QFN package. The connections are limited to:
RF path to/ from the antenna
Interface with the C thanks to an SPI port
Power supply
Ground
From the antenna to the microcontroller, the internal
processing of the signal requires no external compo-
nents, either active or passive, and no calibration, with
the exception of the PA/ LNA path matching. Indeed,
this level of integration makes the signal path very
short.
The RF part of the ATA542x application is composed of
the Power Amplifier output and the Low Noise Amplifier
input. As it is a half- duplex product, one way at a time
can be processed, therefore the integrated Tx/ Rx
switch removes the need for external control over the
direction of the signal. The matching to be applied on
the board is given as a standard recommendation.
www. at mel. com
page 25
I nt egrat ion and Low Current Consumpt ion:
A Realit y Today f or License-f ree Wireless
Applicat ions
FOR YEARS ATMEL HAS BEEN ENGAGED
IN THE WIRELESS MARKET. SUCCESSFUL
STORIES HAVE EMERGED ON THE
AUTOMOTIVE MARKET WITH RKE AND ON
THE INDUSTRIAL MARKET WITH STANDARD
PRODUCTS AS WELL AS WITH ASICS.
THE RF LINK IN MANY INDUSTRIAL
APPLICATIONS CAN SAVE MONEY ON
INSTALLATION BUT ALSO ON THE
MAINTENANCE ITSELF, (APART FROM
THE COST ADVANTAGE OF THE RF MODULE
OR THE BATTERY LIFE). IT ALSO ADDS
THE ADVANTAGE OF REMOVING THE
WIRES.
www. at mel. com
page 26
The sensitivity of the ATA542x device ranks from 105
dBm to 110 dBm in FSK mode and from 110 dBm to
115 dBm in ASK mode, both dependant on the fre-
quency band and on the data rate. This makes this
product at the state- of- art of receivers specifications.
The maximum output power is + 10 dBm or 10 mW.
This is the most common value in the ISM world, which
complies with most of the world standards, without the
addition of any external transistor or PA module.
Despite the very high integration of the receiver chain,
the performance is in terms of selectivity and blocking
very good. Since it is substantially not sufficient to pro-
vide high sensitivity if this level cannot be reached due
to jamming signals, the integrated IF filter of the
ATA542x provides 55 dB rejection at 1 MHz from the
channel, 65 dB at 5 MHz and 70 dB at 20 MHz.
Of course, this new architecture which brings high- level
performance would not be of interest without a strong
attention paid to maintain the current consumption to a
low level. With 10 mA in Receive mode and 20 mA in
Transmit mode for the maximum output power, the low
current consumption target is reached. This makes RF
designs with the ATA542x, a major step for battery life,
that results in more than 20 percent power reduction
versus competing multichannel transceivers.
Field Performances
The sensitivity and output power specifications allow to
reach line- in- sight more than 1 km range in the low fre-
quency bands (315/ 345/ 433 MHz) and not much far
ahead for the upper bands (868/ 915 MHz). Taking into
account that most applications are more or less indoor,
several walls or floors can be crossed through without
impacting on the quality of the reception. The type of
antenna that will be used in the application is also part
of the distance range performance. Using wipe dipole
aerial, which means a / 4 piece of wire, will bring the
best performance for most of the designs. Using print-
ed antenna is also possible with no problem. These
kinds of antenna are very popular as they are manufac-
tured at the same time then the PCB, offering no extra
cost to the application, with the drawbacks of having
less efficiency/ more losses than the wipe antenna. Due
to the high- performance of the ATA542x, the loss of the
printed antenna can be handled and most applications
will still keep the satisfaction of long range transmis-
sion.
As shown, the selectivity and blocking performance
must also be considered as important when dealing
with quality link analysis. At some MHz from the carri-
er, the ATA542x provides a rejection of typical 60 dB.
This is by means corresponding to a ratio of about
1000 in distance range between the distant transmit-
ter and the jammer, both emitting the same power on
their antenna. If the distant transmitter is at 100
meters, then the jammer should be very close to 1 m
to impact the communication. Considering a strong
jammer at 1 W output power, therefore 100 times
stronger than the ATA542x application, it should be at
about 50 m to disturb a communication of 500 m
between the distant ATA542x. These figures are good
enough to limit any disturbance from strong signals
and ensure a good continuous quality link.
The ATA542x, in addition to the main performance
detailed here above, also features an accurate and
agile frequency synthesizer, with less than 1 kHz accu-
racy and some hundreds of s swap time. This makes
easy Listen- Before- Talk and Frequency Agility proto-
cols in Europe as well as FHSS in North America. Agility
and frequency stability are the key points to ensure
power saving protocols in an environment where oth-
ers applications occur.
Last, but not least, the low current consumption drawn
be the ATA542x in both active and PDN mode is the
insurance that the battery life is preserved from use-
less consumption. Especially the PDN figure down to
10 nA typical value makes the ATA542x almost with no
leak when not operating, thereby long battery life is not
a dream any more.
Targeted Applications
With the above- described performance, it makes this
RF family a particularly suitable choice and the ideal
device to target optimized long range/ long battery life
in a lossy environment.
For Alarm and Security systems as well as for Power
Management, the long distance range ability, the low
current consumption and dense implementation are
the required solutions for small intrusion sensors, using
hand- shake protocol and allowing a typical 5- year bat-
tery life.
For Automatic Meter Reading, the low current con-
sumption in both active and power down modes allevi-
ates highly current saving protocols, being at their best.
Targeting 10- year battery life is then possible using the
Rx mode for Waking- Up the remote utility and the Tx
mode for sending metering information.
For the General Purpose Remote Controller since its
implementation and programming is easy for non- RF
expert, many applications fields then become possible
and these systems take the benefits of the short time-
to- production and ultimately time- to- market for
designing an RF remote controller.
0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 1 1 1 0 0 1 1 1 1 0 1 1 0 0
Bitcheck OK
Preburst
Start-bit
Byte 1 Byte 2 Byte 3
ReceivingMode Bit-check Mode
SDO_TMDO
Demod_Out . . .
. . .
Atmel ATA542X Transceiver
Family Overview
ATA5423 The ATA5423 is a highly integrated
315 MHz ASK/ FSK multi- channel half- duplex
transceiver with very low power consumption
supplied in a small 7 x 7 mm QFN48 package.
The receive part is built as a fully integrated low-
IF receiver. It integrates a fractional- N synthesiz-
er with a direct PLL modulation scheme for FSK
transmission and a switching of the PA for ASK
transmission.
ATA5425 The ATA5423 is a highly integrated
345 MHz ASK/ FSK multi- channel half- duplex
transceiver with very low power consumption
supplied in a small 7 x 7 mm QFN48 package.
The receive part is built as a fully integrated low-
IF receiver. It integrates a fractional- N synthesiz-
er with a direct PLL modulation scheme for FSK
transmission and a switching of the PA for ASK
transmission.
ATA5428 The ATA5423 is a highly integrated
433/ 868 MHz ASK/ FSK multi- channel half-
duplex transceiver with very low power con-
sumption supplied in a small 7 x 7 mm QFN48
package. The receive part is built as a fully inte-
grated low- IF receiver. It integrates a fractional- N
synthesizer with a direct PLL modulation scheme
for FSK transmission and a switching of the PA
for ASK transmission.
ATA5429 The ATA5423 is a highly integrated
915 MHz ASK/ FSK multi- channel half- duplex
transceiver with very low power consumption
supplied in a small 7 x 7 mm QFN48 package.
The receive part is built as a fully integrated low-
IF receiver. It integrates a fractional- N synthesiz-
er with a direct PLL modulation scheme for FSK
transmission and a switching of the PA for ASK
transmission.
advan-
tage must
be judged against
the lower cost advantage
provided by RF CMOS. RF CMOS is capable of pro-
ducing a smaller die size because of the smaller
geometries used in advanced CMOS processing.
When compared, bipolar technologies are typically one
or two generations behind CMOS line widths. The
advantage in total die size offered by RF CMOS is a
function of the ratio of the digital- to- analog areas of the
design. Designs with a large digital- to- analog ratio
typically benefit most from the lower geometries of RF
CMOS. RF CMOS is offered by more fabs and there-
fore more readily available to fabless semiconductor
companies. If the design calls for an integrated micro
controller, and stacking a die or placing multiple chips
into a single- chip module is not an option for your
design, RF CMOS will usually accommodate the micro
controller in a smaller area. Without the NPN modules,
RF CMOS processes have fewer masks and signifi-
cantly shorter cycle times. However, as smaller geom-
etry processes emerge, the number of mask layers
used in SiGe BiCMOS and RF CMOS become more
equal, as shown in Figure 1. Having an equal number
of mask levels in the smaller geometry processes helps
to level out process costs.
RF CMOS processes have better linearity across volt-
age than SiGe BiCMOS processes. However, RF CMOS
processes usually do not have the same quality of
noise performance as the same sized geometry SiGe
BiCMOS processes. Noise affects a circuit by introduc-
ing small fluctuations into voltage and current. If the
voltage or current being affected is part of the circuitry
controlling the frequency, devices, such as low- noise
amplifiers, voltage- controlled amplifiers and mixers,
may not work as originally intended. Working with a
silicon- on- insulator (SOI) process will help to insulate
the noise but can add considerable costs to your
By: David Hess, SiGe BiCMOS/ RF
CMOS Foundry Marketing Manager,
Atmel Corporation
Introduction to the Processes
SiGe BiCMOS processes utilize advanced
CMOS technology, integrated with NPN
bipolar transistors and multiple RF passives
for analog functionality. The direct result of
removing the NPN bipolar transistor from the SiGe
BiCMOS process is the RF CMOS process, which is
composed of the remaining CMOS and RF passives.
This results in a lower cost RF solution that is capable
of meeting the requirements for a large percentage of
RF design needs. There are many important factors in
determining which process will best suit your individual
application. Evaluation of your devices specification to
determine AC characteristics, DC characteristics, lin-
earity, matching, temperature dependence, memory
requirements and noise requirements should be made
and documented prior to evaluating different process-
es. Ft and Fmax are measures of a transistors per-
formance that indicate how high of an operating fre-
quency you will be able to implement into your design.
A standard rule of thumb is that the Ft value of the
process should be 10 times the operating frequency of
your device. Fmax is the frequency at which the tran-
sistor will still demonstrate a unity power gain. The
related Ft value is the frequency at which the part will
demonstrate a unity current gain. Both variables are
important in evaluating potential RF performance. SiGe
BiCMOS and RF CMOS processes offer many distinct
advantages, but your design must be evaluated in
whole to determine the process that will offer the best
fit and lowest cost.
SiGe BiCMOS
High- power, low- current RF applications that have
large analog and small digital areas (70% analog and
30% digital) are usually best suited for a SiGe BiCMOS
process. The high power allows for good transmission
power, and the low current enables the part to have a
long battery life. SiGe BiCMOS processes have high
cut- off frequencies and good noise performance,
enabling them to meet the stringent demands of
todays standards set by organizations, such as IEEE.
SiGe BiCMOS processes are capable of higher gain
values than RF CMOS and historically, have had better
models than RF CMOS processes. SiGe BiCMOS usu-
ally demonstrates better performance, although RF
CMOS may be a more viable solution if your limitations
are space and cost.
RF CMOS
Despite the fact that SiGe BiCMOS technologies offer
improved RF performance by virtue of the inherent
capabilities, which the bipolar technology provides, this
www. at mel. com
page 27
SiGe BiCMOS or RF CMOS f or Your Next
Wireless Applicat ion?
SHOULD A SILICON- GERMANIUM (SIGE)
BICMOS PROCESS OR A RADIO FREQUEN-
CY (RF) CMOS PROCESS BE IMPLEMENTED
FOR THE DEVELOPMENT OF YOUR NEXT
WIRELESS APPLICATION, AND HOW IS THIS
DETERMINED? MANAGERS, DESIGNERS
AND EVEN ENTIRE BUSINESS UNITS OFTEN
START DESIGNING IN A PARTICULAR
PROCESS AND DO NOT STOP TO EVALUATE
DIFFERENT PROCESSES FOR EACH NEW
PRODUCT. HOWEVER, IF YOU LOOK AT
DIFFERENT PROCESSES AND HOW EACH
CAN BENEFIT YOUR DESIGN, YOU MIGHT
BE ABLE TO SAVE TIME AND MONEY,
REDUCE RISKS AND IMPROVE THE
QUALITY OF YOUR DESIGN. RIGHT NOW
MIGHT BE A GOOD TIME TO TRY SOME-
THING NEW. TAKE A HARD LOOK AT THE
TWO PRIMARY PROCESSES USED IN RF
DESIGN AND WHAT FACTORS SHOULD BE
CONSIDERED WHEN TRYING TO CHOOSE
A PROCESS FOR YOUR NEXT PROJECT.
IMPLEMENTING A WELL- SUITED PROCESS
FOR YOUR RF DESIGN WILL RESULT IN
GOOD RF PERFORMANCE AND LOW- NOISE
FIGURES. MOST FOUNDRIES OFFER BOTH
SIGE BICMOS AND RF CMOS PROCESSES.
SIGE BICMOS AND RF CMOS PROCESSES
EACH HAVE INDIVIDUAL STRENGTHS AND
OFFER SOLUTIONS TO DESIGN NEEDS IN
THE RF IC MARKET. AS ALL SYSTEM
ENGINEERS KNOW, THE LOWEST COST
PER SQUARE MILLIMETER THAT ACCOM-
MODATES ALL OF THE PERFORMANCE
REQUIREMENTS IS THE MAIN DRIVING
FORCE BEHIND ALL TECHNOLOGY
SELECTION DECISIONS.
www. at mel. com
page 28
design. Many RF CMOS processes offer options, such
as triple- well and deep- trench isolation, to assist in
decreasing noise.
Geometry Size
Geometry size is another important property of a SiGe
BiCMOS or RF CMOS process. Decisions should not be
made based on the newest or smallest available
process unless that is what your device requires. Often,
the newest processes will have smaller geometries, but
the cost savings resulting from a smaller die size does
not make up for the more expensive mask set and sili-
con, especially if your product will be running lower vol-
umes. The geometry sizes are often directly related to
the noise figure, operating voltages, Ft and Fmax val-
ues. To accomplish equivalent performance between
SiGe BiCMOS and RF CMOS, the general rule has his-
torically been that the geometry size of the RF CMOS
must be one generation ahead of the SiGe BiCMOS
process. For example, a 0.25- micron RF CMOS would
produce the same available frequency range of a 0.35-
micron SiGe BiCMOS. Figure 2 shows that as the
geometry size decreases, speed increases. This graph
also shows that certain frequencies can only be
reached by using a SiGe BiCMOS process.
Passive Components
Process options should
also be evaluated as
another important con-
sideration. A process
that offers you many
different types of resis-
tors, capacitors and
inductors allows for the
development of an opti-
mized device. The opti-
mization implemented
into most circuits is
based on the matching
and linearity of the pas-
sive devices. The Q val-
ues for inductors should
be evaluated to ensure
high quality. The use of integrated components can
help to reduce the number of external passive compo-
nents and help to save real estate on printed circuit
boards (PCB). Memory requirements for RAM, ROM,
EEPROM and the corresponding densities of the EEP-
ROM can also be a determining factor for processes.
With new complex packaging techniques, stacking an
additional memory chip is a viable alternative if the
process best suited for your design does not offer
memory. The most important aspect of passive
devices is the quality of the models provided in the
design kits.
Independent Parameters
Temperature dependence, matching and DC charac-
teristics are not necessarily SiGe BiCMOS or RF CMOS
process dependent. Design rule manuals and foundry
datasheets give Q values for inductors, resistivity of the
resistors, capacitance density and linearity values for
various capacitors. Linearity is a measure of the out-
put variance in relation to the input, often used in ref-
erence to the gain of a circuit. Linearity is composed of
many different components. Design of a circuit has a
direct impact on the linearity. The size of the circuit
also affects linearity because as the circuit size
increases, the amount
of capacitance also
increases. Temperature
dependence is usually
described as the tem-
perature coefficient
(TC). The TC is a rela-
tionship between a
physical property and
temperature. This value
is usually given for all
passive components
within individual
processes. Process
qualification data will
often provide informa-
tion as to the processes
overall reaction to tem-
perature. Device characterization of your design over
temperature will demonstrate the temperatures your
product will operate at and what effects low or high
temperature will have. However, many AC parameters
can also be affected by temperature. Examples of
these are transconductance and threshold voltages.
The threshold voltage is the minimum gate source volt-
age for a transistor to turn on. Transconductance is the
ratio of the change in the output current to the change
in the input voltage that was caused by the change of
the output current. Transconductance is also known as
mutual conductance. Transconductance will vary from
process to process, although SiGe BiCMOS tends to
have better transconductance properties than RF
CMOS. The quality of matching is often determined by
the quality of the passive parameters. Matching
enables maximum power dispersion between multiple
circuits.
Conclusion
Change can be good. With a thorough understanding
of RF design and the available processes, your designs
can be placed on a well- suited process. Foundries will
often give you recommendations on the process that
will best fit your design and allow you to evaluate their
design kits. Evaluating the models in the design kits
will allow you to see Ft and Fmax curves, models for all
different passives and possibly even models of test cir-
cuits, such as voltage- controlled oscillators and low-
noise amplifiers. Test circuits of your design that are
run on multi- project wafers can help you to determine
the quality of the models for the process and the
process passives you are using. If your designs are
mostly analog and have specific performance needs
that cannot be met by the RF CMOS processes, SiGe
BiCMOS might be the right path. If your design is
largely digital and performance is not the main criteria,
RF CMOS might give you a reduced die size and lower
cost. Design and process evaluation will help ensure
that your projects will be high quality and low risk,
while meeting budgets and schedules. Unfortunately,
deciding on a process does not have a clear- cut
answer. The answer is it depends, and the best guar-
antee for true success, with the lowest cost per square
millimeter, is to examine and evaluate different
processes from different foundries.
About the Author
David Hess joined Atmel in 2000. Mr. Hess has worked in a
variety of engineering positions during his career with Atmel.
Mr. Hess is currently in Product Marketing for the SiGe
BiCMOS/ RF CMOS Foundry organization in Colorado Springs.
Prior to joining Atmel, Mr. Hess served as an engineer for
Philips Semiconductors working with different technologies
including RF BiCMOS. Mr. Hess has also held engineering
positions with Electrotech and Varian SEG. Mr. Hess received
his B.S. degree in Electrical Engineering from the University of
New Mexico and his M.S.E.E. degree from the University of
Colorado.
Average Mask Counts per Generation
M
a
r
k

C
o
u
n
t
Geometry Size (m)
SiGe BiCMOS
RFCMOS
60
50
40
30
20
10
0
0.5 0.35 0.25 0.13 0.09
Average Highest Achievable Frequency per
Geometry Size
F
r
e
q
u
e
n
c
y

(
G
H
z
)
Geometry Size (m)
SiGe BiCMOS
RFCMOS
0.5 0.35 0.25 0.13 0.09
18
15
12
9
6
3
0
Fi gure 1: Average Hi ghest Achi evabl e Frequency per Geomet r y Si ze
Fi gure 1: Average Mask Count s per Generat i on
By: Markus Schmid, Atmel
The number of electronic components in vehicles has
increased rapidly and continuously during recent years.
On the one hand many new sensors and actuators and
therefore new electronic control units have been devel-
oped to make passengers feel safer. On the other hand,
entertainment and navigation systems have made their
way into cars to make travel more comfortable.
To meet the design challenges due to the different
requirements (capacitance, real- time operation and
cost), several new bus systems have been developed or
improved. This article will provide an overview on some
of the most important bus systems currently used in
cars: CAN, LIN, FlexRay and MOST. The article
focuses on each bus system' s application area and the
provided protocol.
In a car, there are several operating fields with different
requirements regarding the corresponding bus system.
Each of the bus systems mentioned above is used to
serve a certain communication requirement between
the automotive electronic components. The designer
selects the appropriate bus system depending on the
required safety level, the data transmission rate and the
costs. For example, the CAN bus - even though it is
currently the most important automotive bus system -
is not well- suited for very fast data transmission as
needed for multimedia applications. Also, the CAN bus
system is too sophisticated, and therefore too expen-
sive for applications with low data rates, where only few
parts of the system are involved in the transmission, for
example sun roofs or heating systems. For these appli-
cations, new bus systems have been designed.
FlexRay, CAN, and LIN are mainly used for control sys-
tems, whereas MOST is used for telemetric applica-
tions.
MOST - Media Oriented Systems Transport
The MOST bus was developed in 1998 under the lead-
ership of BMW and DaimlerChrysler for all kinds of
automotive multimedia applications such as audio,
video, navigation and telecommunication systems. In
August 2004 the new specification 2.3 was released.
The MOST bus features a very high data rate of up to
24.8 Mbit/ s in synchronous and 14.4 Mbit/ s in asyn-
chronous transmission mode. It has an additional
asynchronous control channel with a data rate of up to
700 kBit/ s. These high data rates make the MOST bus
the best fit for real- time audio and video transmission
applications. To ensure a safe data transmission, an
optical medium (Plastic Optic Fiber, POF), which is not
susceptible to EMC, is used as physical layer.
Furthermore, MOST bus systems support plug&play of
up to 64 nodes, which can be arranged in ring, star or
chain topology. This enable to connect all parts of a
MOST bus system, the so called MOST devices, in a
very flexible way.
MOST Communication
In a MOST network, one device needs to be determined
to be the master of the network. This device will be the
so- called Timing Master, and all other connected
devices are slaves.
The organization of a data transfer according to the
MOST specification is shown in Figure 2.
For control data transport tasks and network manage-
ment, the organization of data transfer in blocks of
frames is required. 16 frames are combined in one
block, each frame consists of 512 bits.
Table 2 (see next page) provides an overview on the
content of these 512 bits.
Synchronous Data
The synchronous area is mainly used for real- time data
transmission like
audio/ video or sen-
sor values. Data
access is realized by
using Time Division
Multiplexing (TDM).
Physical channels
can be allocated for
a certain time while
playing an audio
source for example.
It is possible to vary
the band- width by
allocating any num-
ber of bytes to one
logical channel. To route the synchronous data to the
appropriate sink, a routing engine is used.
The number of synchronous data bytes in one frame is
limited to 60 bytes.
www. at mel. com
page 29
Aut omot ive Bus Syst ems
THIS ARTICLE WILL PROVIDE AN
OVERVIEW ON SOME OF THE MOST
IMPORTANT BUS SYSTEMS CURRENTLY
USED IN CARS: CAN, LIN, FLEXRAY
AND MOST, AND FOCUSES ON EACH
BUS SYSTEM' S APPLICATION AREA
AND THE PROVIDED PROTOCOL.
Tabl e 1: Bus Syst em Over vi ew
LIN CAN FlexRay MOST
Application Low-level Soft real-time Hard real-time Multimedia,
communication systems systems (X-by-wire) telemetrics
systems
Control Single-master Multi-master Multi-master Timing-master
Bus Access Polling CSMA/CA TDMA/FTDMA TDM/CSMA
Bandwidth 19.6 kBit/s 500 kBit/s 10 Mbit/s 24.8 mbit/s
Data Bytes per 0 to 8 0 to 8 0 to 254 0 to 60
Frame
Redundant Not supported Not supported Two channels Not supported
Channel
Physical Layer Electrical Electrical Optical, electrical Mainly optical
(single wire) (twisted pair)
realized by using Carrier Sense Multiple Access
(CSMA), which offers fixed and predictable response
times. Although a complete control data message is
32 bytes long, only two bytes can be transmitted in one
frame. This means that one block (16 frames) is need-
ed to transmit one control data message.
The structure of a control data message is shown in
Table 4.
FlexRay
FlexRay was developed under the leadership of BMW
and DaimlerChrysler in 1999 especially for the new X-
by- wire systems, such as steer- by- wire systems or
brake- by- wire, which
require a very good
error management
along with high
transmission data
rates. Atmel is also a
member of the
FlexRay consortium,
which released the
latest specification
2.0 in June 2004.
FlexRay is based on
the communication
system byteflight ,
which was devel-
oped by BMW earli-
er. To meet the
requirements of the
new bus systems,
the byteflight
method has been
improved in terms of
chronological deter-
ministic and fault tol-
erance.
FlexRay supports
data transmission
with a bandwidth of up to 10 Mbit/ s and is thus well-
suited for real- time operation. There is no need for a
special physical layer, therefore, electrical and optical
transmission mediums are supported by FlexRay.
Furthermore, FlexRay is suited for several network
topologies such as bus, star, cascaded star and hybrid
network topologies.
FlexRay Communication
CAN supports CSMA (Carrier Sense Multiple Access),
which means that every device starts a transmission as
soon as no other device is sending. Since each device
has different priorities, collisions on the bus will not
occur. On the other hand, this prevents exact predic-
tion of which time the sent data will be received (non-
deterministic).
In contrast to that, FlexRay supports TDMA (Time
Division Multiple Access). Each device has a fixed time
window (time slot), during which the device has exclu-
sive access to the bus. These time slots are repeated
in a fixed pattern.
Using TDMA, it is possible to exactly predict the time
when the data will be received by the bus (determinis-
tic bus access). To properly handle that kind of com-
munication, however, all nodes need to have the same
global time.
Figure 3 shows an example of a typical data transmis-
sion using FlexRay with four components. Two out of
the four (device A and device C) have a redundant sec-
ond channel.
The second channel can be used for redundant trans-
mission (C1 in figure 3) or for the transmission of two
messages at the same time (A1 and A2 in Figure 3).
The devices B and D are only connected to channel 1,
so that the corresponding time slot on channel 2 elaps-
es without being used.
If a device has exclusive access to the bus, but has no
data to be sent, the designated time elapses without
being used. In this case, the bandwidth is not used
efficiently. If a device, however, has to send more data
than fits into one time slot, the device needs to wait
until it has exclusive access to the bus again to send
the rest of its data. To avoid this, FlexRay splits the
communication cycle into a static and dynamic part.
The fixed time slots are designated in the static part,
whereas the dynamic part has additional time slots, the
so- called mini- slots, during which the exclusive bus
access is limited for a short time. Only if a bus access
occurs within this time, the mini- slots will be enlarged
as necessary. This method helps to increase the effi-
ciency of the bandwidth.
The message structure is shown in Figure 4 and a
short description is given in Table 5.
LIN - Local Interconnect Network
In contrast to FlexRay, which serves more sophisticat-
ed application needs than CAN, LIN has been devel-
oped for less complex networks, where CAN would be
www. at mel. com
page 30
Asynchronous Data
If asynchronous data needs to be sent in addition to the
synchronous, the boundary descriptor has to be set as
described in table 2 to ensure that the beginning of the
asynchronous data can be determined exactly.
Asynchronous data transmission is mainly used for larg-
er- sized blocks and if larger band- width is required.
The number of asynchronous data bytes on an asyn-
chronous channel is limited to 48 bytes when using the
48 byte data link layer. when using an alternative data
link layer, the maximum packet length is 1014 bytes.
The structure of an asynchronous area in a frame is
given in Table 3.
Control Data
The control data is mainly used for the communication
between the separate nodes of the bus. Data access is
Fi gure 2: MOST Communi cat i on
1 block consists of 16 Frames
1 Frame consists of 512 Bits
synchronous or
asynchronous data
0 ... 480 bits
control
frame
16 bits
Frame
control
7 bits
Parity
1 bits
Boundary
Descriptor
4 bits
Preamble
4 bits
NAME BITS DESCRIPTION
Preamble 4 Synchronizes the MOST core and its internal functions to the bit stream
Boundary 4 If synchronous as well as asynchronous data is transmitted in one
descriptor frame, the boundary descriptor marks the number of 4 byte blocks of
data used for synchronous data in the data block. For example, if 40
bytes of synchronous data and 20 bytes of asynchronous data are
transmitted, the boundary descriptor will be set to 10 by the timing
master
Synchronous or 0...480 See chapter Synchronous Data and chapter Asynchronous Data
Asynchronous data
Control frame 16 See chapter Control Data
Frame control 7 Frame control and status bits
Parity 1 Error detection
Tabl e 2: MOST Frame Archi t ect ure
NAME BITS DESCRIPTION
Arbitration 8 Avoids collisions on the bus
Target 16 When transmitting asynchronous data, the target address has to be transmit-
address ted, too.
Length 24 Length in four byte blocks
Source 16 When transmitting asynchronous data, the source address has to be transmit-
address ted, too.
Data area 0...384 The actual data
CRC 32 Cyclic redundancy check
Tabl e 3: Message Format i n t he Asynchronous Area
www. at mel. com
page 31
too expensive. The LIN specification was
defined by a consortium with the initial
members BMW, DaimlerChrysler, Audi

,
Volvo, Motorola, VW

and Volcano. Atmel

joined this consortium in 2001. After hav-
ing gathered additional experience, the LIN
consortium released the new LIN 2.0 spec-
ification in September 2003.
Typical LIN bus applications include the
connection of intelligent actuators or sen-
sors, such as small motors, temperature or
rain sensors, sun roof or heating control.
For these applications, high transmission
data rates or complex fault management
are not necessary.
This is why LIN supports only data trans-
mission of up to 19.6 kBit/ s. For this data
rate, a cost- effective 12 V single wire is
sufficient as transmission medium.
LIN is based on an SCI (UART) 8- bit inter-
face and supports the Single-
Master/ Multiple Slave concept. UART inter-
faces are available in almost every micro-
controller or ASIC,
and can be implemented in almost any software or
firmware. due to this, there is no need for the use of
other expensive external components. A typical LIN
cluster with one master node and three slave nodes is
illustrated in Figure 5.
It is obvious that the master node performs both a mas-
ter task as well as a slave task.
Due to the simple concept, no node within the LIN net-
work, except the master, will be influenced by adding or
removing another slave. In this case, the only neces-
sary changes concern the master node.
A special feature of LIN is the synchronization mecha-
nism which adjusts the clock rate of the slave nodes to
the master without an external crystal or resonator.
Thanks to the simplicity of the UART communication,
the single- wire transmission and the simplicity of the
clock rate adjustment, a LIN bus system is very cost-
effective.
LIN Communication
The structure of a LIN Bus Message Frame is illustrat-
ed in Figure 6.
Every LIN Bus Message Frame starts with the header
sent by the master. This header consists of a Break
byte field, the Synch byte field and the protected iden-
tifier. Before the slaves send the requested response,
there is a short stop, the so- called response space. the
interframe space at the end of each frame pulls the LIN
bus to high level until the break byte of the next frame
will force the bus line to low level again.
NAME BITS DESCRIPTION
Arbitration 24 Avoids collisions on the bus
Target 16 When interchanging control data between separate nodes, it is important to
address specify the target node.
Source 16 When interchanging control data between separate nodes, it is necessary to
address identify the source node.
Message 8 There are two different message types. Normal messages include single cast,
type group cast and broadcast, system messages include resource allocate,
resource de-allocate and remote getsource.
Data area 0...136 The actual data
CRC 16 Cyclic redundancy check
Transmission 16 Indicates the current status of a transmission
status
Reserved 16 Reserved for further protocol use
Tabl e 4: Message Format i n t he Cont rol Frame
Fi gure 3: Exampl e of a Typi cal Dat a Transmi ssi on wi t h Four Bus Devi ces Usi ng Fl exRay
Fi gure 4: Message Archi t ect ure i n Fl exRay
Header segment Payloadsegment (0... 254bytes)
Cycle
count
6bits
Header segment
FlexRayFrame (5+(0... 254) +3bytes)
Fi gure 5: Typi cal LIN Bus Archi t ect ure
Fi gure 6: LIN Bus Message Frame
Frame slot
Frame
Header Response
Synch
Break
DATA 1 DATA 2 DATA N Checksum Interframe
space
Break
Response
space
Protected
identifier
Each slave is in alert state as soon as it detects the
Break byte field. The following Synch byte field syn-
chronizes the slaves with the master for the following
transmission. The Synch sequence is always a byte
field with the data value Ox55, so all slave noes within
the network can easily synchronize to the clock of the
master by detecting the edges of this signal.
Apart from the Break byte field, which is indicated by a
low level on the LIN bus for at least 13- bit times fol-
lowed by a high level for at least one bit time, all other
byte fields n a LIN message are constructed as shown
in Figure 7.
At the beginning, there is a low level start bit which is
known by almost any UART- based communication,
followed by eight data bits with the LSB first. The byte
field is completed with a stop bit.
The protected identifier consists of six identifier bits
and two parity bits, so there are 64 different identifiers
within one LIN network.
The structure of the protected identifier byte field is
shown in Figure 8. According to the protected identi-
fier and after the response space, a slave begins to
send the requested response, or it expects more data.
this response may contain up to
eight data byte fields plus one
checksum byte field.
With the release of the LIN2.0
specification, a new checksum
calculation has been introduced.
To enable compatibility to the still
used LIN1.3 specification, the
previous type of checksum cal-
culation is also supported by
LIN2.0. The new checksum is
called enhanced checksum and
is calculated by the inverted eight
bit sum along with the carry bit
over all data bytes plus the pro-
tected identifier. The LIN1.3
checksum is called classic
checksum and is calculated as
described above, but without the
protected identifier.
www. at mel. com
page 32
NAME BITS DESCRIPTION
A = Reserved bit 1 This bit is reserved for future protocol use and may not be used by the application.
B = Payload preamble 1 This bit is used to indicate whether or not an optional vector is contained within the payload segment. This vec-
indicator tor is a network management vector if the frame is transmitted in the static segment or a message ID if the frame
transmitted in the dynamic segment.
C = Null frame indicator 1 If this bit is set, the message included contains no useable date in the payload segment.
D = Sync frame indicator 1 If this bit is set, the frame is used to synchronize all receiving nodes.
E = Startup frame 1 This bit is used to indicate whether or not a frame is a start-up frame.
indicator
Frame ID 11 This ID defines a certain slot in which the frame should be transmitted.
Payload length 7 These bits determine the number of data bytes transmitted in the payload frame by setting the payload length bits
to the number of the data bytes divided by two.
Header CRC 11 The Sync frame indicator, the start-up frame indicator, the frame ID and the payload length contribute to the
6 Header CRC.
Cycle count These bits contain the number of the current communication cycles.
Payload segment 2032 In that segment the data will be transmitted. It can contain up to 254 bytes (0...127 two-byte words).
CRC 24 This cyclic redundancy check uses the complete header segment as well as the complete payload segment.
Tabl e 5: Descri pt i on of Message Archi t ect ure i n Fl exRay
Fi gure 7: St ruct ure of a Byt e Fi el d i n a LIN Message Frame
Start
bit
Bit 0
LSB
Bit 7
MSB
Stop
bit
Byte field
Fi gure 8: St ruct ure of t he Prot ect ed Ident i f i er
Start
bit
Stop
bit
IDO ID1 ID2 ID3 ID4 PO P1
By: Dr. Martin Alles, Atmel
Digital Audio Broadcast (DAB)
Digital audio broadcast is the preferred
technology to replace common FM
radio broadcast in the future; currently,
over 300 million people around the
world can receive nearly 600 DAB
services. DAB offers various advan-
tages compared with todays FM sys-
tems. the digital transmission of audio
data allows the DAB system to deliver
near DC- quality stereo sound even to
mobile receivers with a reliability and
robustness which is unthinkable with
today' s FM broadcast system. Another
important advantage of the DAB sys-
tem is that it was designed to carry data transmissions
and program associated data (PAD). The usual DAB
transmission system is especially optimized for auto-
motive applications, i.e., a moving receiver with speeds
of up to 200 km/ h, and using a simple rod antenna.
Todays FM reception is often distorted or interrupted
by multi- path interference, especially when using mov-
ing receivers. The main cause of this behavior is reflec-
tions from hills and buildings, which arrive out of phase
with the main signal and lead to distortions of the fre-
quency modulated carrier; in contrast, DAB uses long
symbol times and special guard intervals. However,
this protection against multi- path propagation leads to
a reduced transmission rate. To compensate for this
behavior the DAB standard uses several carriers at the
same time, a method called the multi- carrier orthogo-
nal frequency division multiplex (OFDM) transmission
standard. the remaining effects from reflections due to
multi- path propagation are used in the DAB transmis-
sion technique to reinforce the main signal, as shown
in Figure 1.
The DAB transmission system is specified with four dif-
ferent modes (see www.worlddab.org for more infor-
mation on the different modes), with each of these
modes optimized for different applications and fre-
quencies. the most important modes are mode I for
terrestrial single frequency network (SFN), used for
overall DAB transmission, and mode II for medium-
scale networks with limited range. All modes are sup-
ported by Atmel' s DAB chipset.
Atmels DAB solution
Atmel offers a complete DAB chipset containing three
highly integrated ICs for DAB reception. The chipset
includes two ICs which cover the analog functions of a
DAB tuner (U2730B, U2731B) and a baseband IC. The
block diagram of a complete DAB receiver is depicted
in Figure 2 (see next page) and the tuner portion of the
receiver is discussed in detail below. Obtaining a total
DAB solution from one supplier optimizes performance
and low bill of materials (BOM), since all ICs match
each other in an ideal way.
The baseband IC (ATR2740) contains a channel
decoder, a source decoder, and a data decoder. The
baseband is responsible for fast Fourier transformation
(FFT, Viterbi decoding, data processing and source
decoding.
The tuner application using the two ICs is optimized
and developed using automotive requirements and
quality standards. The Atmel DAB solution includes
standard interfaces for car audio (CAN, RDI), portable
(keypad, LCD), home (SPI, RS232), and PC
applications.
Atmel DAB Tuner ICs
The Atmel DAB tuner contains
two ICs which convert the DAB
signals to a fixed IF frequency:
the one- chip DAB- receiver IC
U2731B and the L- band
down- converter IC, U273OB.
www. at mel. com
page 33
At mels Complet e Chipset f or DAB
Recept ion in Aut omot ive Environment s
THIS ARTICLE PROVIDES AN OVERVIEW
OF ATMEL' S ADVANCED DAB CHIPSET,
WHICH ALLOWS THE REALIZATION OF A
COMPLETE DAB RECEIVER (EMPHASIS IS
PUT ONLY ON THE TUNER PORTION OF THE
DAB RECEIVER).
Fi gure 1: Mul t i - pat h Propagat i on f or DAB Transmi ssi on Syst ems
can also be used to control an external LNA or attenu-
ator.
The functionality of the U2730B is completed with a
low- power mode, which disables the AGC loop and the
internal VGA and mixer. The oscillator and the PLL loop
remain active even in low- power mode to offer very fast
switching from VHF BIII (175 MHz - 240 MHz) reception
to L- band reception.
A DAB Tuner Using Atmel ICs
The simplified block diagram of the DAB tuner for VHF
BIII and L- band reception using both ICs is illustrated in
Figure 3; Figure 4 shows a photograph of the actual
tuner PCB.
The DAB tuner uses external LNAs for VHF BIII and L-
band reception. Both LNAs are included in the AGC
loops that are controlled from the U2730B or the
U2731B. One of the switches included in the U2731B
is used to toggle between VHF BIII reception and L-
band reception, it selects the external LNA and switch-
es the U2730B down- converter IC to low- power mode.
The DACs are used to control the automatic tuner
alignment (ATA); this special technique is used in the
Atmel tuner ICs to realize an automatic channel selec-
tion with out further alignment. The main advantage of
the ATA is the good channel selectivity which leads to
excellent performance of the tuner. The ATA uses var-
actors to adjust the center frequency of a tunable band
filter to the desired frequency in the reception band.
Since the 3- dB bandwidth of this filter is about 6 dB, it
is possible to have good selectivity even before enter-
ing the SAW filter. More details can be found in the
application note DAB Tuner with U2730B and
u2731B , on Atmels website, www.atmel.com.
www. at mel. com
page 34
The U2731B contains all necessary functionality in
order to convert DAB signals in the frequency range
175 MHz - 240 MHz to a fixed IF frequency. The signal
path for the IC includes an input amplifier with variable
gain, and a down- converter to a fixed IF of 38.912 MHz
with an integrated SAW driver.
After passing the SAW filter, the signal is again ampli-
fied in a VGA and, optionally, down- converted. The
U2731B allows an IF frequency of 38.912 MHz, 38.912
MHz - ref. frequency or 38.912 MHz - 2x ref. frequen-
cy, depending on the customers demands according to
the baseband chip used. An integrated AGC loop con-
trols the RF power at the SAW filter by adjusting the gain
of the internal VGA and an external VGA or variable
attenuator. Another AGC loop adjusts the gain of the
VGA at the IF output port of the U2731B in order to
deliver optimum IF output power.
The timing of both AGC loops can be adjusted inde-
pendently, leading to good channel selection and excel-
lent selectivity, i.e., protection against adjacent channel
power and other distortion sources. The incoming RF
signal is fed via one of the two RF inputs into the
U2731B.
The IC includes a VCO and a fractional PLL circuit for
the generation of the necessary LO signal, which is
locked to the integrated quartz oscillator or an external
reference frequency. The reference frequency signal is
available at an output pin in order to be connected to
the U2730B, if present.
The functionality of the IC is complete with three switch-
es and three DACs, which are used for the automatic
tuner alignment.
All functionality of the U2731B is controlled with a two-
wire bus from the baseband.
To add L- band (1.452 to 1.492 GHz) DAB reception to
the tuner, it is necessary to use the U2730B. This IC
includes a mixer for down conversion of the incoming
signal from L- band to a frequency range which can be
processed by the U2731B. The IC contains a PLL con-
trolled oscillator for the generation of the LO signal and
a VGA, which is included in an AGC loop. This AGC loop
Fi gure 2: At mel DAB Recei ver f or VHF Bi l l and L- band Recept i on (Si mpl i f i ed)
Fi gure 3: DAB Tuner Usi ng U2730B and U2731B (Si mpl i f i ed)
VHFBill
175MHz- 240MHz
L-band
1452MHz- 1492MHz
L-band
down-
converter
ref. fequency
two-wirebus
baseboard
VHFBill
175- 240MHz
L-Band
1452- 1492MHz
SAWfixedIF
38.912MHz
IFout,e.g.
2.048MHz
Fi gure 4: Phot ograph of t he At mel DAB Tuner
www. at mel. com
page 35
The signal flow through the tuner for VHF BIII reception
is as follows: The antenna signal is first band- pass fil-
tered with a tunable filter which is adjusted using the
VCO voltage and one of the DACs. The external gain
controlled LNA amplifies the signal, which is then again
band- pass filtered with the next tunable filter using the
other two DACs and the VCO voltage. The signal enters
the U2731B using RF port 1. It is amplified using the
internal VGA. The following mixer converts the incom-
ing signal to a fixed IF of 38.912 MHz. This is done by
adjusting the VCO and the PLL to a desired LO fre-
quency. The DAB signal enters the SAW filter which
removes all signal parts outside the adjusted DAB
channel. Finally, the signal again enters the U2731B
for an additional VGA stage and an optional mixer
stage.
The signal flow for L- band reception includes an exter-
nal LNA with adjustable gain and a fixed band- pass fil-
ter. This signal is fed to the U2730B, where it is again
amplified with a VGA and down- converted to a fre-
quency range of 190 MHz - 230 MHz. This signal is
band- pass filtered with a tunable filter using two DACs
and the VCO voltage of the U2731B. The signal is fed
to the RF port 2 of the U2731B and follows the above
described signal flow for VHF BIII.
Design Hints
Since the DAB signal is an OFDM signal with a band-
width of about 1.5 MHz, it is important that the ampli-
fiers and mixers used inside and outside the ICs have
excellent linearity. The tunable filters and the SAW fil-
ter used should have low frequency response in the 1.5
MHz bandwidth of the DAB signal in order to limit fre-
quency distortion.
The described tuner has a noise figure of about 3.5 dB
for VHF BIII and less than 5 dB for L- band reception,
and a dynamic range of about 100 dB for both fre-
quency bands. The sensitivity of the DAB receiver
using the described tuner is better than - 95 dBm for
VHF BIII and L- band. Without changing any parts, a
large signal performance of + 10 dBm for both receive
bands can be achieved. the use of an EEPROM is also
recommended, to store the frequency dependent val-
ues for the DACs used in the ATA principle. An EEP-
ROM using, e.g., a simple two- wire bus can be easily
integrated in the DAB tuner.
The modular conception of the DAB tuner with one IC
for VHF BIII reception or two ICs for VHF BIII and L- band
reception allows optimum BOM for both tuner types.
Summary
A lot of different DAB broadcasting services are already
available around the world, and every DAB receiver
needs an RF tuner and a baseband to decode the DAB
signal. The Atmel chipset allows an easy realization of
a DAB receiver with leading performance. The tuner is
the most important key for high quality reception of
DAB signals under difficult conditions, such as occurs
with moving receivers.
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Rolling Shutter Description
With a rolling shutter sensor:
Integration time occurs just before the readout of
each line
The readout resets the pixel content
Therefore the integration time for each line is not done
at the same time.
Depending on the required speed, the chosen integra-
tion time might be longer or shorter than the frame
readout time.
By: Jacques Leconte, Camera & Application
Development Manager, Atmel
Do you think shutter is a brand new question which
appeared with digital photography? Well just con-
sider this old well- known picture made with a roller-
blind shutter by Jacques Henry Lartigue (a French pho-
tographer in the early twentieth century).
What happened? The camera was moving horizontally
during the image grab to follow the car. Due to the
irregular camera movement, the static subjects seem
to lean over while the wheel in motion still reflects a
geometric distortion (the camera should have been
moving slower). Comparatively drivers are well grabbed
with no distortion at all.
When grabbing images a shutter is required in partic-
ular with objects in the scene moving too fast com-
pared to the integration time. The effect of the blur
obtained is well known when the speed is too slow dur-
ing the shooting of pictures with moving objects.
The camera speed or, for industrial camera users, the
integration time must be chosen so that the image of
the object may not move more than one pixel (for
example) during the exposure time.
The blur is easy to explain, but what about distortion
effect? This article describes the advantages and
drawbacks of two existing solutions in the progressing
scan sensor area: the rolling shutter and the global
shutter.
Image Readout
In progressive sensor areas, each line is read one after
the other.
www. at mel. com
page 37
Areascan Cameras: How t o Choose
Bet ween Global and Rolling Shut t er
www. at mel. com
page 38
Global Shutter Description
With a global shutter, all lines have their integration time
simultaneously.
A global reset is done just before starting the readout
At the end of integration the pixel content is stored in
memory
Then the readout may start
Characteristics of Each Solution
Rolling Shutter Characteristics
The rolling shutter pixel structure is the easiest solution
to implement. Only three transistors are needed at pixel
level. This allows a good signal- to- noise ratio. Micro
lenses used to optimize the fill factor (% of the pixel
array sensitive to light) are much easier and more toler-
ant when using wide aperture lens.
The main drawback of the rolling shutter is the image
distortion when an image of a moving object is grabbed
and if the integration time is too short in comparison
with the readout time.
Next an example of image distortion of a moving object
analyzed with a rolling shutter fixed camera.
As shown below, the helmet at the above part of the
image will be integrated first and then the bottom part
at the last time. Therefore between these two exposure
times the object has moved.
This will cause a distortion on the grabbed image.
We can notice that in order to reach this distortion this
picture is shot at full field with a square sensor. The
speed of this object is approximately 1 m in 20 ms
(resulting from a maximum frame rate of 50 image per
second), or 180 km/ h / 112 miles/ h.
An other example on a sun pattern grabbed with the
Atmos camera with a speed rotation of 85T/ mn and
1ms integration time/ 20ms readout time:
After the pattern drawing on the left, the first image
with no rolling shutter effect shows that the lines are
straight. On the second image, with the rolling shutter
effect and the same integration time we can notice that
the lines are bent.
Global Shutter Characteristics
To perform the global shutter function, a memory
area must be used beside each pixel. Here below an
example with an additional single transistor.
This memory zone must be non- sensitive, which
means there is no light leak.
In fact, on the available components nowadays, this
memory zone is always sensitive to light and sometime
very sensitive. We may find global shutter with the
worst ratio of 1/ 15, while standard ratio ranks from
1/ 200 to1/ 500 and last best ratio announced today is
1/ 5000.
For family pictures this may be acceptable. However
this is not sufficient in most high demanding industrial
applications. Therefore an electrical shutter seems to
be a very good solution. In the case of a global shutter
the user does not have to take care of light conditions
The effect of a bad shutter efficiency level is shown in
the following pictures. A bright white point is moving
from left to right during readout. On the right of the
white point an ghost image may be visible. Contrast
and size of the ghost image will depend of the speed
and of the shutter efficiency itself.
When working with a 12- bit resolution, the global shut-
ter at a ratio better than 1/ 4000 is necessary as to
avoid any wrong information that might be generated.
During the image readout the light of path continues to
move illuminating the memory zone of the sensor thus
creating a brighter light intensity.
This ratio should be divided as follows:
By the over- saturation factor you may have on the
image (x 100 even x 1000) when metallic reflections
occur
And also by the ratio between the integration
time to the longest memory time as an example with
a 10 ratio
Meaning a 1/ (4 10
6) ratio, which is not feasible today.
The memory zone is built using room at pixel level (by
adding one to three transistors) which results in
Before buying or building a vision system the image
quality required must be defined. If no ghost image and
no distortion is allowed the light will have to be pulsed.
Therefore the shutter type is not a key feature. The
user needs to be able to synchronize the light pulse.
Therefore the camera must offer either a light output
signal or an input trigger.
Atmel cameras provide these two possibilities. Both the
Atmos 1M30/ 1M60 and Atmos 2M30/ 2M60 offer high
resolution, high speed with a Camera Link

interface
able to work at 8- 10 or 12- bit.
www. at mel. com
page 39
decreasing the pixel aperture ratio and therefore
requiring micro lenses of higher efficiency. This often
means that micro lenses are less tolerant to telecen-
tricity errors of the image side of lens. These addition-
al transistors may also induce noise. In fact it is a com-
promise between shutter efficiency (increase of num-
ber of transistors) and pixel aperture (decrease of the
number of transistors)
A Solution?
The unique solution is to pulse the light. But if there is
a need for pulsing the light why not choosing the rolling
shutter with its better signal- to- noise ratio and its bet-
ter pixel aperture without micro lenses?
Conclusion
There are already many applications where a type of
rolling shutter is used. Often this parameter is not tak-
ing into consideration by end users:
Example 1:
Roller blind cameras (24 x 36 film camera, for exam-
ple) are still used without any complaint from users.
Example 2:
All the old vacuum tube cameras were using a readout
that reset the pixel.
Example 3:
All line scan cameras are also using different integra-
tion times for each line. To prevent any distortion in this
case, the object speed to the camera speed should be
adjusted.
Based on a rolling shutter sensor these cameras allow
excellent dynamic range. The Atmos 2.5M can capture
48 fps at full resolution, 60 fps at 2M, and 160 fps in
VGA format for the 2M60 thanks to the region of inter-
est function. With a 44 mm square section design, plus
a C- mount adapter, Atmos cameras are among the
smallest in the market.
The Atmos cameras features are particularly suited for
typical machine vision tasks: Inspection (glass, Flat
Panel Display, PCB) robot- guidance, metrology, as well
as various applications such as microscopy or surveil-
lance.
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By: Franois Bor, Sandrine Bruel and Marc
Wingender
1. Introduction
A high- speed ADC that offers good linearity over a
range of high frequency inputs is a key component for
tomorrows broadband RF transmitters using high
Intermediate Frequency (IF) architectures.
New architectures for ADC allow now to reach perform-
ances which were barely conceivable a few years ago.
Broadband IF Sampling ADC architectures are today
capable of directly digitizing wideband signals around
second or first IF zones while keeping excellent lineari-
ty performance, paving the way to Software Radio.
The architectural shift to broadband data conversion
leads to increased ADC sampling rate, creating new
challenges in design, package and test methodology.
A 10- bit 2.2 Gsps ADC has been developed based on a
75 GHz SiGe HBT process, including special features
for better industrial test coverage.
Key issues for design, test and circuit specification,
altogether with characterization results are presented
and analyzed.
2. Purpose of high- speed ADCs
An ADC is used to produce a quantization of a continu-
ous time varying continuous signal, therefore part of the
information included in the input signal will be lost by
this sampling and quantization process (aliasing, quan-
tization noise), and some parasitic information will be
added due to the non ideality of the ADC (aperture
uncertainty, thermal noise, non linearity).
The relevance of an ADC for a given application is its
ability to keep the ratio of useful information over para-
sitic (or undesired) information as high as possible for a
given power budget.
A good ADC must be able to code a small signal close
to a large signal (interferer). This feature is mandatory
for any broadband (multi channel) application were an
ADC is used to code all the channels and the demodu-
lation is performed through digital processing. The con-
straint on the ADC is thus on inter- modulation products
(IMD) which level must be below the smallest signal to
code.
2.1 Relevant parameter for ADC specification
Global parameters such as Effective Number Of Bits
(ENOB) are not always relevant to select the best pos-
sible ADC for a given application. This is especially true
for very high speed ADC (over 1 Gsps), because of the
very large bandwidth of integration, Signal to Noise
Ratio is dominated by thermal noise, and SNR becomes
the dominant factor in ENOB. Therefore ADC displaying
similar ENOB figures may have very different linearity
figures (Spurious Free Dynamic Range and/ or Total
Harmonic Distortion). For instance an ADC featuring
8- bit ENOB can display only 50 dB SFDR while another
would display 60 dB SFDR.
Furthermore, frequency independent and deterministic
non ideal characteristics of the ADC can be compen-
sated by digital signal processing (e.g. look- up table).
For operation at Nyquist (Fin~ Fs/ 2) and above, the
clock phase noise (also called jitter) has direct impact
on SNR. Jitter can be split in 2 components: external jit-
ter (due to the sources used, or potential board routing
issues), and internal jitter (generated in the ADC by
thermal noise on clock path, coupling with other sig-
nals, or poor power supply rejection). Therefore internal
jitter is also a very important parameter of the ADC.
Parameters to consider for a high speed ADC are there-
fore: THD, SFDR, IMD (multitone), SNR, Noise Power
Ratio (for broadband application), ADC added Jitter (for
2nd Nyquist application).
2.2 Parameters for comparison of ADCs
An SNR value is relevant only if considering also the
ADC sampling frequency altogether with the ADC full
scale, combining the three informations we can pro-
duce a relevant indicator of ADC performance, the per
Hz Normalized Noise Floor expressed in dBm/ Hz:
NNF = FS[dBm] SNR[dBFS] 10*log(Fclock/ 2)
Reachable limit of NNF for a reasonable power dissipa-
tion seems to be about - 150dBm/ Hz.
Another relevant indicator of ADC performance is the
quantization energy, that is the energy needed to deliv-
er an effective level of quantization:
EQ= P/ (Fsampling*2ENOB)
where P is the ADC power dissipation.
EQ should of course be kept as low as possible.
Normalized Useful Bandwidth can be defined as:
NUB= Finmax/ Fclock (where Finmax is maximum input
frequency leading to a 3dB degradation of SINAD).
These indicators allow for comparisons between ADC
designed for various domains of operation.
3. Design challenges
As previously discussed a pertinent 10- bit high speed
ADC should meet the following criteria:
www. at mel. com
page 43
A 10-bit 2.2 Gsps ADC Operat ing
Over First and Second Nyquist Zones
Code Pat ch Code Pat ch
THIS PAPER INTRODUCES A 10 BIT 2.2
GSPS (GIGA SAMPLE PER SECOND)
FULLY BIPOLAR ANALOG TO DIGITAL
CONVERTER, DEVELOPED ON A 75 GHZ
CUT OFF FREQUENCY HBT SIGE PROCESS,
DESIGNED FOR OPERATION OVER FIRST
AND SECOND NYQUIST ZONES.
PERFORMANCES OVER 8 EFFECTIVE
BITS HAVE BEEN DEMONSTRATED
UP TO 2 GSPS NYQUIST. THIS ADC,
DISSIPATING ONLY 4.2W, ACHIEVES
A 10- BIT EQUIVALENT LINEARITY FOR
2 GHZ INPUT.
www. at mel. com
page 44
1. Linearity over first and second Nyquist zone:
beyond 57dB SFDR.
2. Good NNF: around or below - 145dBm/ Hz
3. Stable spectral response over sampling rate,
temperature and input frequency to allows for single
look- up table processing.
4. Clock phase noise added by the ADC must be kept
as low as possible.
5. Power dissipated and EQ must be as low as
possible.
6. Bit Error Rate should be kept at a level compatible
with the application (values commonly admitted :
instrumentation 10
- 12, transmission 10- 6).
Items 1 and 2 are related to the internal front end Track
and Hold (T/ H) which is mandatory for Nyquist and
above Nyquist operations, and T/ H clock management
in the ADC, item 3 is related to settling through the
quantifier. Item 4 is related to the clock tree design
strategy. Item 5 is related to the overall design strate-
gy of the ADC, and item 6 is depending on the decod-
ing and logic part of the ADC.
When taking all these factors into consideration two
architectures are possible:
1. A single core ADC
2. A massively interleaved ADC [1]
We have discarded this second option because of clock
jitter management issues. Nevertheless our ADC fea-
tures all the tuning needed to allow for easy interleav-
ing (offset adjust, gain adjust, aperture delay fine
adjust).
3.1 Front End Track and Hold Amplifier
In a fast ADC the front end T/ H is a major design issue.
The performances of the ADC will be dominated by the
performances of the front end T/ H, granted that the
quantifier settles properly in its time slot. Depending on
the front end T/ H, the ADC will be able to operate over
first and second Nyquist zones, over first Nyquist zone
only or in base band only.
Most of the thermal noise is also generated in the T/ H
and associated preamplifiers, so special care must be
taken in the trade- off of power and noise.
The structure retained for the T/ H stage was based on
a fully differential S.E.F (Switched Emitter Follower),
since this structure is well known for its robustness. A
differential output amplifier is used to filter out the
common mode bounces at the T/ H output before driv-
ing the analog quantifier. A gain 2 differential input
amplifier, is used in front of the T/ H in order to be able
to display a constant impedance at the ADC input thus
allowing analog filtering.
The main difficulty is to keep a good linearity over the
second Nyquist zone, since in this frequency domain
closed loop structures are not relevant. We will see in
the result section that performances are quite good.
3.2 Quantifier
Quantifier structure choice is a key issue in the design
of an ADC, specially when we are looking simultane-
ously for speed, accuracy and power efficiency.
Pipeline and sub- ranging architectures are discarded,
because for this sampling range they are not relevant,
especially regarding B.E.R (Bit Error Rate) issue.
A full flash architecture is also not acceptable because
of loading effect caused at T/ H output due to too many
comparators (2
10+ 1), and also because of power
spillage that this architecture would imply.
Finally we retained a successively folded and interpo-
lated architecture which offers the best trade- off
between speed, accuracy and power dissipation.
The MSBs are generated by a coarse cycle pointer, and
are corrected in accordance with LSBs transition in the
logic part. Gain adjustment is made by controlling the
bias of the reference resistor chain.
3.3 Logic part
The function of the logic part in a fast ADC is three fold:
1. Provide a B.E.R. compatible with the specified
application (e.g: 10- 12 for instrumentation).
2. Realize the fusion between MSBs and LSBs
delivered by the quantifier, and eventually correction
of MSBs.
3. Convert the internal coding into Binary code.
3.3.1 Bit Error Rate
The purpose of regeneration latches is to convert ana-
log signals coming from the quantifier into full swing
synchronized logical signals for further processing.
When an analog level coming from the quantifier is very
close to its transition level the regeneration latch will
perform one of the following:
1. Take the good decision and produce a full swing
logical level.
2. Take the wrong decision, and produce a full swing
logical level, depending on the internal coding the
impact can be major (Binary coding, glitch energy 2
N
quantum, where N is the index of the considered bit),
or minor (Gray coding, glitch energy 1 quantum,
because only one bit can be in the danger area at a
time).
3. Take no decision (i.e. meta- stability), or produce a
logic level of reduced swing which jeopardize
subsequent logical operation.
Taking no decision causes B.E.R. In this case the latch
does not have enough time to generate a true logical
level from analog signal coming from the quantifier,
thus jamming the subsequent decoding.
With an increase in the sampling rate, B.E.R is a major
issue which cannot be neglected. To minimize B.E.R. it
is necessary to use latches which have very low diver-
gence time constant, and/ or to spread the divergence
over several half clock period.
3.3.2 Merging of MSBs and LSBs
The second function of the logic part is to combine
information coming from the MSB (coarse) and LSB
(fine) sections, in order to produce a full length word.
This function performs a correction of the coarse (inac-
curate) transitions in accordance with the fine (accu-
rate) transitions. We have been using this method suc-
cessfully for many years beginning with TS8388 [2]
(8- bit 1 Gsps ADC), released in 1997.
The NRZ function is also performed in this logic block.
This function makes sure that underflow (or overflow
respectively) will not produce codes other than the min-
imum code (or maximum code respectively).
3.3.3 Binary encoding
The code conversion from Gray code to natural Binary
code is rather straightforward: a cascaded XOR from
MSB to LSB. To avoid limitations due to propagation
ripple in this decoding, we have spread the decoding
over one and a half clock periods. This decoding circuit
includes a multiplexer, in order to be able to deliver also
Gray code at the output of the ADC.
The output of this decoder is feeding a master slave
bank of latches driving differential ECL / LVDS compat-
ible output buffers.
3.4 Clock tree
For a fast ADC operating in second Nyquist zone, the
jitter observed on the switch of the T/ H amplifier can
dramatically degrade the performances in term of SNR.
Special care has been taken in the design of:
the clock circuitry in order to minimize the jitter
induced on chip,
the package which was optimized to avoid coupling
between the clock and other unclean signals, al-
together with thermal management optimization [3].
The first idea is to use a fully differential circuitry in
order to have optimal rejection of power supply ripple,
and to induce as little as possible power supply ripples.
The second idea is to use internal clock edges as steep
as possible in order to minimize the thermal noise
effect at each stage of the clock path. For the same
reason the clock driving the T/ H switch must be kept as
sharp as possible.
There is a direct relationship between internal clock
edge sharpness, fastest transient (or maximum signal
frequency) to digitize and acceptable thermal noise
level in clock circuitry to meet a specified SNR level.
All the structures used in the clock tree have already
been proven in our former 10- bit 2Gsps ADC
TS83102G0 [4]. The measured jitter including board,
generator and ADC, based on locked histogram method,
using very good generators is about 150fsrms.
www. at mel. com
page 47
A test mode provides special clocking for output latch-
es, decimating by 32 the converted data, thus deliver-
ing a word rate compatible with industrial test.
4. ADC main features
This ADC is now introduced as a standard product ref-
erenced AT84AS008 [5], it is mechanical and electrical
compatible with TS83102G0, but offers extended per-
formances and extended functionality domain while
saving 10% of power, thus allowing seamless upgrade
of system designed with TS83102G0.
Die size: 14.7mm
2
Process: SiGe HBT 75GHz cutoff, 3 layers of metal
Max Sampling Rate: 2.2 Gsps
Full Power Input Bandwidth: 3.5 GHz
Full Scale: 500 mVpp diff (tunable + / - 10%).
Power dissipation: 4.2 W
Package: CBGA152, pitch 1.27 mm.
5. Characterization results
Test characterization has demonstrated very good
operation over first (Figures 2, 5) and second (Figure 3)
Nyquist zones up to 2.2 Gsps, ENOB at Nyquist is over
8.0 bits up to 2 Gsps.
Characterizations demonstrated also a good perform-
ance stability over a wide temperature range (Figure 4
& 5).
6. State of the art survey
Using NNF and EQ indicators, as defined in section 2.2,
we have compared our performances with other com-
mercial, or published ADCs.
For ADC operating at medium frequency the use of
large full scale input allows for a significant enhance-
ment of NNF when expressed in dBFS/ Hz. Full scale
increase is not possible at higher frequency for practi-
cal reasons (linearity and power dissipation impact).
Fi gure 1: Vi ew of t he ADC l ayout
Fi gure 2: SFDR, THD, SNR, SINAD vs Fcl ock at Nyqui st , Ai n= - 1 dBFS
Fi gure 3: SFDR, THD, SNR, SINAD vs Fi n at Fcl ock= 2 Gsps, Ai n= - 1 dBFS
Fi gure 4: SFDR, THD, SNR, SINAD vs Tj at 1.7 Gsps, Fi n= 848 MHz, Ai n= - 1 dBFS
www. at mel. com
page 48
Fi gure 5: 32k poi nt s FTT spect rum at 2 Gsps, 995 MHz, Ai n= - 1 dBFS
Ref erence Resol ut i on & E
Q
NNF FS NUB
Sampl i ng rat e [ pJ] [ dBm/ [ dBm]
Hz]
[1] 8 bit 20 Gsps 7.8 - 138 - 2 0.1
Thi s work 10 bi t 2.2 Gsps 8.2 - 144 - 2 > 1
[4] 10 bit 2 Gsps 13.6 - 143 - 2 1
[6] 8 bit 1.5 Gsps 27.2 - 140 - 2 0.8
[7] 12 bit 210 Msps 5.1 - 137 + 7.5 0.9
[8] 12 bit 185 Msps 2.4 - 137 + 10 1
[9] 14 bit 105 Msps 3.8 - 141 + 11 0.8
Tabl e 1: Publ i shed or commerci al ADC sur vey
This survey from commercial and published results
indicates that at least one of the three parameters EQ,
NNF and NUB degrades with max sampling frequency.
7. Conclusion
We have designed a fast ADC for Nyquist and above
Nyquist operation, exhibiting a unique Normalized
Noise Floor (NNF) while keeping a Quantization Energy
(EQ) among the lowest in its frequency range.
Furthermore, we have pushed the sampling rate
beyond 2 Gsps while keeping an ENOB of 8.0 bits at
Nyquist, and offering outstanding performance over
second Nyquist zone, thus paving the way to high inter-
mediate frequency (IF) digital processing.
8. Acknowledgements
The authors thank their colleagues Benoit Dervaux,
Christian Morino, Claudie Allene, and Jean- Philippe
Amblard for their contributions.
References:
[1] Ken Poulton, et al A 20GS/ s 8b ADC with 1MB
Memory in 0.18mm CMOS ISSCC Digest of Technical
Papers, Feb 2003.
[2] Datasheet of ATMELs TS8388B 8- bit 1Gsps ADC,
rev 2144C- BDC- 04/ 03.
[3] Benoit Dervaux, A Ceramic BGA 148 Package for
assembly of a 2 Gsps Analog to Digital Converter ,
European Microelectronics Packaging and
Interconnection Symposium, Cracow, Poland, 16- 18
June 2002.
[4] Datasheet of ATMELs TS83102G0B 10- bit 2 Gsps
ADC rev 2101D- BDC- 06/ 04.
[5] Summar y datasheet of ATMELs ATMELs
AT84AS008 10- bit 2.2Gsps ADC, rev 5404AS- BDC-
01/ 05.
[6] Datasheet of Maxims MAX108 8- bit 1.5 Gsps ADC.
[7] Datasheet of ADIs AD9430- 210 12- bit 210 Msps
ADC.
[8] Datasheet of Linear Technologys LTC2220- 1 12- bit
185 Msps ADC.
[9] Datasheet of ADIs AD6654- 105 14- bit 105 Msps
ADC.
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