Topic 5: Servo Chip Design
Topic 5: Servo Chip Design
Topic 5: Servo Chip Design
Topic 5:
Servo Chip Design
Servo Chip Design
1
The Subsystems in a closed-loop Control System
Control
Element
Measurement
Element
Input
Output
+
- Reference Value
Error
Signal
Correction
Element
Process
Element
Controlled
Variables
Comparison
Element
Controller
Correction Element: Actuator
Process Element: Plant
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Topic 5:
Servo Chip Design
Servo Chip Design
Four Characteristics of a Servo System
(1) Exerted by the error between the desired and actual outputs.
(2) The output power is much larger than the input signal.
(3) The output power is proportional tothe composition of the error
signal and its derivatives.
(4) Actual servo system is stable.
-- Closed Loop
-- Drives
-- Linear
-- Negative Feedback
2
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Servo Chip Design
Servo Chip Design
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For a DC Motor,
Electrical I nput
Motor
Load
Rotation
B
Magnetic Field
i
a
F
b
B
L
F =B ia L
One wire of armature coil
With N wires
F =N B ia L
T =N B ia L b
Therefore, the torque T
We can also write it as
T =k1B ia
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Servo Chip Design
Servo Chip Design
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The back e.m.f. is proportional to the rate or rotation of the armature and the flux linked by
the coil,hence the flux density B. Thus
B k v
b 2
=
For B is constant, we can also write it as
3
k v
b
=
a
L
a
R
a
i
a
v
b
v
Armature Circuit
Load
T
a a
a
a b a
i R
dt
di
L v v + =
a a
a
a a
i R
dt
di
L k v + =
3
a a
i k Bi k T
4 1
= =
We have known that,
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Servo Chip Design
Servo Chip Design
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Armature
Circuit
E. m.
Induction
+
-
Armature
Coil
Load
a
v
b a
v v
a a
a
a b a
i R
dt
di
L v v + =
a
i
T
c T
dt
d
I =
Back e. m. f.
b
v
Armature-Controlled D.C. Motor
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Servo Chip Design
Servo Chip Design
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C
+
-
d
a
v
T
T
K
a s
K
+
=
d 1
x
& &
= 0 x
1
T K a =
T K x a
1 d
= ) (
T K a ax
d 1
+ =
) (
a T d 1
v K K a ax + =
)
a d 1
v K a ax + =
In which K K K
T
=
We set ) (
1
1
x K a
K
v
p d a
+ =
Then
1 p 1 1
x K ax x =
&
1 p
x K a ) ( + =
However, it is hard to get the value of , so
we must use PI Controller.
K
Velocity Control for DC Servo Motor:
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Servo Chip Design
Servo Chip Design
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There are some works needed to be studied in advance:
(1) Assumed sensor signals are A, B phases detected from Encoder.
(2) 4 times frequency generator
(5) Control range and resolution determination
(6) The control value modification for AD - DA transformation
(3) The mechanical and electrical bandwidth
(7) The relationship between sampling rate and control gains
(8) How to implement? What is the Servo Chip Structure?
(4) Drive mechanism understanding
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Servo Chip Design
Servo Chip Design
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CLK
Phase A
Phase B
Encoder Waveform Analysis: (CW) Encoder Waveform Analysis: (CW)
A
B
not(A)
not(B)
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Servo Chip Design
Servo Chip Design
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Phase A
Encoder Waveform Analysis: (CW) Encoder Waveform Analysis: (CW)
A
not(A)
A+
not(Phase A)
A-
f2A
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Servo Chip Design
Servo Chip Design
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Phase B
Encoder Waveform Analysis: (CW) Encoder Waveform Analysis: (CW)
B
not(B)
B+
not(Phase B)
B-
f2B
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Servo Chip Design
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Phase B
Encoder Waveform Analysis: (CW) Encoder Waveform Analysis: (CW)
B+
B-
Phase A
A+
A-
f4
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Servo Chip Design
Servo Chip Design
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Encoder Waveform Analysis: (CCW) Encoder Waveform Analysis: (CCW)
CLK
Phase A
Phase B
A
B
not(A)
not(B)
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Servo Chip Design
Servo Chip Design
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Encoder Waveform Analysis: (CCW) Encoder Waveform Analysis: (CCW)
Phase A
A
not(A)
A+
not(Phase A)
A-
f2A
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Encoder Waveform Analysis: (CCW) Encoder Waveform Analysis: (CCW)
Phase B
B
not(B)
B+
not(Phase B)
B-
f2B
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Servo Chip Design
Servo Chip Design
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Encoder Waveform Analysis: (CCW) Encoder Waveform Analysis: (CCW)
Phase B
B+
B-
Phase A
A+
A-
f4
Therefore, we can get the 4 times frequency and decide the rotation direction!!
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Servo Chip Design
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+12V
+12V
-12V
VCC
VCC
+12V
-12V
D8
D0
D1 D10
D11
D7 D4
D6
D2
D3
D5
D9
R11
R
R13
R
U7
AD7541
1
2
3
4
5
6
7
8
9 10
11
12
13
14
16
17
18
15
Iout1
Iout2
GND
BIT1 (MSB)
BIT2
BIT3
BIT4
BIT5
BIT6 BIT7
BIT8
BIT9
BIT10
BIT11
V+
Vref IN
Rfeedback
BIT12 (LSB)
+
-
U8A
LM358
3
2
1
8
4
R12
R
R14
13.3K
R16
R
R17
R
+
-
U8B
LM358
5
6
7
8
4
Analog_out
D D- -to to- -A Schematics: A Schematics:
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Stepping Motor:(Permanent Magnet) Stepping Motor:(Permanent Magnet)
A
B
C
D
A
B
C
D
(1) (2) (3) (4)
(Position Control Structure)
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Stepping Motor:(Full Step Sequential Control) Stepping Motor:(Full Step Sequential Control)
A
B
C
D
A
B
C
D
CW
CCW
1 2 3 4 1 2 3 4
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Stepping Motor:(Half Step Sequential Control) Stepping Motor:(Half Step Sequential Control)
A A
B B B
C
C C
D D
A
D
(1) (2) (3) (4)
(5) (6) (7) (8)
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Stepping Motor:(Half Step Sequential Control) Stepping Motor:(Half Step Sequential Control)
A
B
C
D
CW
CCW
1 2 3 4 5 6 7 8
A
B
D
C
1 2 3 4 5 6 7 8
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Stepping Motor:(VHDL Code) Stepping Motor:(VHDL Code)
Step <= 0001 when Seq = 0 else -- A
0011 when Seq = 1 else -- ..BA
0010 when Seq = 2 else -- ..B.
0110 when Seq = 3 else -- .CB.
0100 when Seq = 4 else -- .C..
1100 when Seq = 5 else -- DC..
1000 when Seq = 6 else -- D...
1001; -- D..A
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Stepping Motor:(Velocity Control) Stepping Motor:(Velocity Control)
For stepping motors, velocity control is equivalent to frequency control.
We have learned frequency divisionmethods before, therefore, we can set the
different counter valueto make different frequency.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Divid_n is
port(
clk_in :in std_logic;
Divid_n_out :out std_logic
);
end Divid_n;
architecture a of Divid_n is
signal Q : integer range 0 to 24000;
signal Rst_n : std_logic;
begin
Divid_n_process:process(clk_in, Rst_n)
begin
if Rst_n ='1' then
Q <= 0;
elsif clk_in'event and clk_in='1' then
Q <= Q + 1;
end if;
end process Divid_n_process;
Rst_n <= '1' when Q = Value else '0';
Divid_n_out <= '1' when Q >= (Value/2) else '0';
end a;
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Stepping Motor:(Step Miss) Stepping Motor:(Step Miss)
The major cause for step miss is the bandwidth differencebetween mechanical
moving and electrical control mechanism. (Torqueand I nertia)
Therefore, to avoid the step miss to happen, the velocity control curvemust be
programmed in advance.
velocity
time
Stop
Speed
up
Constant
Speed
Speed
down Stop
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Mechanical Bandwidth and Electrical Bandwidth: Mechanical Bandwidth and Electrical Bandwidth:
Bandwidth is meant to be the responding capability(how quick it can be?) due to input
signals. That can be also looked as the frequencythat has -180 degrees phase lag from
the view point of Bode Diagram.
From the view point of time domain, we can have the another explanation that how
change it can be made during a certain period? (Newton second law)
I T =
t
I
=
t
f
I
= 2
f I
)
2 =
(How many times change per 1 second)
Therefore, depends on T and I .
f
)
For a mechanical system,
Analyzing the unit level, the bandwidth of mechanical systems isalmost
during ten to some hundreds hertz.
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For a electrical system,
Vin
+
-
R1 R2
R3 R4 I
4 2 3
1
1 1
1
R R R
R R
eq
+
+
+ =
I f R denotes C, then R = 1/CS; I f R denotes L, then R = LS. I f open , then R = infinite;
I f short, then R = 0.
Analyzing the unit level, the bandwidth rangeof electrical systems is very large.
Generally, for a control system, the bandwidth of electrical systems is over 1000 hertz.
(for a digital system, we must check the system clock)
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Driving Mechanism: Driving Mechanism:
DC Motors:
Stator Rotor
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Drive DC Motors:
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AC Motors:
Stator Rotor
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Drive AC Motors:
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Block Diagram of a Servo Motor used a Analog PI Controller:
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Digital Control:
ADC
Measurement
+
-
DAC
Correction
element
Micro-
processor
Process
Clock
Output
I nput
Analog Discrete Discrete
Analog
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PWM:
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Variable Frequency Drive:
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Control Range and Resolution Determination: (I n the finite bounded and signal
sampling world)
A/D Calculation D/A
I
U
C
Y
R
S
I n which, , ,
+ R R R + S S S
} I , , I , {I I
1 2
1 0
n
L
, , } C , , C , {C C
1 2
1 0
n
L } U , , U , {U U
1 2
1 0
m
L
and
+ Y Y Y
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Control Range: , and
R
S Y
Resolution: or or
n
2
R
n
2
S
m
2
Y
~
~ ~
~
R
Y
n
2
m
2
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The Control Value Modification for AD-DA Transformation:
I f n=m, then the gain is modified by A/D and D/A hardware.
~
~ ~
~
R
Y
K
m
=
I f n m, then the gain is modified not only by A/D and D/A hardware, but also
should be modified by digital scheduling(Digit Shift).
n m
n
m
D
2
2
2
K
= =
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For example, deriving P control law as below:
m p
K S) (R K Y =
]
2
Y
K
R
2
[ S) (R K
m
D
n
p
=
] K K [K S) (R K
D/A D A/D p
=
D/A D A/D p
K K K S) (R K =
D/A D p
K K I K =
D/A p
K U K =
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By Hardware
D/A D p A/D
K K K K S) (R Y =
We can modify the relation as below:
By Hardware
Gain(Control Law) Mappingand Digit Shift I mplemented by VHDL Code
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I t also can be written as below:
D/A A/D A/D D p
K ) K S K (R K K Y =
D/A A/D D p
K ) K S (C K K =
D/A D p
K I ) (C K K =
Gain(Control Law) Mappingand Digit Shift I mplemented by VHDL Code
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I n which, can be represented as 2s power sequence in advance.
p
K
D/A D p
K I ) (C K K
{0,1,1,, 0}
(Shift and ADD)
Shift Digit
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Angle Velocity Calculation for a Motor Drive (n pulses for 1 round):
T t
=
(rad/sec)
m
n T
2
n
2
T
m
= =
(rad/sec)
n
60
T
m
2
60
n
2
T
m
= =
(rpm)
m
n T
60
=
(rpm)
Therefore, we can choose the values of T and nto make the value as 2s
multiple. However, they also determine the control resolution.
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For example (360 pulses/round):
rpm (pulses/1ms) (pulses/2ms) (pulses/8ms) pulses of half duty (pulses/16ms) pulses of half duty
4000 96.00 192.00 768.00 384.00 1536.00 768.00
3999 95.98 191.95 767.81 383.90 1535.62 767.81
3998 95.95 191.90 767.62 383.81 1535.23 767.62
3997 95.93 191.86 767.42 383.71 1534.85 767.42
3996 95.90 191.81 767.23 383.62 1534.46 767.23
3995 95.88 191.76 767.04 383.52 1534.08 767.04
3994 95.86 191.71 766.85 383.42 1533.70 766.85
3993 95.83 191.66 766.66 383.33 1533.31 766.66
360 Pulses/Round, so
1440 Pules/Round
1002 24.05 48.10 192.38 96.19 384.77 192.38
1001 24.02 48.05 192.19 96.10 384.38 192.19
1000 24.00 48.00 192.00 96.00 384.00 192.00
999 23.98 47.95 191.81 95.90 383.62 191.81
998 23.95 47.90 191.62 95.81 383.23 191.62
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We can find a trade-off that should be determined in advance, the control rangecan
not be expended arbitrarily:
Counts
Sampling
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For high velocity and quick sampling, we can calculate the velocity by another method.
CLK
Counts
n p
60
n T
60
m
n T
60
p
=
Therefore,
That is,
Constant
n
60
p =
=
d d
p p =
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PWM (Pulse Width Modulation):
V+
V-
OP
Vin
Vout
Duty Cycle = Ton / (Ton + Toff)
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10%
30%
50%
10%
30%
50%
10%
30%
50%
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Entity PWM is
port(DB :inout std_logic_vector(7 downto 0);
DP :out std_logic;
CS :in std_logic; -- Chip Selector
SWR:in std_logic; -- Sync Write
CLK:in std_logic
);
architecture a of PWM is
signal CNT: std_logic_vector(7 downto 0);
signal Q : std_logic_vector(7 downto 0);
signal Q_D: std_logic_vector(7 downto 0);
signal EC : std_logic;
begin
Counter: process(CLK)
begin
if CLKevent and CLK=1 then
Q<=Q-1;
end if;
end process Counter;
CNT <= Q;
Comparator: process(CLK)
begin
if CLKevent and CLK=1 then
if EC =1 then
Q_D <= DB;
end if;
end if;
end process Comparator;
EC <= SWR and CS;
OP <= 1 when Q_D>CNT else0;
end a;
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Control Design Flow:
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Servo Chip Structure:
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How to implement Servo Chip?
(1) A, B Phase Encode
(4) Digital Filter Design
(5) Position and Velocity Design
(6) Command Decode(or A-to-D I mplementation)
(7) Control Algorithm I mplementation
(8) D-to-A I mplementation
(9) PWM I mplementation
(2) 4 Times Frequency Design
(3) Timer Design