1/18 June 2002

M24512
512 Kbit Serial IC Bus EEPROM
I Two Wire I
2
C Serial Interface
Supports 400 kHz Protocol
I Single Supply Voltage:
4.5V to 5.5V for M24512
2.5V to 5.5V for M24512-W
1.8V to 3.6V for M24512-S
I Write Control Input
I BYTE and PAGE WRITE (up to 128 Bytes)
I RANDOM and SEQUENTIAL READ Modes
I Self-Timed Programming Cycle
I Automatic Address Incrementing
I Enhanced ESD/Latch-Up Behavior
I More than 100,000 Erase/Write Cycles
I More than 40 Year Data Retention
DESCRIPTION
These I
2
C-compatible electrically erasable
programmable memory (EEPROM) devices are
organised as 64Kx8 bits, and operate down to
2.5 V (for the -W version), and down to 1.8 V (for
the -S version).
These devices are compatible with the I
2
C
memory protocol. This is a two wire serial interface
that uses a bi-directional data bus and serial clock.
The devices carry a built-in 4-bit Device Type
Identifier code (1010) in accordance with the I
2
C
bus definition.
Figure 1. Logic Diagram
AI02275
SDA
V
CC
M24512
WC
SCL
V
SS
3
E0-E2
Table 1. Signal Names
E0, E1, E2 Chip Enable
SDA Serial Data
SCL Serial Clock
WC Write Control
V
CC
Supply Voltage
V
SS
Ground
PDIP8 (BN)
0.25 mm frame
8
1
LGA8 (LA)
LGA
8
1
SO8 (MW)
200 mil width
M24512
2/18
Figure 2A. DIP Connections
Figure 2B. LGA Connections
SDA V
SS
SCL
WC E1
E0 V
CC
E2
AI02276
M24512
1
2
3
4
8
7
6
5
SDA V
SS
SCL
WC E1
E0 V
CC
E2
AI03791
M24512
1
2
3
4
8
7
6
5
Figure 2C. SO8 Connections
1
AI04035
2
3
4
8
7
6
5 SDA V
SS
SCL
WC E1
E0 V
CC
E2
M24512
Table 2. Absolute Maximum Ratings
1
Note: 1. Except for the rating Operating Temperature Range, stresses above those listed in the Table Absolute Maximum Ratings may
cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality
documents.
2. IPC/JEDEC J-STD-020A
3. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 , R2=500 )
Symbol Parameter Value Unit
TA Ambient Operating Temperature 40 to 125 C
T
STG
Storage Temperature 65 to 150 C
T
LEAD Lead Temperature during Soldering
PDIP: 10 seconds
SO: 20 seconds (max)
2
260
235
C
V
IO
Input or Output range 0.6 to 6.5 V
V
CC
Supply Voltage 0.3 to 6.5 V
VESD Electrostatic Discharge Voltage (Human Body model)
3
4000 V
3/18
M24512
The device behaves as a slave in the I
2
C protocol,
with all memory operations synchronized by the
serial clock. Read and Write operations are
initiated by a Start condition, generated by the bus
master. The Start condition is followed by a Device
Select Code and RW bit (as described in Table 3),
terminated by an acknowledge bit.
When writing data to the memory, the device
inserts an acknowledge bit during the 9
th
bit time,
following the bus masters 8-bit transmission.
When data is read by the bus master, the bus
master acknowledges the receipt of the data byte
in the same way. Data transfers are terminated by
a Stop condition after an Ack for Write, and after a
NoAck for Read.
Power On Reset: V
CC
Lock-Out Write Protect
In order to prevent data corruption and inadvertent
Write operations during Power-up, a Power On
Reset (POR) circuit is included. The internal reset
is held active until V
CC
has reached the POR
threshold value, and all operations are disabled
the device will not respond to any command. In the
same way, when V
CC
drops from the operating
voltage, below the POR threshold value, all
operations are disabled and the device will not
respond to any command. A stable and valid V
CC
must be applied before applying any logic signal.
SIGNAL DESCRIPTION
Serial Clock (SCL)
This input signal is used to strobe all data in and
out of the device. In applications where this signal
is used by slave devices to synchronize the bus to
a slower clock, the bus master must have an open
drain output, and a pull-up resistor must be
connected from Serial Clock (SCL) to V
CC
. (Figure
3 indicates how the value of the pull-up resistor
can be calculated). In most applications, though,
this method of synchronization is not employed,
and so the pull-up resistor is not necessary,
provided that the bus master has a push-pull
(rather than open drain) output.
Serial Data (SDA)
This bi-directional signal is used to transfer data in
or out of the device. It is an open drain output that
may be wire-ORed with other open drain or open
collector signals on the bus. A pull up resistor must
be connected from Serial Data (SDA) to V
CC
.
(Figure 3 indicates how the value of the pull-up
resistor can be calculated).
Chip Enable (E0, E1, E2)
These input signals are used to set the value that
is to be looked for on the three least significant bits
(b3, b2, b1) of the 7-bit Device Select Code. These
inputs must be tied to V
CC
or V
SS
, to establish the
Device Select Code. When unconnected, the Chip
Enable (E2, E1, E0) signals are internally read as
V
IL
(see Tables 7 and 8).
Write Control (WC)
This input signal is useful for protecting the entire
contents of the memory from inadvertent write
operations. Write operations are disabled to the
entire memory array when Write Control (WC) is
driven High. When unconnected, the signal is
internally read as V
IL
, and Write operations are
allowed.
When Write Control (WC) is driven High, Device
Select and Address bytes are acknowledged,
Data bytes are not acknowledged.
Figure 3. Maximum R
L
Value versus Bus Capacitance (C
BUS
) for an I
2
C Bus
AI01665
V
CC
C
BUS
SDA
R
L
MASTER
R
L
SCL
C
BUS
100
0
4
8
12
16
20
C
BUS
(pF)
M
a
x
i
m
u
m

R
P

v
a
l
u
e

(
k

)
10 1000
fc = 400kHz
fc = 100kHz
M24512
4/18
DEVICE OPERATION
The device supports the I
2
C protocol. This is
summarized in Figure 4. Any device that sends
data on to the bus is defined to be a transmitter,
and any device that reads the data to be a
receiver. The device that controls the data transfer
is known as the bus master, and the other as the
slave device. A data transfer can only be initiated
by the bus master, which will also provide the
serial clock for synchronization. The M24512
device is always a slave in all communication.
Start Condition
Start is identified by a falling edge of Serial Data
(SDA) while Serial Clock (SCL) is stable in the
High state. A Start condition must precede any
data transfer command. The device continuously
monitors (except during a Write cycle) Serial Data
(SDA) and Serial Clock (SCL) for a Start condition,
and will not respond unless one is given.
Stop Condition
Stop is identified by a rising edge of Serial Data
(SDA) while Serial Clock (SCL) is stable and
driven High. A Stop condition terminates
communication between the device and the bus
master. A Read command that is followed by
NoAck can be followed by a Stop condition to force
the device into the Stand-by mode. A Stop
condition at the end of a Write command triggers
the internal EEPROM Write cycle.
Acknowledge Bit (ACK)
The acknowledge bit is used to indicate a
successful byte transfer. The bus transmitter,
whether it be bus master or slave device, releases
Serial Data (SDA) after sending eight bits of data.
During the 9
th
clock pulse period, the receiver pulls
Serial Data (SDA) Low to acknowledge the receipt
of the eight data bits.
Figure 4. I
2
C Bus Protocol
SCL
SDA
SCL
SDA
SDA
START
Condition
SDA
Input
SDA
Change
AI00792B
STOP
Condition
1 2 3 7 8 9
MSB ACK
START
Condition
SCL
1 2 3 7 8 9
MSB ACK
STOP
Condition
5/18
M24512
Data Input
During data input, the device samples Serial Data
(SDA) on the rising edge of Serial Clock (SCL).
For correct device operation, Serial Data (SDA)
must be stable during the rising edge of Serial
Clock (SCL), and the Serial Data (SDA) signal
must change only when Serial Clock (SCL) is
driven Low.
Memory Addressing
To start communication between the bus master
and the slave device, the bus master must initiate
a Start condition. Following this, the bus master
sends the Device Select Code, shown in Table 3
(on Serial Data (SDA), most significant bit first).
The Device Select Code consists of a 4-bit Device
Type Identifier, and a 3-bit Chip Enable Address
(E2, E1, E0). To address the memory array, the 4-
bit Device Type Identifier is 1010b.
Up to eight memory devices can be connected on
a single I
2
C bus. Each one is given a unique 3-bit
code on the Chip Enable (E0, E1, E2) inputs.
When the Device Select Code is received on
Serial Data (SDA), the device only responds if the
Chip Enable Address is the same as the value on
the Chip Enable (E0, E1, E2) inputs.
The 8
th
bit is the Read/Write bit (RW). This bit is
set to 1 for Read and 0 for Write operations.
If a match occurs on the Device Select code, the
corresponding device gives an acknowledgment
on Serial Data (SDA) during the 9
th
bit time. If the
device does not match the Device Select code, it
deselects itself from the bus, and goes into Stand-
by mode.
Write Operations
Following a Start condition the bus master sends
a Device Select Code with the RW bit reset to 0.
The device acknowledges this, as shown in Figure
6, and waits for two address bytes. The device
responds to each address byte with an
acknowledge bit, and then waits for the data byte.
Writing to the memory may be inhibited if Write
Control (WC) is driven High. Any Write instruction
with Write Control (WC) driven High (during a
period of time from the Start condition until the end
of the two address bytes) will not modify the
memory contents, and the accompanying data
bytes are not acknowledged, as shown in Figure 5.
Each data byte in the memory has a 16-bit (two
byte wide) address. The Most Significant Byte
(Table 4) is sent first, followed by the Least
Significant Byte (Table 5). Bits b15 to b0 form the
address of the byte in memory.
When the bus master generates a Stop condition
immediately after the Ack bit (in the 10
th
bit time
slot), either at the end of a Byte Write or a Page
Write, the internal memory Write cycle is triggered.
Table 3. Device Select Code
1
Note: 1. The most significant bit, b7, is sent first.
Device Type Identifier Chip Enable Address RW
b7 b6 b5 b4 b3 b2 b1 b0
Device Select Code 1 0 1 0 E2 E1 E0 RW
Table 4. Most Significant Byte
Table 5. Least Significant Byte
b15 b14 b13 b12 b11 b10 b9 b8
b7 b6 b5 b4 b3 b2 b1 b0
Table 6. Operating Modes
Note: 1. X = VIH or VIL.
Mode RW bit
WC
1
Bytes Initial Sequence
Current Address Read 1 X 1 START, Device Select, RW = 1
Random Address Read
0 X
1
START, Device Select, RW = 0, Address
1 X reSTART, Device Select, RW = 1
Sequential Read 1 X 1 Similar to Current or Random Address Read
Byte Write 0 VIL 1 START, Device Select, RW = 0
Page Write 0 VIL 128 START, Device Select, RW = 0
M24512
6/18
Figure 5. Write Mode Sequences with WC=1 (data write inhibited)
S
T
O
P
S
T
A
R
T
BYTE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN
WC
S
T
A
R
T
PAGE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN 1
WC
DATA IN 2
AI01120C
PAGE WRITE
(cont'd)
WC (cont'd)
S
T
O
P
DATA IN N
ACK ACK ACK NO ACK
R/W
ACK ACK ACK NO ACK
R/W
NO ACK NO ACK
A Stop condition at any other time slot does not
trigger the internal Write cycle.
During the internal Write cycle, Serial Data (SDA)
is disabled internally, and the device does not
respond to any requests.
Byte Write
After the Device Select code and the address
bytes, the bus master sends one data byte. If the
addressed location is Write-protected, by Write
Control (WC) being driven High, the device replies
with NoAck, and the location is not modified. If,
instead, the addressed location is not Write-
protected, the device replies with Ack. The bus
master terminates the transfer by generating a
Stop condition, as shown in Figure 6.
Page Write
The Page Write mode allows up to 128 bytes to be
written in a single Write cycle, provided that they
are all located in the same row in the memory:
that is, the most significant memory address bits
(b15-b7) are the same. If more bytes are sent than
will fit up to the end of the row, a condition known
as roll-over occurs. This should be avoided, as
data starts to become overwritten in an
implementation dependent way.
The bus master sends from 1 to 128 bytes of data,
each of which is acknowledged by the device if
Write Control (WC) is Low. If Write Control (WC) is
High, the contents of the addressed memory
location are not modified, and each data byte is
followed by a NoAck. After each byte is
transferred, the internal byte address counter (the
7 least significant address bits only) is
incremented. The transfer is terminated by the bus
master generating a Stop condition.
Minimizing System Delays by Polling On ACK
During the internal Write cycle, the device
disconnects itself from the bus, and writes a copy
of the data from its internal latches to the memory
7/18
M24512
Figure 6. Write Mode Sequences with WC=0 (data write enabled)
S
T
O
P
S
T
A
R
T
BYTE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN
WC
S
T
A
R
T
PAGE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN 1
WC
DATA IN 2
AI01106B
PAGE WRITE
(cont'd)
WC (cont'd)
S
T
O
P
DATA IN N
ACK
R/W
ACK ACK ACK
ACK ACK ACK ACK
R/W
ACK ACK
cells. The maximum Write time (t
w
) is shown in
Table 9, but the typical time is shorter. To make
use of this, a polling sequence can be used by the
bus master.
The sequence, as shown in Figure 7, is:
Initial condition: a Write cycle is in progress.
Step 1: the bus master issues a Start condition
followed by a Device Select Code (the first byte
of the new instruction).
Step 2: if the device is busy with the internal
Write cycle, no Ack will be returned and the bus
master goes back to Step 1. If the device has
terminated the internal Write cycle, it responds
with an Ack, indicating that the device is ready
to receive the second part of the instruction (the
first byte of this instruction having been sent
during Step 1).
Read Operations
Read operations are performed independently of
the state of the Write Control (WC) signal.
Random Address Read
A dummy Write is performed to load the address
into the address counter (as shown in Figure 8) but
without sending a Stop condition. Then, the bus
master sends another Start condition, and repeats
the Device Select Code, with the RW bit set to 1.
The device acknowledges this, and outputs the
contents of the addressed byte. The bus master
must not acknowledge the byte, and terminates
the transfer with a Stop condition.
Current Address Read
The device has an internal address counter which
is incremented each time a byte is read. For the
Current Address Read operation, following a Start
condition, the bus master only sends a Device
Select Code with the RW bit set to 1. The device
acknowledges this, and outputs the byte
M24512
8/18
counter rolls-over, and the device continues to
output data from memory address 00h.
Acknowledge in Read Mode
For all Read commands, the device waits, after
each byte read, for an acknowledgment during the
9
th
bit time. If the bus master does not drive Serial
Data (SDA) Low during this time, the device
terminates the data transfer and switches to its
Stand-by mode.
addressed by the internal address counter. The
counter is then incremented. The bus master
terminates the transfer with a Stop condition, as
shown in Figure 8, without acknowledging the
byte.
Sequential Read
This operation can be used after a Current
Address Read or a Random Address Read. The
bus master does acknowledge the data byte
output, and sends additional clock pulses so that
the device continues to output the next byte in
sequence. To terminate the stream of bytes, the
bus master must not acknowledge the last byte,
and must generate a Stop condition, as shown in
Figure 8.
The output data comes from consecutive
addresses, with the internal address counter
automatically incremented after each byte output.
After the last memory address, the address
Figure 7. Write Cycle Polling Flowchart using ACK
WRITE Cycle
in Progress
AI01847C
Next
Operation is
Addressing the
Memory
START Condition
DEVICE SELECT
with RW = 0
ACK
Returned
YES
NO
YES NO
ReSTART
STOP
DATA for the
WRITE Operation
DEVICE SELECT
with RW = 1
Send Address
and Receive ACK
First byte of instruction
with RW = 0 already
decoded by the device
YES NO START
Condition
Continue the
WRITE Operation
Continue the
Random READ Operation
9/18
M24512
Figure 8. Read Mode Sequences
Note: 1. The seven most significant bits of the Device Select Code of a Random Read (in the 1
st
and 4
th
bytes) must be identical.
S
T
A
R
T
DEV SEL * BYTE ADDR BYTE ADDR
S
T
A
R
T
DEV SEL DATA OUT 1
AI01105C
DATA OUT N
S
T
O
P
S
T
A
R
T
CURRENT
ADDRESS
READ
DEV SEL DATA OUT
RANDOM
ADDRESS
READ
S
T
O
P
S
T
A
R
T
DEV SEL * DATA OUT
SEQUENTIAL
CURRENT
READ
S
T
O
P
DATA OUT N
S
T
A
R
T
DEV SEL * BYTE ADDR BYTE ADDR
SEQUENTIAL
RANDOM
READ
S
T
A
R
T
DEV SEL * DATA OUT 1
S
T
O
P
ACK
R/W
NO ACK
ACK
R/W
ACK ACK ACK
R/W
ACK ACK ACK NO ACK
R/W
NO ACK
ACK ACK ACK
R/W
ACK ACK
R/W
ACK NO ACK
M24512
10/18
Table 7. DC Characteristics
(T
A
= 0 to 70 C or 40 to 85 C; V
CC
= 4.5 to 5.5 V or 2.5 to 5.5 V)
(T
A
= 0 to 70 C or 20 to 85 C; V
CC
= 1.8 to 3.6 V)
Note: 1. This is preliminary data.
Table 8. Input Parameters
1
(T
A
= 25 C, f = 400 kHz)
Note: 1. Sampled only, not 100% tested.
Symbol Parameter Test Condition Min. Max. Unit
I
LI
Input Leakage Current
(SCL, SDA)
V
IN
= V
SS
or

V
CC 2 A
I
LI
Input Leakage Current
(E2, E1, E0, WC)
V
IN
= V
SS 5 A
ILO Output Leakage Current VOUT = VSS or VCC, SDA in Hi-Z 2 A
ICC Supply Current
V
CC
=5V, f
c
=400kHz (rise/fall time < 30ns) 2 mA
-W series: V
CC
=2.5V, f
c
=400kHz (rise/fall time < 30ns) 1 mA
-S series: V
CC
=1.8V, f
c
=400kHz (rise/fall time < 30ns)
0.8
1
mA
I
CC1
Supply Current
(Stand-by)
VIN = VSS or VCC , VCC = 5 V 10 A
-W series: V
IN
= V
SS
or

V
CC
, V
CC
= 2.5 V 2 A
-S series: VIN = VSS or VCC , VCC = 1.8 V
1
1
A
V
IL Input Low Voltage 0.3 0.3V
CC V
V
IH Input High Voltage 0.7V
CC
V
CC
+1 V
V
OL
Output Low
Voltage
I
OL
= 3 mA, V
CC
= 5 V 0.4 V
-W series: IOL = 2.1 mA, VCC = 2.5 V 0.4 V
-S series: I
OL
= 0.15 mA, V
CC
= 1.8 V
0.2
1
V
Symbol Parameter Test Condition Min. Max. Unit
C
IN Input Capacitance (SDA) 8 pF
C
IN Input Capacitance (other pins) 6 pF
Z
L Input Impedance (E2, E1, E0, WC) VIN VIL 50 300 k
Z
H Input Impedance (E2, E1, E0, WC) V
IN
V
IH 500 k
tNS
Pulse width ignored
(Input Filter on SCL and SDA)
Single glitch 200 ns
11/18
M24512
Table 9. AC Characteristics
Note: 1. For a reSTART condition, or following a Write cycle.
2. Sampled only, not 100% tested.
3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.
4. This is preliminary data.
Symbol Alt. Parameter
M24512
Unit
V
CC
=4.5 to 5.5 V
T
A
=0 to 70C or
40 to 85C
V
CC
=2.5 to 5.5 V
T
A
=0 to 70C or
40 to 85C
V
CC
=1.8 to 3.6 V
T
A
=0 to 70C or
20 to 85C
4
Min Max Min Max Min Max
t
CH1CH2
t
R
Clock Rise Time 300 300 300 ns
t
CL1CL2
t
F Clock Fall Time 300 300 300 ns
t
DH1DH2
2
t
R
SDA Rise Time 20 300 20 300 20 300 ns
t
DL1DL2
2
t
F
SDA Fall Time 20 300 20 300 20 300 ns
t
CHDX
1
t
SU:STA
Clock High to Input Transition 600 600 600 ns
tCHCL tHIGH Clock Pulse Width High 600 600 600 ns
tDLCL tHD:STA Input Low to Clock Low (START) 600 600 600 ns
t
CLDX
t
HD:DAT
Clock Low to Input Transition 0 0 0 s
t
CLCH
t
LOW Clock Pulse Width Low 1.3 1.3 1.3 s
tDXCX tSU:DAT
Input Transition to Clock
Transition
100 100 100 ns
t
CHDH
t
SU:STO Clock High to Input High (STOP) 600 600 600 ns
t
DHDL
t
BUF
Input High to Input Low (Bus
Free)
1.3 1.3 1.3 s
t
CLQV
3
t
AA
Clock Low to Data Out Valid 200 900 200 900 200 900 ns
t
CLQX
t
DH
Data Out Hold Time After Clock
Low
200 200 200 ns
f
C
f
SCL Clock Frequency 400 400 400 kHz
tW tWR Write Time 10 10 10 ms
Table 10. AC Measurement Conditions
Input Rise and Fall Times 50 ns
Input Pulse Voltages 0.2V
CC
to 0.8V
CC
Input and Output Timing
Reference Voltages
0.3V
CC
to 0.7V
CC
Figure 9. AC Measurement Conditions
AI00825
0.8V
CC
0.2V
CC
0.7V
CC
0.3V
CC
M24512
12/18
Figure 10. AC Waveforms
SCL
SDA In
SCL
SDA Out
SCL
SDA In
tCHCL
tDLCL
tCHDX
START
Condition
tCLCH
tDXCX tCLDX
SDA
Input
SDA
Change
tCHDH tDHDL
STOP
Condition
Data Valid
tCLQV tCLQX
tCHDH
STOP
Condition
tCHDX
START
Condition
Write Cycle
tW
AI00795C
START
Condition
13/18
M24512
Table 11. Ordering Information Scheme
Note: 1. The -S version (V
CC
range 1.8 V to 3.6 V) only available in temperature ranges 5.
Example: M24512 W MW 6 T
Memory Capacity Option
512 512 Kbit (64K x 8) T Tape and Reel Packing
Operating Voltage
blank 4.5 V to 5.5 V
W 2.5 V to 5.5 V
S
1
1.8 V to 3.6 V
Package Temperature Range
BN PDIP8 (0.25 mm frame) 5 20 C to 85 C
MW SO8 (200 mil width) 6 40 C to 85 C
LA LGA8 (Land Grid Array)
ORDERING INFORMATION
Devices are shipped from the factory with the
memory content set at all 1s (FFh).
The notation used for the device number is as
shown in Table 11. For a list of available options
(speed, package, etc.) or for further information on
any aspect of this device, please contact your
nearest ST Sales Office.
M24512
14/18
PDIP8 8 pin Plastic DIP, 0.25mm lead frame, Package Outline
Note: 1. Drawing is not to scale.
PDIP-B
A2
A1
A
L
b e
D
E1
8
1
c
eA
b2
eB
E
PDIP8 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data
Symb.
mm inches
Typ. Min. Max. Typ. Min. Max.
A 5.33 0.210
A1 0.38 0.015
A2 3.30 2.92 4.95 0.130 0.115 0.195
b 0.46 0.36 0.56 0.018 0.014 0.022
b2 1.52 1.14 1.78 0.060 0.045 0.070
c 0.25 0.20 0.36 0.010 0.008 0.014
D 9.27 9.02 10.16 0.365 0.355 0.400
E 7.87 7.62 8.26 0.310 0.300 0.325
E1 6.35 6.10 7.11 0.250 0.240 0.280
e 2.54 0.100
eA 7.62 0.300
eB 10.92 0.430
L 3.30 2.92 3.81 0.130 0.115 0.150
15/18
M24512
SO8 wide 8 lead Plastic Small Outline, 200 mils body width
Note: Drawing is not to scale.
SO-b
E
N
CP
B
e
A2
D
C
L A1
H
A
1
SO8 wide 8 lead Plastic Small Outline, 200 mils body width
Symb.
mm inches
Typ. Min. Max. Typ. Min. Max.
A 2.03 0.080
A1 0.10 0.25 0.004 0.010
A2 1.78 0.070
B 0.35 0.45 0.014 0.018
C 0.20 0.008
D 5.15 5.35 0.203 0.211
E 5.20 5.40 0.205 0.213
e 1.27 0.050
H 7.70 8.10 0.303 0.319
L 0.50 0.80 0.020 0.031
0 10 0 10
N 8 8
CP 0.10 0.004
M24512
16/18
LGA8 - 8 lead Land Grid Array
Symb.
mm inches
Typ. Min. Max. Typ. Min. Max.
A 1.040 0.940 1.140 0.0409 0.0370 0.0449
A1 0.340 0.300 0.380 0.0134 0.0118 0.0150
A2 0.700 0.640 0.760 0.0276 0.0252 0.0299
D 8.000 7.900 8.100 0.3150 0.3110 0.3189
D1 0.100 0.0039
E 5.000 4.900 5.100 0.1969 0.1929 0.2008
E1 1.270 0.0500
E2 3.810 0.1500
E3 0.390 0.0154
k 0.100 0.0039
T1 0.410 0.0161
T2 0.670 0.0264
T3 0.970 0.0382
ddd 0.100 0.0039
LGA8 - 8 lead Land Grid Array
Note: 1. Drawing is not to scale.
D
E
A2
A1
T1
T2
E2
E1
E3
T3 D1
LGA-Z01B
CONTACT 1
A
ddd
k
17/18
M24512
Revision History
Date Rev. Description of Revision
29-Jan-2001 1.1
Lead Soldering Temperature in the Absolute Maximum Ratings table amended
Write Cycle Polling Flow Chart using ACK illustration updated
LGA8 and SO8(wide) packages added
References to PSDIP8 changed to PDIP8, and Package Mechanical data updated
10-Apr-2001 1.2
LGA8 Package Mechanical data and illustration updated
SO16 package removed
16-Jul-2001 1.3 LGA8 Package given the designator LA
02-Oct-2001 1.4 LGA8 Package mechanical data updated
13-Dec-2001 1.5
Document becomes Preliminary Data
Test conditions for ILI, ILO, ZL and ZH made more precise
VIL and VIH values unified. tNS value changed
12-Jun-2001 1.6 Document becomes Full Datasheet
M24512
18/18
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