2012 International Conference on Computer Science and Service System

The 8-bit parallel CRC-32 research and Implementation in USB 3.0

Ying Wu

Yuehong Qiu

Xian Institute of Optics and Precision Mechanics

Chinese Academy of Sciences
Xian, China
Wing435@126.com

Xian Institute of Optics and Precision Mechanics

Chinese Academy of Sciences
Xian, China
yhqiu68@opt.ac.cn
modulo2 arithmetic. The modulo2 arithmetic is realized by
XOR gate. Therefore the coding of CRC means that
transforming the information bits into the bits that can be
divided by the generated multinomial. At the receiver side,
we can use the generated multinomial G ( x) to divide the
received code. If the result is zero, there is no error, or else
the error emerged.

AbstractThis thesis proposed 8-bit parallel CRC-32 in

order to meet the high throughput of USB3.0. The highest
speed of USB3.0 reaches 5G bps. Firstly, we researched the
Data Packet structure and the principles of the CRC-32 in the
USB3.0 Specification. Secondly, deduced the equation of the 8bit input data and the CRC-32. Finally, implemented the CRC32 coding and decoding by the verilog HDL, verified the
correctness of the design. The 8-bit parallel CRC-32 can
process 8 bits every clock cycle.

III.

Keywords- Universal Serial bus 3.0; 8-bit parallel; Cyclic

Redundancy Check- 32

I.

Super-Speed USB uses four basic packet types:

1. Link Management Packets (LMP) only travel between a
pair of links and is primarily used to manage that link.
2. Transaction Packets (TP) traverse all the links directly
connecting the host to a device. They are used to report
the status of data transaction and can return values
indicating successful reception of data packets, command
acceptance or rejection, flow control, and halt condition.
Transaction Packets have no data payload.
3. Data Packets (DP) traverse all the links directly
connecting the host to a device. The host uses this packet
to send data to a device. Devices use this packet to return
data to the host in response to an ACK TP.
4. Isochronous Timestamp Packets (ITP) multicast on all
the active links from the host to one or more devices to
deliver timestamps. ITP is used to provide host timing
information to device for synchronization.

INTRODUCTION

Cyclic Redundancy Check (CRC) is a commonly used

error-checking method. It comes from the branch of linear
block code and is widely used in communication systems.
The CRC code generation is simple, and it can check
whether a packet is changed or not during the transmission.
In the USB3.0, the CRC-32 is used to protect the Data
Packets. In this paper, the 8-bit parallel CRC-32 is
implemented by verilog HDL.
II.

THEORY OF CYCLIC REDUNDANCY CHECK

The information data are expressed as multinomial

M ( x ) , in the multinomial, x stands for the position of the

code, the bits of the data are the coefficients of the
polynomial. We use generated multinomial G ( x) to

M ( x ) * xk (K is the last exponent of generated

multinomial G ( x) ), the residual is the CRC code. When

The DP is permissible to send a data packet with a zero

length data block; however, it shall have a CRC-32. Data
Packets have two parts: a Data Packets Header (DPH) and a
Data Packet Payload (DPP). The DPH structure is formatted
in Fig 1.The Data Packet Header is 20 symbols long. It
includes 4 bytes of header packet framing, 12 bytes of header
information, 2-byte CRC-16, 2-byte Link Control Word.
CRC-16 is used to protect the data integrity of the 12-byte
header information. The 2 bytes of Link Control Word
includes 5-bits CRC-5 which protects the integrity of the
Link Control Word. The DPP consists of a data packet
payload framing, and variable length of data followed by 4
bytes of CRC-32.The structure is showed in Fig 2.
At the receiver side, if there is no error during the
transmission, an ACK TP will be forward, otherwise arrange
for retransmission of the damaged frame.

divide

transmitting, the CRC code is appended to the information

data.
For example the information data is 1111, its
multinomial is:

M ( x ) = x3 + x 2 + x + 1 .The generated

multinomial of CRC-4 is:

G ( x ) = x4 + x + 1

M ( x ) * x 4 x 7 + x 6 + x5 + x 4
x
=
= x3 + x 2 + x + 4
G ( x)
x4 + x + 1
x + x +1

(1)

The residual multinomial is x, so the corresponding

CRC-4 of 1111 is 0010. At the sending side, the bits
11110010 will be forwarded. We can see that the CRC
encoding theory is based on polynomial manipulation using
978-0-7695-4719-0/12 $26.00 2012 IEEE
DOI 10.1109/CSSS.2012.273

THE PACKET TYPE AND CYCLIC REDUNDANCY

CHECK IN USB 3.0

1079

x32 (d k 1 x k 1 + d k 2 x k 2 ++ d1 x + d 0 )modG ( x )
i +1 31
i +1 30
i +1 29
= c31
x + c30
x + c29
x ++ c2i +1 x 2 + c1i +1 x + c0i +1

cij stands for the bit j of CRC-32 after inputting i bits .

The relationship of
Figure 1. Data Packet Header

cij+1 and cij is showed as equations

5.
i
c0i +1 = g0 ( c31
+d)

(5)

i
cij+1 = cij + gi ( c31
+d)

Based on equation 5:

7
7
c08 = g 0 ( c31
+ d 0 ) = c31
+ d0

Figure 2. Data Packet Payload

IV.

7
6
6
6
c31
= c30
+ g31 ( c31
+ d1 ) = c30

8-BITS PARALLEL CRC-32.

6
5
5
5
c30
= c29
+ g 30 ( c31
+ d 2 ) = c29

The classical hardware structure performing the CRC

computation consists of a Feedback Shift Register. The
Feedback Shift Register implements the CRC computation
serially, processing one message bit per clock cycle. The
super-speed can provide the highest speed of 5-Gbps. In
order to support the high throughput, the 8-bit parallel CRC32 is proposed, 8 bits can be processed per clock cycle. The
Generated multinomial of the CRC-32 is:

G ( x ) = x32 + x 26 + x 23 + x 22 + x16 + x12 + x11 +

x10 + x8 + x 7 + x5 + x 4 + x 2 + x + 1

5
4
3
2
c29
= c28
= c27
= c26
2
1
0
0
c26
= c125 + c31
+ d 6 = c24
+ c30
+ d6
0
0
c08 = c24
+ c30
+ d6 + d0

Deducing from multinomial1,we get:

(2)

0
0
c08 = c24
+ c30
+ d6 + d0
0
0
0
c18 = c24
+ c30
+ 025 + c31
+ d 6 + d 0 + d 7 + d1

The binary representation of the generated multinomial

of CRC-32 is: 100000100110000010001110110110111, that
is denoted as: g 32 , g 31...g 2 , g1 , g 0 . gi is the coefficient of
the
If

(6)

0
0
0
0
c28 = c26
+ c30
+ 025 + c31
+ c24
+ d 6 + d 0 + d 7 + d1 + d 2

x of the G( x) .

i 31
i
i
c31
x + c30
x30 + c29
x29 ++ c2i x2 + c1i x + c0i

= x32 (dk 1 xk 1 + dk 2 xk 2 ++ d1 x + d0 )modG ( x )

0
0
0
0
0
c78 = c27
+ c29
+ c26
+ c31
+ c24

+ d 7 + d0 + d5 + d 2 + d3

(7)

(3)
When 8<=i<=31

After inputting a binary number d, we get:

x32 (dk 1 xk + dk 2 xk 1 ++ d0 x + d )modG ( x )

0
1
ci8 = ci08 + gi 7 ( c31
+ d 7 ) + gi 6 ( c32
+ d6 ) + ...

= x33 (dk 1xk 1 + dk 2 xk 2 ++ d1 x + d0 )modG ( x) + x32dmodG ( x) (4)

6
7
+ gi 1 ( c31
+ d1 ) + gi ( c31
+ d0 )

i
i
= ( c30
+ g31c31
) x31 + ( c29i + g30c31i ) x30 ++ ( c0i + g1c31i ) x + g0c31i

+ g31dx31 + g30dx30 ++ g1dx + g0d

(8)

Now, the equation of the 8-bit parallel input data and

CRC-32 is got. So, the CRC-32 coding and decoding can be
implemented by verilog HDL.

32

= g0 ( c 31i +d ) + cij 1 + gi ( c30i + d ) *xi

j =1

Denote:

1080

V.

THE DESIGN OF CRC-32 ENCODING AND DECODING

In USB3.0, the data integrity of the Data Payload is

protected by CRC-32. There are some principles of CRC-32
in the USB3.0 Specification:
1. The CRC-32 polynomial is 04C1 1DB7h
2. In order to avoid the influence of extra zeros in front of
the DPP, the initial value of CRC-32 is 0xFFFF FFFF.
3. CRC-32 is calculated for all bytes of the Data Packet
Payload.
4. CRC-32 calculation shall begin at byte 0, bit 0 and
continue to bit 7 of each of the bytes of the DPP.
5. Avoiding the influence of extra zeros at the end of the
DPP, complementing the remainder of CRC-32.
6. The inversion of the CRC-32 remainder adds an offset of
0xFFFF FFFF that will create a constant CRC-32
residual of C704DD7Bh at the receiver side, called
magic number.
7. the bit order of the output is listed in Fig 3

Figure 4. The simulation of CRC-32 encoding

The bytes 0 to 8 are the information bits showing in Fig

5. Since the CRC-32 calculation begins at byte 0, bit 0 and
continue to bit 7 of each of the bytes of the DPP, the
information bits are 0x084C 2A6E 195D 3B7F 08(all the
data in this paper are expressed from low byte to high byte).
8 bits will be inputted and calculated per clock cycle.
According to the principles above, when the reset signal
valid, the CRC will be 0xFFFF FFFF. We get 0x2E30B91F
after 8-clock cycles calculation. After complementing it, we
get 0x1CF46E0.Reorder it according Fig 3. Finally we get
0x0762F38B, which is the same as the CRC-32 showing in
Fig5.

Figure 5. Sample Data Packet

Fig 6 shows the decoding module. The s_p_8 module

converts the serial bits to the 8-bit parallel. The received data
is decoded in the module crc-32. The CRC-32 module of the
decoding does not have the complementing process and
reordering process. The test module verifies the result of
decoding.

Figure 6. The CRC-32 decoding module

Fig 7 shows the simulation of CRC-32 decoding. After

inputting the data 0x0123 4567 89AB CDEF 01B8 3F26 70
(from byte 0 to byte 8, from low bit to high bit) serially to
the s_p_8 module, we get 0x084C 2A6E 195D 3B7F 08D1
CF46 E0, and decode it. Then we get 0xC704DD7B which is
equal to the magic number. Finally, the transmission is
successful.
VI.

CONCLUSION

In this paper, we implement the 8-bit parallel CRC-32 by

verilog HDL for the DPP of the USB 3.0and reorder the
CRC-32 according the principles in the USB3.0
Specification. In this design, 8 bits can be processed every
clock cycle. The speed of the 8-bit parallel CRC-32 is higher
than the serial CRC. The clock frequency of FPGA can reach

Figure 3. CRC-32 mapping.

1081

more than 200MHz using PLL, so the design can meet the
high throughput. It can be used in the USB3.0 transmission.

[2]

ACKNOWLEDGMENT

[3]

This work is supported by the nature scientific

foundation of China, No.10978005/A030801 and
No.61178033/F05070.

[4]

REFERENCES
[1]

[5]

KOU Ke-nan, RU Xiao, SUN Zhi-yue, REN Guang-hui Research on

parallel CRC32 algorithm based on SATA interface, The
Techniques of Automation &Application, vol. 29, pp. 40-43,August
2010.

Figure 7.

[6]

Hewlett-Packard Company Intel Corporation Microsoft Corporation,

NEC, TI, ST-NXP wireless, Universal Serial Bus 3.0 Specification,
Revision 1.0, NOV, 2008.
LI You-mou,The design of the 8bits parallel CRC-32 soft-core in
Ethernet,Journal
of
Xian
University
of
Post
and
Telecommunication, vol.11, pp.32-35, sep. 2006.
Tongsheng Zhang and Qun Ding, Design and implementation of
CRC based on FPGA, 2011 Second International Conference on
Innovations in Bio-inspired Computing and Applications,2011,
pp.160-162.
YU Xun, The 32-bit Cyclic Redundancy Check parallel algorithm
and hardware implementation", Information Technology, pp.71-74,
2007.
GAO Fan,XIONG chuan, GE ren-hua, The implement of IEEE802 3
CRC-32 by VHDL, Journal of Gui Lin College of Aerospace
Technology, pp.8-9, 2006.

The simulation of CRC-32 decoding

1082