LG Ht303su Ht353sd SM (ET)
LG Ht303su Ht353sd SM (ET)
LG Ht303su Ht353sd SM (ET)
Website http://biz.lgservice.com
SERVICE MANUAL
MODEL: HT303SU(SH33SU-S/W)/HT353SD(SH33SD-S/W)
DVD/CD RECEIVER
SERVICE MANUAL
HT303SU
P/NO : AFN33723386
JANUARY, 2008
HT353SD
[CONTENTS]
SECTION 1. GENERAL
SERVICING PRECAUTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
ESD PRECAUTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
SERVICE INFORMATION FOR EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
HOW TO UPDATE AUDIO MICOM & DVD PROGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-47
1-1
SECTION 1. GENERAL
SERVICING PRECAUTIONS
NOTES REGARDING HANDLING OF THE PICK-UP
1. Notes for transport and storage
1) The pick-up should always be left in its conductive bag until immediately prior to use.
2) The pick-up should never be subjected to external pressure or impact.
Drop impact
2. Repair notes
1) The pick-up incorporates a strong magnet, and so should never be brought close to magnetic materials.
2) The pick-up should always be handled correctly and carefully, taking care to avoid external pressure and
impact. If it is subjected to strong pressure or impact, the result may be an operational malfunction and/or
damage to the printed-circuit board.
3) Each and every pick-up is already individually adjusted to a high degree of precision, and for that reason
the adjustment point and installation screws should absolutely never be touched.
4) Laser beams may damage the eyes!
Absolutely never permit laser beams to enter the eyes!
Also NEVER switch ON the power to the laser output part (lens, etc.) of the pick-up if it is damaged.
Pressure
Magnet
Pressure
Conductive Sheet
6) Never attempt to disassemble the pick-up.
Spring has excess pressure. If the lens is extremely dirty, apply isopropyl alcohol to the cotton swab.
(Do not use any other liquid cleaners, because they will damage the lens.) Take care not to use too much
of this alcohol on the swab, and do not allow the alcohol to get inside the pick-up.
1-2
Resistor
(1 Mohm)
Resistor
(1 Mohm)
Conductive
Sheet
1-3
ESD PRECAUTIONS
Electrostatically Sensitive Devices (ESD)
Some semiconductor (solid state) devices can be damaged easily by static electricity. Such components
commonly are called Electrostatically Sensitive Devices (ESD). Examples of typical ESD devices are integrated
circuits and some field-effect transistors and semiconductor chip components. The following techniques should
be used to help reduce the incidence of component damage caused by static electricity.
1. Immediately before handling any semiconductor component or semiconductor-equipped assembly, drain off
any electrostatic charge on your body by touching a known earth ground. Alternatively, obtain and wear a
commercially available discharging wrist strap device, which should be removed for potential shock reasons
prior to applying power to the unit under test.
2. After removing an electrical assembly equipped with ESD devices, place the assembly on a conductive surface
such as aluminum foil, to prevent electrostatic charge buildup or exposure of the assembly.
3. Use only a grounded-tip soldering iron to solder or unsolder ESD devices.
4. Use only an anti-static solder removal device. Some solder removal devices not classified as "anti-static" can
generate electrical charges sufficient to damage ESD devices.
5. Do not use freon-propelled chemicals. These can generate electrical charges sufficient to damage ESD
devices.
6. Do not remove a replacement ESD device from its protective package until immediately before you are
ready to install it. (Most replacement ESD devices are packaged with leads electrically shorted together by
conductive foam, aluminum foil or comparable conductive materials).
7. Immediately before removing the protective material from the leads of a replacement ESD device, touch the
protective material to the chassis or circuit assembly into which the device will by installed.
CAUTION : BE SURE NO POWER IS APPLIED TO THE CHASSIS OR CIRCUIT, AND OBSERVE ALL OTHER
SAFETY PRECAUTIONS.
8. Minimize bodily motions when handing unpackaged replacement ESD devices. (Otherwise harmless motion
such as the brushing together of your clothes fabric or the lifting of your foot from a carpeted floor can generate static electricity sufficient to damage an ESD device).
1-4
Remote control
Pause key-->1-->4-->7-->2 in order.
OPT
OPT
OPT
OPT
OPT
OPT
OPT
OPT
OPT
OPT
OPT
OPT
OPT
OPT
OPT
OPT
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
G
HEX
<A>
44
45
30
FF
22
05
FC
32
AC
00
00
00
00
00
00
00
HEX
<B>
45
53
11
FF
22
05
FC
32
AC
00
00
00
00
00
00
00
HEX
<C>
48
55
20
FF
22
05
FC
32
AC
00
00
00
00
00
00
00
HEX
<D>
52
4F
20
FF
22
05
FC
32
AC
00
00
00
00
00
00
00
1-5
FLD OP-0.
: HT303
HEX
82
CA
21
27
00
MODEL
NAME
OPT 1
OPT 2
OPT 3
OPT 4
OPT 5
: HT353
HEX
82
CA
20
27
00
FLD write ok or up ok
1-6
1-7
SPECIFICATIONS
GENERAL
Power supply
Power consumption
Net Weight
External dimensions (W x H x D)
Operating conditions
Operating humidity
AMPLIFIER
Output Power
(* Depending on the sound mode
settings and the source, there may
be no sound output.)
SPEAKERS (SH33SU)
Impedance
Net Dimensions
(W x H x D)
Net Weight (1EA)
Front/Rear/Center Speaker
(SH33SU-S)
4
99 x 114 x 86 mm
Passive Subwoofer
(SH33SU-W)
8
156 x 325 x 320 mm
0.35 kg
3.5 kg
Front/Rear/Center Speaker
(SH33SD-S)
4
99 x 114 x 86 mm
Passive Subwoofer
(SH33SD-W)
8
156 x 325 x 320 mm
0.35 kg
3.5 kg
SPEAKERS (SH33SD)
Impedance
Net Dimensions
(W x H x D)
Net Weight (1EA)
1-8
NO
YES
Turn power on.
YES
NO
Check power supply circuit.
Is power on?
YES
Does red power led
turn on?
NO
Check laser circuit.
YES
Check disc.
NO
Check tracking servo circuit.
Does it play?
YES
Does it output
audio?
NO
Check audio circuit.
YES
OK
2-1
POWER ON.
YES
NO
Check if
PN103 is ok?
YES
NO
Reconnect it.
YES
NO
Is the Digitron on
correctly?
NO
YES
YES
Check if all
buttons are ok?
YES
NO
Check if
RC2 is ok?
NO
YES
Front B/D ok.
2-2
Check if the
power part of the
front is ok?
NO
Refer to power(SMPS).
YES
Check if
R345~R350
ok?
NO
YES
Replace R345 ~ R350.
NO
Refer to power(SMPS).
YES
Check if the remote
control waveform of PN301
pin5 is ok?
NO
Refer to MICOM circuit.
YES
Check if RC2
voltage is ok(5V)?
NO
YES
Check RM circuit
2-3
POWER ON.
Show LOGO.
YES
YES
Tray closed?
NO
Tray close to closed position.
YES
SLED at inner
side?
NO
SLED moves to inner position.
Recieve
OPEN/ CLOSE
Key?
NO
1. Execute Pressed Key & IR Key.
2. System operation routine loop.
NO
Receive
CLOSE Key?
2-4
TEST.
YES
Check the
AC voltage Power PCBA (110V
or 220V).
NO
YES
Switch on the Power PCBA.
YES
Are the
DC Voltage outputs OK? (12V, 5.6V,
3.5V, 5V,7V, 34V).
NO
YES
Are 3.5V and
5V DC outputs normal on main
PCBA?
NO
YES
Update
FLASH successfully?
NO
YES
1. Check
2. Check
3. Check
RWR.
4. Check
A
Replace FLASH.
2-5
A
YES
Power On.
YES
Show LOGO?
NO
Flash
Memory operates
properly?
NO
YES
YES
SDRAM
works properly?
NO
YES
MT1389/L
VIDEO outputs
properly?
NO
NO
NO
NO
YES
Check AV cable
connection to TV set.
Does
Tray move inside when it
is not at closed
position?
YES
NO
Normal
OPEN_SW,
CLOSE_SW
signal?
YES
Normal
IN_SW & OUT_SW
signal?
YES
Normal
LOAD+ & LOAD-signal?
YES
Check AV cable connection
between main PCBA and
loader. (MECHA)
2-6
B
YES
Does
the SLED move to inner
side when it is at outer
position?
Motor
Driver DRV_MUTE
pin is high?
NO
NO
NO
YES
YES
Motor
Driver DRV_MUTE
pin is High?
YES
SLED+ and
SLED- output
properly?
NO
YES
Do not put in disc
and close tray.
Optical Lens
has movements for
searching Focus?
NO
NO
NO
YES
YES
YES
Check cable connection with
pick-up head.
C
Copyright 2008 LG Electronics. Inc. All right reserved.
Only for training and service purposes
2-7
C
YES
NO
DVDLD or
CDLD output
property?
NO
YES
YES
Collector
voltage of power transistor
is OK?(Q401, Q402)
NO
YES
Check cable connection
between transistor output and
pick-up head.
NO
Laser off.
YES
Disc ID is correct?
NO
Proper
RF signal on MT1389/L.
YES
NO
NO
NO
YES
Check the RF connection
between AM5890 and MT1389/L.
YES
NO
Proper
SPINDLE signal on
MT1389/L.
YES
SPNP
SPNN output
properly?
D
LGE Internal Use Only
YES
Check the cable connection
between spindle and main
PCB.
2-8
D
YES
Proper
signals on A, B, C,
D of MT1389/L.
NO
Focus on ok?
NO
NO
YES
YES
Proper
CD-DVDCT signal
on MT1389/L.
YES
Check CD_DVDCT connection
between AM5890 and
MT1389/L.
Track On OK?
NO
Proper
CD-DVDCT signal
on MT1389/L.
YES
NO
NO
NO
YES
Proper
TRACK signal
on MT1389/L.
YES
YES
Check cable connection
on pick-up head.
Disc Playback?
NO
YES
E
Copyright 2008 LG Electronics. Inc. All right reserved.
Only for training and service purposes
2-9
E
YES
Normal Audio
output when disc
playback?
YES
NO
PWM IC
received correct data
stream?
NO
NO
YES
Normal
PWM IC out?(IC704).
YES
TEST END.
2-10
6. AMP Protection
NO
OK.
YES
Is the IC101 pin54
"LOW" signal(0V)?
NO
Replace IC101.
YES
NO
Is the Q701 and Q702 normal?
YES
Replace ST AMP IC(IC702 and IC703)
2-11
NO
Does Aux,
Scart, opt and FM 87.5
appear at FLD.
NO
Does
no Disc or Time NO
appear at FLD?
Check
if DVD an audio
micom insert is
OK.
Check
power part of Main
B/D.
Check
oscillator o
X101.
NO
Refer to SMPS.
NO
Refer to oscillator circuit.
YES
YES
NO
YES
YES
YES
Does
it appear DVD Error
at FLD?
YES
YES
Check Power.
OK
NO
YES
Does
Loading appear
at FLD?
YES
NO
Check
if IC101 Pin5
is high.
NO
YES
Check
if IC101 Pin9,36,59 are
high(5V).
NO
Check 3.3V line.
YES
YES
Check SMPS.
Check
if IC101 Pin49
is high.
YES
Replace IC101.
2-12
FIG 1-1
1
2
3
4
3
FIG 1-2
4
IC501
Copyright 2008 LG Electronics. Inc. All right reserved.
Only for training and service purposes
2-13
FIG 1-4
2. SDRAM CLOCK
1) MT1389/L main clock is at 27MHz(X501)
DCLK = 93MHz, Vp-p=2.2, Vmax=2.7V
FIG 2-1
2-14
1
1
2
2
3
FIG 3-2
FIG 3-1
1
2
3
4
FIG 3-3
3
4
2-15
1
2
FIG 4-1
3
4
2-16
1
2
1
3
FIG 5-1
3
2
1
3
1
2
2
3
FIG 6-1
2-17
2
3
2
IC501
IC501
LGE Internal Use Only
2-18
2
3
2
IC501
IC501
Copyright 2008 LG Electronics. Inc. All right reserved.
Only for training and service purposes
2-19
8. FOCUS ON WAVEFORMS
1
2
3
IC501
1
2
3
4
3
LGE Internal Use Only
2-20
1
2
1
3
FIG 9-1
2
3
1
2
3
1
4
IC501
FIG 10-1(DVD)
2-21
1
2
3
4
FIG 10-2(CD)
3
4
11. MT1389/L VIDEO OUTPUT WAVEFORMS
1) Full colorbar signal(COMPOSIT)
1
1
FIG 11-1
LGE Internal Use Only
2-22
2) Y
1
1
IC501
FIG 11-2
1 3
ASDATA3
1
2
3
IC501
FIG 12-1
2-23
2)
R703 TP704
R720 TP711
3)
4)
R704 TP707
or
R717 TP705
R709 TP713
5)
6)
R707 TP702
R701 TP708
6
5
4
3
2
1
2-24
FS
DACVSSC
CVBS
DACVDDB
DACVDDA
G
B
R
AADVSS
AKIN2 / GPIO19 / Audio_mute
ADVCM / GPIO20 /
AKIN1 / GPIO21 / Audio_mute
AADVDD
APLLVDD
APLLCAP
ADACVSS2
ADACVSS1
ARF / LFE / GPIO
ARS / GPIO
AR / GPIO0
AVCM
AL / GPIO1
ALS / GPIO
ALF / CENTER / GPIO
ADACVDD1
ADACVDD2
AVDD18_1
AGND18
RFIP
RFIN / OPOUT /
RFG / OPINP /
RFH / OPINN /
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
RFA
RFB
RFC
RFD
RFE
RFF
AVDD18_2
AVDD33_1
XTALI
XTALO
AGND33
V20
V14
REXT
MDI1
MDI2
LDO1
LDO2
AVDD33_2
DMO
FMO
TRAY_OPEN
TRAY_CLOSE
TRO
FOO
FG / GPIO2
USB_DP
USB_DM
VDD33_USB
VSS33_USB
PAD_VRT
VDD18_USB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
MT1389L
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
VREF
DACVDDC
GPIO13
SPDIF / GPIO12
GPIO11
GPIO10
DVDD18
GPIO9
GPIO8
GPIO7 / CKE
RA3
RA2
DVDD33
RA1
RA0
RA10
BA1
DVSS18
BA0
RAS#
CAS#
RWE#
RA4
RA5
RA6
RA7
RA8
RA9
DVDD33
RA11
RCLK
DQM1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
RD8
RD9
RD10
RD11
DVSS33
RD12
RD13
RD14
RD15
DQM0
DVDD18
RD7
RD6
RD5
DVDD33
RD4
RD3
RD2
RD1
RD0
IR
PRST#
ICE
UP1_7 / SDA
UP1_6 / SCL
SF_CK
SF_DI
SF_DO
SF_CS_
GPIO6
GPIO4
GPIO3 / INT#
2-25
1. IC501 MPEG(MT1389L)
BLOCK DIAGRAM
DVD
PUH
Module
Debug
Port
CVBS, Y/C
Component
Video
108MHz
TV Encoder
RF Amplifier
Video DAC
Servo IO
Motor
Drive
Servo
Processor
Video
Processor
Spindle
Control
FLASH
ROM
Deinterlacer
MPEG-1/2/4
Memory
Controller
Audio
DSP
JPEG
Video Decoder
Internal
6ch Audio DACs
6ch Audio Analog
outputs
DRAM
PCM output
System
Parser
Audio
Ouptut
CPPM/CPR
M
DRM
GPIO
System
CPU
SDPIF
Audio Mic1
32-bit
RISC
Audio Mic2
In ternal
Audio ADC
IR/VFD
Audio
DAC
2-26
MS/SD/MMC
Card
Controller
MS/SD/MMC
Flash Card
1. IC501 MPEG(MT1389L)
PIN DESCRIPTION
Abbreviations:
SR: Slew Rate
PU: Pull Up
PD: Pull Down
SMT: Schmitt Trigger
4mA~16mA: Output buffer driving strength.
Pin
Main
125
126
127
128
1
2
3
4
5
6
7
8
9
10
11
12
13
RFIP
RFIN
RFG
RFH
RFA
RFB
RFC
RFD
RFE
RFF
AVDD18_2
AVDD33_1
XTALI
XTALO
AGND33
V20
V14
14
REXT
15
16
17
18
19
20
21
22
23
MDI1
MDI2
LDO1
LDO2
AVDD33_2
DMO
FMO
TRAY_OPEN
TRAY_CLOSE
24
TRO
25
FOO
26
FG
27
28
29
30
31
32
95
96
97
98
99
USB_DP
USB_DM
VDD33_USB
VSS33_USB
PAD_VRT
VDD18_USB
DACVDDC
VREF
FS
DACVSSC
CVBS
Alt.
OPOUT
OPINP
OPINN
GPIO2
Type
Description
Analog I nterface (66)
Analog Input
AC coupled DVD RF signal input RFIP
Analog Input
AC coupled DVD RF signal input RFIN
Analog Input
Main beam, RF AC input path
Analog Input
Main beam, RF AC input path
Analog Input
RF main beam input A
Analog Input
RF main beam input B
Analog Input
RF main beam input C
Analog Input
RF main beam input D
Analog Input
RF sub beam input E
Analog Input
RF sub beam input E
Analog power
Analog 1.8V power
Analog power
Analog 3.3V power
Input
27MHz crystal input
Output
27MHz crystal output
Analog Ground
Analog Ground
Analog output
Reference voltage 2.0V
Analog output
Reference voltage 1.4V
Current reference input. It generates reference current for
Analog Input
RF path. Connect an external 15K resistor to this pin and
AVSS
Analog Input
Laser power monitor input
Analog Input
Laser power monitor input
Analog Output
Laser driver output
Analog Output
Laser driver output
Analog Power
Analog 3.3V power
Analog Output
Disk motor control output. PWM output
Analog Output
Feed motor control. PWM output
Analog Output
Tray PWM output/Tray open output
Analog Output
Tray PWM output/Tray close output
Tracking servo output. PDM output of tracking servo
Analog Output
compensator
Focus servo output. PDM output of focus servo
Analog Output
compensator
1) Motor Hall sensor input
Analog
2) GPIO
Analog Input
USB port DPLUS analog pin
Analog Input
USB port DMINUS analog pin
USB Power
USB Power pin 3.3V
USB Ground
USB ground pin
Analog Inout
USB generating reference current
USB Power
USB Power pin 1.8V
Power
Power
Analog
Bandgap reference voltage
Analog
Full scale adjustment (suggest to use 560 ohm)
Ground
Ground pin for video DAC circuitry
Analog
Analog composite output
2-27
Pin
100
101
102
103
104
105
`
Main
DACVDDB
DACVDDA
Y/G
B/CB/PB
R/CR/PR
AADVSS
106
AKIN2
107
ADVCM
108
AKIN1
109
110
111
112
113
AADVDD
APLLVDD3
APLLCAP
ADACVSS2
ADACVSS1
114
ARF / LFE
GPIO
115
ARS
GPIO
116
AR
117
AV CM
118
AL
GPIO
119
ALS
GPIO
120
ALF /CENTER
GPIO
121
122
123
124
ADACVDD1
ADACVDD2
AVDD18_1
AGND18
54, 90
DVDD18
Alt.
Type
Power
Power
Analog
Analog
Analog
Ground
Description
3.3V power pin for video DAC circuitry
3.3V power pin for video DAC circuitry
Green, Y, SY, or CVBS
Blue, CB/PB, or SC
Red, CR/PR, CVBS, or SY
Ground pin for 2ch audio ADC circuitry
1) Audio ADC input 2
2) MS_CLK set B
3) MCDATA
Analog
4) Audio Mute
5) HSYN/VSYN output
6) C5
7) GPIO
1) 2ch audio ADC reference voltageC
Analog
2) C6
3) GPIO
1) Audio ADC input 1
2) MS_D0 set B
3) Audio Mute
Analog
4) HSYN/VSYN output
5) C7
6) GPIO
Power
3.3V power pin for 2ch audio ADC circuitry
Power
3.3V Power pin for audio clock circuitry
Analog InOut
APLL external capacitance connection
Ground
Ground pin for audio DAC circuitry
Ground
Ground pin for audio DAC circuitry
1) Audio DAC sub-woofer channel output
2) While internal audio DAC not used:
Analog Output
a. ACLK
b. GPIO
1) Audio DAC right Surround channel output
2) While internal audio DAC not used:
Analog Output
a. ABCK
b. GPIO
1) Audio DAC right channel output
2) While internal audio DAC not used:
Analog Output
a. SDATA2
b. GPIO
c. RXD2
Analog
Audio DAC reference voltage
1) Audio DAC left channel output
2) While internal audio DAC not used:
Analog Output
a. SDATA1
b. GPIO
c. RXD1
1) Audio DAC left Surround channel output
2) While internal audio DAC not used:
Analog Output
a. ALRCK
b. GPIO
1) Audio DAC center channel output
2) While internal audio DAC not used:
Analog Output
a. ASDATA0
b. GPIO
Analog Power
3.3V power pin for audio DAC circuitry
Analog Power
3.3V power pin for audio DAC circuitry
Analog Power
Analog 1.8V power
Analog Ground
Analog Ground
General Power/ Ground (7)
Power
1.8V power pin for internal digital circuitry
2-28
Pin
79
50, 68,84
60
Main
DVSS18
DVDD33
DVSS
Alt.
33
GPIO3
INT#
34
GPIO4
35
GPIO6
36
SF_CS_
37
SF_DO
38
SF_DI
39
SF_CK
40
UP1_6
SCL
41
UP1_7
SDA
42
ICE
43
PRST#
44
IR
Dram
45
RD0
46
RD1
47
RD2
48
RD3
49
RD4
51
RD5
52
RD6
53
RD7
55
DQM0
56
RD15
57
RD14
58
RD13
Type
Description
Ground
1.8V Ground pin for internal digital circuitry
Power
3.3V power pin for internal digital circuitry
Ground
3.3V Ground pin for internal digital circuitry
Micro Controller , Flash I nterface and GPIO(12)
InOut
1) General purpose IO 3
8mA, SR
2) Microcontroller external interrupt 1
PD, SMT
InOut
General purpose IO 4
4mA, PD
InOut
General purpose IO 6
4mA, PD
InOut
8mA, SR
Serial Flash Chip Select
PU, SMT
InOut
8mA, SR
Serial Flash Dout
PD, SMT
InOut
8mA, SR
Serial Flash Din
PU, SMT
InOut
8mA, SR
Serial Flash Clock
PD, SMT
InOut
1) Microcontroller port 1-6
8mA, SR
2) I2C clock pin
PU, SMT
InOut
1) Microcontroller port 1-7
4mA, SR
2) I2C data pin
PU, SMT
Input
Microcontroller ICE mode enable
PD, SMT
Input
Power on reset input, active low
PU, SMT
Input
IR control signal input
SMT
Interface (37) (Sorted by position)
InOut
DRAM data 0
4mA
InOut
DRAM data 1
4mA
InOut
DRAM data 2
4mA
InOut
DRAM data 3
4mA
InOut
DRAM data 4
4mA
InOut
DRAM data 5
4mA
InOut
DRAM data 6
4mA
InOut
DRAM data 7
4mA
InOut
Data mask 0
4mA, PD
InOut
DRAM data 15
4mA
InOut
DRAM data 14
4mA
InOut
DRAM data 13
4mA
2-29
Pin
Main
59
RD12
61
RD11
62
RD10
63
RD9
64
RD8
65
DQM1
66
RCLK
67
RA11
69
RA9
70
RA8
71
RA7
72
RA6
73
RA5
74
RA4
75
RWE#
76
CAS#
77
RAS#
78
BA0
80
BA1
81
RA10
82
RA0
83
RA1
85
RA2
86
RA3
87
GPIO7
Alt.
CKE
Type
InOut
4mA
InOut
4mA
InOut
4mA
InOut
4mA
InOut
4mA
InOut
4mA, PD
InOut
4mA, PD
InOut
4mA, PD
InOut
4mA, PD
InOut
4mA, PD
InOut
4mA, PD
InOut
4mA, PD
InOut
4mA, PD
InOut
4mA, PD
Output
4mA, PD
Output
4mA, PD
Output
4mA, PD
InOut
4mA, PD
InOut
4mA, PD
InOut
4mA, PD
InOut
4mA, PD
InOut
4mA, PD
InOut
4mA, PD
InOut
4mA, PD
InOut
4mA, PD
Description
DRAM data 12
DRAM data 11
DRAM data 10
DRAM data 9
DRAM data 8
Data mask 1
Dram clock
DRAM address bit 11
DRAM address 9
DRAM address 8
DRAM address 7
DRAM address 6
DRAM address 5
DRAM address 4
DRAM Write enable, active low
DRAM column address strobe, active low
DRAM row address strobe, active low
DRAM bank address 0
DRAM bank address 1
DRAM address 10
DRAM address 0
DRAM address 1
DRAM address 2
DRAM address 3
1)
2)
3)
4)
5)
6)
GPIO 7
Dram Clock Enable
MS_CLK set A
Audio Mute
HSYN/VSYN input
C0
1)
2)
3)
4)
5)
GPIO8
MS_BS set A
SD_CLK set A
ASDATA2
ACLK
GPIO (6)
88
GPIO8
InOut
4mA, PD
2-30
Pin
Main
Alt.
89
GPIO9
InOut
4mA, PD
91
GPIO10
InOut
4mA, PD
92
GPIO11
InOut
4mA, PD
93
SPDIF
94
GPIO13
GPIO12
Type
InOut
2mA, PD
InOut
4mA, PD
Description
6) Audio Mute
7) HSYN/VSYN input
8) C1
1) GPIO9
2) MS_D0 set A
3) SD_CMD set A
4) ASDATA1
5) ABCK
6) C2
7) RXD1
1) GPIO10
2) SD_CLK set B
3) SD_D0 set A
4) ASDATA0
5) ALRCK
6) HSYN/VSYN output
7) C3
8) TXD1
1) GPIO11
2) SD_CMD set B
3) MS_BS set B
4) Audio Mute
5) HSYN/VSYN output
6) C4
1) SPDIF output
2) GPIO12
1) GPIO13
2) SD_D0 set B
3) ALRCK
4) Audio Mute
5) YUVCLK
2-31
BLOCK DIAGRAM
2-32
1. IC501 MPEG(MT1389L)
PIN DESCRIPTION
2-33
3. IC101 MICOM1389L)
P31
P30
VSS3
VDD3
PC7/DBGP2
PC6DBGP1
PC5/DBGP0
PC4
PC3
PC2
PC1
PC0
P86/AN6
P85/AN5
P84/AN4
P83/AN3
PIN CONFIGURATION
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
P70/INT0/T0LCP/AN8
49
32
P32/UTX1
P71/INT1/T0HCP/AN9
50
31
P33/URX1
P72/INT2/T0IN/NKIN
51
30
P34/UTX2
P73/INT3/T0IN
52
29
P35/URX2
RES
53
28
P36
XT1/AN10
54
27
P37
XT2/AN11
55
26
P27/INT5/T1IN
VSS1
56
25
P26/INT5/T1IN
CF1
57
24
P25/INT5/T1IN
CF2
58
23
P24/INT5/T1IN/INT7
VDD1
59
22
P23INT4/T1IN
P80/AN0
60
21
P22/INT4/T1IN
P81/AN1
61
20
P21/INT4/T1IN
P82/AN2
62
19
P20/INT4/T1IN/INT6
63
18
P07/T7O
64
17
P06/T6O
9 10 11 12 13 14 15 16
P13/SO1
P14/SI1/SB1
P15/SCK1
P16/T1PWML
P17/T1PWMH/BUZ
PWM2
PWM3
VDD2
2-34
P05/CKO
P04
P03
P02
P01
P00
VSS2
1
P12/SCK0
P10/SO0
P11/SI0/SB0
LC87F5M64A
Top view
BLOCK DIAGRAM
Interrupt control
IR
Standby control
ROM correct
CF
Xtal
Flash ROM
Clock
generator
RC
PLA
MRC
PC
SIO0
Bus interface
SIO1
Port 0
ACC
Timer 0
Port 1
B register
Timer 1
Port 2
C register
Timer 4
Port 7
ALU
Timer 5
Port 8
Timer 6
ADC
PSW
Timer 7
INT0 to INT7
Noise filter
RAR
Base timer
Port 3
RAM
PWM2/3
Port C
Stack pointer
UART1
Watchdog timer
UART2
On-chip Debugger
2-35
3. IC101 MICOM
PIN DESCRIPTION
Pin Name
I/O
Description
Option
VSS1, VSS2
VSS3
No
VDD1, VDD2
VDD3
No
Yes
Port 0
I/O
P00 to P07
I/O
Yes
P10 to P17
I/O
Yes
Rising
Falling
INT4
enable
enable
INT5
enable
enable
INT6
enable
INT7
enable
Rising/
H level
L level
enable
disable
disable
enable
disable
disable
enable
enable
disable
disable
enable
enable
disable
disable
2-36
Falling
Pin Name
Port 7
I/O
I/O
Description
Option
No
P70 to P73
Port 8
I/O
Rising
Falling
INT0
enable
enable
INT1
enable
enable
INT2
enable
INT3
enable
Rising/
H level
L level
disable
enable
enable
disable
enable
enable
enable
enable
disable
disable
enable
enable
disable
disable
Falling
No
P80 to P86
Shared pins
AD converter input port : AN0 (P80) to AN6 (P86)
PWM2
I/O
PWM3
Port 3
No
I/O
Yes
P30 to P37
I/O
Yes
PC0 to PC7
Input
Reset pin
No
XT1
Input
No
Shared pins
General-purpose input port
AD converter input port : AN10
Must be connected to VDD1 if not to be used.
XT2
I/O
No
Shared pins
General-purpose I/O port
AD converter input port : AN11
Must be set for oscillation and kept open if not to be used.
CF1
Input
No
CF2
Output
No
2-37
4. IC201 ADC(CS5345)
TSTI
NC
NC
NC
SDOUT
SCLK
LRCK
MCLK
DGND
VD
INT
OVFL
PIN CONFIGURATION
48 47 46 45 44 43 42 41 40 39 38 37
SDA/CDOUT
36
VLS
SCL/CCLK
35
TSTO
AD0/CS
34
NC
AD1/CDIN
33
NC
VLC
32
AGND
RESET
31
AGND
AIN3A
30
VA
AIN3B
29
PGAOUTB
AIN2A
28
PGAOUTA
AIN2B
10
27
AIN6B
AIN1A
11
26
AIN6A
AIN1B
12
25
MICBIAS
CS5345
2-38
AIN5B
AIN5A
AIN4B/MICIN2
AIN4A/MICIN1
TSTO
FILT+
TSTO
VQ
AFILTB
AFILTA
VA
AGND
13 14 15 16 17 18 19 20 21 22 23 24
4. IC201 ADC(CS5345)
BLOCK DIAGRAM
+3.3V to +5V
10 F
0.1 F
0.1 F
VD
+1.8V
to +5V
0.1 F
0.1 F
+3.3V to +5V
10 F
VA
VA
3.3 F
PGAOUTA
VLS
3.3 F
PGAOUTB
MCLK
SCLK
Digital Audio
Capture
AIN1A
1800 pF *
LRCK
SDOUT
AIN1B
INT
1800 pF
AIN2A
OVFL
1800 pF *
10 F 100
100 k
10 F
100 k
100
10 F 100
100 k
10 F
100 k
RESET
MicroController
SCL/CCLK
AIN2B
1800 pF
100
SDA/CDOUT
AIN3A
AD1/CDIN
1800 pF *
AD0/CS
2k
AIN3B
2k
See Note 1
+1.8V
to +5V
VLC
1800 pF *
AIN4B/MICIN2
1800 pF
AIN5A
NC
NC
NC
NC
NC
AIN4A/MICIN1
0.1 F
1800 pF
1800 pF *
AIN5B
1800 pF
AINA
TSTI
TSTO
TSTO
TSTO
1800 pF *
AIN6B
1800 pF
10 F
0.1 F
47 F
AGND
AGND
0.1 F
AFILTA
AFILTB
AGND
DGND
2-39
100 k
10 F
100 k
100
10 F 100
100 k
10 F
100 k
100
10 F 100
100 k
10 F
100 k
100
10 F 100
100 k
10 F
100 k
100
See Note 2
MICBIAS
VQ
FILT+
10 F 100
47 F
*
RL
*
2.2nF 2.2nF
PIN DESCRIPTION
Pin Name
Pin Description
SDA/CDOUT
Serial ControlData (Input/Output) - SDA is a data I/O in IC Mode. CDOUT is the output data line for
the control port interface in SPITM Mode.
SCL/CCLK
Serial Control Port Clock (Input) - Serial clock for the serial control port.
AD0/CS
Address Bit 0 (IC) / Co ntrol Port Chip Select (SPI) (Input) - AD0 is a chip address pin in IC Mode;
CS is the chip-select signal for SPI format.
AD1/CDIN
Address Bit 1 (IC) / Ser ial Control Data Input (SPI) (Input) - AD1 is a chip address pin in IC Mode;
CDIN is the input data line for the control port interface in SPI Mode.
VLC
ControlPort Power (Input) - Determines the required signal level for the control port interface. Refer
to the Recommended Operating Conditions for appropriate voltages.
RESET
Reset (Input) - The device enters a low-power mode when this pin is driven low.
AIN3A
AIN3B
7
8
Stereo Analog Input 3 (Input) - The full-scale level is specified in the ADC Analog Characteristics
specification table.
AIN2A
AIN2B
9
10
Stereo Analog Input 2 (Input) - The full-scale level is specified in the ADC Analog Characteristics
specification table.
AIN1A
AIN1B
11
12
Stereo Analog Input 1 (Input) - The full-scale level is specified in the ADC Analog Characteristics
specification table.
AGND
13
Analog Ground (Input) - Ground reference for the internal analog section.
VA
14
Analog Power (Input) - Positive power for the internal analog section.
AFILTA
15
Antialias Filter Connection (Output) - Antialias filter connection for the channel A ADC input.
AFILTB
16
Antialias Filter Connection (Output) - Antialias filter connection for the channel B ADC input.
VQ
17
Quiescent Voltage (Output) - Filter connection for the internal quiescent reference voltage.
TSTO
18
FILT+
19
Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.
TSTO
20
AIN4A/MICIN1
AIN4B/MICIN2
21
22
Stereo Analog Input 4 / MicrophoneInput 1 & 2 (Input) - The full-scale level is specified in the ADC
Analog Characteristics specification table.
AIN5A
AIN5B
23
24
Stereo Analog Input 5 (Input) - The full-scale level is specified in the ADC Analog Characteristics
specification table.
MICBIAS
25
MicrophoneBias Supply (Output) - Low-noise bias supply for external microphone. Electrical characteristics are specified in the DC Electrical Characteristics specification table.
AIN6A
AIN6B
26
27
Stereo Analog Input 6 (Input) - The full-scale level is specified in the ADC Analog Characteristics
specification table.
PGAOUTA
PGAOUTB
28
29
PGA Analog AudioOutput(Output) - Either an analog output from the PGA block or high impedance.
VA
30
Analog Power (Input) - Positive power for the internal analog section.
AGND
31
32
Analog Ground (Input) - Ground reference for the internal analog section.
NC
33
34
No Connect - These pins are not connected internally and should be tied to ground to minimize any
potential coupling effects.
TSTO
35
VLS
36
Serial Audio Interface Power (Input) - Determines the required signal level for the serial audio interface. Refer to the Recommended Operating Conditions for appropriate voltages.
TSTI
37
NC
38,
39,
40
No Connect - These pins are not connected internally and should be tied to ground to minimize any
potential coupling effects.
SDOUT
41
Serial Audio Data Output (Output) - Output for twos complement serial audio data.
SCLK
42
Serial Clock (Input/Output) - Serial clock for the serial audio interface.
LRCK
43
Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the
serial audio data line.
MCLK
44
Master Clock (Input/Output) - Clock source for the ADCs delta-sigma modulators.
DGND
45
Digital Ground (Input) - Ground reference for the internal digital section.
VD
46
Digital Power (Input) - Positive power for the internal digital section.
INT
47
OVFL
48
2-40
5. IC704 PWM
PWM3_M
IO_VSS
PWM2_P
PWM2_M
53
52
51
PWM3_P
54
PWM4_M
58
55
PWM4_P
59
IO_VSS
IO_VSS
60
IO_VDD
PWM5_M
61
56
PWM5_P
62
57
IO_VSS
DVSS
63
PWM6_P
68
IO_VDD
IO_VSS
69
64
PWM7_M
70
65
PWM7_P
71
PWM6_M
IO_VDD
72
DVDD
IO_VSS
73
66
PWM8_M
74
67
PWM8_P
75
PIN CONFIGURATION
OVERLOAD
76
50
IO_VSS
EPD_ENA
77
49
PWM1_P
SO/SDA
78
48
PWM1_M
SCK/SCL
79
47
IO_VDD
DVDD
80
46
PWM_HP_L_P
DVSS
81
45
PWM_HP_L_M
SI/I2C_AD0
82
44
IO_VSS
/CS/I2C_AD2
83
43
DVSS
SPI/I2C
84
42
DVDD
IO_VSS
85
41
PWM_HP_R_P
XIN
86
40
PWM_HP_R_M
XOUT
87
39
IO_VDD
DMIX_LRCK
88
38
IO_VSS
DMIX_BCK
89
37
PWM_SWL_P
DMIX_SDOUT
90
36
PWM_SWL_M
DVDD
91
35
DVSS
DVSS
92
34
DVDD
DMIX_MCLK
93
33
MIC_SDIN
IO_VDD
94
32
MIC_LRCK
IO_VSS
95
31
MIC_BCK
/RESET
96
30
MIC_MCLK
TEST_MODE1
97
29
IO_VDD
TEST_MODE2
98
28
IO_VSS
SCAN_ENA
99
27
EXT_MUTE
100
26
SSDIN3
14
15
16
17
18
19
20
21
22
23
24
25
DVSS
MSDIN0
MSDIN1
MSDIN2
MSDIN3
SBCK
SLRCK
IO_VSS
IO_VDD
SSDIN0
SSDIN1
SSDIN2
9
IO_VSS
13
8
PLL_AVSS
DVDD
7
IO_VSS
12
6
PLL_AVDD
11
5
IO_VSS
MBCK
4
IO_VDD
MLRCK
3
PLL_DVDD
10
IO_VDD
1
IO_VSS
PLL_DVSS
TEST_MODE3
PULSUS
BLOCK DIAGRAM
Serial
Audio
Output
interface
Down
Mixer
Automatic
Gain
Limiter
Input
Mapper
PWM3_P/M
PWM4_P/M
PWM5_P/M
PWM6_P/M
PWM7_P/M
Internal Reset
PWM8_P/M
PWM_HP_L_P/M
PWM_HP_R_P/M
POP
NR
2-41
EPD_ENA
OVERLOAD
IO_VSS
IO_VDD
DVSS
Power Supply
PLL
DVDD
Crystal
Oscillator
PWM_SWL_P/M
PLL_AVSS
Internal Controls
XOUT
Host
Interface
(I2C, SPI)
XI N
EXT_MUTE
Trim
Volume
Main
Volume
PWM
Modulator
Internal Clock
DMIX_SDOUT
PWM2_P/M
Mic.
Input
Processor
SPI/I2C
SO/SDA
SCK/SCL
SI/I2C_AD0
/CS/I2C_AD2
Bass
Manager
PLL_AVDD
MIC_BCK
MIC_LRCK
MIC_SDIN
EQ
/RESET
MIC_MCLK
Mixer
DMIX_MCLK
OLRCK
OBCK
PWM1_P/M
Output Mapper
Sample
Rate
Converter
Serial Audio
Output
interface
PLL_DVSS
SBCK
SLRCK
SSDIN[0:3]
Input
&
Output
MUX
PLL_DVDD
MBCK
MLRCK
MSDIN[0:3]
5. IC704 PWM
PIN DESCRIPTION
Name
Pin NO.
Type
Description
Power and Ground
PLL_AVDD
Analog
Power
PLL_AVSS
Analog
Ground
PLL_DVDD
PLL
Power
PLL_DVSS
PLL
Ground
DVDD
Power
DVSS
Ground
IO_VDD
4,
10, 22, 29, 39, 47,
56, 65, 72, 94
Power
IO_VSS
1, 5, 7, 9, 21,
28, 38, 44, 50,
53, 57, 60, 64,
69, 73, 85, 95
Ground
96
XIN
86
Analog
XOUT
87
Analog
11
I/O
MLRCK
12
I/O
MSDIN [3:0]
SBCK
19
I/O
SLRCK
20
I/O
SSDIN [3:0]
I/O
2-42
MIC_MCLK
30
MIC_BCK
31
I/O
MIC_LRCK
32
I/O
MIC_SDIN
33
DMIX_MCLK
93
DMIX_BCK
89
DMIX_LRCK
88
DMIX_SDOUT
90
PWM1_P
49
PWM1_M
48
PWM2_P
52
PWM2_M
51
PWM3_P
55
PWM3_M
54
PWM4_P
59
PWM4_M
58
PWM5_P
62
PWM5_M
61
PWM6_P
68
PWM6_M
67
PWM7_P
71
PWM7_M
70
PWM8_P
75
PWM8_M
74
PWM_HP_L_P
46
PWM_HP_L_M
45
PWM_HP_R_P
41
PWM_HP_R_M
40
PWM_SWL_P
37
PWM_SWL_M
36
SPI/I2C
84
SO/SDA
78
I/O
2-43
SCK/SCL
79
SI/I2C_AD0
82
/CS/I2C_AD2
83
Chip selector (CS) for SPI mode or Slave Address 2 for I2C
mode.
Schmitt-Trigger input.
Internal pull-down resistor.
27
OVERLOAD
76
EPD_ENA
77
TEST_MODE1
97
TEST_MODE2
98
SCAN_ENA
99
TEST_MODE3
100
All inputs and bi-directional inputs are 5 Volt tolerant. The corresponding pins can be connected to the buses that can
swing between 0V and 5V. The output-only pins are not 5V tolerant and the buses they are connected to can swing only
between 0V and 3.3V.
2-44
WIRING DIAGRAM
CABLE1
PN202
2007. 11. 30
2-45
2-46
2007. 11. 30
2-47
2-48
CIRCUIT DIAGRAMS
1. SMPS(POWER) CIRCUIT DIAGRAM
IMPORTANT SAFETY NOTICE
WHEN SERVICING THIS CHASSIS, UNDER NO CIRCUMSTANCES SHOULD THE ORIGINAL DESIGN BE
MODIFIED OR ALTERED WITHOUT PERMISSION
FROM THE LG CORPORATION. ALL COMPONENTS
SHOULD BE REPLACED ONLY WITH TYPES IDENTICAL TO THOSE IN THE ORIGINAL CIRCUIT. SPECIAL
12
11
10
NOTES)
NOTE)
NOTE)
NOTE)
NOTE)
Warning
Parts that are shaded are critical
With respect to risk of fire or
electricial shock.
2007. 11. 30
F
2-49
2-50
12
11
10
2007. 11. 30
A
2-51
2-52
12
11
10
2007. 11. 30
A
2-53
2-54
12
11
10
2007. 11. 30
A
2-55
2-56
12
11
10
2007. 11. 30
A
2-57
2-58
12
11
10
2007. 11. 30
A
2-59
2-60
12
11
10
2007. 11. 30
A
2-61
2-62
12
11
10
2007. 11. 30
A
2-63
2-64
12
11
10
2007. 11. 30
A
2-65
2-66
12
11
10
2007. 11. 30
A
2-67
2-68
2-69
2-70
2-71
2-72
NOTE: Warning
Parts that are shaded are critical With
respect to risk of fire or electrical shock.
2-73
2-74
2-75
2-76
462
A26
250
B
283
A50
463
452
463
A43
C
462
PN302
CABLE1
A47
MA
E
SM
D
PS
PN202
IN
300
465
467
A46
465
E
275
279
FR
A41
ON
A44
JA
CK
262
261
260
3-1
3-2
261
A26
001
002
A02
A01
003
439
018
013
014
020
017
435
016
015B
015
015A
440
026
010
442
012A
012
A03
019
012
442
3-3
3-4
OPTIONAL PART
808 BATTERY
801
OWNER'S MANUAL
804 BAG
803 PACKING, CASING
803 PACKING, CASING
802 BOX
3-5
SPEAKER SECTION
1. SATELLITE SPEAKER(SH33SU-S)
A80
A81
F.L SPK
F.R SPK
A82
CENTER SPK
A83
R.L SPK
A84
R.R SPK
853
852
WIRE80
F.L SPK
WIRE81
F.R SPK
WIRE82
CENTER SPK
WIRE83
R.L SPK
WIRE84
R.R SPK
851
850
3-6
2. SATELLITE SPEAKER(SH33SD-S)
A80
A81
F.L SPK
F.R SPK
A82
CENTER SPK
A83
R.L SPK
A84
R.R SPK
853
WIRE80
852
851
F.L SPK
WIRE81
F.R SPK
WIRE82
CENTER SPK
WIRE83
R.L SPK
WIRE84
R.R SPK
850
3-7
3. PASSIVE SUBWOOFER(SH33SU-W/SH33SD-W)
A90
952
WIRE90
956
950
954
951
955
953
3-8
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. 4-4
. 4-4
. 4-4
. 4-4
4. Rubber Rear . . . . . . . . . . .
5. Frame Assembly Up/Down
6. Belt Loading . . . . . . . . . . .
7. Gear Pulley . . . . . . . . . . . .
8. Gear Loading . . . . . . . . . .
9. Guide Up/Down . . . . . . . .
10. PWB Assembly Loading
11. Base Main . . . . . . . . . . . .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. 4-4
. 4-5
. 4-5
. 4-5
. 4-5
. 4-5
. 4-5
. 4-5
EXPLODED VIEW
1. DECK MECHANISM EXPLODED VIEW (DP-12TV) . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
4-1
Procedure
Parts
Fixing Type
Starting No.
Main Base
4-1
Clamp Assembly
4-1
Disc
1, 2
Plate Clamp
4-1
1, 2, 3
Magnet Clamp
4-1
1, 2, 3, 4
Clamp Upper
4-1
Tray Disc
4-2
1, 6
4-3
4 Screws,
1, 2, 6
Gear Feed
1 Connector
4-3
1 Locking Tabs
1, 2, 6, 8
4-3
Gear
Middle
10 Gear Rack
1 Screw
4-3
1 Screw
Bottom 4-4
9
1, 2, 7
11 Rubber Rear
1, 2, 7
12 Frame Assembly
1, 2
13 Belt Loading
1, 2 ,13
14 Gear Pulley
4-3
Up/Down
16 Guide Up/Down
14
17 PWB Assembly
1, 2, 13
Loading
1 Locking Tab
4-4
4-4
1 Locking Tab
4-4
1 Locking Tab
Bottom 4-4
4-4
1 Hook
2Screw
2 Locking Tabs
4-4
Bottom View
Note
When reassembling, perform the procedure in
reverse order.
The Bottom on Disassembly column of above
Table indicates the part should be disassembled
at the Bottom side.
LGE Internal Use Only
4-2
TRAY DISC
MAIN BASE
DISC CLAMP ASSEMBLY
PLATE CLAMP
MAGNET CLAMP
CLAMP UPPER
(Fig. A)
BASE MAIN
HOLDER
LEVER
BASE MAIN
BASE MAIN
BOTTOM SIDE VIEW
Fig. 4-1
Fig. 4-2
4-3
RUBBER DAMPER
Distinguish upper and
lower sides
(Assemble with care)
RUBBER DAMPER
Distinguish upper and
lower sides
(Assemble with care)
RUBBER DAMPER
BASE PU
(S2)
(S2)
RUBBER DAMPER
Fig. 4-3
4-4
GUIDE UP/DOWN
GEAR LOADING
GEAR PULLEY
SCREW INSERTION
TORGUE CONTROL
(800gf DOWN)
(L6)
(L6)
BASE MAIN
(L4)
BELT LOADING
(H1)
(C2)
(S4)
BASE MAIN
(S4)
(A)
(A)
GUIDE UP/DOWN
(A)
(B)
(L5)
(B)
FIG. (A)
FIG. (B)
GUIDE UP/DOWN
(C)
(B)
GUIDE UP/DOWN
FIG. (C)
Fig. 4-4
Note
4-5
A26
001
002
A02
A01
003
439
018
013
014
020
017
435
016
015B
015
015A
440
026
010
442
012A
012
A03
019
4-6
012
442