Modelling and Controller Design For VSC-HVDC Attached To An Ac Network
Modelling and Controller Design For VSC-HVDC Attached To An Ac Network
Modelling and Controller Design For VSC-HVDC Attached To An Ac Network
ATTACHED TO AN AC NETWORK
Martyn Durrant , Herbert Werner , Keith Abbott
Abstract
In this paper a model and a controller design method for controlling the power and line voltage of a voltage source converter
(VSC) in VSC HVDC (High Voltage Direct Current Transmission) attached to an AC system are introduced. The control structure proposed consists of a cascade from power and
AC voltage onto a VSC current controller. The controller for
the VSC current loop is designed using a standard low order
model and the power and voltage controllers are designed using a model extended to included power and AC voltage behaviour. A good validation of the extended model against a
rigorous PSCAD model is demonstrated for SCR=4.0 .
Introduction
vcld,v clq
Lc
isd,i sq
vl
system
impedance
Rc
DC voltage
icd,icq
vcd, vcq
v DC
AC filter
vs
AC system
d
icd
dt
d
icq
dt
=
=
Rc
icd + icq
Lc
Rc
icq icd
Lc
1
vcld
Lc
1
vclq ,
Lc
(1)
hence AC system strength and SCR [5]. It is therefore proposed to carry out the control design in two stages, leading to
a cascade structure for control of power and line voltage using VSC currents. In this structure the objectives of the slave
controller are to control converter currents to setpoint, attenuate harmonic disturbances from the VSC, and be robust to
unmodelled dynamics effects in the VSC. The objectives of the
master controller are to control power and voltage to setpoint,
and to be robust to changes in AC system characteristics.
where
vcd = m vDC cos vl
(2)
vcld + vl
)
vclq
m=
vclq
sin
vDC
(3)
d
isd
dt
d
isq
dt
=
=
Rs
isd + isq +
Ls
Rc
isq isd
Lc
1
(vs cos s VL ) (4)
Lc
1
(vs sin s )
Lc
vl =
Ls vcld
icd Ls Rc
icd Rs +
Lc
Lc
s
(icq Ls Rc + icq Lc Rs Ls vclq )2
+ vs 1
L2c vs2
(5)
P =vl icd
i md
LQR controller
gain matrix
(2*4)
v dd
i nd
setpoint pre-filters
i dsp
i qsp
1+T 1s
1+T 2s
1+T 1s
1+T 2s
vcld
1
s
v cldr
1
s
v clqr
i cd
linearised
plant
input
DYN
v clq
output
DYN
i cq
i nq
v dq
i mq
x = Ax + Bu
ylinear = Cx
(6)
The controller was designed for operating point 3 using the linear model. A pre-filter was included in the PID controller and
the controller designed using an IMC SISO procedure [9].
ynonlinear = h(ylinear , p)
where the inputs, linear outputs, nonlinear outputs and parameter vector are :
u = [ispd ispq ]T
icd icq T
x = [icd icq
]
s s
ylinear = [icd icq vcld vclq ]T
(7)
ynonlinear = [P vl ]T
p = [vs Rs Ls ]
i.e. it is a linear system (A, B and C are the conventional
state space matrices) with a static non-linearity appended to
its output, the non-linearity being a function of the parameter
vector p.
6.2
o.p.
SCR , power
o.p. 1
SCR=4.0,
power=0.25 pu
o.p. 2
SCR=4.0,
power=1.0 pu
o.p. 3
SCR=1.0,
power=0.25 pu
o.p. 4
SCR=1.0,
power=0.4 pu
o.p. 5
SCR=1.0,
power=0.6 pu
o.p. 6
SCR=1.0,
power=0.79pu
description
id
0.25
spi d
0.2
v cld
power
Current
controller
spi q
AC voltage
Vl
iq
0.1
power change (pu)
v clq
linear model
0.15
VSC
2
0.05
0.05
PID controller
AC voltage
setpoint
0.1
0.15
spP
Vl
Power
setpoint
spP
0.2
voltage (pu)
linear model
non linear model
0.06
0.08
0.1
time(s)
0.12
0.14
0.16
0.18
0.2
Figure 4:
Line voltage change responses to 0.5 pu Change in
ispq at 3 operating points, linear and nonlinear models
0.12
0.14
0.16
0.18
0.2
8 Acknowledgements
This work has been jointly funded by EPSRC and ALSTOM
T&D ltd.
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ABB Review, 1:49, 1998.
0.04
0.1
time(s)
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2001.
0.5
0.02
0.08
References
0.06
0.5
0.04
Figure 5:
6.3
0.02
Conclusions
This paper demonstrates that the 2 state model of the VSC and
the simple linearised model of the VSC connected to an AC
1.2
1.2
PSCAD model
Linear model
0.8
0.8
power(pu)
power(pu)
PSCAD model
Linear model
0.6
0.6
0.4
0.4
0.2
0.2
0.1
0.2
0.3
0.4
time(s)
0.5
0.6
0.7
0.8
1.5
0.1
0.2
0.3
0.4
time(s)
0.5
0.6
1.4
1.3
1.3
1.2
1.2
voltage(pu)
voltage(pu)
0.8
PSCAD model
Linear model
PSCAD model
Linear model
1.4
1.1
1.1
0.9
0.9
0.8
0.8
0.7
0.7
0.6
0.7
1.5
0.1
0.2
0.3
0.4
time(s)
0.5
0.6
0.7
0.8
Figure 6:
Power and voltage responses to 1pu power setpoint
step with LQR,operating point 1
0.6
0.1
0.2
0.3
0.4
time(s)
0.5
0.6
0.7
0.8
Figure 7:
Power and voltage responses to 1pu power setpoint
step with LQR,operating point 3
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