State-of-the-Art

ASIC Design Flow

part 2
David Smola
Vladimr Strako

SCG Czech Design Center

Goals of this presentation:

to understand what ASIC means

to understand how an ASIC is developed

idea

chip realization

OUTLINE:

Introduction

ASIC design flow

ASIC design example

Conclusion

chip application

OUTLINE:

Introduction

ASIC design flow

ASIC design example

Conclusion

Introduction

What is ASIC?

Application Specific Integrated Circuit

Introduction

ASIC is actually an integrated circuit (IC),

so lets talk about its history a bit

Introduction - history

IBM 1996, 180 000

transistors, few grams,
70mm2, 200mW

ENIAC 1946, 17 500

vacuum tubes, 27 tons,
167m2, 150kW

50years

Introduction key milestones

The first transistor: 1947

John Bardeen

Walter Brattain

William Shockley

Introduction key milestones

Integrated circuit invention:

Geoffrey Dummer

Jack Kilby

In 1952 came with an idea

to fabricate multiple circuits
in one substrate.

In February 1959 he applied

for a patent for actually the
first integrated circuit.

Robert Noyce
In April 1961 he was awarded
a patent for the first multitransistor integrated circuit.

Introduction key milestones

The first IC: 1959

One transistor and few passive components on ONE Germanium

substrate. The first usage was in military application.
Ref: Texas Instruments

Introduction

Why are actually nowadays ASICs widely used in highly

specialized applications as well as in mass production?

Lets demonstrate the benefits of ASICs

Introduction example

Example: we want to implement a battery control system

12V
17V
Black
box

Introduction example

Method #1:

Implement the function with passive components

many
supporting
devices

comparator

Introduction example

Method #2:

Implement the function with an ASIC

few
supporting
devices

ASIC

Introduction example

What method is more perspective for a customer in the

following cases:

10 FUNCTIONAL CIRCUITS

10 000 000 FUNCTIONAL CIRCUITS

?
?
?
?

?
?
? ? ?
?

Introduction example

Method #1: suppose we use one IC for 1$, 5 caps for 0.5$,
LM317 for 1$ and PCB for 3$ total =7.5$ per 1PCB
-10 FUNCTIONAL CIRCUITS: 75$
-10 000 000 FUNCTIONAL CIRCUITS: 75Mil $
Method #2: suppose the design work expenses are 1Mil $,
1 set of masks for chip manufacturing 1Mil $, testing
instruments 1Mil $ total = 3Mil $ per 1 designed ASICs
-10 FUNCTIONAL CIRCUITS: 3Mil $
-10 000 000 FUNCTIONAL CIRCUITS: 3Mil +/- 3Mil $
General advantage of ASICs: much cheaper
for a mass production

Introduction example

ASIC circuits in highly specialized fields of engineering:

In all these fields there is just few
ICs needed, but very advanced,
robust and immune.

Introduction advantages

Advantages of ASICs:

An ASIC solution gives better functionality and better

performance than a corresponding discrete solution,
especially for systems requiring low power consumption.

The weight and volume of the final product are often

reduced significantly with ASICs.

An ASIC solution means perfect product economy if the

product is manufactured in a given minimum volume.

An ASIC provides excellent protection against copying of

a product.

Introduction applications

Where do we use ASICs?

In any field of nowadays human activity you can think of:
Any industry
Ecology
Aeronautics
Astronomy
Medical
Military

etc

OUTLINE:

Introduction

ASIC

design flow

ASIC design example

Conclusion

ASIC design flow

When talking about ASICs, we talk about

digital or mixed-mode integrated circuits

The following part will show steps that are followed during
design of an ASIC in AMIS: from initial contact with the
customer to release of the product into production

ASIC design flow

Product
phases
overview:
Product phases overview:
Phase 0 feasibility and quoting
Phase 1 PreStudy
Phase 2 development
Phase 3 Limited production

PreStudy start

PreStudy end
Project plan specified
Design start
Design Tape Out
Testing prototypes
Customer prototype approval

Limited transfer to production

ASIC design flow Phase 0

Phase 0 feasibility and quoting

Customer expectations enter the appropriate
business unit through the Sales Department

The goal:

to evaluate commercial interest of the project

to evaluate the technical feasibility, which
means technology capability, library availability,
test capability, CAD tool, human resources (all
by system architect)
to determine the need for ESD testing

ASIC design flow Phase 1

Phase 1 PreStudy
Customer design requirements are analysed in
detail. Preliminary design activity starts in order
to arrive at Project Specifications

The goal:

to construct a Project Plan

to start a hybrid design (behavioural modelling)
to identify the complete design team members
to sign the Project Specifications and Test
Plan by both customer and the ASIC developer

ASIC design flow Phase 1

Quality level:

determined at the end of prestudy

Quality level measures:

ppm<1 . automotive, medical (life critical), Aero
ppm=1400 medical (not life critical), telecom
(industrial), industrial safety
ppm>400 consumer electronics, telecom
(commercial), industrial, computer peripherals

ASIC design flow Phase 2

Phase 2 Development
The Product Specifications must be signed
before entering this phase. Practical designing
of the ASIC

The goal:
to execute design and layout tasks to fulfil
parameters according to the Product Specifications
to manufacture the prototype and to test it
to receive customers prototype approval

ASIC design flow Phase 2

Actual chip design

TOP-DOWN
Top-level schematic is
constructed before
individual cells are
designed. Behavioural
models of cells are used
Top-down

BOTTOM-UP
The individual cell are
designed at the transistor
level before or in parallel
with the construction of
top-level schematic

design methodology is preferred whenever practical

ASIC design flow Phase 2

Top-down development sub-phases:

Chip level design

Chip level design

Cell / block design
Cell layout
Chip-level layout
Chip-level post-layout
Tech transfer
Fabrication and characterisation
Product reliability qualification
Transfer to production

Cell/block design
Cell layout
Chip-level layout
Chip-level post-layout
Tech transfer
Fab,characterisation
Product reliability q.
Limited transfer to pr.

ASIC design flow Phase 2

Chip level design

BUS
12V

3V

Chip level design

1.2V

REG

BG
ref

Cell/block design
Cell layout

sensor 1

Chip-level layout

analog

Memory bank

digital

OA

Chip-level post-layout
Tech transfer
Fab,characterisation

ref

OA

ADC

C

Product reliability q.
sensor 2

Limited transfer to pr.

OA

OSC
ref

includes top-level floor-planning and top-level simulations

ASIC design flow Phase 2

Cell / block design

analog

digital

OA

Chip level design

C

Cell/block design
Cell layout
Chip-level layout

Manual circuit design

Logic synthesis

Schematic creation

Logic simulation

Chip-level post-layout
Tech transfer
Fab,characterisation
Product reliability q.
Limited transfer to pr.

Automated

/ manual
schematic creation

Schematic simulation

Schematic simulation

ASIC design flow Phase 2

Manual analog cell / block design

Analog block
OpAmp

Circuit topology
2-stage folded cascode OpAmp

OA

System-level kind of
specifications:
- DC gain
- unity gain frequency
- supply voltage
- maximal power
consumption
- noise specifications
- THD specifications

Device parameters
2-stage folded cascode OpAmp

W
10
=
L
0.5

Simulations
(DC, TR, AC, Noise)
Appropriate circuit
topology selection

Device sizing
optimisation, biasing
currents setting,
threshold voltages
setting

iterative
processes

Corner simulations
(slow, fast, high/low temp)

Verified schematic

ASIC design flow Phase 2

Cell / block layout analog or digital

Manual or automated
layout design

Parasitic extraction

schematic update,
simulation with
parasitic devices

LVS, DRC

Chip level design

Cell/block design
Cell layout
Chip-level layout
Chip-level post-layout
Tech transfer
Fab,characterisation
Product reliability q.
Limited transfer to pr.

ASIC design flow Phase 2

LVS Layout Versus Schematic

Device count and device sizes must equal

ASIC design flow Phase 2

DRC Design Rule Check

layouted devices and metal
or silicon tracks must must
have allowed dimensions,
overlapping and spacing

ASIC design flow Phase 2

Chip-level layout

Completion of the chip from cells/blocks into a top-level system

Parasitic extraction, update, simulation with parasitic devices

LVS, DRC

Chip level design

Cell/block design
Cell layout
Chip-level layout
Chip-level post-layout
Tech transfer
Fab,characterisation
Product reliability q.
Limited transfer to pr.

ASIC design flow Phase 2

Chip-level post-layout

Bonding diagram creation

Where applicable, DRC

Chip level design

Cell/block design
Cell layout
Chip-level layout
Chip-level post-layout
Tech transfer
Fab,characterisation
Product reliability q.
Limited transfer to pr.

ASIC design flow Phase 2

Tech transfer

Generating reticle information

Creating masks for lithography

Chip level design

Cell/block design
Cell layout
Chip-level layout
Chip-level post-layout
Tech transfer
Fab,characterisation
Product reliability q.
Limited transfer to pr.

ASIC design flow Phase 2

Fabrication

Wafer fabrication

Packaging

Chip level design

Cell/block design
Cell layout
Chip-level layout
Chip-level post-layout
Tech transfer
Fab,characterisation
Product reliability q.
Limited transfer to pr.

ASIC design flow Phase 2

Testing, characterisation

Chip level design

Cell/block design
Cell layout
Chip-level layout
Chip-level post-layout
Tech transfer
Fab,characterisation
Product reliability q.
Limited transfer to pr.

Prototype evaluation and characterisation

ASIC design flow Phase 2

Product reliability qualification

ESD and latch-up testing

Chip level design

Cell/block design
Cell layout
Chip-level layout
Chip-level post-layout

OBR. ESD testing

Tech transfer
Fab,characterisation
Product reliability q.
Limited transfer to pr.

Life-time testing
(baking, freezing, moisturizing, pressurizing)

ASIC design flow Phase 2

Limited transfer to production

Chip level design

Cell/block design
Cell layout
Chip-level layout
Chip-level post-layout
Tech transfer
Fab,characterisation
Product reliability q.
Limited transfer to pr.

Customer prototype approval

Direction into Phase 3 prototype ready

OUTLINE:

Introduction

ASIC design flow

ASIC

design example

Conclusion

ASIC design examples

ASIC examples fully

developed at AMIS, Brno

ASIC design example #1

System for ADAPTIVE LIGHTING

System description:
shifting lights to either side of the driving direction
so that the light beam direction is adapted as
needed during driving.

ASIC function:

angular position control of a stepper motor

communication with controller and sensors via
bus

ASIC design example #1

The principle of adaptive lighting:

non-adapted
light beam

adapted
light beam

driving direction

ASIC design example #1

The adaptive light bulb with a stepper motor:

ASIC design example #1

The sensors:
driving
direction
sensor

ambient
light
sensor

ASIC design example #1

The IC represents sophisticated system

containing sensors interface, analog and
signal processing, bus communication
interface and supporting functions.

So, what is really hidden behind the words?

ASIC design example #1

ASIC system schematic:

PWIN/sleep

LIN

HW[2:0]

TST

LIN
transceiver

Position controller

Main control
& Registers
OTP + ROM

DACs

PWM
regulator
Y

VBAT
Voltage
regulator

MOTXP

MOTXN

Sinewave
table

LIN slave
controller

Synchronous
I/O controller
(test)

Decoder

PWM
regulator
X

Oscillator
Charge pump

VDD

VCP CPN CPP

Reference voltage
&
Thermal monitoring

MOTYP

MOTYN

ASIC design example #1

ASIC connection:
HALL sensing with PWM output

1 HW0

PWMIN 20

2 HW1

VBAT

C1 100nF

C5 1F
tantalum

19

3 VDD

MOTXP 18

4 GND

GND 17

C6 100nF

5 TST

MOTXN 16

6 LIN

MOTYP 15

LIN bus

ESD
7 GND
Adr Connector

GND 14

R2 1k:

C8 2.7nF

D1

C2 100nF

8 HW2

MOTYN

13

9 CPN

VBAT

12

C4 220nF

C3 220nF

10 CPP

Battery

VCP 11

ASIC design example #1

Design challenges of this ASIC:

controlling quite high currents

motor microstepping via PWM
handling error conditions
automotive requirements (strict ESD,
EMC, EMI, temperature and vibration
conditions)

C0 100F

ASIC design example #1

Example summary:

Challenging analog design

Now in production.

ASIC design example #2

Integrated system for SMART PARKING

System description:
warning of the driver for any obstacle in the
closest vicinity of a car when driving back or forth.

ASIC function:

driving/reading piezo-element
regulation of the ultra-sound level
communication via bus with the control unit

ASIC design example #2

the aim of designers is to reduce accidents

ASIC design example #2

Basic principle:

VBAT

IO
GND

Trafo
ASIC

Piezo

OBSTACLE

ASIC design example #2

R1
100
0.33W

D1
BAS321

L1
ACB2012M_040

Tr
n=7.6

ST1

Piezo
ST4

Rfb1
6k8
C1
330pF

ASIC system
schematic:

Cdd2
22nF

Cdd1
68uF
35V

Ccl
1n5

Rfb2
560
ST5

Cdda
1uF

9: VDD 12: NC

Cref
1uF

11: VDDA

14: VREF

13: NC

5: OUT2

7: OUT1

Rio3
10k
Voltage
Regulators

Oscillator
307.2 kHz

Frequency
Divider

Amplitude
Regulation

Transmit
Power
Stage

1: NC

6: VSSE

24: NC
4: FB
Rio1
47

Rio2
1k

Logic

10: IO

Fosc

2: Testio
TESTS

ST2

17: TestinEE
EEPROM
16: TestioEE

Cio
330p
Threshold
Slope
Control

&

18: Testout1

Vref
40k
15: S

D/A

Cs
4n7

Vref
+

Vref

23: IN
80pF

8: VSSD
ST3

3: Testin

19: V3

20: V2

21: V1

22: VSSA

Rbp1
330k
Cbp1
100p
Cbp2
100p

Rre3
2.87k

ASIC design example #2

Safe parking system in a car

Rre2
220k

Rre1
12k

Cre
330p

ASIC design example #2

example of an ideal usage case:

http://www.leftlanenews.com/2006/02/17/video-bmws-automatic-parking-system/

ASIC design example #2

Design challenges of this ASIC:

receiving sensitivity in a range of mV

very high robustness to ESD, and
temperature conditions
very low EM radiation

OUTLINE:

Introduction

ASIC design flow

ASIC design example

Conclusion

Conclusion

ASIC stands for Application Specific Integrated Circuit

ASIC provides compact solution for complex applications

ASIC solution is well fitted for mass production and for

highly-specialized applications

ASIC is developed in a design flow

The design flow consists from steps design phases:

Design feasibility phase

Pre-study phase

Development phase

Limited Production phase

Intermezzo

What are actually the most often designed analog

building blocks during an ASIC design at AMIS?
operational amplifiers

analog-to-digital converters

transconductance stages

dc-dc converters

comparators

charge pumps

signal filters

regulators

drivers, buffers

bandgap references

oscillators