This document describes a 1-Kbit nonvolatile memory chip. It has the following key features:
- 128 x 8-bit organization with 5V supply voltage
- Data can be reprogrammed over 104 times per address with over 10 year retention
- Serial interface for data transfer using 3 lines - data, clock, and chip enable
- Memory can be erased or written in 10ms by sending control signals down the serial interface
- Operates from 0-70°C
This document describes a 1-Kbit nonvolatile memory chip. It has the following key features:
- 128 x 8-bit organization with 5V supply voltage
- Data can be reprogrammed over 104 times per address with over 10 year retention
- Serial interface for data transfer using 3 lines - data, clock, and chip enable
- Memory can be erased or written in 10ms by sending control signals down the serial interface
- Operates from 0-70°C
This document describes a 1-Kbit nonvolatile memory chip. It has the following key features:
- 128 x 8-bit organization with 5V supply voltage
- Data can be reprogrammed over 104 times per address with over 10 year retention
- Serial interface for data transfer using 3 lines - data, clock, and chip enable
- Memory can be erased or written in 10ms by sending control signals down the serial interface
- Operates from 0-70°C
This document describes a 1-Kbit nonvolatile memory chip. It has the following key features:
- 128 x 8-bit organization with 5V supply voltage
- Data can be reprogrammed over 104 times per address with over 10 year retention
- Serial interface for data transfer using 3 lines - data, clock, and chip enable
- Memory can be erased or written in 10ms by sending control signals down the serial interface
- Operates from 0-70°C
Features Word-organized, reprogrammable nonvolatile memory in
n-channel floating-gate technology
128 8-bit organization Supply voltage 5 V Three lines between control processor and E2PROM for
data transfer and chip control
Serial data bus (eight data bits, seven address bits, one control bit) More than 104 reprogramming cycles per address Data retention for more than ten years (operatingtemperature range) Unlimited number of readout operations without refresh Erase or write in 10 ms Temperature range 0 to 70 C
P-DIP-8
Type
Ordering Code
Package
SDA 2506-5
Q67100-H5090
P-DIP-8
Semiconductor Group
15
06.94
SDA 2506-5
Circuit Description Data Transfer and Chip Control Three lines, each with several functions, are necessary for overall data transfer between the control processor and the E2PROM: a)
Data line D bidirectional serial data transfer serial entry of address and control bit direct control, D = 1 for erase, D = 0 for write
b) Clock line shift clock for data, address and control bits start readout with transfer of data from memory into shift register or start of data change during reprogramming c) Chip-enable line CE chip reset and data input (active high) chip enable (active low) Before the chip is enabled, data, address and control information is clocked in on the bidirectional data bus. These data are retained in the shift register during reprogramming and readout until the second clock pulse. The following data formats have to be entered: a) Readout memory, one 8-bit control word consisting of seven address bits A0 through A6 (A0 first as LSB) one control bit CB = "0" after A6 Reprogram Memory b) Erase, 8-bit input information consisting of seven bits of address information A0 through A6 (A0 first as LSB) one bit of control information CB = "1" after A6 c)
Write, 16-bit input information consisting of
eight bits of new memory information D0 through D7 (D0 first as LSB) seven bits of address information A0 through A6 (A0 first as LSB after D7) one bit of control information CB = "1" after A6
d)
Erase and write, 16-bit input information consisting of
eight bits of new memory information D0 through D7 (D0 first as LSB) seven bits of address information A0 through A6 (A0 first as LSB after D7) one bit of control information CB = "1" after A6
Read (see figure 1)
After data entry, and with CB = 0, the readout operation of the selected word address is started with the transition of CE from "1" to "0". The information on the data line during chip enable has no effect. With the first clock pulse after CE = 0, the data word of the selected memory address is transferred into the shift register. With the trailing edge of the first clock pulse the data output goes lowimpedance and the first data bit D0 can be read on the data pin. Every further clock pulse shifts another data bit to the output. The data line goes high-impedance again when CE changes from "0" to "1". Semiconductor Group
16
SDA 2506-5
Reprogram (see figure 2a, 2b and 3)
A complete reprogramming operation consists of an erase operation followed by a write operation. During erase, all bits of the selected word are set to a uniform 1 state, and during write, 0 states are created according to the information in the shift register. A reprogramming operation is started when, after data entry in chip enable, the control bit CB = "1" appears in the appropriate cell of the shift register. Whether an erase or a write operation is performed will depend on the information on data line D during chip enable. For resetting to the "1" state there must also be a "1" on the data input during the transition of CE from high to low. If a write operation to the 0 state is to be started however, there must be a 0 on the data line during chip enable. Reset A memory that is not selected is automatically in reset status because of the "1" state of CE. All flipflops of the process control are reset. The information in the shift register is retained on the other hand and is not altered until data are shifted. The reset status is also produced by an on-chip circuit when the memory is powered on. After chip enable a start pulse is required on clock line to initiate programming. The control information on data line D must remain stable until the rising edge of the start pulse. The programming operation begins with the trailing edge of the start pulse and ends with transition of CE from low to high. The reprogramming of a word begins with an erase operation. For this the word address is entered together with control bit CB = "1". The entry of the data word is omitted for an erase. But at this point the data for a following write operation can be entered. If this is intended, the data D0 through D7 for the write operation are entered before entry of the control word for the erase operation. For the erase the data line has to be kept high during chip enable, i.e. transition of CE from high to low, and until the falling edge of the start pulse. An erase operation can be followed immediately by a write operation without entry of the data and word address. For this the data line is sent low, CE is again driven from high to low (chip enable) and the start pulse for the write operation is put on clock line . The data line must be kept low until the falling edge of the start pulse (see figure 3). Erase and write can also be executed separately. For writing, a 16-bit control word (word address with control bit CB = "1", data D0-D7) is entered. For erasing, only the word address and CB = "1" are entered. For the erase operation the data line must be kept high during chip enable and until the falling edge of the start pulse, and for the write operation it must be kept low (see figure 2a and 2b). Total Erase If input TP2 (pin 7) is put on VCC = 5 V, this activates the mode for total erasure of memory. The word address 0 and control bit CB = "1" must be entered. The data line has to be kept high during chip enable (transition of CE from high to low) and until the falling edge of the start pulse. A total erase operation is ended when CE goes from low to high and by switching input TP2 to 0 V.
