ANALYSIS OF FULL ADDER FOR POWER

EFFICIENT CIRCUIT DESIGN

A Thesis Submitted
in Partial Fulfilment of the Requirements
for the Degree of
MASTER OF TECHNOLOGY
in

VLSI DESIGN
By

TRAPTI MITTAL
(Roll No. 1202708515)
Under the Supervision of
Asst. Prof. UMA SHARMA
AJAY KUMAR GARG ENGINEERING COLLEGE

to
Department of Electronics & Communication Engineering
DR. A.P.J. ABDUL KALAM TECHNICAL UNIVERSITY
LUCKNOW, INDIA
December, 2015

CERTIFICATE
Certified that Trapti Mittal (1202708515) has carried out the research work
presented in this thesis entitled ANALYSIS OF FULL ADDER FOR POWER
EFFICIENT CIRCUIT DESIGN for the award of Master of Technology from Uttar
Pradesh Technical University, Lucknow under my supervision. The thesis embodies
results of original work, and studies as are carried out by student herself and the
contents of the thesis do not form the basis for the award of any other degree to the
candidate or to anybody else from this or any other University/Institution.

Signature
Asst. Prof. Uma Sharma
Deptt. of Electronics & Comm.Engg.
Ajay Kumar Garg Engineering College

Date- ..
Place: Ghaziabad

ii

ANALYSIS OF THE FULL ADDER FOR THE POWER EFFICIENT

CIRCUIT DESIGN
Trapti Mittal
ABSTRACT
MOS Current Mode Logic (MCML) has surfaced as a logic style that is
capable of achieving high speeds while consuming a lesser amount of power than the
typical CMOS circuits. In this project, an active class of dynamic differential logic
family that specifies a self-timing operations and low output logic swing behaviors are
monitored and investigated. In return, it reduces total power supplied to it. The basic
block is fast enough and consuming low power supply and working on TSMC 180 nm
technology that it can lead to the improved and fast results. If it is properly designed,
MCML circuits can achieve significant power reduction compared to their CMOS
counterparts at lower frequencies.

. An important aspect to be reduced is the power along with Power Delay

Product (PDP) for any synchronous or in-tune design. In order to reduce the total Power
Delay Product (PDP), delay and power should be simultaneously reduced. In the most of
digital circuits, delay is reduced at the cost of increased power and low switching
frequency.

This full adder design will not only be compact in terms of transistor units
but also be fast enough for the large adders to provide the faster switching within its
blocks. This full adder design will speed up the carry part of the circuit so that the next
block proceeds faster. To decrease the delay further, the switching frequency must be
changed.

iii

ACKNOWLEDGMENTS
I place on record and warmly acknowledge the continuous encouragement,
invaluable supervision, timely suggestions and inspired guidance offered by my guide
Asst. Prof. Uma Sharma, Department of Electronics and Communication Engineering,
Ajay Kumar Garg Engineering College, Ghaziabad, in bringing this report to a
successful completion. Without her wise counsel and able guidance, it would have been
impossible for me to complete the thesis in this manner.

I am grateful to Dr. P.K. Chopra, Prof. & Head of the Department of

Electronics and Communication Engineering, for permitting us to make use of the
facilities available in the department to carry out the thesis successfully.

I also would like to extend my gratitude to Dr R. K. Agarwal, Director of

Ajay Kumar Garg engineering College, who provides all the facilities needed for
completing the project and with his encouraging words, he motivated us a lot for
completing the project. Last but not the least sincere thanks is expressed to all of our
friends who have patiently extended all sorts of help for accomplishing this undertaking.
Also all those who are directly or indirectly involved in the successful completion of this
thesis work.

Trapti Mittal

iv

TABLE OF CONTENTS

CHAPTER 1.
1.1
1.2
1.3
1.4
CHAPTER 2.
2.1
2.2
2.3
CHAPTER 3.
3.1
3.2

3.3
3.4
3.5
3.6
3.7
3.8

CHAPTER 4.

Certificate
Abstract
Acknowledgements
List of Tables
List of Figures
List of Abbreviations
INTRODUCTION
INTRODUCTION
LITERATURE REVIEW
OBJECTIVE
REPORT ORGANIZATION
DESIGN OF ADDER STRUCTURE
BACKGROUND
ADDER DESIGN
RIPPLE CARRY ADDER
2.3.1 Ripple Carry Addition
POWER REDUCTION TECHNIQUES
POWER
POWER CONSUMPTION COMPONENTS
3.2.1
Static Power Consumption
3.2.2
Dynamic Power Dissipation
DIODE LEAKAGE CURRENT
BIASING CURRENT
SUB THRESHOLD LEAKAGE CURRENT
SHORT CIRCUIT POWER DISSIPATION
INTERNAL POWER
LOW LEAKAGE POWER CIRCUIT TECHNIQUES
3.8.1
Leakage Control by Body Biasing
3.8.2
Leakage Control by MTCMOS Technique
3.8.3
Leakage Control by MVCMOS Technique
MOS CURRENT MODE LOGIC

Page No.
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1-14
1
5
14
14
15-21
15
17
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22
23
25
27
27
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29
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29
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4.1
4.2
4.3
4.4
4.5

4.7
CHAPTER 5.
5.1
5.2
5.3

OUTLINE
MCML BASIC OPERATION
MCML ADVANTAGES
MCML DISADVANTAGES
MOSFET MODELS
4.5.1 Threshold Voltage
4.5.2 DC Power Supply
PERFORMANCE PARAMETER
4.6.1 Power Supply Switching Noise
4.6.2 Voltage Swing Ratio
4.6.3 PMOS Load Transistor Sizes (WRFP, LRFP)
4.6.4 NMOS Load Transistor Sizes (WRFN, LRFN)
DYNAMIC MCML
SIMULATION RESULTS
TOOL USED
INPUT PARAMETERS
RESULTS

33
34
35
36
37
37
37
38
38
38
39
39
39
42-60
42
42
43

CHAPTER 6.

CONCLUSION & FUTURE WORK

61-62

CONCLUSION
FUTURE WORK
REFERENCES
APPENDICES
LIST OF PUBLICATION
CARRICULAM VITAE

61
62
63-65
66-90
91
92

4.6

6.1
6.2

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LIST OF TABLES
Page No.
2

Table 1.1

Truth table for the 1 bit full adder

Table 5.1

Input parameters for the design

42

Table 5.2
Table 5.3
Table 5.4

Comparison of various full adder designs at 5 V

Comparison of various full adder designs at 1 V
Comparison of delay of sum bits of ripple carry adder
designs (for 5 V)
Comparison of delay of sum bits of ripple carry adder
designs (for 1V)

51
52
59

Table 5.5

vii

60

LIST OF FIGURES
Fig No.
Fig 1.1
Fig 1.2
Fig 2.1
Fig 2.2
Fig 3.1
Fig 3.2
Fig 3.3
Fig 3.4
Fig 4.1
Fig 4.2
Fig 5.1
Fig 5.2
Fig 5.3
Fig 5.4
Fig 5.5
Fig 5.6
Fig 5.7
Fig 5.8
Fig 5.9
Fig 5.10
Fig.5.11
Fig.5.12
Fig.5.13
Fig.5.14
Fig.5.15
Fig.5.16

Generalized block diagram of full adder

Schematic Design of Generalized Full Adder
An example of ripple carry addition
4-bit Ripple Carry Adder
Static Power Consumption for The Inverter
Leakage current in the logic gate
Generalized schematic of MTCMOS technique
MVCMOS Technique
Basic MCML operation
Dynamic CML style
Schematic of the Mirror CMOS Full Adder
Input Voltage Waveform for Mirror CMOS Full Adder
Output Voltage Waveform for Mirror CMOS Full Adder
Schematic of the Proposed Full Adder
Input Voltage Waveform for proposed Full Adder for 5V
Output Voltage Waveform for proposed Full Adder for 5 V
Input Voltage Waveform for proposed Full Adder for 1V
Output Voltage Waveform for proposed Full Adder for 1V
Circuit Testing Arrangement of Full Adder
Generalized setup for 4-bit RCA Adder
Waveform for the Mirror CMOS RCA Circuit for S0, S1, S2 Bits
Waveform for the Mirror CMOS RCA Circuit for S3, Cout Bits for
5V
Waveform for the Proposed CMOS RCA Circuit for S0, S1, S2 Bits
for 5V
Waveform for the Proposed CMOS RCA Circuit for S3, Cout Bits
for 1V
Waveform for the Proposed CMOS RCA Circuit for S0, S1, S2 Bits
for 1V
Waveform for the Proposed CMOS RCA Circuit for S3, Cout Bits
for 1V

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LIST OF ABBRIVIATIONS
CLRCL
CPL
DCVSL
DDCVSL
EDP
GDI
HS-Domino
LSCML
MCML
MOSCAP
NTC
PDP

Complementary and Level Restoring Carry Logic

Complimentary Pass Transistor Logic
Differential Current Voltage Source Logic
Dynamic Differential Current Voltage Source Logic
Energy Delay Product
Gate Diffusion Input
High Speed Domino
Low Swing Current Mode Logic
MOS Current Mode Logic
Metal Oxide Semiconductor Capacitor
Near Threshold Circuit
Power Delay Product

PG
SERF
SRMCML

Power Gating
Sense Energy Recovery Full Adder
Single-Rail MOS Current Mode Logic

SRPL-BBL

Swing Restored Pass Transistor Logic and Branch Based

Logic
Silicon on Insulator
Ultra Low Power Diode

SOI
ULPD

ix

CHAPTER 1
INTRODUCTION

1.1 INTRODUCTION

Addition is the most frequently and extensively used operation in the

arithmetic procession for any number of digitalized signal processing units and
microprocessors and embedded systems and other such systems. It often works as a
speed limiting element for the larger and complicated blocks where the pace of the
operation serves as a constraint. The full adders are an arithmetic unit which adds three
1-bits at a time and gives unit-bit result and generates the result as sum and carry output.
These low power designs affect the performance in requisites of speed of operation,
time taken in completing the operation and also the complete power delay product
(PDP) of the logical circuit structure [1].

A
B

SUM
FULL ADDER
CARRY

Fig 1.1: Generalized block diagram of full adder

Here, Fig 1.1 shows the generalized block diagram of the 1-bit full adder.
Here A, B, C is the inputs of the block called full adder in the left hand side and SUM
and CARRY are the output produced out of the block in the right hand side. Generally a
block is given in the figure is designed and implemented in number of ways and
according to the application and requirement of operation speed.
1

Table 1.1 Truth table for the 1 bit full adder

A

Sum

Carry

Table 1.1 above shows the truth table for the 1-bit full adder operation. Here
we can see that by adding three 1-bits at a time, we get the result in terms of sum and
carry at 000, the sum and carry output shows 0 and at 111, the sum and carry shows
1 output.

For various logic units and multiplier designs, it is regarded as a prime

element for the arithmetic operations for various logic units and multiplier designs. In
todays time, there is a requirement of the circuit design that can work with low power.
These circuits consume less power and generate the desired result with the less power
dissipation. These low power designs affect the performance in terms of speed of
operation, time taken in completing the operation and also the complete power delay
product (PDP) of the circuit. Low power designs are beneficial in terms of delay, speed
and power delay product, as the power consumption is low. These are needed for
speeding up the arithmetic logic units (ALU) and other like applications. It oftenly
works as a speed limiting element for the large blocks or the complicated blocks where
the speed of the operation serves as a constraint. Todays power management process of
advanced CMOS technology process drives the need to consider the satisfactory scale
driven fundamental material limitations with almost same applications and other

products and designs for the evaluation requirements in the low power VLSI design
industry [2].

Suitable power design approach of VLSI circuits has always been

considered as a careful identification of a critical technological need of present day and
also the advanced years from now on. During the last few years, the demand of portable
electronics products has been increased up to the sky heights and increasing day by day
for its low power benefit by the consumers. So, the need of designing such products has
also increased. And in regarding to this factor, many innovative designs has been
produced and is producing for fundamental logic designs using the approaches such as
pass transistors and transmission gates. They are discussed and approached in the
literature recently and is using now and then [3].

For all the portable information systems and other system applications,
power dissipation is a constricting factor and a top priority issue of discussion for VLSI
circuit design. Power dissipation vastly affects the weight, size of the system, effective
cost of design and the battery life as the portable systems rum over a battery so the
weight, size and cost should be such as which can be bearded. To have such a cost
effective design, the VLSI engineer faces a lot of challenge to find and apply the circuit
techniques effectively in order to corporate the primary requirements for the easy
carrying devices. The circuit designing method should be chosen that can balance the
need for performance critical unit with those of power dissipation.

.
Due to the less power consumption factor, ultra low power circuit designs
become the appropriate candidates for portable units. With the intention of realizing
these circuit designs, various techniques already have been introduced and invented that
provides all the required features. The technique should be selected very carefully as the
portable devices are more power sensitive. Therefore, for designing and drawing any
complex structure or system, its fundamental building block should be fast enough to
generate their results in the mean time. These features affect the overall performance
and output of the proposed design and following the large complex design [4].

The very low power design of any circuit consumes less energy which
means we can input a very low voltage suggestively less then 1V these days, but at the
cost of increment in the leakage currents such as dynamic current, sub-threshold leakage
current, gate induced bulk leakage current and drain induced bulk leakage current etc.
Due to the low input voltage, power dissipation can also be increased. Various designing
methods to reduce the standby leakage currents of the chip have become a boon for the
VLSI designers. It enables the designer to reduce the leakage current, heat generation

and power dissipation. These techniques also enable the continued transistor scaling by
relaxing the gate and sub threshold leakage current and planer device structural
limitations.

The working design of any circuit relies upon the various factors and could
be designed using various aspects. They are implemented at various levels such as,
architectural level, logic level, transistor level and switching level. Each and every level
of design has own advantages and their own challenges too [5].

Fig 1.2: Schematic Design of Generalized Full Adder

Fig 1.2 illustrates the schematic of the full adder structure one of the
simplest kind. This transistor level full adder device has been realized using 28 MOS
transistors. The above full adder realization has been altered to have the more improved
design as per the needs and features. These alterations and modifications are based upon
transistor size, speed, time to process the operation, technology used, W/L ratio, power
supply reduction, delay reduction, leakage current magnitude, area requirement and
different categories of power dissipation, scaling of transistor [6].

During the designing of an adder we have to compose two choices in regard

to different design abstraction levels. One is responsible for the adders architecture
implemented with the one-bit full adder as a building block. The other choice defines
the unambiguous design style at transistor level to execute the one-bit full adder [7].

While deciding on the circuit technique for designing, one has to make sure
of the number of transistor used in the proposed designing. In this thesis project, a new
design is built by reducing the transistor count from the original design of the referred
paper. In the referred paper, the design consists of 36 transistors. So, in order to increase
the efficiency, we reduced the transistor count in between 20-25 transistors. The new
design, proposed here will be based upon the MOS Current Mode Logic (MCML) style
which is a power efficient concept. In the design approach, a current source will be used
as the power supply option rather than a voltage source and the current mirrors for each
and every stage that will be connected to each other in successive procession further, so
that delay and power can be further reduced. Based upon the given power supply using
the current source in any digital circuit helps in reducing the power dissipate, delay and
power delay product. It helps in reducing the noise level and stabilizes the voltage
swing. With the static CMOS the only real parameter that could be changed is the size
of the design has advantages, it also has few drawbacks that will have to overcome such
as, the supply current of a CML gate is independent of the working frequency; there will
be stationary power dissipation that generates during the condition when both of the
transistors are in ON state. But at the upper operating frequencies, less energy is
dispersed away that the static CMOS design approach. This condition however leads to
a reduction in power delivery and current. Scaling down the following parameters will
lead to a far worse problem of leakage current, which damages the circuit [23].
1.2 LITERATURE REVIEW

With the aim of understanding, the designing and approaches of full adder,
we have to study and elaborate the various methods to design the new one. By review
the various papers and thesis and other work by the author, we can understand the
problem of power, delay and power delay product (PDP). Under this subdivision, we
will have the literature (prose) review of different papers.

R. Zimmermann et.al, 1997 [1] compared between CPL and CMOS logic
style to show their advantages. The comparison had been drawn in between these two of
the logic styles with respect to speed efficiency, area utilization, power dissipated and
power delay product. Different full adder circuit designs, based on these two logic styles
were compared and elaborated. CMOS style had shown the robustness with respect to
voltage scaling, ease of use, switching capacitance reduction, supply voltage reduction,
5

switching activity reduction, short circuit current reduction. Here, the CPL logic style
worked 20% faster than the CMOS logic style, as the former drew low power while
operating the full adder circuit designs. The comparison had been carried out on
HSPICE, 3.3V & 1.5V, 20 MHz.

H. Lee et.al, 1997 [2] had realized a full adder by combining XOR gates and
Double Pass Transistor Logic. The objective to design such type of full adder was to
achieve the features such as low power dissipation, low supply voltage, and full voltage
swing. This 18 Transistors design which eliminated the problem of threshold voltage
drop and higher rate of power consumption, also reduced the problem of static short
circuit current. To eliminate this problem another high performance 23-T full adder that
uses a level restoration technique was proposed. The simulation was carried out on
HSPICE 0.4 m CMOS process at Vdd=2V.
Ahmed M. Shams et.al, 2000 [3] proposed a 16-T full adder using 4-T XOR
& XNOR gates using pass transistor logic. It has offered high speed & lower power
consumption, reduction in transistor count and delay capacitances. The previous 14-T
full adder had shown the glitch problem due to which inverter connected to it, so in new
design XNOR circuit was connected to eliminate the problem. The new design balanced
the delay of generating intermediate stages which led glitches. It eliminated the short
circuit power component.

D. Radhakrishnan et.al, 2001 [4] realized a new 14 transistors 1-bit full

adder cell that could be operated on low voltage power supply. A new combined XOR
and XNOR circuit was constructed using 6 transistors that generate the output
simultaneously. This XOR and XNOR circuit was fully compensated for threshold
voltage drop. This XOR-XNOR would work properly if its supply voltage was scaled
down and not to allow to fall below 2Vtp. This circuit had been provided the full voltage
swing and non-zero static current components. The new 14T full adder had few
following advantages. For this design, the width to length ratio was very important, as
they would ensure the role of driving capability of the transistors. To serve the purpose,
several simulations were run and evaluated to fix width to length ratio. For NMOS, W/L
ratio was 0.8 m/0.35 m and for PMOS, 3.5 m/0.35 m, except for the feedback
NMOS and PMOS. They were set to 0.5 m/0.35 m and 1.8 m/0.35 m, respectively.

A. T. Schwarzbacher et.al, 2002 [5] had compared seven types of adder

structures. As every adder structures was designed at different level and had different
implementation techniques and technologies. All structures were implemented using the
VHDL hardware description language. Designs were synthesized and carried out into

ES2 ECDP 0.7 m CMOS technology using Synopsys Design Controller. The
parameters that evaluated were area requirement, active capacitance, operating
frequency. The area requirement for Carry Look Adder was growing faster with respect
to its bit size. Active capacitance was directly proportional to power dissipated and
depended upon physical node capacitance and switching activity. For being the first
fastest operational adder, maximum operating frequency was required by CCA-2.

Hung Tien Bui, et.al, 2002 [6] proposed an approach and method of
designing a large sum of 41 new full adder cells consisted of 10 transistors for each.
These full adder cells were built using the new kind of XOR and XNOR gates,
consisting of 4 transistors for each module. The authors of the following paper had run
the exhaustive simulation for all the 41 full adder cells for different input patterns,
different operating frequencies and load capacitances. This paper had the drawback of
threshold voltage loss due to the consumption of less power supply. Here each input
pattern was simulated using the operating frequencies ranging from 50 KHz to 200 MHz
and with that load capacitance of 0.3 pF, 0.5 pF and 0.02 pF was taken. The transistors
were scaled with length of 0.6 m and a width of 2.4 m, having a power supply of
3.3V. The netlist of the adder was extracted and simulated using HSPICE over an Ultra
SPARC 2 machine.

Massimo Alioto et.al, 2002 [7] analyzed and compared the different type of
topologies of one-bit full adders. These full adders would be elaborated on the basis of
power, delay and the power delay product (PDP). The comparison had been executed
with two classes of circuits, the former one was achieved by using the minimum size
transistor to minimize the power consumption, and the latter one was carried out with
the optimized dimensions of transistors in order to reduce the power delay product.
They were not only simulated for its schematic but to evaluate the area requirement, its
layout was also designed. The simulations were carried out using the specific Cadence
environment with 0.35 m process, Vdd = 3.3V, and W/L=1 m/0.3 m.

Yingtao Jiang et.al, 2004 [8] had realized low power multiplexer based 12T
full adder called as MBA-12T. For building the following adder, six indistinguishable
multiplexers circuits were used, each multiplexer circuit is realized using two
transistors. This new full adder was designed with the objective of maximum speed,
attenuation in short current power consumption. The full adder was compared with
conventional CMOS transistor and four other low power full adder designs. Simulation
had been run at different frequencies ranging from 10 MHz to 200 MHz and
capacitances ranging from 500 fF to 0.97 fF. The MBA 12-T consumed less power than
the conventional one and saves 23% more power over 10-T transistors and also 64%
faster than them. The simulation was carried out using HSPICE with TSMC 0.35 m
CMOS technology process with V=3.3V.
7

C. H. Chang et.al, 2005 [9] had presented the hybrid low adder design that
can be operated at lower power supplies, had less area requirements and time to perform
the operation. It could easily be used for pre dictate the tree structured arithmetic
circuits. The new XOR and XNOR circuit was formed to reduce the problem of
switching delay problem. The hybrid full adder segregates in 3 modules. The first
module was made of 6-T XOR-XNOR gates, using a level restoration technique. The
middle part was responsible of generating the sum part and the last part generated the
carry part, each consisted of 6 and 10 transistors. The simulation was carried out using
HSPICE TSMC 0.18 m CMOS technology process with the supply voltage ranging
from (0.8V to 2.4V).

S. Goel et.al, 2006 [10] has designed a 1-bit full adder hybrid CMOS design
using a hybrid logic style. The objective of such design was to attain a good driving
capability, noise robustness and low energy operations for deep sub micrometer region.
It was built using XOR and XNOR structure that generated full swing output
simultaneously and registered the improvement of 5% to 37% in terms of PDP. The
output stage had shown good driving capability in cascading structure and showed 40%
reduction. The 4 bits and 8 bits carry save adders were also built, using the same design
and evaluated for its area requirements. The simulation was carried out using 0.18 m
TSMC HSPICE, MAGIC layout editor 7.1, Fr = 50 Hz, Vdd=1.8V.
D. Levacq et.al, 2007 [11] proposed a 7-T SRAM storage cell based on the
permutation of two reverse biased CMOS based diodes. This new storage cell showed
ultra low leakage current and a negative impedance characteristic in reverse bias mode.
The diodes that were used here, called as ultra low power diodes (ULPD) in the SOI
(Silicon on Insulator) technology. In the forward biasing, ULPD worked as the
conventional standard diode. In the reverse biasing, ULPD showed the low leakage
current process. This new cell was used to form a 2561 bit SRAM column to show the
ultra low leakage current. The simulation was carried out using ELDO simulator 0.13
m SOI technology using ST BSIM3SOI models.

Jin Fa Lin et.al, 2007 [12] has proposed a 10-T 1-bit full adder design
called as CLRCL (Complementary and Level Restoring Carry Logic). This design was
energy efficient uses less transistor count and gave high performance and consumed less
power The design was constructed using 2-XNOR gates (consists of 2- 2:1MUX and 2INV) and a MUX. The XOR gate constructed here was inverter buffered design which
was used to eliminate the problem of threshold voltage drop of pass transistor. The
simulation was accomplished by HSPICE platform based on TSMC 2P4M 0.35 m
process models. It ensured that the suggestive design has lowest acting Vdd and highest

working operating frequency. And as the word length kept increasing, the efficiency of
adder had also been increased.

Flavio Carbognani et.al, 2008 [13] presented a Wallace tree multiplier

architecture by combining TG (Transmission Gate) and CMOS called as TG-MULT.
It has shown better leakage reduction, process variation & voltage scaling. It has
suppressed the glitches via R-C low pass filtering, while preserving unaltered driving
capabilities. As it showed less glitch, took less power and occupied less area. The
proposed design illustrated 30% more power saving in comparison to other two
multiplier designs. The simulation process was carried out on Spectre by Cadence in
0.18 m CMOS technology at Vdd=0.75V.

Walid Ibrahim et.al, 2008 [14] analyzed the three different full adder design,
approaches the different majority gate methods. The reliability of these three different
majority gates design, was compared with the standard XOR-based full adder. The
simulation was carried using PTM modules and monte-carlo simulation for minority
functions.

Farshad Moradi et.al, 2008 [15] proposed a new full adder (FA) circuit
synthesized and minimized for the ultra low power operation. The circuit was designed
using modified XOR-XNOR circuit which required total of 16 transistors for the
operation. As the count of transistors were increased so the area requirement also
increased in the same amount, the simulations were achieved by using 65 nm bulk
CMOS process for the voltage ranging from 0.1V to 0.25V and the operating
frequencies were ranging from 1 KHz to 20 MHz.

Mi Chang Chang et.al, 2008 [16] evaluated the matters associated with
transistor scaling or resizing of dimensions and co-optimization for power management
circuit-design methods for active and leakage power control modes. Circuit techniques
to contain system standby leakage and active power have become the fundamental
enabler of continued CMOS transistor scaling by conciliating scaling driven
fundamental material limitations with product and application evolution requirements.

Farshad Moradi et.al, 2009 [17] designed low power full adder topologies
based on SERF (sense energy recovery full adder) and GDI (gate diffusion input)
technique. SERF had the advantage of using less number of transistor count. The GDI
based full adder worked better then the SERF based adders but with some limitations.
For operating voltage 0.5V, the SERF full adder showed the satisfactory output results.

The simulation was carried out using 65 nm technology, operating frequencies varies
from 100 KHz to 10 MHz.

Yi WEI et.al, 2011 [18] proposed an 8-T 1-bit full adder cell, which
combined three MUX and an inverter. The objective was to reduce the transistor count
and power consumption. This full adder design had realized the boolean expression.
Here the inverter had shown few advantages such as it sped up the carry propagation as
a buffer along the carry chain, provides complementary signals needed for the
generation of sum. The inverter has improved the output voltage swing as a level
restorer circuit. For the simulation process, various frequency ranges from 100 MHz to
500 MHz were taken and load capacitance of 100 fF was taken. Simulation was done
using TSMC 180 nm HSPICE, at Vdd=1.8V.

V. V. Shubin et.al, 2011 [19] proposed a new mirror CMOS circuit

implementation. It demonstrated zero static power consumption and less voltage
variations at internal nodes which mean no voltage recovery was required. This
proposed adder provided the better speed operation at the carry part. It provided a
suitable transition for building multi bit adders. It also reduced the maximum delay
through n-bit RCA. This full adder design worked better for the RCA, where the bits n
was more than 3. The creation of delay for each and every logic gate fluctuated with its
own output parasitic capacitances and total channel resistance between each output node
and the power or ground line in pull up/pull down network. The simulation was carried
out with PSPICE software from ORCAD 9.2 (Cadence Design System) on 3rd level
model, 3 m CMOS process, Vdd=5V.
Sohan Purohit et.al, 2012 [20] suggested the 3 new 1-bit full adder designs
and analyzed their design and characterization. These all full adders were synthesized
and evaluated by IBM 90 nm process technology. These adder circuits were examined
with the power supply of 1.2V and operating frequency of 1 GHz. Using these full
adders, 32-bit ripple carry adder and 84 multiplier were also built to observe the effect
of sum and carry propagation bit delays on the overall functionality consumed power.
The Monte Carlo analysis was repeated with varied supply voltages ranging from 1.2V
down to 0.9V to estimate changeability under scaled voltage operating conditions.

D. V. Morozov et.al, 2013 [21] proposed a single bit CMOS full adder cell
to increase the performance and reliability of the circuit. This proposed design had been
consisted of total of 24 transistors. The proposed circuit for better evaluation is
considered. Here, first 12 transistors consisted of 6 PMOS and 6 NMOS used for
generating the carry part stage. The formation circuit of the sum signal was to be
implemented based on transistors T13T24. The simulation was carried on Virtuoso
10

IC5.1.41 platform by Cadence Design Systems 0.18 m CMOS technology, with the
power supply of 1.8V.

Hamid Reza Naghizadeh et.al, 2013 [22] proposed two 1-bit full adder cells
using hybrid design techniques. The first full adder was designed by adjoining the
Swing Restored Pass-transistor Logic and Branch-Based Logic, called as SRPLBBL cell and the second full adder had been realized by merging the Gate Diffusion
Input technique and Majority function which was also called as GDI-Majority cell.
Simulation results were executed by HSPICE in TSMC 0.13 m CMOS process with
the power supply of 1.2V and operating frequency of 12.5 MHz, at the room
temperature of 25C.

Yavuz Delican et.al, 2011 [23] presented a high performance 8x8 bit
multiplexer based multiplier using MOS Current Mode Logic (MCML). In this paper,
logic gates based on MCML method was designed, which consisted of 2:1 MUX,
NAND/AND logics and full adder were planned and optimized further for evaluation of
low power and high speed operation and then examined for two different supply
currents. An 8-bit multiplier had been formed using the library which was tested further
with two different current magnitudes. Here the transistor sizes of NMOS and PMOS
should be chosen such as that the dc gain was of the magnitude of 2. This MCML full
adder consisted of 24 transistors and sum of 76 full adders were used in the 8-bit
multiplier design. The simulation had been run on HSPICE, with UMC 0.18 m CMOS
process technology and the power supply ranging from 1V to 8V.

Subodh Wairya et.al, 2011 [24] proposed a high speed 1-bit full adder
circuit based on hybrid mode logic family. The goal of this was to design a 1-bit adder
circuit using the current mode logic. Here, in this paper, the authors had also evaluated a
high speed hybrid majority based full adder, which used MOS capacitors (MOSCAP) in
its design. Dynamic CMOS approach had more advantages than the static in terms of
delay, area required and testability of the circuit. The design was simulated and run by
Virtuoso Schematic Composer on UMC 0.18 m bulk CMOS process models at 1.8V.
Simulation had been run on Spectre S.

Hong Li et.al, 2012 [25] proposed a single rail model of MCML circuits.
The design approach of the fundamental single rail MOS Current Mode Logic
(SRMCML) circuits was exhibited. All circuits were simulated with HSPICE model
with the SMIC 130 nm CMOS process model technology. The power dissipations of the
vital SRMCML cells were compared with the conventional dual rail MCML circuit
designs. The power dissipation of the proposed SDMCML circuits was nearly the same

11

as the conventional dual rail logic design. The operating frequency of this experiment
varied from 100 MHz to 1 GHz.

Yangbo Wu et.al, 2013 [26] proposed a 1-bit full adder based on the power
gating technique in order to decrease the standby power of the near threshold region
MCML. In near threshold MCML designs, the transistor pulled down the bias voltage of
the current source to zero reduce the static power. The drawback of MCML circuit was
its standby power. A 10 bit counter was also formed using the MCML technique and
both showed the standby power of 1 nW and 3 nW. The simulation was run on HSPICE
with 45 nm CMOS process technology using the NCSU PTM models with the supply
voltage of 0.7V and bias current of 10 A.

Zhenguo Vincent Chia et.al, 2013 [27] designed a high speed analog to
digital converter based upon the CMOS current mode logic (MCML). The MCML
circuit did not need a voltage swing from rail to rail lines as for the typical CMOS was
required against its CMOS version. The MCML showed the benefit of propagation
delay from one stage to another stage. The CML circuits were frequency independent.
For achieving high resolution, a high speed coder-decoder was also used in forming an
analog to digital converter. Here the simulation results were observed and showed that
MCML could operate within the voltage range of 1.08V to 1.3V with the working
temperature varies from -40C to +120C.

Alexander Shapiro et.al, 2014 [28] presented a work on the basis of the
combination of the NTC (Near Threshold Circuit) technology with MOS current mode
logic (MCML), here a circuit was formed by adjoining MCML with NTC. Due to this
implementation constant power consumption of MCML was reduced to some level,
which can tolerate the leakage power levels in some of the applications. The simulation
was carried out with 14 nm FinFET process. With this full adder, a 32-bit Kogge Stone
full adder was chosen to form the feasibility analysis. The following circuit also showed
the lower noise levels compared to typical CMOS. This circuit combination provided a
balanced circuit methodology. The outcome of the above analysis and design showed
that coupling of near threshold circuit and MCML was efficient for higher operating
frequencies and activity factors.

Osman Bakri Musa Abdulkarim et.al, 2006 [29] presented a simple analysis
of propagation delay models based upon the MCML circuits. This thesis work showed
the mathematical analysis for MCML based circuit library for their delay model. It had
also evaluated the condition for the circuit to work in DC and AC operational modes.
The expressions were developed for the delay models and verified using various
parameters. A 4-bit ripple carry adder and an 8-bit decoder were also designed which
12

was optimized using the less complex MCML circuit. The proposed model here reduced
the complexity of the MCML delay model effectively.

Ilham Hassoune et.al, 2006 [30] analyzed a novel category of active

differential logic family. It featured a low output voltage swing and self timing
operation. Even the discrepancy and active nature of low swing current mode logic
(LSCML) style brought the benefits in reduction of power consumption deviation,
which in return proves the LSCML logic style a potential implementation option against
the power analysis of other. This technique was the secure way of building the
encryption devices. Here a new hybrid full adder structure had performed which was
built using pass transistors. Also an 8-bit ripple carry adder was also implemented using
the hybrid adder and compared with the static version and shows the reduction and
better power delay product.

E. Pattanaik et.al, 2013 [31] proposed an 8-bit multiplier circuit, designed

using the MCML logic. Here multiplier architecture was drawn and analyzed with
respect to high speed applications, the 88 bit multiplier consisted of inverter, AND
gates, XOR gate, half adder and a full adder MCML circuits. This multiplier was then
simulated using Cadence design tool on Virtuoso platform, on 0.6 m standard CMOS
double metal double poly process. These circuits had been operated with the working
frequency of 1.31 GHz and had the power consumption values vary from 4.3 mW to
18.6 mW.

Mohamad W. Alam et.al, 2000 [32] showed the study of five categories of
logic family. These logic families were analyzed for their scalability feature and their
potential for creating the future technology more effective and reliable. The technology
scaling effected the performance of any circuit design based upon the power, speed and
power delay product. Here also a new logic family was created, called as High speed
Domino (HS-Domino) and combined the features of low power supply speed and noise
resistance of CML circuits with the design simplicity and lower standby current. The
new logic family showed the improvement in delay by 73% and in power by 7% against
the typical CMOS style. A typical 16-bit Carry Look Full Adder was also designed and
simulated and fabricated using 0.6 m CMOS technology.

Uma Sharma et.al, 2014 [33] showed the analysis of the various full adder
topologies. These topologies were discussed and tested by the authors. The following
paper shows the review of the given topologies. By reviewing the 4 topologies, the best
full adder was ULPFA which is simulated and fabricated using 0.13 m PD-SOI CMOS

13

technology with the power supply of 1.2V. It gave the drastic reduction the power
consumption and time to perform the operation and power delay product.

Trapti Mittal et.al, 2015 [34] showed the new full adder design based on
MCML method, which gives more reliable results than CMOS technology. The
proposed adder design is the compared with other design approaches also a 4-bit RCA is
also designed using the same full adder circuit. On comparing the results of sum part, it
is concluded that MCML based design shows more efficient results. The simulation is
carried out using Tanner EDA Tool V 14.0.

1.3 OBJECTIVE

The full adder design is crucial for the complex and large operations as it
serves as a basic building block. After having review the literature of several journals,
thesis and books, for setting the parameter and drawing technique, three main
parameters are decided to achieve through this review that shows the affect on the
performance of the digital design, is power, speed and power delay product (PDP).
Here, in this thesis, for creating a full adder, MOS Current Mode Logic (MCML)
technique will be used [8, 9]. The objectives that are need to be achieved:

(a) To design a 1-bit full adder.

(b) To improve the power consumption of the overall circuit.
(c) To reduce the delay of the circuit.
(d) To reduce the PDP.
(e) To implement the proposed full adder in the application such as Ripple
Carry Adder (RCA).

1.4 REPORT ORGANIZATION

In chapter 1, literature survey of various papers and research work has been
reviewed and objectives are identified. In chapter 2, adder structures are defined, where,
ripple carry adder is discussed. The discussion starts from its background to its working.
The chapter 3 explains the power techniques and different type of power induced in the
design. The chapter 4 gives the review of the technique used, MOS Current Mode Logic
(MCML). While chapter 5 shows all the results that are extracted from simulations on
various full adder design. And last but not the least chapter 6, discusses the conclusion
and future work.

14

CHAPTER 2
DESIGN OF ADDER STRUCTURE

2.1 BACKGROUND

For evaluating any digital circuit and to know about the circuit proficiency,
three factors are very important such as power, delay and power delay product (PDP).
These factors show the proper working evaluation for any digital circuit and helps in
deciding the usefulness. The other deciding factors are transistor count, technique used
for designing the circuit, logical expression, gain and robustness [11].

The objective of achieving efficiently powered full adder can be acquired by

lowering the supply voltage. Since, we not only desire a low power feature but also the
high speed recognition as property, so we work on higher operating frequencies. To
carry out the work on higher frequencies, not only low power property but high speed is
also desirable. It helps in achieving the efficient speed operation which helps in speedy
and timely delivery of the results. So the lesser delay will also be achieved. This in turn
helps in retrieving a power delay product, shows the efficiency of any electronic circuit.

For designing a proposed full adder, the studies of the previous full adder
designs are needed to be understood and find out about their advantages and
disadvantages. Since the full adder is developed, various kind of full adder design has
come in light. There are number of authors exists that worked on several design and is
working on them continuously. This is a topic of vast discussion, as there are so many
experiments have taken place already [10].

The full adders are designed in terms of power, speed, power speed product
and number of transistors used. In order to achieve this goal, transistor size can be
scaled down. The channel length and width should be selected in such a way that helps
in reducing the leakage current, dynamic current and gate leakage current. The selection
of transistor size affects the channel density, power density, and process variation. The

15

transistor sizing can be done to the boundary limit after which the leakage current and
drastic changes in the circuit behavior can occur.

CMOS VLSI technology has recognized as the major breakthrough in

technology in the VLSI industry. Almost of all the circuit and devices are built and
designed using the CMOS design style. The VLSI designers have invented so many
categories and types of logic styles, all using the CMOS technology. The logic style
such as pass transistor logic family, dynamic logic family, and current mode logic based
family clan etc. The bulk CMOS technology has the various advantage of working at
very low power inputs and higher speed operations and shows the greater reduction in
energy speed product, but it also has few non desiring disadvantages such as these
CMOS logic styles do not work properly for the low operating frequencies. Due to the
strict and constant demands of higher speed operation for portable devices and other
application has pushed the working in deep sub micron region, where low supply
voltage can be utilized. As the supplied is getting lesser, the risk of introduction of
leakage current is also increased

In the present time, design with handful of transistors and power supply
lesser than the 1V makes it more and more difficult to keep the full voltage swing in
limits and even updated. Complementary and level restoring carry logic (CLRCL) full
adder is designed to reduce the complexity of the circuit and the cascading operation.
This adder shows a speedy operation at the carry part, which serves better for the n-bit
operations. Level restoring is needed in order to avoid the multiple threshold loss
problems [13].

As the full adder happens to be a basic building block, it can be used in

building the complex and large circuits and systems applications, through which a
multiplier or an n-bit adder can be constructed. In the base paper, a 4-bit RCA is
constructed. This full adder works best for the 4-bit or large adders. With the use of
same full adder, other high operation adders can also be constructed as in application.

MCML architectures provide higher invulnerability to supply noise due to

their differential structure, lower cross talk due to the reduced output voltage swing and
lower noise generated due to the constant current flowing through the supply rails. The
constant current used in MCML is the reason for constant power consumption, which is
independent of the frequency of operation or gate activity. MCML is the best alternative
when the frequency is the issue in the circuit designing. The power consumption is
independent from the frequency because the two branches are driven symmetrically and
in opposition of phase.

16

It is seen that the sum and carry delays for a one bit adder cell differ from
each other, making it difficult to draw conclusions regarding the performance of the
resultant n bit adder, all the more so since it depends on n as well. In fact, our
simulations of four bit adders made up of each version of a one bit adder cell revealed
that the proposed implementation should provide faster n bit adders for n = 4, not to
mention the larger capacities, as compared with the transmission gate implementation.

A full adder is a digital circuit that performs addition of numbers which

gives the sum and carry as an output. The objective of this design is to create a high
speed multi bit adders. This full adder designs concerned more on the carry part of the
circuit then the sum part, in order to make the transition faster. It deals with the n-bit
ripple carry adders. The results are simulated using Cadence ORCAD 9.2 tool with the
operating frequency of 50 MHz.

With above considerations in mind, a feasible way can be found to reduce

the capacitive load involved in passing a carry from input to output, at the cost of
increased transistor count involved in sum generation. This solution should enable the
designer to construct n-bit ripple carry full adders that would be superior in speed to the
alternative implementations if n > 3, as supported by computer simulations [12].

2.2 ADDER DESIGN

In this proposed work, along with the designing of full adder, a ripple carry
adder is also designed using the same one and compared with the other realizations.
Ripple carry adder is the most basic and easy adder design to implement and to carry out
on the mathematical level. In another way, there are many large adders used in practice
such as carry select adder (CSA). Conditional carry adder (CCA), carry look-ahead
adder (CLA), carry skip adder (CSA) and there are many other adder that are used to
add n-bit full adder rail.

However, Ripple carry adders are slow in functioning i.e., takes

comparatively more time in propagating the carry output from one stage to the next
stage. It takes typically more area as D (n) and delay of D (n). While the carry select
adder and carry skip adder has same area of D (n) but shows the delay of D (n(l+2/l+l) and
calculates the output faster. Carry look-ahead adder occupies the area of D (nlog(n))
and delay is D(log n), but it has suffered from the problem of irregular layout problem,
due to this it does not prove to be good adder at the physical implementation level. As
there is no restriction on the number of fan in/fan out condition, but the implementation
has to be done using only two gate level stages. On the other hand, carry select adders
17

(CSA) reduces the total output calculation time by calculating the sum of all possible
carry bits 0 and 1. When the carry is decided then according to the carry values, sum
of the bits is computed using the multiplexer.

Presently carry select adders are the fastest adders available, but they face
the restriction of numbers of fan outs can be accommodated since the required quantity
of multiplexers is also increased exponentially. For a worst case scenario, a carry signals
can select total of n/2 multiplexers for the particular n-bit adder. When three or more of
the bits are to be added simultaneously using two operand bit adders than the carry
propagation will be repeated many times, which is really time consuming [14].

2.3 RIPPLE CARRY ADDER

Ripple carry adder is the basest and simplest design among the family of the
long chain adder. The following adder can be designed by cascading the n number of
full adder cells. For generating a carry for the next stage, one bit adder generates the
sum along with the ripple result for next stage. Here the result of one stage, i.e.
carry_out is fed to the next stage carry_in. However, being the simplest one, the ripple
carry adder could not be used for the long chain of adder as it will not be sufficient. The
main drawback has shown by the following adder that its delay increases as the adder
chain extends. Ripple carry adder shows the case of worst delay scenario when carry
line goes through all the participated stages of adder block rail from least significant bit
right to the most significant bit [15].
t= n1 t +t

(2.1)

Where t is the total time taken by the ripple carry adder, t be the delay to calculate the
sum of last stage and t is the delay through the carry stage. The benefits of ripple carry
adder are its simple design, lower power consumption and take less area on the layout.
The time to perform operation in ripple carry adder is linearly proportional to n, the
total number of bits used. Hence, the performance of ripple carry adder is bordered
when number of bits n, nurtures larger.

In the ripple carry adder, one get the sum output of the most significant bit,
while generating the carry by the previous stage. Here the result would be known, after
the carry generated from the previous stage. This is why; the sum of most significant is
generated after the carry wave signal is flow through the adder to the most significant bit

18

from the least significant bit. As a consequence, the final result of sum and carry are
generated with the sizeable delays.

2.3.1 Ripple Carry Addition

This is the simplest form of addition that used to perform in former

electronic computers. Adding the binary numbers is same as adding the decimal, only in
binary numbers there all only two digits, 0 and 1. Several numbers can be added at a
time by propagating the carry from one set of digits to another nearby. Ripple carry
addition are used in the application where the complexity is the constraint and time can
be adjusted [16].

An example can be taken for binary addition, two binary numbers such as
(100111)2 and (1011)2 for ripple carry adder.

Fig. 2.1: Example of ripple carry addition

As shown in Fig 2.1, example of ripple carry addition, the carry generated
by the first to bits in the right hand side, i.e. ith bit is propagated to the next stage of

19

(i+1)th bits as an operand for the addition operation. This process keeps repeated until all
the digits added and left the sum with carry. Here, the sum is acquired from the
sequence of least significant t0 to most significant bit t5, i.e. the output of the
example is 110010 with carry 0. The performance of the ripple carry adder can be
limited when number of bits n becomes larger and flow goes from least significant bit
(LSB) to most significant bit (MSB), while generating the carry from previous stage
[17].

The fundamental unit i.e. Arithmetic logic unit (ALU) in a digital computer
carries the addition by using full adder. The output expression for the sum (Si) and carry
(Ci+1) th at the ith bit can be established by equation (2.2) and equation (2.3).
S = A B C + A B C + A B C + A B C
C

= A B + B C + C A

Where
and
are the operands of the ith bit and
stage for the long chain addition.

Fig. 2.2: 4-bit Ripple Carry Adder

20

(2.2)
(2.3)

is the carry into the ith

The circuit implementation for the n-bit adder is shown in Fig 2.2. The
adder is constructed by cascading the n full adders in the long chain. Fig 2.1 describes
the addition pattern and the sums are acquired at the rail sequence of time from Si-2th bit
at t0 to Si+1th at t3. The time taken by adder chain to complete the operation of the given
design is equal to the (2n+1)tp.

21

CHAPTER 3
POWER REDUCTION TECHNIQUES

3.1 POWER

For any digitalized circuit, power can be characterized as the key element
for boosting the performance. Any changes in terms of power consumption make a
device more reliable and competent. The need for devices that consume a minimum
quantity of power is the most important driving force behind the expansion of CMOS
technologies. These devices are best known for their suitable power consumption
feature. However, by simply having the theoretical knowledge that CMOS technology
requires less power than the equivalent devices and logic families does not prove of
much use when it comes to the power obligations of a board or system. It is also very
important to know not only how to calculate total power consumption, but it is also
needed to understand how factors such as input voltage level, input rise time, fall time,
power-dissipation, input voltage swing, internal capacitances, and output loading affect
the power consumption of any device. The MCML technique also requires lesser power
supply and can work on high operating frequencies. The power consumed by devices is
divided into the different categories. This function statement addresses the different
nature of power consumption in a MCML logic circuit, and, finally, the purpose of
entire power consumption in a MCML appliance [18].

3.2 POWER CONSUMPTION COMPONENTS

Due to the requirement of working on suitable operating frequencies compel

a stringent limit on power consumption for all the digital circuits and in computer
systems as a whole. Consequently, the power expenditure of each and every device on
the board and system should be minimized. The consumption of power also leads to the
leakage current problem, which happens due to the power supplied to the device. The
power computations create the transistor sizing, power supply, current requirements,
sizing and criteria for device selection. Power calculations can also be used to determine
the maximum reliable operating frequencies [19].
22

Two components determine the power consumption in digital circuits:

(a) Static power consumption

(b) Dynamic power consumption

Digital devices show very low static power consumption due to which
leakage current forms and flows through the circuits and devices. Static power
consumption occurs when there is no power supply given to the circuit, but after that
current leak through it causing a device to run. This kind of power consumption happens
when all inputs are seized at some valid logic level and the circuit is not in charging
states. On the other hand, when the circuit is switched at higher frequencies, dynamic
power consumption is capable to contribute considerably to the overall power
consumption.

Dynamic power consumption can vary severely at a very higher rate. The
switching activity causes the charging and discharging of the capacitive load in the
circuits, causing a further increment in the given dynamic power consumption. The
functional report shows the power consumption in CMOS logic families, operating at 5
volts. These reports elaborate the new and existing methods according to the circuit for
estimating the dynamic and static power consumption. Additional information is also
required to present the help in clarifying the sources of power consumption of any
category, and presents the possible resolutions to diminish the power utilization in a
CMOS circuits and systems.

3.2.1 Static Power Consumption

The working of the static power gears become a matter of importance when
the devices are at rest. It means the device shows no activity and all are biased to a
particular state. The working of the static power gears become a matter of importance
when the devices are at rest. It means the device shows no activity and all are biased to a
particular state. Due to the occurrence of the static power dissipation, leakage current,
the static power dissipation includes sub threshold and reversed biased diode leakage
currents.

Due to the necessary but harmful (in a leakage power sense) down scaling of
threshold voltages, the sub threshold leakage has become more and more essential.
When threshold voltage is in weak inversion, the transistors have not been completely
off. The sub threshold current has strong dependence on threshold voltage [20].
23

The working of the static power gears become a matter of importance when
the devices are at rest. It means the device shows no activity and all are biased to a
particular state. Due to the occurrence of the static power dissipation, reversed biased
diode leakage current. The static power dissipation includes sub threshold and reversed
biased diode leakage currents the sub threshold leakage current flows through it. Due to
the necessary but harmful (in a leakage power sense) down-scaling of threshold
voltages, the sub threshold leakage is becoming more and more pronounced. Below the
threshold voltage, in weak inversion, the transistors are not completely off. The sub
threshold current has a strong dependence on the threshold voltage

Fig 3.1: Static Power Consumption for the inverter

In general, all of the low-voltage devices have a CMOS inverter circuit

design in their input and output stages and also used in test bench circuit. Therefore, for
a obvious understanding of static power consumption in inverter circuit, the CMOS
inverter modes is referred as shown in Fig 3.1. It is built with the connection of a pair of
PMOS and NMOS transistors.

24

As shown in Fig 3.1, if the input is at logic 0, the n-MOS device is OFF,
and the p-MOS device is ON (Case 1). The output voltage is VCC or logic 1. Similarly,
when the input is at logic 1, the associated NMOS device is biased ON and the PMOS
device is OFF. The output voltage is on GND terminal, or logic 0, it is to be noted
that one of the transistors is always in OFF stage when the gate is in either of these
logic states. Since no current are flowing into the gate terminal, and there is no dc
current conducting path from VCC to GND, the resultant steady-state (quiescent)
current is at zero stage, therefore, static power consumption is zero. There are three
main sources of static power dissipation, diode leakage current, sub threshold current
and bias current.

3.2.2 Dynamic Power Dissipation

Dynamic power dissipation is defined as the power consumed while all or

few of the inputs are active. When the inputs are active and capacitors are charging and
discharging, as a result dissipated power varies through it. It can be divided into two
mechanisms such as: switched power dissipation and short circuit power dissipation.
The value of each and every of its component is a function of the topology used for
circuit and the logic style adopted [21].

(a). Switched power dissipation,

(b) Short-circuit power dissipation,
(c) Glitch power dissipation.

All of these categories of power dissipation depend more or less on the

switching activities, operation timing, output node capacitances and equipped voltage of
the circuit. The process of discharging and charging of the circuit of the output node
capacitance is repeatedly needed for transmitting the information in CMOS and MCML
circuits. The MCML based circuit causes the low leakage currents flows through them.
On the other hand, repeated charging and discharging of the output capacitance is
necessary to transmit information in CMOS circuits. The switching power dissipation
occurs due to the charging and discharging of the internal capacitances. The power
consumed in any digital circuit can be represented by equation (3.1).
P = f.C.Vdd2 + f.Ishort.Vdd + Ileak.Vdd
Where

25

(3.1)

f is the clock frequency,

C is the average switched Capacitance per clock cycle,
Vdd is the supply voltage,
Ishort is the short circuit current,
Ileak is the leakage current.
Here equation (3.1) gives the mathematical expression for the power
consumed due to the switching activity of the digital circuit and system. This expression
shows that the dissipated power is dependent upon the operating frequency, output node
capacitance, supply voltage, short circuit current and leakage current flow through the
circuit.

In a thoroughly optimized efficient power VLSI circuits, the first term of

equation (3.1) is by far the governing factor. The standby power redution is accounted
for by the third and the last term. Since by increasing the power supply leakage current
will also be increased by far, so power supply to the device is kept low. Regarding the
first term, in order to reduce the dynamic power consumption, power supply is chosen to
be lower valued, since the dissipated power is the square of the supplied power. It is an
effective way of reducing the dynamic power dissipation. The above power dissipation
expression also shows that the short circuit power and leakage power consumption are
also robustly dependent upon the power supplied to the circuit, even when using the
lower value of power supply degrades the performance.

The dissipated power for any digital circuit and device is dependent upon
the operating frequency, output node capacitance, supply voltage, short circuit current
and leakage current flow through them.

(a) Output node capacitance of the logic gate: This capacitance occurred
due to the drain diffusion region.
(b) Total interconnects capacitance: The interconnect capacitance effects
vastly as technology node shrinks.
(c) Input node capacitance of the driven gate: Due to the induced gate oxide
capacitance. Input node capacitance occurs.

For calculating the estimation of average power required to charge up the

output node to power supply Vdd and to charge down the output capacitance to the
ground level is incorporated. This estimated average power is independent of its
characteristics.
26

Dynamic power consumption can also be reduced by lower the supply

voltage Vdd, lowering the voltage swing at all nodes, reducing the transition factor
(switching probability) and reducing the output load capacitance.

3.3 DIODE LEAKAGE CURRENT

When the transistor is turned OFF and some other transistor charges up or
down with respect to former bulk latent voltage, then this situation causes the diode
leakage current. For example in case of CMOS inverter, when high voltage is applied,
PMOS turned OFF, creating an open path from power supply to the output as drain to
body potential is equal to (- VDD)and NMOS transistor is ON, creating a short circuit
path from output to ground, and it gives the output 0. The final diode leakage current
can be established as equation (3.2).
I = A J

(3.2)

Where, is the leakage current density can be fixed by standard technology

models and
is the drain diffusion area. Since for reflectably small reverse bias
potential, diode can be reached to the highest limit of reverse bias current, the leakage
current is dependent on supply voltage partially. The leakage current is directly
proportional to the diffusion area and the perimeter of the drain terminal. Thus it is
understandable to minimize the diffusion are and perimeter in the layout design. The
leakage current density also increases at the higher temperatures abruptly, so it can
conclude that leakage current density is exponentially proportional to the temperature.

3.4 BIASING CURRENT

MOS current mode logic (MCML) circuit utilizes the biasing current in speeding up the
estimation of the logic function by avoiding the process in the cut-off region. Although
CMOS circuits do not show the static power dissipation, but few of the logic families
that are used in speed up operation such as MCML and pseudo NMOS circuit use it to
replace the total pull up PMOS network to a single PMOS transistor. The above power
dissipation expression also shows that the short circuit power and leakage power
consumption are also robustly dependent upon the power supplied to the circuit. This
helps in reducing the total number of transistors which in turn reduces the capacitance,
hence lowers the power dissipation. However, the transistor sizes can be varied
according to the requirement of generating a valid logic at the output level.

27

3.5 SUB THRESHOLD LEAKAGE CURRENT

The causes for sub threshold leakage current are same as the diode current.
In the inverter, for high power supply, PMOS is turned OFF. When the transistor is idle
that is VGS = 0, there is still some current flowing through it because of the negative
value of VDD. The ID vs. VDS shows an exponential relation in the sub threshold region
(VGS < VTH) [22].
Fig 3.2 shows the sub threshold current magnitude at gate to source voltage
VGS = 0V. The sub threshold current magnitude is shown as the function of device size,
supply voltage and process variation. The reduction in threshold voltage exponentially
increases the sub threshold current, as it principally affects the magnitude of the given
current. Even the threshold current is directly proportional to the transistor size W/L,
also an exponential function of the power supply.

Fig 3.2: Leakage current in the logic gate

28

3.6 SHORT CIRCUIT POWER DISSIPATION

In actual circuits and systems, signals have non-zero rising times for P net
and N net and in the same way have non-zero fall times for P net and N net which
causes both of the nets of the CMOS gate to conduct current at the same time. This leads
to the flow of a short circuit current for a short period of time. The input and output
slopes of the gate should be equal to minimize the overall short circuit dissipation in
devices. Also large load capacitance can significantly reduce the short circuit dissipation
of the driving part [23].

3.7 INTERNAL POWER

The internal power consumption occurs when the inputs are changing but
the circuit is not changing the values at the output in the end. Logic circuits do not
necessarily keep changing the values and conducts the current through it. They do not
escort a change in the output node at every change in the input value. The full voltage
swing of power supply Vdd which leads to the partial voltage swing happens to be
greater than the internal node voltage swing [24].

3.8 LOW LEAKAGE POWER CIRCUIT TECHNIQUES

Although with the continuous technology scaling, dynamic power

dissipation is keep reducing, but the leakage power dissipation tends to increase every
now and then and is looking forward to become a large active component in the total
power dissipation in the coming future technology generations. A high leakage power
heat up condition can therefore be dangerous for portable electronic devices and circuits.
Over the last decade, a plenty of leakage power management techniques and approaches
have been developed and addressed in the open literature. In the following section, most
common amongst of these methods are discussed [25].

3.8.1 Leakage Control by Body Biasing

The body biasing approach consists of increasing the threshold voltage (Vt)
of NMOS devices and PMOS devices during the standby (preservation) mode by
diverging the values of body bias voltage (VB), this in turn helps in reducing the leakage
current through devices. In order to obtain the threshold voltage Vth higher than the

29

threshold voltage at source and body point i.e., Vth0, the body terminal of the NMOS
device is kept to bias at the lower point than the ground (threshold voltage for a sourceto-body voltage (VSB = 0). In the similar fashion, in order to keep the increment going in
Vth, the body terminal of the PMOS device is made to bias to a voltage higher than the
supply voltage Vdd.
In the active mode, the NMOS transistors body nodule is biased to ground,
Vss in the meanwhile the body nodule of the PMOS transistor is biased to the power
supply Vdd, in order to obtain the normal lower value of threshold voltage Vth and
obtain the normal speed. Dynamic threshold CMOS (DTCMOS) is an alternative of the
leakage control by body biasing since the body is tied up to the gate terminal and a
changeable threshold voltage is realized in accordance to the device condition.

3.8.2 Leakage Control by MTCMOS Technique

MTCMOS based schematic diagram is shown in Fig. 3.3.

Fig 3.3: Generalized schematic of MTCMOS technique

30

In multi-threshold CMOS (MTCMOS) technique, high threshold voltage Vt

switch transistors are used to control leakage. In order to turn off the gates when they
are in idle state, the given logic family technique uses low leakage transistors as
illustrated in Fig 3.3.

To increase the gate delay time, the gate transistor uses low threshold
voltage. But if we lower the threshold voltage, the leakage current increases in turn
sources to induce the sleep transistor. This sleep transistor has high threshold voltage to
diminish the leakage current. During the reserve mode, the switch transistors are turned
OFF and bounds the leakage current credit to their high threshold voltage Vt. In the
active mode, the switch transistors are turned ON and act as a virtual Vdd and ground.

To control these transistors, a signal SLEEP" is asserted by the sleep

transistor in order to turn ON or OFF the switch transistors to manage the power
supply, and this gated power supply is termed as virtual VDD. During the reserve mode,
the switch transistors are turned OFF and bound the leakage current magnitude to
their high threshold voltage Vt. In the active mode, the switch transistors are turned
ON and act as a virtual VDD and ground. If we lower the threshold voltage, the
leakage current flows one by one through sources to induce the sleep transistor. This
sleep transistor has high threshold voltage to diminish the leakage current. During the
reserve mode, the switch transistors are turned OFF and bound the leakage current to
their high threshold voltage Vt [26].

3.8.3 Leakage Control by MVCMOS Technique

Multi-voltage CMOS (MVCMOS) is depicted in Fig 3.4. Unlike in

MTCMOS where the SLEEP" transistors have high Vt, the MVCMOS technique uses
SLEEP" transistors with low Vt whose gates are controlled by a voltage which is larger
than VDD for the PMOS transistor and lower than ground for the NMOS transistor
during the standby mode. This results in negative Vgs values for both NMOS and
PMOS and subsequently in smaller leakage. The magnitude of threshold voltage Vt is
dependent upon the supply voltage.

The power consumption depends on the switching activity, the number of

transistors and on parasitic capacitances. The die area is influenced by the number of
transistors, their sizes and the routing complexity. The choice of the macro-cells
schematics is therefore the first important step to design low power circuits. The circuit
performances are strongly influenced by the preference of the logic style exploited in
designing the fundamental gates.
31

Fig 3.4: MVCMOS Technique

The Fig 3.4 above here consists of low Vt logic, which comprised of
particular logical boolean expression. This logic network is set to the lower threshold
voltage value. Doing this will help in switching off the circuit, while the sleep
transistor is set on high threshold will be responsible for the working of total circuit
[27].

32

CHAPTER 4
MOSFET CURRENT MODE LOGIC (MCML)

4.1 INTRODUCTION TO MCML

MOS current mode logic (MCML) is a new alternative for the traditional
CMOS logic style for mixed signal analog applications. It is stated that as the operating
frequency and integration density increases for the digital circuit, it will become difficult
to protect noise perceptive analog circuitry from noisy digital circuit. It will difficult the
integration of analog and digital circuits which is very important. The MCML library
shows the less power dissipation at the operating frequency of higher values and more in
comparison to the conventional CMOS style. It is nearly impossible to create robust,
power efficient and cost effective design and time to market product. To reduce this
problem there are many MCLML techniques are used and found the success.

Many efforts have been taken to realize the importance of MCML style. The
circuits constructed by using MCML logic style face the problem of complexity and
robustness. To reduce this problem, there are many MCML techniques are used and
found the success. The MCML universal gate, the popular topology due to the relatively
small size and versatility has an asymmetric topology and has considerable robustness.
The irregularity at the gate terminal of MCML logic style degrades the overall circuit
functionality. It increases the complexity of any prospective MCML model of any gate
for simulation [28].

MCML architectures provide higher invulnerability to supply noise due to

their differential structure and lower cross talk due to the reduced output voltage swing
and lower noise generated due to the constant current flowing through the supply rails.
This method enables the designer to explore different execution options For many of
applications the prime objective for the design to be efficient is power consumption,
speed and power delay product. And these can be explained in the simple terms of
process parameters and transistor dimensions. However in the case of MCML
technology, it is hard to achieve since the gate terminal of it is supplied with the analog

33

signal so the robustness is hard to accomplish since the signal will always be
fluctuating, this is why it imposes tight restraint over the MCML design to get less error.
[29].

4.2 MCML BASIC OPERATION

Basically MOS current mode logic (MCML) is a digital realization of the

differential amplifier. As displayed in Fig 4.1, by transferring the current form one stage
to another stage, the given logic can be realized [30].

Fig 4.1: Basic MCML operation

Compare to the nature of analog amplifier, the MCML logic is happened to

work in non linear region.

34

The following circuit consists of logic realization network, its input blocks
in the both side consist of logic implementation. They generally consist of differential
pair or set of differential pair organized in certain fashion to regulate the current in one
branch and then share it to the other and simultaneously switching off the other input
combination applied to it. The output voltage levels are set as shown in equation (4.1),
and equation (4.2), where high voltage value is equal to supply voltage and low voltage
is equal to the consumed voltage value.

VH = VDD,

for logic high

(4.1)

VL = VDD V,

for logic low

(4.2)

Where V = ISS R is the voltage swing.

Here, the load resistance R can be replaced by an active load such as PMOS
transistor operating in the linear region whereas the tail current ISS is replaced and
controlled by the active transistor in the saturation type [32].

4.3 MCML ADVANTAGES

All advantages of MCML are credited to its differential part character.

Firstly, a differential topology has high resistance to common mode noise. Secondly, the
effective voltage swing can be doubled by the differential signaling which shows the
direct proportionality relationship with the noise margin. The proof of improvement in
noise margin and noise invulnerability enables designers to accommodate extra noise
margin for the voltage swing. As delay is directly proportional to the voltage swing,
when voltage swing improves, its delay is also improved. The delay is improved in
accordance to the equation (4.3).

D=

"$
%&&

(4.3)

Where, C is the capacitance at the output node. The major reason for
switching noise is the abrupt and extreme current change in the supply rail lines causing
effects such as charge injection and ground bounce into the substrate. The current drop
in MCML gates provides a steady current regardless of the switching activity. Converse

35

to the CMOS approach, the current drop in MCML gates provides a highly steady
current regardless of the switching activity making MCML a mixed signal environment
friendly alternative [33].

4.4 MCML DISADVANTAGES

The static DC current, which happens to be responsible for the smooth

operation of MCML circuits cause the gate terminal to leak excess power even when the
gate is in inactive state. Incongruously, it shows mainly imperative advantage of the
MCML logic style proves to be its most awful disadvantages. However, the MCML
technique is still a beneficial method.

In the CMOS circuit, the power is dissipated in the form of static power and
dynamic power. Static power dissipates due to the charge leakage problem and dynamic
power dissipates due to the switching activity at the internal nodes. The static leakage
power proves to be a bigger problem, as transistor sizes are getting smaller. The smaller
the transistor size, more the leakage power will flow. The dynamic power dissipation is
due to the discharging and charging of the output node capacitance. The dynamic power
dissipation can be stated as equation (4.4).
P"() = f C V

(4.4)

Where the switching activity, f is the operating clocking frequency and CL

is the capacitance hanging at the output node. The power dissipated through the CMOS
circuit is directly proportional to the operating frequency.

Whereas on the other hand, the prime source of power dissipation in MCML
circuit is static power and is expressed in equation (4.5).

P("( = I

(4.5)

The expression gives the power in MCML circuit by multiplying the source
current to the power supply. The equation above gives the direct relationship in between
the power consumed in the process to the current flown in the circuit multiplied by the

36

total supply voltage. The MCML circuit shows the effective improvement work for the
lower power devices.

4.5 MOSFET MODELS

The MOSFET working depends on various model parameters design using

which the efficiency and its operation is defined. The MOSFET operates in the
saturation region. The few related models parameters are discussed here [31].

4.5.1 Threshold Voltage

The threshold voltage for any device can be defined as a minimum voltage
at which the transistor works and causes the current to flow through it. Threshold
voltage creates the spot at which the sturdy inversion process occurs in the MOSFET
channel part. Threshold voltage can also be set differently for different transistor in the
single circuit. MTCMOS circuit is the example of such concept, where low and high
threshold levels are required for conduction. Threshold voltage is defined as the function
of the potential across the device terminal and several other material related parameters.
The threshold voltage can be articulated by equation (4.6).

V. = V./ + 1 | 2 |5 + V

|25 |

(4.6)

Where VT0 is the threshold voltage at VSB = 0, VSB is source to body

voltage, 5 is the Fermi potential and is the parameter that shows the effect of the
change of the VSB on VT.

4.5.2 DC Power Supply

The power consumption of any logical circuitry is directly proportional to

the power supply VDD so it should be reduced as much as feasible. In order to achieve
the lower power consumption, the lower supply voltage is required. NMOS current
source imposes the lower limit on the power supply VDD. In MCML method when bias
Vb starts working for that period of time, the load transistor P1 and P2 cuts off the
power supply and leave the circuit dependent upon the bias voltage. In this way, power
supply cannot be able to corrupt the circuit operation.

37

The reduction in the power supply VDD drives the circuit design out of the
saturation region the output impedance of the current source in the tail end does not
harm. Due to this, the voltage gain AV is reduced in consequence. The other outcome of
this degradation is that the current in gate is reduced and Current Matching Ratio
(CMR) is begun to decrease. Due to the scaling down of the size, voltage is also scaled
down, thus the problem of current leakage is increased.

4.6 PERFORMANCE PARAMETER

Under this title, performance factors are explained. There are three
performance parameters that are affecting the MCML circuit, working efficiency such
as power, delay and power delay product. In chapter 3, power techniques have already
been described. Here we will describe the gate delay parameter only [32].

4.6.1 Power Supply Switching Noise

This parameter metric is used to evaluate the capability of MCML circuit to

incorporate with analog circuitry. The following metric used can be expressed as the
percentage variation of the supply current from its DC average.

4.6.2 Voltage Swing Ratio

Preferably, MCML NMOS transistors act as perfect switches awakening all

the DC current from one stage to the other. However, practically, only a fractional part
of the tail current is switched from side to side leaving some current behind in the
OFF part or stage. The Voltage Swing Ratio (VSR) is defined as the ratio of the
current in ON branch to the tail current ISS. Large transition width is required to
execute, if one needs to achieve the aim of 100% VSR ratio. Due to this, it witnesses the
generous drop in speed. The higher VSR helps in attaining the low leakage current. A
small amount of VSR degrades the dc gain of gate and causes the signal to weaken as it
processed through the stages.

A reasonable circuit speed can be achieved using with 95% Voltage Swing
Ratio which guarantees the assured and smooth operation. For achieving the 100 %
VSR device , one needs to have large transition width. If the square law model is used to
calculate approximately the transistor DC current saturation, then

38

89: =

<
=

>?@ A>B C

D>E@

F@@

(4.12)

Where 8 is the drain to source voltage of the differential pair.

4.6.3 PMOS Load Transistor Sizes (WRFP, LRFP)

One of the most complicated tasks is to boost the size of PMOS load
transistors, a non linear work to create the efficient MCML circuit. The affect of sizing
these transistors imposed on various parameters such as Signal Swing Ratio (SSR),
propagation delay, RFP control voltage limit, voltage mismatch and the voltage gain,
also this affects the area transactions. To increase the voltage gain of the device, length
of PMOS load transistor can be increased. This factor strongly effects when we increase
the length of PMOS from minimum to higher.

4.6.4 NMOS Load Transistor Sizes (WRFN, LRFN)

The tradeoffs between area and robustness are important in selecting the transistor sizes
of the tail current source. The use of non-minimum length devices for the current source
is desirable as it helps in both to decrease the mismatch effects and increase the output
impedance. It is required to decrease the VDSAT voltage which further allows the
decrement in supply voltage VDD by having a large width to length ratio (W/L). Here we
have to impose a restriction over the width to length ratio as the area of the device starts
to grow dramatically.

4.7 DYNAMIC MCML

Dynamic current mode logic (DyCML) has been designed to overcome the
problem of static power dissipation problem in standard MCML. It is an active logical
implementation of MCML. This MCML style has limited voltage swing, reduces the
number of gates and interconnects power dissipation. It combines the advantage of MOS
current mode logic (MCML) circuits with that of dynamic logic families to achieve the
higher performance at lower power supply, dissipates low power. The main advantage
of DyCML is that they do not have any static current source. This quality makes it a
suitable alternative for battery powered systems and portable devices. Fig 4.2, on the
next page, shows the Dynamic CML logic style gate. The operation of the Dynamic

39

CML can be performed in two phases such as formely precharge pcycle and later one is
evaluation cycle.

Fig4.2: Dynamic CML style

In the precharge phase, when the low clock frquency is applied, M2, M3 and
M4 are turned ON. Therefore causing the outputs to rise upto VDD and capacitor C1 is

40

discharged to ground. While, in the evaluation phase, when the clock is at high level and
M2, M3 and M4 are turned OFF. And therefore, closing the path from CL to ground.
Depending on the arrangement of input combination, charges will be start flowing from
one of the output terminals to the capacitor CL which acts as a current drop. And
transistors M5, M6 of PMOS type are acting as a latch to preserve any of he logic value.
The Dynamic CML logic style can shows the considerable power reduction in
comparison to Standard MCML. There are disadvantages too with Dynamic MCML
style such as increased switching noise and design complexity [38].

41

CHAPTER 5
SIMULATION RESULTS

5.1 TOOL USED

For designing and simulating schematic and creating its output waveform
TANNER EDA 14.1 Tool will be used. TANNER EDA Tool can be used for digital
simulation as well as analog simulation. Tanner tool used for designing the circuit,
where the parameter of transistor set to the desired level. The design is edited using Sedit tool. This report is displayed under the T-edit tool. This report is displayed under
the T-edit tool, if there is any connection missing or made wrong, then it will show the
errors.

5.2 INPUT PARAMETERS

For achieving the desired results, the proposed design has been set to some
certain parameters. These are given below in table 5.1.

Table 5.1 Input parameters of the design

PARAMETERS

VALUES

Operating Frequency

50 MHz

Supply Voltage

5.0V

Table 5.1 shows the parameters on which the given designs are simulated
and results are achieved on these set parameters.

42

5.3 RESULTS

The simulation results for all the full adder designs are as shown in here. Fig
5.1 shows the schematic of conventional full adder and Fig 5.2 and Fig 5.3 shows the
input voltage waveform of the conventional full adder.

Fig 5.1: Schematic of Mirror CMOS Full Adder

Fig 5.1 shows the schematic diagram of mirror CMOS full adder. It consists
of 36 transistors. Fig 5.2 shows the voltage waveforms for all the inputs varying from 0
to 5 volts and shows every possible input combination. For each and every possible

43

input combination, Fig 5.3 shows the changes in output voltage waveforms consist of
sum and carry parts, driven from the inputs. These waveforms are approximately same
for all other full adder designs [Appendix I.1].

The mirror circuit casts the same image for the bottom half part, as we can
see through the schematic and OR gate and AND gate fed to the previous stage. The
mirror CMOS based circuits work on the principle of replicating the pull up network to
the pull down network. This approach helps in layout designing stage. Where it is stated
the more the blocks are same, the simpler the layout design can be possible.

Here, we are displaying the results for the digital schematic part. The
following mirror Cmos circuit is implemented using 36 transistors, among half of the
transistors is comprised of PMOS transistor and other halves are NMOS transistors. The
design is implemented using 5 v power supply and 50 Hz frequency which is used for
deciding the period for which the circuit runs for the particular bit.

Fig 5.2: Input Voltage Waveform for Mirror CMOS Full Adder

44

Fig 5.3: Output Voltage Waveform for Mirror CMOS Full Adder

Fig. 5.1 shows the inputs A, B, C for the output generation of Mirror CMOS
full adder. The inputs are varying from 0V to 5V, having the rise time and fall time of
5ns. The inputs are varying on the plot of time against voltage such as the input pulses
are varying from the 0V to 5V with respect to the time period varying in nano seconds.

Fig. 5.2 shows the output as sum and Cout as a response of the inputs A, B,
C. Here, it can be seen that the output are changing according the inputs at every pulse.
If the following outputs are compared to the truth table of the full adder, the above
results can be verified and it can be seen that it gives the noise free results and its
simulation results for the power, delay and power delay will show the values for the
output changing. Due to the excess of transistors, this design takes more power.

MOS Current Mode logic based full adder shown here works on the current
mirror circuit, where the current replicate from one branch to next branch and the next
one and so on
45

Fig 5.4: Schematic of the Proposed Full Adder

MOS Current Mode logic works in triode region, where the whole operation
depends upon the biasing transistor. The transistor can be replaced by current source and
current is replicated from one stage to another stage. Fig. 5.4 shows the schematic of the
proposed full adder based on the concept of MOS Current Mode Logic (MCML). Here,
a current source is replaced by a transistor and a bias voltage vb is applied on the gate.
For replacing the current source to the transistor and bias voltage, the transistor should
be in saturation region i.e.VGS-Vt > VDS should be satisfied in the pull down network. In
the pull up network, a transitor is used with complementry bias voltage to make a path
on the 0 value. Its W/L ratio kept at 0.25/0.25 to show the resistance as the width
decreases.
46

Fig 5.5: Input Voltage Waveform for proposed Full Adder

Fig 5.6: Output Voltage Waveform for proposed Full Adder

47

Fig 5.7: Input Voltage Waveform for proposed Full Adder

Fig 5.8: Output Voltage Waveform for proposed Full Adder

48

The half of the circuit gives the sum and its complementry, which is
transmitted further to give the carry of the circuit. This circuit detects two cases at which
the three 1-bit addition remain the same and does not change i.e., 000, 111.

Fig 5.5 shows the input of the circuit design proposed and Fig. 5.6 shows the
output for the same circuit, as we can see it gives the true output for the circuit. The
proposed design consists of 24 transistors, using the concept of MCML which helps in
reducing the number of transistor count. The following circuit is simulated using 5V
power supply here the inputs are varying from 0V to 5V. The inputs are varying on the
plot of time against voltage such as the input pulses are varying from the 0V to 5V with
respect to the time period varying in nano seconds. Here, it can be seen that the output
are changing according the inputs at every pulse. If the following outputs are compared
to the truth table of the full adder, the above results can be verified and it can be seen
that it gives the improved results and its simulation results for the power, delay and
power delay will show the values for the output changing. Due to the excess of
transistors, this design takes more power. Although it faces the problem of robustness of
the circuit and leakage will be increasing if the corresponding current increases or the
power [Appendix II.2].

Similarly, fig.5.7 shows the inputs for the same circuit and fig. 5.8 shows the
output wave form for the following input string. This waveform carried out for the lower
power supply of 1V. The MCML based full adder works best in the lower power area,
where the lower power is required. It gives the lower threshold voltage. So by using the
following circuit, lower power threshold conditions can be achieved. Here, in the
schematic of the NMOS is working as a switch as it is connected to the bias voltage the
bias voltage supplied to the tail transistor working as a current source. It works as a
clock as for the time being it is ON state, the circuit works otherwise remains in the
OFF state. Due to this feature, MCML based devices consumes less power [Appendix
II.2].
To design a low power full adder, this is one of the most power efficient
concepts to work on. As MOS current mode logic (MCML) techniques are usually used
for high speed applications such as high speed processors and Gbps multiplexers for
optical transceivers. With the growing uses of portable and wireless electronic systems,
energy efficient designs have become more and more important in integrated circuits.
MCML circuits have large static power consumption due to its constant operation
current. Therefore, the power dissipation of MCML circuits is much larger than the
conventional CMOS ones at low operating frequencies [33].

For replacing the current source to the transistor and bias voltage, the transistor should
be in saturation region i.e.VGS-Vt > VDS should be satisfied in the pull down network. In
49

the pull up network, a transitor is used with complementry bias voltage to make a path
on the 0 value. Its W/L ratio kept at 0.25/0.25 to show the resistance as the width
decreases.

Preferably, MCML NMOS transistors act as perfect switches awakening all

the DC current from one stage to the other. However, practically, only a fractional part
of the tail current is switched from side to side leaving some current behind in the
OFF part or stage.

Fig 5.9: Circuit Testing Arrangement of Full Adder

Here, Fig 5.9 displays the testing arrangement of all the one-bit full adder
circuit. It shows the couple of inverters are inserted before every input and after every
output so that there will be no noise included while measuring the power and delay for
any particular circuit.

The inverters connected into this full adder are also designed using the same
parameters such as used in the full adder transistors. The NMOS and PMOS transistors
width to length ratios are the same of the full adder block. The couple of inverters are
deposited before the inputs strings and also after the output string, it is due to fact that, it
shows no noise and other disturbances while computing the simulation and calculating
the power delay and power delay product. This is called as the test bench of the circuit

50

which verifies the correctness and accuracy of the design as well as eliminates the threat
of any noise presented in the circuit to some extent.

Table 5.2 Comparison of full adder designs at 5 volts

Implement
ation
(Vdd=5.0v)

Delay, ns

Cout

Mirror
CMOS [19]

5.847

14.504

Proposed
design
simulated
results

0.269

0.106

Power
consumptio
n
(mW) at 50
MHz

Power Delay Product

(mWns)

Transisto
r count

Cout

0.738

4.315

10.703

36

0.0161

0.043

0.171

24

Table 5.2 shows the numerical comparison of the two type of full adders,
one results is taken from the paper and the other one is driven by the actual simulation
of another design which is proposed as thesis contribution, shows the numerical
analysis. The following table gives the result for the 5V power supply. Here, it can be
noticed that there is a improvement in the results for the proposed full adder design i.e.
MOS Current Mode Logic (MCML) based full adder design against the Mirror CMOS
based full adder design.

The power consumption is improved for the proposed full adder design as
well as the delay for sum and carry bits. In the base paper, carry part works faster than
the sum part, but here sum part also works faster and that too from carry part.

The improvement is achieved by using the MCML concept and also due to
the fact that transistor count is decreased from 36 to 24.
51

Table 5.3 Comparison of full adder designs 1 volt

Implement
ation
(Vdd=1.0v)

Delay, ns

Cout

Mirror
CMOS [19]

5.847

14.504

Proposed
design
simulated
results

0.484

0.148

Power
consumptio
n
(mW) at 50
MHz

Power Delay Product

(mWns)

Transisto
r count

Cout

0.738

4.315

10.703

36

0.0924

0.0047

0.0137

24

Table 5.3 shows an extended work, where the full adder design are also
compared for the low power supply for the sake of the low power design studies and its
analysis and effect on the results of full adder designs

The numerical comparison of the two type of full adders, shows the
numerical analysis. The following table gives the result for the 1V power supply. The
improvement is achieved by using the MCML concept and also due to the fact that
transistor count is decreased from 36 to 24.

The power consumption is improved for the proposed full adder design as
well as the delay for sum and carry bits. In the base paper, carry part works faster than
the sum part, but here sum part also works faster and that too from carry part.

Here, it can be noticed that there is more improvement in the results for the
proposed full adder design i.e. MOS Current Mode Logic (MCML) based full adder
design against the Mirror CMOS based full adder design, if we reduce the power supply
and it can give more better results.
52

Fig 5.10: Generalized setup for 4-bit RCA Adder

Fig 5.10 shows the symbolic representation of 4-bit Ripple Carry Adder
(RCA). Here, three initial inputs such as bit A, bit B, and bit C, has been supplied to the
first full adder in the adder chain. This full adder spawns the carry and sum as an
outcome. The output is then supplied to the next adder in the adder chain, acts as third
input along with bits A and B and so on. This process continues until the fourth adder
where the final carry and sum is spawned for 4-bit RCA.

The objective of this design is to calculate the delay on sum signal caused by
the process of propagating the carry signal. Here, all the delay of all the sum signals is
evaluated and determined. In the MCML design, for driving the outputs from the ripple
carry adder, buffers are also added in order to get the less rippled signals. The delays are
calculated here for the sum signals. A 4-bit RCA is an important realization for having
understood the working nature of MCML in large designs.

After estimating the parameters in the single adder, a large 4-bit RCA is
designed and simulated using the same tanner tool and estimated. Fig 5.18 and Fig 5.19
shows the voltage waveform for its sum signal and its carry out signal. In the above
Figure, it is shown that every sum signal is different in one way or the other. Bit S1 is
different than S0 as its one of the input signal is changed because of the carry signal
generated from the previous adder [Appendix I.2].

53

Fig 5.11: Waveform for the Mirror CMOS Full Adder Circuit for S0, S1, S2 Bits

Fig 5.12: Waveform for the Mirror CMOS RCA Circuit for S3, Cout Bits

54

The mirror CMOS signal is exploited to construct the Ripple Carry Adder
(RCA). Fig 5.11 displays the voltage waveform for sum signals. The bit S2 shows the
short ripple which has fallen immediately, the ripple is so because intermediate signal is
changing at the moment. The sum bit S2 also shows the minute ripple by falling below
the threshold level [Appendix I.2].

The final sum and carry pointer is produced and displayed in Fig 5.12 and
gives the results. The Mirror based design is dependent upon the identical image. Here,
AND and OR gate is also used for refraining the particular bits and filters the others.

Fig 5.13: Waveform for the Proposed CMOS RCA Circuit for S0, S1, S2 Bits

The intermediate sum and carry pointer is produced and displayed in Fig
5.13 and gives the results. The MCML based design is dependent upon the bias voltage.

55

This circuit only works while the bias voltage is given to the circuit. The circuit works
only for the particular pulse width, and for the rest of waveform, it is off. This bias
voltage works more like a clock signal in the domino circuit network with the little
difference that MCML design do not have to put inverter at the output. So this is helpful
in power saving.

Fig 5.14: Waveform for the Proposed CMOS RCA Circuit for S3, Cout Bits

The voltage waveform is shown, in Fig 5.14 for S3 bit and Cout bit. The
ripple showed in sum bit is due to the delay induced by the previous state. The
following waveform displays the placement of bits according to the intermediate carry
bit which is extracted from the second intermediate stage [Appendix II.2].

Here, table 5.4 shows the calculation for the sum signals for ripple carry
adder (RCA). Four individual adders are connected in series position and construct the
RCA.
56

The final sum and carry pointer is produced and displayed in Fig 5.25 and
gives the results. The Mirror based design is dependent upon the identical image. Here,
AND and OR gate is also used for refraining the particular bits and filters the others.

Fig 5.15: Waveform for the Proposed CMOS RCA Circuit for S0, S1, S2 Bits

The intermediate sum and carry pointer is produced and displayed in Fig
5.15 and gives the results. The MCML based design is dependent upon the bias voltage.
This circuit only works while the bias voltage is given to the circuit. The circuit works
only for the particular pulse width, and for the rest of waveform, it is off. This bias
voltage works more like a clock signal in the domino circuit network with the little
difference that MCML design do not have to put inverter at the output. So this is helpful
in power saving.

57

Fig 5.16: Waveform for the Proposed CMOS RCA Circuit for S3, Cout Bits

The voltage waveform is shown, in Fig 5.16 for S3 bit and Cout bit. The
ripple showed in sum bit is due to the delay induced by the previous state. The
following waveform displays the placement of bits according to the intermediate carry
bit which is extracted from the second intermediate stage the sum and carry bit varies to
1volt power supply from 0 volt. The transition is absorbed for each pulse and verified
against the full adder truth table. MCML method is more approachable if we use lower
power supply[Appendix II.4].

Here, table 5.4 shows the calculation for the sum signals for ripple carry
adder (RCA). Four individual adders are connected in series position and construct the
RCA.

58

Table 5.4 Comparison of delay of sum bits of RCA designs (for 5Volts) [19]
Delay, ns

S0

S1

S2

S3

Mirror CMOS

14.521

20.817

27.124

33.437

Proposed design
simulated results

0.071

0.142

0.126

0.151

Table 5.4 shows the estimation of sum bits for all RCA designs. From the
above comparison it can be concluded that proposed design shows the improvement in
delay from other approaches. The following ripple carry adder results are simulated and
carried out for voltage supply of 5 volts. This table 5.4 analyzes the results for the
consumed power and also for the reduced delay and total power delay product (PDP).
The following results shows the MCML based full adder based ripple carry adders are
also power efficient circuits and reduce the delay to the manageable limit.

There are various applications where is the delay reduction is the basic
requirement and also requires a circuit which works for the mixed signal approach. RCA
is one of the application where when it is used somewhere in the other application
requires the vast reduction in power supply.

Here the RCA is supplied with 5V power supply, and even then it shows the
vast reduction in the delay for each bit. For the S0 bit it shows minimum delay and for
the S3 bit, it shows maximum delay. It is because of the fact that while processing the
stage, it faces the lag from the previous input stage

Ripple carry adder (RCA) is one of the simplest multi bit adder, with the
sight of its design representation, it is one of the simplest and consumes less power. It is
used in the places, where the complexity is already presented in the complex diagrams.
The circuit is used only to serve the basic block of the devices. [34].

59

Table 5.5 Comparison of delay of sum bits of RCA designs (for 1Volts) [19]
Delay, ns

S0

S1

S2

S3

Mirror CMOS

14.521

20.817

27.124

33.437

Proposed design
simulated results

0.488

0.412

0.475

0.346

Table 5.5 shows the delay results for the ripple carry adder for 1V power
supply. This simulation is also done for the sake of the verifying the MCML features.
MCML circuits and relative application can work for the lower power supplies and
gives the reduced delay.

From the results above we can conclude that the MCML is one of the best approaches
that can be used in place of the CMOS logic style design. Here we can see the delay at
S3 bit is the minimum one However working in the MCML is slightly difficult as it is
the mixed signal approach. It accepts the analog signal and produces the results in
analog signal. The best working of MCML design in the mixed signal environment,
where the interaction in between the digital and analog environment is neccesary. Here
we can see the delay at S3 bit is the minimum.

60

CHAPTER 6
CONCLUSION & FUTURE WORK

6.1 CONCLUSION

In todays time, there is a requirement of the circuit design that can work
with efficient power scheme. These circuits devour power and generate the desired
result with the less power consumption. These designs are needed for speeding up the
arithmetic logic units (ALU) and other like applications. The suitable power designs
affect the performance in terms of speed of operation, time taken in completing the
operation and also the total power delay product (PDP) of the circuit. Power
management process of advanced CMOS technology process drives the need to consider
the satisfactory scale driven fundamental material limitations with like applications and
other products and designs for the evaluation requirements in the low power VLSI
design industry.

In this project, several full adder designs have been studied. There are four
full adders, simulated from the base paper. A new full adder is also created with the help
of MCML approach using 24 transistors. This new full adder uses current mirror
approach and biasing voltage in the tail. The biasing voltage with the NMOS transistor
is replaced by current source. MCML approach is frequency independent approach, thus
it takes less power than the CMOS approach. MCML has also high resistance to
common noise. For improving the delay, transistor count is decreased. The MCML
technology is exploited so that we can have one more convenient option for designing
the logic design. Converse to the CMOS, the current drop in MCML gates provides a
steady current, regardless of the switching activity, making MCML a mixed signal
environment friendly alternative.

From the above simulation, a new implementation of one bit full adder cell
is proposed that is superior in power reduction, a major factor in constructing multi bit
adders. Although the improvement is achieved at the cost of an increased delay in sum
generation, the computer simulations show the adder cell to be suitable for building n bit

61

ripple carry full adders with n > 3 that offer higher speeds of operation than any other
alternative CMOS implementation reported so far. The ripple carry adder constructed
for more than three bits shows the real observable affect on delay, power and PDP [33].

The MOS Current Mode Logic (MCML) method is adopted to acquire the
set goals. The goal was to reduce the number of transistors used in design, reducing total
consuming power and delay, also the corresponding power delay product (PDP). The
objective is also to reduce the delay from the carry terminal as the carry is fed to the
next stages in the large adders. Also the sum signals are compared for the 4-bit ripple
carry adder (RCA). By analyzing the results, we can conclude that the MCML based
adder is most efficient adder. The following adders were simulated at 50 MHz.

6.2 FUTURE WORK

In extend to this proposed circuit, It is needed to design its application such

as multi bit adders to show its vulnerabilities. Here, not only RCA (Ripple Carry Adder)
can be designed but also other adders too in order to show the speedy addition and
usefulness in comparison to other adders by reducing the supply voltage to 1volts. The
full adders are used in various applications or the applications which are useful for other
complex applications in the digital design systems. MCML adders are the efficient
devices for the high speed applications. MCML circuits can be categorized by high
noise immunity and low noise generation, which enable the alternative of putting analog
and digital blocks together. An analog signal is fed to the input and digital signal is
acquired at the output. Due to its current mirror advantage, less power will be consumed
and circuit will work faster. In order to achieve more revived results, the given designs
have been run for supply voltage of 1 volts, it shows the relative reduction in power and
delay and PDP.

62

REFERENCES
[1] R. Zimmermann and W. Fichtner, 1997, Low Power Logic Styles: CMOS Versus PassTransistor Logic, IEEE J. Solid-State Circuits, Vol. 32, no. 7, pp. 10791089.
[2] H. Lee and G. E. Sobelman, 1997, A New Low Voltage Full Adder Circuit, in IEEE proc.
7th great lakes symosium vlsi, pp. 8892.
[3] Ahmed M. Shams and Magdy A. Bayoumi, 2000, A Novel High Performance CMOS 1-Bit
Full Adder Cell, IEEE transactions on circuits and systemsii: analog and digital signal
processing, Vol. 47, pp. 478-481.
[4] D. Radhakrishnan, 2001, Low Voltage Low Power CMOS Full Adder, IEE proc. online
no. 20010170 do1 io. 1049/ ip-cds: 20010170 IEE proc.-circuits devices system, Vol. 148, no. 1,
pp 19-24.
[5] A. T. Schwarzbacher, J. P. Silvennoinen, and J. T. Timoney, 2002, Benchmarking CMOS
Adder Structures, in proc. ISSC, pp. 231234.
[6] Hung Tien Bui, Yuke Wang, Yingtao Jiang, 2002, Design and Analysis of Low Power 10
Transistor Full Adders Using Novel XORXNOR Gates, IEEE transactions on circuits and
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[7] Massimo Alioto, Gaetano Palumbo, 2002, Analysis and Comparison on Full Adder Block
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[8] Yingtao Jiang, Abdulkarim Al-Sheraidah, Yuke Wang, Edwin Sha, and Jin Gyun Chung,
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[9] C. H. Chang, J. Gu, and M. Zhang, 2005, A Review of 0.18 m Full Adder Performances
for Tree Structured Arithmetic Circuits, IEEE transanctions. very large scale integr. (vlsi)
syst., Vol. 13, no. 6, pp. 686694.
[10] S. Goel, A. Kumar, and M. A. Bayoumi, 2006, Design of robust, energy-efficient full
adders for deep-submicrometer design using hybrid-CMOS logic style, IEEE transactions very
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[11] D. Levacq, V. Dessard, and D. Flandre, 2007 Low Leakage SOI CMOS Static Memory
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[12] Jin Fa Lin, Yin Tsung Hwang, Ming Hwa Sheu and Cheng Che Ho, 2007,A Novel highSpeed and Energy Efficient 10 Transistor Full Adder Design, IEEE transactions on circuits
and systemsI, regular papers, Vol. 54, no. 5, pp. 1050-1059.
[13] Flavio Carbognani, Felix Buergin, Norbert Felber, Hubert Kaeslin and Wolfgang Fichtner,
2008, Transmission Gates Combined with Level Restoring CMOS Gates Reduce Glitches in
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(vlsi) systems, Vol. 16, no. 7, pp. 830-836.
[14] Walid Ibrahim, Valeriu Beiu, Mawahib Hussein Sulieman, 2008, On the Reliability of
Majority Gates Full Adders, IEEE transactions on nanotechnology, Vol. 7, no. 1, pp. 56-67.
[15] Farshad Moradi, Dag T. Wisland, Ali Peiravi, Hamid Mahmoodi, 2008, 1 Bit Sub
Threshold Full Adders in 65nm CMOS Technology, IEEE international conference on
microelectronics, pp. 268-271.
[16] Mi Chang Chang, Chih Sheng Chang, Chih Ping Chao, Ken Ichi Goto, Meikei Ieong, Lee
Chung Lu, Carlos H. Diaz, 2008, Transistor- and Circuit-Design Optimization for Low-Power
CMOS, IEEE transactions on electron devices, Vol. 55, no. 1, pp. 84-95.
[17] Farshad Moradi, Dag. T. Wisland, Hamid Mahmoodi, Snorre Aunet,Tuan Vu Cao, Ali
Peiravi,2009, Ultra Low Power Full Adder Topologies, IEEE Nano electronics Group,
Department of Informatics, University of Oslo, NO-0316 Oslo, Norway 978-1-4244-3828-0/09,
pp. 88-92.
[18] Yi Wei, Ji zhong Shen, 2011, Design of a Novel Low Power 8 Transistors 1 Bit Full
Adder Cell, journal of zhejiang university-science c (computers & electronics) issn 1869-1951
(print); issn 1869-196x (online) , pp. 604-607, www.zju.edu.cn/jzus, www.springerlink.com.
[19] V. V. Shubin, 2011, New CMOS Circuit Implementation of a One Bit Full Adder Cell,
ISSN 10637397, russian microelectronics, Vol. 40, no. 2, pp. 119127. pleiades publishing,
ltd. www.springerlink.com.
[20] Sohan Purohit, Martin Margala, 2012, Investigating the Impact of Logic and Circuit
Implementation on Full Adder Performance, IEEE transactions on very large scale integration
(vlsi) systems, Vol. 20, no. 7, pp. 1327-1321.
[21] D. V. Morozov, M. M. Pilipko, 2013, A Circuit Implementation of a Single Bit CMOS
Adder, ISSN 10637397, russian microelectronics, 2013, Vol. 42, no. 2, pp. 113118.
pleiades publishing, ltd www.springerlink.com.
[22] Hamid Reza Naghizadeh, Mohammad Sarvghad Moghadam, Saber Izadpanah Tous,
Abbas Golmakani, 2013, Design of Two High Performance 1-Bit CMOS Full Adder Cells,
international journal of computing and digital systems 2, no. 1, pp. 47-52.
[23] Yavuz Delican, Tlay Yildrim, 2011, High Performance 8-Bit MUX Based Multiplier
Design Using MOS Current Mode Logic, ELECO 2011 7th international conference on
electrical and electronics engineering Vol. 2, pp. 78-83.
64

[24] Subodh Wairya, Rajendra Kumar Nagaria, Sudarshan Tiwari, 2011, New Design
Methodologies for High Speed Mixed Mode CMOS Full Adder Circuits, international journal
of vlsi design & communication systems Vol.2, no.2, pp. 78-98.
[25] Hong Li, Ruiping Cao, Jianping Hu, 2012, Single Rail MOS Current Mode Logic Circuits
for Low Power and High Speed Applications, advances in information sciences and service
sciences(aiss) Vol 4, no 22, 27-36.
[26] Yangbo Wu, Xiaohui Fan, Haiyan Ni, Jianping Hu, 2013, Low Power Near Threshold
MOS Current Mode Logic with Power Gating Techniques, proc. of the 2nd international
conference on computer science and electronics engineering Vol 3, pp. 1694-1697.
[27] Zhenguo Vincent Chia, Sheung Yan Simon Ng, and Minkyu Je, 2013, Current Mode
Logic Circuits for 10-bits 5 GHz High Speed Digital to Analog Converter, world academy of
science, engineering and technology international journal of electrical, robotics, electronics and
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[28] Alexander Shapiro Eby G. Friedman, 2014, MOS Current Mode Logic Near Threshold
Circuits, journal of low power electronics and applications, Vol 2, pp.138-152.
[29] Osman Bakri Musa Abdulkarim, 2006, Design and Optimization of MOS Current Mode
Logic Circuits, carleton university, ottawa, canada, masters thesis.
[30] Ilham Hassoune , 2006 Design And Optimization of Digital Circuits for Low-Power and
Security Applications, ucl, louvain, belgium, PhD thesis.
[31] E. Pattanaik, A. K. Panda, M. Suresh, 2013,An analysis of MCML 8-bit multiplier for
high speed application, international journal of vlsi and embedded systems, Vol 04, issue 01,
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[32] Mohamad W. Alam, 2000, New Methodologies for Low Power High Performance Digital
Design, Waterloo, Ontario, Canada, PhD thesis.
[33] Trapti Mittal, Ms Uma Sharma, 2014, A Review Paper on Power Reduction Technique
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[34] Trapti Mittal, Ms Uma Sharma; October, 2015, Analysis of Full Adder for Power
Efficient Circuit Design, International Journal of Advance Research in Science &
Engineering (ISSN 2319-8354), Vol 04, issue 10, pp 26-32.

65

APPENDIX I
I.1 Mirror CMOS Full Adder

* SPICE export by:

* Export time:
* Design:
* Cell:
* View:
* Export as:
* Export mode:
* Exclude empty cells:
* Exclude .model:
* Exclude .end:
* Expand paths:
* Wrap lines:
* Root path:
* Exclude global pins:
* Control property name:

S-Edit 14.11
Mon Aug 17 15:39:40 2015
mirror
Cell3
view0
top-level cell
hierarchical
yes
no
no
yes
no
C:\Users\SONY VAIO\Desktop\mirror
no
SPICE

********* Simulation Settings - General section *********

.probe
.option probev
.include "C:\Users\SONY VAIO\Desktop\fadd180\tsmc_180nm.txt"
*************** Subcircuits *****************
.subckt INV A Out Gnd Vdd
*-------- Devices: SPICE.ORDER < 0 -------* Design: LogicGates / Cell: INV / View: Main / Page:
* Designed by: Tanner EDA Library Development Team
* Organization: Tanner EDA - Tanner Research, Inc.
* Info: Inverter
* Date: 6/14/2007 1:47:11 AM
* Revision: 3
*-------- Devices: SPICE.ORDER > 0 -------MN1 Out A Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u

66

MP1 Out A Vdd Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u AD=2.25p
PD=6.8u
.ends
.subckt mircm A B Cin Cout S Gnd Vdd
*-------- Devices: SPICE.ORDER > 0 -------MNMOS_1 N_3 B N_4 Gnd NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MNMOS_2 N_3 Cin N_9 Gnd NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MNMOS_3 N_4 A Gnd Gnd NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MNMOS_4 N_9 B Gnd Gnd NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MNMOS_5 N_9 A Gnd Gnd NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MNMOS_6 N_8 N_3 N_12 Gnd NMOS W=360n L=180n AS=324f PS=2.52u
AD=324f PD=2.52u
MNMOS_7 N_12 B Gnd Gnd NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MNMOS_8 N_12 A Gnd Gnd NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MNMOS_9 N_8 Cin N_15 Gnd NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MNMOS_10 N_15 B N_10 Gnd NMOS W=360n L=180n AS=324f PS=2.52u
AD=324f PD=2.52u
MNMOS_11 N_10 A Gnd Gnd NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MNMOS_12 N_15 N_13 Gnd Gnd NMOS W=360n L=180n AS=324f PS=2.52u
AD=324f PD=2.52u
MNMOS_13 N_6 A N_11 Gnd NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MNMOS_14 N_11 B Gnd Gnd NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MNMOS_15 S N_8 Gnd Gnd NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MNMOS_16 Cout N_3 Gnd Gnd NMOS W=360n L=180n AS=324f PS=2.52u
AD=324f PD=2.52u
MNMOS_17 N_13 A Gnd Gnd NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MNMOS_18 Gnd B N_13 Gnd NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u

67

MPMOS_10 S N_8 Vdd Vdd PMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MPMOS_11 N_14 A Vdd Vdd PMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MPMOS_12 Cout N_3 Vdd Vdd PMOS W=360n L=180n AS=324f PS=2.52u
AD=324f PD=2.52u
MPMOS_13 N_7 N_6 Vdd Vdd PMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MPMOS_14 N_16 A Vdd Vdd PMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MPMOS_15 N_7 B N_16 Vdd PMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MPMOS_16 N_8 Cin N_7 Vdd PMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MPMOS_17 N_13 B N_14 Vdd PMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MPMOS_20 N_8 N_3 N_5 Vdd PMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MPMOS_1 N_1 A Vdd Vdd PMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MPMOS_2 N_1 B Vdd Vdd PMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MPMOS_3 N_2 A Vdd Vdd PMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MPMOS_4 N_3 B N_2 Vdd PMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MPMOS_5 N_3 Cin N_1 Vdd PMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MPMOS_6 N_6 A Vdd Vdd PMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MPMOS_7 N_5 A Vdd Vdd PMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MPMOS_8 N_5 B Vdd Vdd PMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MPMOS_9 Vdd B N_6 Vdd PMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
.ends
********* Simulation Settings - General section *********
.probe
.option probev
.include "C:\Users\SONY VAIO\Desktop\fadd180\tsmc_180nm.txt"
*************** Subcircuits *****************
68

.subckt INV A Out Gnd Vdd

*-------- Devices: SPICE.ORDER < 0 -------* Design: LogicGates / Cell: INV / View: Main / Page:
* Designed by: Tanner EDA Library Development Team
* Organization: Tanner EDA - Tanner Research, Inc.
* Info: Inverter
* Date: 6/14/2007 1:47:11 AM
* Revision: 3
*-------- Devices: SPICE.ORDER > 0 -------MN1 Out A Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MP1 Out A Vdd Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u AD=2.25p
PD=6.8u
.ends
.subckt tgc A B Cin Cout S Gnd Vdd
*-------- Devices: SPICE.ORDER > 0 -------MNMOS_16 N_9 N_4 Gnd Gnd NMOS W=360n L=180n AS=324f PS=2.52u
AD=324f PD=2.52u
MNMOS_3 N_3 N_2 Gnd Gnd NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MNMOS_4 N_1 A Gnd Gnd NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MNMOS_5 N_5 B Gnd Gnd NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MNMOS_6 N_7 N_5 N_3 0 NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MNMOS_7 N_7 N_6 N_1 0 NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MNMOS_8 N_8 N_5 N_1 0 NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MNMOS_9 N_8 N_6 N_3 0 NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MNMOS_10 N_9 N_7 N_10 0 NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MNMOS_11 N_4 N_7 N_11 0 NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MNMOS_12 N_4 N_8 N_10 0 NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MNMOS_13 N_5 N_8 N_11 0 NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MNMOS_14 S N_10 Gnd Gnd NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
69

MNMOS_1 N_4 Cin Gnd Gnd NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MNMOS_15 Cout N_11 Gnd Gnd NMOS W=360n L=180n AS=324f PS=2.52u
AD=324f PD=2.52u
MNMOS_2 N_2 A Gnd Gnd NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MPMOS_10 N_9 N_8 N_10 Vdd PMOS W=720n L=180n AS=648f PS=3.24u
AD=648f PD=3.24u
MPMOS_11 N_4 N_8 N_11 Vdd PMOS W=720n L=180n AS=648f PS=3.24u
AD=648f PD=3.24u
MPMOS_12 N_4 N_7 N_10 Vdd PMOS W=720n L=180n AS=648f PS=3.24u
AD=648f PD=3.24u
MPMOS_13 N_5 N_7 N_11 Vdd PMOS W=720n L=180n AS=648f PS=3.24u
AD=648f PD=3.24u
MPMOS_14 S N_10 Vdd Vdd PMOS W=720n L=180n AS=648f PS=3.24u AD=648f
PD=3.24u
MPMOS_15 Cout N_11 Vdd Vdd PMOS W=720n L=180n AS=648f PS=3.24u
AD=648f PD=3.24u
MPMOS_16 N_9 N_4 Vdd Vdd PMOS W=720n L=180n AS=648f PS=3.24u AD=648f
PD=3.24u
MPMOS_1 N_4 Cin Vdd Vdd PMOS W=720n L=180n AS=648f PS=3.24u AD=648f
PD=3.24u
MPMOS_2 N_2 A Vdd Vdd PMOS W=720n L=180n AS=648f PS=3.24u AD=648f
PD=3.24u
MPMOS_3 N_3 N_2 Vdd Vdd PMOS W=720n L=180n AS=648f PS=3.24u AD=648f
PD=3.24u
MPMOS_4 N_1 A Vdd Vdd PMOS W=720n L=180n AS=648f PS=3.24u AD=648f
PD=3.24u
MPMOS_5 N_5 B Vdd Vdd PMOS W=720n L=180n AS=648f PS=3.24u AD=648f
PD=3.24u
MPMOS_6 N_7 N_6 N_3 Vdd PMOS W=720n L=180n AS=648f PS=3.24u AD=648f
PD=3.24u
MPMOS_7 N_7 N_5 N_1 Vdd PMOS W=720n L=180n AS=648f PS=3.24u AD=648f
PD=3.24u
MPMOS_8 N_8 N_6 N_1 Vdd PMOS W=720n L=180n AS=648f PS=3.24u AD=648f
PD=3.24u
MPMOS_9 N_8 N_5 N_3 Vdd PMOS W=720n L=180n AS=648f PS=3.24u AD=648f
PD=3.24u
.ends
********* Simulation Settings - Parameters and SPICE Options *********
*-------- Devices: SPICE.ORDER == 0 -------Xtgc_1 N_4 N_5 N_6 N_7 N_8 Gnd Vdd tgc
70

XINV_1 A N_1 Gnd Vdd INV

XINV_2 B N_9 Gnd Vdd INV
XINV_3 Cin N_10 Gnd Vdd INV
XINV_4 N_1 N_4 Gnd Vdd INV
XINV_5 N_9 N_5 Gnd Vdd INV
XINV_6 N_10 N_6 Gnd Vdd INV
XINV_7 N_7 N_2 Gnd Vdd INV
XINV_8 N_8 N_3 Gnd Vdd INV
XINV_10 N_2 Cout Gnd Vdd INV
XINV_11 N_3 S Gnd Vdd INV
*-------- Devices: SPICE.ORDER > 0 -------VVoltageSource_1 Vdd Gnd DC 900m
VVoltageSource_2 A Gnd PULSE(0 900m 10n 500p 500p 9.5n 20n)
VVoltageSource_3 B Gnd PULSE(0 900m 20n 500p 500p 19.5n 40n)
VVoltageSource_4 Cin Gnd PULSE(0 900m 40n 500p 500p 39.5n 80n)
********* Simulation Settings - Analysis section *********
.tran 1n 80n
.power VVoltageSource_1 1n 80n
.measure tran <SS>
+ trig v(B) val=0.45 fall=1
+ targ v(S) val=0.45 rise=2
.measure tran <SSs>
+ trig v(A) val=0.45 rise=3
+ targ v(Cout) val=0.45 rise=2
********* Simulation Settings - Additional SPICE commands *********
.end
********* Simulation Settings - Parameters and SPICE Options *********
*-------- Devices: SPICE.ORDER == 0 -------Xmircm_1 N_1 N_2 N_3 N_4 N_5 Gnd Vdd mircm
XINV_1 N_6 N_2 Gnd Vdd INV
XINV_2 B N_6 Gnd Vdd INV
XINV_3 N_4 N_8 Gnd Vdd INV
XINV_4 N_8 Cout Gnd Vdd INV
XINV_5 N_5 N_9 Gnd Vdd INV
XINV_6 N_9 S Gnd Vdd INV
XINV_7 N_10 N_1 Gnd Vdd INV
XINV_8 A N_10 Gnd Vdd INV
XINV_9 N_7 N_3 Gnd Vdd INV
XINV_10 Cin N_7 Gnd Vdd INV
*-------- Devices: SPICE.ORDER > 0 -------71

VVoltageSource_5 Vdd Gnd DC 900m

VVoltageSource_6 A Gnd PULSE(0 900m 10n 500p 500p 9.5n 20n)
VVoltageSource_7 B Gnd PULSE(0 900m 20n 500p 500p 19.5n 40n)
VVoltageSource_8 Cin Gnd PULSE(0 900m 40n 500p 500p 39.5n 80n)
********* Simulation Settings - Analysis section *********
.tran 1n 80n
.power VVoltageSource_5 1n 80n
.measure tran <SS>
+ trig v(B) val=2.50 fall=1
+ targ v(S) val=2.50 rise=2
.measure tran <SSs>
+ trig v(A) val=2.50 rise=3
+ targ v(Cout) val=2.50 rise=2
********* Simulation Settings - Additional SPICE commands *********
.end

I.2 Mirror CMOS Ripple Carry Adder

* SPICE export by:

* Export time:
* Design:
* Cell:
* View:
* Export as:
* Export mode:
* Exclude empty cells:
* Exclude .model:
* Exclude .end:
* Expand paths:
* Wrap lines:
* Root path:
* Exclude global pins:
* Control property name:

S-Edit 14.11
Mon Aug 17 15:56:40 2015
mirror
Cell1
view0
top-level cell
hierarchical
yes
no
no
yes
no
C:\Users\SONY VAIO\Desktop\mirror
no
SPICE

********* Simulation Settings - General section *********

.probe
.option probev
.lib "C:\Users\SONY VAIO\Desktop\fadd180\tsmc_180nm.txt"
*************** Subcircuits *****************
.subckt mircm A B Cin Cout S Gnd Vdd
72

*-------- Devices: SPICE.ORDER > 0 -------MNMOS_1 N_3 B N_4 Gnd NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MNMOS_2 N_3 Cin N_9 Gnd NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MNMOS_3 N_4 A Gnd Gnd NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MNMOS_4 N_9 B Gnd Gnd NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MNMOS_5 N_9 A Gnd Gnd NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MNMOS_6 N_8 N_3 N_12 Gnd NMOS W=360n L=180n AS=324f PS=2.52u
AD=324f PD=2.52u
MNMOS_7 N_12 B Gnd Gnd NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MNMOS_8 N_12 A Gnd Gnd NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MNMOS_9 N_8 Cin N_15 Gnd NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MNMOS_10 N_15 B N_10 Gnd NMOS W=360n L=180n AS=324f PS=2.52u
AD=324f PD=2.52u
MNMOS_11 N_10 A Gnd Gnd NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MNMOS_12 N_15 N_13 Gnd Gnd NMOS W=360n L=180n AS=324f PS=2.52u
AD=324f PD=2.52u
MNMOS_13 N_6 A N_11 Gnd NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MNMOS_14 N_11 B Gnd Gnd NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MNMOS_15 S N_8 Gnd Gnd NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MNMOS_16 Cout N_3 Gnd Gnd NMOS W=360n L=180n AS=324f PS=2.52u
AD=324f PD=2.52u
MNMOS_17 N_13 A Gnd Gnd NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MNMOS_18 Gnd B N_13 Gnd NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MPMOS_10 S N_8 Vdd Vdd PMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MPMOS_11 N_14 A Vdd Vdd PMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MPMOS_12 Cout N_3 Vdd Vdd PMOS W=360n L=180n AS=324f PS=2.52u
AD=324f PD=2.52u
73

MPMOS_13 N_7 N_6 Vdd Vdd PMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MPMOS_14 N_16 A Vdd Vdd PMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MPMOS_15 N_7 B N_16 Vdd PMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MPMOS_16 N_8 Cin N_7 Vdd PMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MPMOS_17 N_13 B N_14 Vdd PMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MPMOS_20 N_8 N_3 N_5 Vdd PMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MPMOS_1 N_1 A Vdd Vdd PMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MPMOS_2 N_1 B Vdd Vdd PMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MPMOS_3 N_2 A Vdd Vdd PMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MPMOS_4 N_3 B N_2 Vdd PMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MPMOS_5 N_3 Cin N_1 Vdd PMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MPMOS_6 N_6 A Vdd Vdd PMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MPMOS_7 N_5 A Vdd Vdd PMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MPMOS_8 N_5 B Vdd Vdd PMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MPMOS_9 Vdd B N_6 Vdd PMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
.ends
********* Simulation Settings - General section *********
.probe
.option probev
.lib "C:\Users\SONY VAIO\Desktop\fadd180\tsmc_180nm.txt"
*************** Subcircuits *****************
.subckt tgc A B Cin Cout S Gnd Vdd
*-------- Devices: SPICE.ORDER > 0 -------MNMOS_16 N_9 N_4 Gnd Gnd NMOS W=360n L=180n AS=324f PS=2.52u
AD=324f PD=2.52u

74

MNMOS_3 N_3 N_2 Gnd Gnd NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MNMOS_4 N_1 A Gnd Gnd NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MNMOS_5 N_5 B Gnd Gnd NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MNMOS_6 N_7 N_5 N_3 0 NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MNMOS_7 N_7 N_6 N_1 0 NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MNMOS_8 N_8 N_5 N_1 0 NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MNMOS_9 N_8 N_6 N_3 0 NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MNMOS_10 N_9 N_7 N_10 0 NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MNMOS_11 N_4 N_7 N_11 0 NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MNMOS_12 N_4 N_8 N_10 0 NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MNMOS_13 N_5 N_8 N_11 0 NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MNMOS_14 S N_10 Gnd Gnd NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MNMOS_1 N_4 Cin Gnd Gnd NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MNMOS_15 Cout N_11 Gnd Gnd NMOS W=360n L=180n AS=324f PS=2.52u
AD=324f PD=2.52u
MNMOS_2 N_2 A Gnd Gnd NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MPMOS_10 N_9 N_8 N_10 Vdd PMOS W=720n L=180n AS=648f PS=3.24u
AD=648f PD=3.24u
MPMOS_11 N_4 N_8 N_11 Vdd PMOS W=720n L=180n AS=648f PS=3.24u
AD=648f PD=3.24u
MPMOS_12 N_4 N_7 N_10 Vdd PMOS W=720n L=180n AS=648f PS=3.24u
AD=648f PD=3.24u
MPMOS_13 N_5 N_7 N_11 Vdd PMOS W=720n L=180n AS=648f PS=3.24u
AD=648f PD=3.24u
MPMOS_14 S N_10 Vdd Vdd PMOS W=720n L=180n AS=648f PS=3.24u AD=648f
PD=3.24u
MPMOS_15 Cout N_11 Vdd Vdd PMOS W=720n L=180n AS=648f PS=3.24u
AD=648f PD=3.24u
MPMOS_16 N_9 N_4 Vdd Vdd PMOS W=720n L=180n AS=648f PS=3.24u AD=648f
PD=3.24u
75

MPMOS_1
PD=3.24u
MPMOS_2
PD=3.24u
MPMOS_3
PD=3.24u
MPMOS_4
PD=3.24u
MPMOS_5
PD=3.24u
MPMOS_6
PD=3.24u
MPMOS_7
PD=3.24u
MPMOS_8
PD=3.24u
MPMOS_9
PD=3.24u
.ends

N_4 Cin Vdd Vdd PMOS W=720n L=180n AS=648f PS=3.24u AD=648f
N_2 A Vdd Vdd PMOS W=720n L=180n AS=648f PS=3.24u AD=648f
N_3 N_2 Vdd Vdd PMOS W=720n L=180n AS=648f PS=3.24u AD=648f
N_1 A Vdd Vdd PMOS W=720n L=180n AS=648f PS=3.24u AD=648f
N_5 B Vdd Vdd PMOS W=720n L=180n AS=648f PS=3.24u AD=648f
N_7 N_6 N_3 Vdd PMOS W=720n L=180n AS=648f PS=3.24u AD=648f
N_7 N_5 N_1 Vdd PMOS W=720n L=180n AS=648f PS=3.24u AD=648f
N_8 N_6 N_1 Vdd PMOS W=720n L=180n AS=648f PS=3.24u AD=648f
N_8 N_5 N_3 Vdd PMOS W=720n L=180n AS=648f PS=3.24u AD=648f

********* Simulation Settings - Parameters and SPICE Options *********

*-------- Devices: SPICE.ORDER == 0 -------Xtgc_3 A B N_3 N_2 S2 Gnd Vdd tgc
Xtgc_4 A B N_2 Cout S3 Gnd Vdd tgc
Xtgc_1 A B Cin N_1 S0 Gnd Vdd tgc
Xtgc_2 A B N_1 N_3 S1 Gnd Vdd tgc
*-------- Devices: SPICE.ORDER > 0 -------VVoltageSource_1 Vdd Gnd DC 900m
VVoltageSource_3 B Gnd PULSE(0 900m 20n 500p 500p 19.5n 40n)
VVoltageSource_4 Cin Gnd PULSE(0 900m 40n 500p 500p 39.5n 80n)
VVoltageSource_2 A Gnd PULSE(0 900m 10n 500p 500p 9.5n 20n)
********* Simulation Settings - Analysis section *********
.tran 1n 80n
.power VVoltageSource_1 1n 80n
.measure tran <SS>
+ trig v(Cin) val=0.45 rise=1
+ targ v(S0) val=0.45 rise=2
.measure tran <SS1>
+ trig v(N_1) val=0.45 fall=1
+ targ v(S1) val=0.45 fall=1
.measure tran <SS2>
76

+ trig v(N_3) val=0.45 fall=1

+ targ v(S2) val=0.45 fall=1
.measure tran <SS3>
+ trig v(N_2) val=0.45 rise=2
+ targ v(S3) val=0.45 fall=2
********* Simulation Settings - Additional SPICE commands *********
.end
********* Simulation Settings - Parameters and SPICE Options *********
*-------- Devices: SPICE.ORDER == 0 -------Xmircm_3 A B N_2 N_3 S2 Gnd Vdd mircm
Xmircm_4 A B N_3 Cout S3 Gnd Vdd mircm
Xmircm_1 A B Cin N_1 S0 Gnd Vdd mircm
Xmircm_2 A B N_1 N_2 S1 Gnd Vdd mircm
*-------- Devices: SPICE.ORDER > 0 -------VVoltageSource_5 Vdd Gnd DC 900m
VVoltageSource_6 A Gnd PULSE(0 900m 10n 500p 500p 9.5n 20n)
VVoltageSource_7 B Gnd PULSE(0 900m 20n 500p 500p 19.5n 40n)
VVoltageSource_8 Cin Gnd PULSE(0 900m 40n 500p 500p 39.5n 80n)
********* Simulation Settings - Analysis section *********
.tran 1n 80n
.power VVoltageSource_5 1n 80n
.measure tran <SS>
+ trig v(A) val=2.50 rise=4
+ targ v(S0) val=2.50 rise=3
.measure tran <SS1>
+ trig v(N_1) val=2.50 rise=2
+ targ v(S1) val=2.50 fall=2
.measure tran <SS2>
+ trig v(N_2) val=2.50 fall=1
+ targ v(S2) val=2.50 fall=1
.measure tran <SS>
+ trig v(N_3) val=2.50 rise=2
+ targ v(S3) val=2.50 fall=2
********* Simulation Settings - Additional SPICE commands *********
.end

77

APPENDIX II
II.1 MCML Full Adder

* SPICE export by:

* Export time:
* Design:
* Cell:
* View:
* Export as:
* Export mode:
* Exclude empty cells:
* Exclude .model:
* Exclude .end:
* Expand paths:
* Wrap lines:
* Root path:
* Exclude global pins:
* Control property name:

S-Edit 14.11
Mon Aug 17 16:34:07 2015
fulladder_trapti
proposed_mcml_Fig
view0
top-level cell
hierarchical
yes
no
no
yes
no
C:\Users\SONY VAIO\Desktop\fulladder_trapti
no
SPICE

********* Simulation Settings - General section *********

.probe
.option probev
.option probei
.include "C:\Users\SONY VAIO\Desktop\fadd180\tsmc_180nm.txt"
********* Simulation Settings - Parameters and SPICE Options *********
*-------- Devices: SPICE.ORDER > 0 -------MNMOS_3 N_5 B_b N_9 0 NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MNMOS_17 N_11 B_b N_12 0 NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MNMOS_4 N_9 A N_10 0 NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MNMOS_18 Sum Cin N_5 0 NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u

78

MNMOS_5 N_11 B N_9 0 NMOS W=360n L=180n AS=324f PS=2.52u AD=324f

PD=2.52u
MNMOS_19 Sum Cin_b N_11 0 NMOS W=360n L=180n AS=324f PS=2.52u
AD=324f PD=2.52u
MNMOS_6 N_4 vb Gnd 0 NMOS W=560n L=180n AS=504f PS=2.92u AD=504f
PD=2.92u
MNMOS_7 N_1 Cin N_8 0 NMOS W=180n L=180n AS=162f PS=2.16u AD=162f
PD=2.16u
MNMOS_8 N_8 A N_7 0 NMOS W=180n L=180n AS=162f PS=2.16u AD=162f
PD=2.16u
MNMOS_9 N_7 B Gnd 0 NMOS W=180n L=180n AS=162f PS=2.16u AD=162f
PD=2.16u
MNMOS_20 Sbar Cin N_11 0 NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MNMOS_21 Sbar Cin_b N_5 0 NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MNMOS_10 N_1 Sbar N_4 0 NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MNMOS_11 N_10 vb Gnd 0 NMOS W=560n L=180n AS=504f PS=2.92u AD=504f
PD=2.92u
MNMOS_12 Cout N_1 Gnd 0 NMOS W=180n L=180n AS=162f PS=2.16u AD=162f
PD=2.16u
MNMOS_1 N_12 A_b N_10 0 NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MNMOS_2 N_5 B N_12 0 NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MPMOS_3 N_6 A N_3 Vdd PMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MPMOS_4 Sum vb_b Vdd Vdd PMOS W=180n L=180n AS=162f PS=2.16u AD=162f
PD=2.16u
MPMOS_5 Sbar vb_b Vdd Vdd PMOS W=180n L=180n AS=162f PS=2.16u AD=162f
PD=2.16u
MPMOS_6 N_1 B N_6 Vdd PMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MPMOS_7 N_3 Cin Vdd Vdd PMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MPMOS_8 N_1 vb_b Vdd Vdd PMOS W=180n L=180n AS=162f PS=2.16u AD=162f
PD=2.16u
MPMOS_9 Cout N_1 Vdd Vdd PMOS W=560n L=180n AS=504f PS=2.92u AD=504f
PD=2.92u
VVoltageSource_11 Vdd Gnd DC 900m
VVoltageSource_12 Cin Gnd PULSE(0 900m 10n 500p 500p 9.5n 20n)
VVoltageSource_13 B Gnd PULSE(0 900m 20n 500p 500p 19.5n 40n)
79

VVoltageSource_14 A Gnd PULSE(0 900m 40n 500p 500p 39.5n 80n)

VVoltageSource_15 vb_b Gnd PULSE(900m 0 0 200p 200p 500p 10n)
VVoltageSource_16 Cin_b Gnd PULSE(900m 0 10n 500p 500p 9.5n 20n)
VVoltageSource_17 A_b Gnd PULSE(900m 0 40n 500p 500p 39.5n 80n)
VVoltageSource_18 B_b Gnd PULSE(900m 0 20n 500p 500p 19.5n 40n)
VVoltageSource_19 vb Gnd PULSE(0 900m 0 500p 500p 500p 10n)
.PRINT TRAN V(vb)
.PRINT TRAN V(Cin)
.PRINT TRAN V(B)
.PRINT TRAN V(A)
********* Simulation Settings - Analysis section *********
.tran 1n 80n
.power VVoltageSource_1 1n 80n
.measure tran <SS>
+ trig v(B) val=0.45 fall=1
+ targ v(S) val=0.45 rise=2
.measure tran <SSs>
+ trig v(Cin) val=0.45 rise=3
+ targ v(Cout) val=0.45 rise=2
********* Simulation Settings - Additional SPICE commands *********
.end

II.2 mirror based Ripple Carry Adder

* SPICE export by:

* Export time:
* Design:
* Cell:
* View:
* Export as:
* Export mode:
* Exclude empty cells:
* Exclude .model:
* Exclude .end:
* Expand paths:
* Wrap lines:
* Root path:
* Exclude global pins:
* Control property name:

S-Edit 14.11
Mon Aug 17 16:38:44 2015
fulladder_trapti
rca
view0
top-level cell
hierarchical
yes
no
no
yes
no
C:\Users\SONY VAIO\Desktop\fulladder_trapti
no
SPICE
80

********* Simulation Settings - General section *********

.probe
.option probev
.option probei
.include "C:\Users\SONY VAIO\Desktop\fadd180\tsmc_180nm.txt"
*************** Subcircuits *****************
.subckt buffer buff in inv Gnd vdd_buff
*-------- Devices: SPICE.ORDER > 0 -------MNMOS_12 inv in Gnd 0 NMOS W=180n L=180n AS=162f PS=2.16u AD=162f
PD=2.16u
MNMOS_1 buff inv Gnd 0 NMOS W=180n L=180n AS=162f PS=2.16u AD=162f
PD=2.16u
MPMOS_1 buff inv vdd_buff Vdd PMOS W=560n L=180n AS=504f PS=2.92u
AD=504f PD=2.92u
MPMOS_9 inv in vdd_buff Vdd PMOS W=560n L=180n AS=504f PS=2.92u AD=504f
PD=2.92u
.ends
.subckt buffer2 buff in Gnd vdd_buff
*-------- Devices: SPICE.ORDER > 0 -------MNMOS_12 N_1 in Gnd 0 NMOS W=180n L=180n AS=162f
PD=2.16u
MNMOS_1 buff N_1 Gnd 0 NMOS W=180n L=180n AS=162f
PD=2.16u
MPMOS_1 buff N_1 vdd_buff Vdd PMOS W=560n L=180n
AD=504f PD=2.92u
MPMOS_9 N_1 in vdd_buff Vdd PMOS W=560n L=180n
AD=504f PD=2.92u
.ends

PS=2.16u AD=162f
PS=2.16u AD=162f
AS=504f PS=2.92u
AS=504f PS=2.92u

.subckt proposed_mcml_Fig A A_b B B_b Cin Cin_b Cout Sum vb vb_b Gnd Vdd
*-------- Devices: SPICE.ORDER > 0 -------MNMOS_3 N_5 B_b N_9 0 NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MNMOS_17 N_11 B_b N_12 0 NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MNMOS_4 N_9 A N_10 0 NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MNMOS_18 Sum Cin N_5 0 NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MNMOS_5 N_11 B N_9 0 NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MNMOS_19 Sum Cin_b N_11 0 NMOS W=360n L=180n AS=324f PS=2.52u
AD=324f PD=2.52u
81

MNMOS_6 N_4 vb Gnd 0 NMOS W=560n L=180n AS=504f PS=2.92u AD=504f

PD=2.92u
MNMOS_7 N_1 Cin N_8 0 NMOS W=180n L=180n AS=162f PS=2.16u AD=162f
PD=2.16u
MNMOS_8 N_8 A N_7 0 NMOS W=180n L=180n AS=162f PS=2.16u AD=162f
PD=2.16u
MNMOS_9 N_7 B Gnd 0 NMOS W=180n L=180n AS=162f PS=2.16u AD=162f
PD=2.16u
MNMOS_20 Sbar Cin N_11 0 NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MNMOS_21 Sbar Cin_b N_5 0 NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MNMOS_10 N_1 Sbar N_4 0 NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MNMOS_11 N_10 vb Gnd 0 NMOS W=560n L=180n AS=504f PS=2.92u AD=504f
PD=2.92u
MNMOS_12 Cout N_1 Gnd 0 NMOS W=180n L=180n AS=162f PS=2.16u AD=162f
PD=2.16u
MNMOS_1 N_12 A_b N_10 0 NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MNMOS_2 N_5 B N_12 0 NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MPMOS_3 N_6 A N_3 Vdd PMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MPMOS_4 Sum vb_b Vdd Vdd PMOS W=180n L=180n AS=162f PS=2.16u AD=162f
PD=2.16u
MPMOS_5 Sbar vb_b Vdd Vdd PMOS W=180n L=180n AS=162f PS=2.16u AD=162f
PD=2.16u
MPMOS_6 N_1 B N_6 Vdd PMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MPMOS_7 N_3 Cin Vdd Vdd PMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MPMOS_8 N_1 vb_b Vdd Vdd PMOS W=180n L=180n AS=162f PS=2.16u AD=162f
PD=2.16u
MPMOS_9 Cout N_1 Vdd Vdd PMOS W=560n L=180n AS=504f PS=2.92u AD=504f
PD=2.92u
.ends

********* Simulation Settings - Parameters and SPICE Options *********

*-------- Devices: SPICE.ORDER == 0 -------Xbuffer_3 N_12 N_11 N_13 Gnd vdd_buff buffer

82

Xproposed_mcml_Fig_1
proposed_mcml_Fig
Xproposed_mcml_Fig_2
proposed_mcml_Fig
Xproposed_mcml_Fig_3
proposed_mcml_Fig
Xproposed_mcml_Fig_4
proposed_mcml_Fig

A A_b B B_b Cin Cin_b N_5 N_1 vb vb_b Gnd Vdd

A A_b B B_b N_6 N_7 N_8 N_2 vb vb_b Gnd Vdd
A A_b B B_b N_9 N_10 N_11 N_3 vb vb_b Gnd Vdd
A A_b B B_b N_12 N_13 Cout N_4 vb vb_b Gnd Vdd

Xbuffer2_1 S0 N_1 Gnd vdd_buff buffer2

Xbuffer2_2 S1 N_2 Gnd vdd_buff buffer2
Xbuffer2_3 S2 N_3 Gnd vdd_buff buffer2
Xbuffer2_4 S3 N_4 Gnd vdd_buff buffer2
Xbuffer_1 N_6 N_5 N_7 Gnd vdd_buff buffer
Xbuffer_2 N_9 N_8 N_10 Gnd vdd_buff buffer
*-------- Devices: SPICE.ORDER > 0 -------VVoltageSource_10 vdd_buff Gnd DC 900m
VVoltageSource_11 Vdd Gnd DC 900m
VVoltageSource_12 Cin Gnd PULSE(0 900m 10n 500p 500p 9.5n 20n)
VVoltageSource_13 B Gnd PULSE(0 900m 20n 500p 500p 19.5n 40n)
VVoltageSource_14 A Gnd PULSE(0 900m 40n 500p 500p 39.5n 80n)
VVoltageSource_15 vb_b Gnd PULSE(900m 0 0 200p 200p 500p 10n)
VVoltageSource_16 Cin_b Gnd PULSE(900m 0 10n 500p 500p 9.5n 20n)
VVoltageSource_17 A_b Gnd PULSE(900m 0 40n 500p 500p 39.5n 80n)
VVoltageSource_18 B_b Gnd PULSE(900m 0 20n 500p 500p 19.5n 40n)
VVoltageSource_19 vb Gnd PULSE(0 900m 0 500p 500p 500p 10n)
.PRINT TRAN V(vb)
.PRINT TRAN V(Cin)
.PRINT TRAN V(B)
.PRINT TRAN V(A)
.PRINT TRAN V(S0)
.PRINT TRAN V(S1)
.PRINT TRAN V(S2)
.PRINT TRAN V(S3)
.PRINT TRAN V(Cout)
********* Simulation Settings - Analysis section *********
.tran 1n 80n
.power VVoltageSource_11 1n 80n
.measure tran <SS>
+ trig v(Cin) val=2.50 rise=4
+ targ v(S0) val=2.50 rise=3
83

.measure tran <SS1>

+ trig v(N_6) val=2.50 rise=2
+ targ v(S1) val=2.50 fall=2
.measure tran <SS2>
+ trig v(N_9) val=2.50 rise=2
+ targ v(S2) val=2.50 fall=1
.measure tran <SS3>
+ trig v(B) val=2.50 rise=2
+ targ v(S3) val=2.50 rise=2
********* Simulation Settings - Additional SPICE commands *********
.end

II.3 MCML Full Adder (for 1V)

* SPICE export by:

* Export time:
* Design:
* Cell:
* View:
* Export as:
* Export mode:
* Exclude empty cells:
* Exclude .model:
* Exclude .end:
* Expand paths:
* Wrap lines:
* Root path:
* Exclude global pins:
* Control property name:

S-Edit 14.11
Mon Aug 17 16:34:07 2015
fulladder_trapti
proposed_mcml_Fig
view0
top-level cell
hierarchical
yes
no
no
yes
no
C:\Users\SONY VAIO\Desktop\fulladder_trapti
no
SPICE

********* Simulation Settings - General section *********

.probe
.option probev
.option probei
.include "C:\Users\SONY VAIO\Desktop\fadd180\tsmc_180nm.txt"
********* Simulation Settings - Parameters and SPICE Options *********
*-------- Devices: SPICE.ORDER > 0 --------

84

MNMOS_3 N_5 B_b N_9 0 NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MNMOS_17 N_11 B_b N_12 0 NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MNMOS_4 N_9 A N_10 0 NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MNMOS_18 Sum Cin N_5 0 NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MNMOS_5 N_11 B N_9 0 NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MNMOS_19 Sum Cin_b N_11 0 NMOS W=360n L=180n AS=324f PS=2.52u
AD=324f PD=2.52u
MNMOS_6 N_4 vb Gnd 0 NMOS W=560n L=180n AS=504f PS=2.92u AD=504f
PD=2.92u
MNMOS_7 N_1 Cin N_8 0 NMOS W=180n L=180n AS=162f PS=2.16u AD=162f
PD=2.16u
MNMOS_8 N_8 A N_7 0 NMOS W=180n L=180n AS=162f PS=2.16u AD=162f
PD=2.16u
MNMOS_9 N_7 B Gnd 0 NMOS W=180n L=180n AS=162f PS=2.16u AD=162f
PD=2.16u
MNMOS_20 Sbar Cin N_11 0 NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MNMOS_21 Sbar Cin_b N_5 0 NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MNMOS_10 N_1 Sbar N_4 0 NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MNMOS_11 N_10 vb Gnd 0 NMOS W=560n L=180n AS=504f PS=2.92u AD=504f
PD=2.92u
MNMOS_12 Cout N_1 Gnd 0 NMOS W=180n L=180n AS=162f PS=2.16u AD=162f
PD=2.16u
MNMOS_1 N_12 A_b N_10 0 NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MNMOS_2 N_5 B N_12 0 NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MPMOS_3 N_6 A N_3 Vdd PMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MPMOS_4 Sum vb_b Vdd Vdd PMOS W=180n L=180n AS=162f PS=2.16u AD=162f
PD=2.16u
MPMOS_5 Sbar vb_b Vdd Vdd PMOS W=180n L=180n AS=162f PS=2.16u AD=162f
PD=2.16u
MPMOS_6 N_1 B N_6 Vdd PMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MPMOS_7 N_3 Cin Vdd Vdd PMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
85

MPMOS_8 N_1 vb_b Vdd Vdd PMOS W=180n L=180n AS=162f PS=2.16u AD=162f
PD=2.16u
MPMOS_9 Cout N_1 Vdd Vdd PMOS W=560n L=180n AS=504f PS=2.92u AD=504f
PD=2.92u
VVoltageSource_11 Vdd Gnd DC 900m
VVoltageSource_12 Cin Gnd PULSE(0 900m 10n 500p 500p 9.5n 20n)
VVoltageSource_13 B Gnd PULSE(0 900m 20n 500p 500p 19.5n 40n)
VVoltageSource_14 A Gnd PULSE(0 900m 40n 500p 500p 39.5n 80n)
VVoltageSource_15 vb_b Gnd PULSE(900m 0 0 200p 200p 500p 10n)
VVoltageSource_16 Cin_b Gnd PULSE(900m 0 10n 500p 500p 9.5n 20n)
VVoltageSource_17 A_b Gnd PULSE(900m 0 40n 500p 500p 39.5n 80n)
VVoltageSource_18 B_b Gnd PULSE(900m 0 20n 500p 500p 19.5n 40n)
VVoltageSource_19 vb Gnd PULSE(0 900m 0 500p 500p 500p 10n)
.PRINT TRAN V(vb)
.PRINT TRAN V(Cin)
.PRINT TRAN V(B)
.PRINT TRAN V(A)
********* Simulation Settings - Analysis section *********
.tran 1n 80n
.power VVoltageSource_1 1n 80n
.measure tran <SS>
+ trig v(B) val=0.45 fall=1
+ targ v(S) val=0.45 rise=2
.measure tran <SSs>
+ trig v(Cin) val=0.45 rise=3
+ targ v(Cout) val=0.45 rise=2
********* Simulation Settings - Additional SPICE commands *********
.end

II.4 Mirror Based Ripple Carry Adder (for 1V)

* SPICE export by:

* Export time:
* Design:
* Cell:
* View:
* Export as:
* Export mode:

S-Edit 14.11
Mon Aug 17 16:38:44 2015
fulladder_trapti
rca
view0
top-level cell
hierarchical
86

* Exclude empty cells:

* Exclude .model:
* Exclude .end:
* Expand paths:
* Wrap lines:
* Root path:
* Exclude global pins:
* Control property name:

yes
no
no
yes
no
C:\Users\SONY VAIO\Desktop\fulladder_trapti
no
SPICE

********* Simulation Settings - General section *********

.probe
.option probev
.option probei
.include "C:\Users\SONY VAIO\Desktop\fadd180\tsmc_180nm.txt"
*************** Subcircuits *****************
.subckt buffer buff in inv Gnd vdd_buff
*-------- Devices: SPICE.ORDER > 0 -------MNMOS_12 inv in Gnd 0 NMOS W=180n L=180n AS=162f PS=2.16u AD=162f
PD=2.16u
MNMOS_1 buff inv Gnd 0 NMOS W=180n L=180n AS=162f PS=2.16u AD=162f
PD=2.16u
MPMOS_1 buff inv vdd_buff Vdd PMOS W=560n L=180n AS=504f PS=2.92u
AD=504f PD=2.92u
MPMOS_9 inv in vdd_buff Vdd PMOS W=560n L=180n AS=504f PS=2.92u AD=504f
PD=2.92u
.ends
.subckt buffer2 buff in Gnd vdd_buff
*-------- Devices: SPICE.ORDER > 0 -------MNMOS_12 N_1 in Gnd 0 NMOS W=180n L=180n AS=162f
PD=2.16u
MNMOS_1 buff N_1 Gnd 0 NMOS W=180n L=180n AS=162f
PD=2.16u
MPMOS_1 buff N_1 vdd_buff Vdd PMOS W=560n L=180n
AD=504f PD=2.92u
MPMOS_9 N_1 in vdd_buff Vdd PMOS W=560n L=180n
AD=504f PD=2.92u
.ends

PS=2.16u AD=162f
PS=2.16u AD=162f
AS=504f PS=2.92u
AS=504f PS=2.92u

.subckt proposed_mcml_Fig A A_b B B_b Cin Cin_b Cout Sum vb vb_b Gnd Vdd
*-------- Devices: SPICE.ORDER > 0 -------MNMOS_3 N_5 B_b N_9 0 NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u

87

MNMOS_17 N_11 B_b N_12 0 NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MNMOS_4 N_9 A N_10 0 NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MNMOS_18 Sum Cin N_5 0 NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MNMOS_5 N_11 B N_9 0 NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MNMOS_19 Sum Cin_b N_11 0 NMOS W=360n L=180n AS=324f PS=2.52u
AD=324f PD=2.52u
MNMOS_6 N_4 vb Gnd 0 NMOS W=560n L=180n AS=504f PS=2.92u AD=504f
PD=2.92u
MNMOS_7 N_1 Cin N_8 0 NMOS W=180n L=180n AS=162f PS=2.16u AD=162f
PD=2.16u
MNMOS_8 N_8 A N_7 0 NMOS W=180n L=180n AS=162f PS=2.16u AD=162f
PD=2.16u
MNMOS_9 N_7 B Gnd 0 NMOS W=180n L=180n AS=162f PS=2.16u AD=162f
PD=2.16u
MNMOS_20 Sbar Cin N_11 0 NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MNMOS_21 Sbar Cin_b N_5 0 NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MNMOS_10 N_1 Sbar N_4 0 NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MNMOS_11 N_10 vb Gnd 0 NMOS W=560n L=180n AS=504f PS=2.92u AD=504f
PD=2.92u
MNMOS_12 Cout N_1 Gnd 0 NMOS W=180n L=180n AS=162f PS=2.16u AD=162f
PD=2.16u
MNMOS_1 N_12 A_b N_10 0 NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MNMOS_2 N_5 B N_12 0 NMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MPMOS_3 N_6 A N_3 Vdd PMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MPMOS_4 Sum vb_b Vdd Vdd PMOS W=180n L=180n AS=162f PS=2.16u AD=162f
PD=2.16u
MPMOS_5 Sbar vb_b Vdd Vdd PMOS W=180n L=180n AS=162f PS=2.16u AD=162f
PD=2.16u
MPMOS_6 N_1 B N_6 Vdd PMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MPMOS_7 N_3 Cin Vdd Vdd PMOS W=360n L=180n AS=324f PS=2.52u AD=324f
PD=2.52u
MPMOS_8 N_1 vb_b Vdd Vdd PMOS W=180n L=180n AS=162f PS=2.16u AD=162f
PD=2.16u
88

MPMOS_9 Cout N_1 Vdd Vdd PMOS W=560n L=180n AS=504f PS=2.92u AD=504f
PD=2.92u
.ends

********* Simulation Settings - Parameters and SPICE Options *********

*-------- Devices: SPICE.ORDER == 0 -------Xbuffer_3 N_12 N_11 N_13 Gnd vdd_buff buffer
Xproposed_mcml_Fig_1
proposed_mcml_Fig
Xproposed_mcml_Fig_2
proposed_mcml_Fig
Xproposed_mcml_Fig_3
proposed_mcml_Fig
Xproposed_mcml_Fig_4
proposed_mcml_Fig

A A_b B B_b Cin Cin_b N_5 N_1 vb vb_b Gnd Vdd

A A_b B B_b N_6 N_7 N_8 N_2 vb vb_b Gnd Vdd
A A_b B B_b N_9 N_10 N_11 N_3 vb vb_b Gnd Vdd
A A_b B B_b N_12 N_13 Cout N_4 vb vb_b Gnd Vdd

Xbuffer2_1 S0 N_1 Gnd vdd_buff buffer2

Xbuffer2_2 S1 N_2 Gnd vdd_buff buffer2
Xbuffer2_3 S2 N_3 Gnd vdd_buff buffer2
Xbuffer2_4 S3 N_4 Gnd vdd_buff buffer2
Xbuffer_1 N_6 N_5 N_7 Gnd vdd_buff buffer
Xbuffer_2 N_9 N_8 N_10 Gnd vdd_buff buffer
*-------- Devices: SPICE.ORDER > 0 -------VVoltageSource_10 vdd_buff Gnd DC 900m
VVoltageSource_11 Vdd Gnd DC 900m
VVoltageSource_12 Cin Gnd PULSE(0 900m 10n 500p 500p 9.5n 20n)
VVoltageSource_13 B Gnd PULSE(0 900m 20n 500p 500p 19.5n 40n)
VVoltageSource_14 A Gnd PULSE(0 900m 40n 500p 500p 39.5n 80n)
VVoltageSource_15 vb_b Gnd PULSE(900m 0 0 200p 200p 500p 10n)
VVoltageSource_16 Cin_b Gnd PULSE(900m 0 10n 500p 500p 9.5n 20n)
VVoltageSource_17 A_b Gnd PULSE(900m 0 40n 500p 500p 39.5n 80n)
VVoltageSource_18 B_b Gnd PULSE(900m 0 20n 500p 500p 19.5n 40n)
VVoltageSource_19 vb Gnd PULSE(0 900m 0 500p 500p 500p 10n)
.PRINT TRAN V(vb)
.PRINT TRAN V(Cin)
.PRINT TRAN V(B)
.PRINT TRAN V(A)
.PRINT TRAN V(S0)
.PRINT TRAN V(S1)
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.PRINT TRAN V(S2)

.PRINT TRAN V(S3)
.PRINT TRAN V(Cout)
********* Simulation Settings - Analysis section *********
.tran 1n 80n
.power VVoltageSource_11 1n 80n
.measure tran <SS>
+ trig v(Cin) val=0.45 rise=4
+ targ v(S0) val=0.45 rise=3
.measure tran <SS1>
+ trig v(N_6) val=0.45 rise=2
+ targ v(S1) val=0.45 fall=2
.measure tran <SS2>
+ trig v(N_9) val=0.45 rise=2
+ targ v(S2) val=0.45 fall=1
.measure tran <SS3>
+ trig v(B) val=0.45 rise=2
+ targ v(S3) val=0.45 rise=2
********* Simulation Settings - Additional SPICE commands *********
.end

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LIST OF PUBLICATIONS
[1] Trapti Mittal, Ms Uma Sharma; July 2014, A Review Paper on Power Reduction
Technique for Full Adder , International Journal of Advanced Technology in
Engineering and Science (ISSN 2348-7550), Vol 02, Issue 06, pp 402-409.
[2] Trapti Mittal, Ms Uma Sharma; October, 2015, Analysis of Full Adder for Power
Efficient Circuit Design, International Journal of Advance Research in Science &
Engineering (ISSN 2319-8354), Volume 04, Issue 10, pp 26-32.

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CARRICULAM VITAE

Trapti has received her B.Tech degree in Electronics and Communication

Engineering from Aligarh College of Engineering and Technology, Aligarh in June
2012 and pursuing her M.Tech degree in VLSI Design from Ajay Kumar Garg
Engineering College, Ghaziabad from September 2012. Her area of research work is to
introduce an analysis of full adder for power efficient circuit design.

During her graduation, she worked on the project named as GSM Based
Electronic Voting Machine. The objective of the project is to cast a vote using mobile
phone via GSM technology. For designing a project, the microprocessor chip address
lines has been divided according to the number of candidates and vote is casted by
according to their number and the vote recorded in the database.

During her research period, she has published two research papers
successfully. First paper publishes in International Journal of Advanced Technology in
Engineering and Science (IJTES) is a review paper on various full adder designing
methods and their comparison. The second published paper is about the proposed work
and its results of full adder design and RCA design published in International Journal of
Advance Research in Science & Engineering (IJARSE).

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