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    Unsigned Divider RTL Model

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    gadha
    The document describes the algorithm for 8-bit binary division. It involves: 1. Setting the quotient and remainder to 0 initially. 2. Shifting and comparing the dividend and divisor from left to right. 3. If the portion of the dividend is greater than the divisor, subtracting the divisor and adding 1 to the quotient. Otherwise adding 0 to the quotient. 4. Shifting the divisor right and repeating the process until the dividend is less than the divisor. The final quotient and remainder are then output.

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    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd

    Unsigned Divider RTL Model

    Uploaded by

    gadha
    254 views10 pages
    The document describes the algorithm for 8-bit binary division. It involves: 1. Setting the quotient and remainder to 0 initially. 2. Shifting and comparing the dividend and divisor from left to right. 3. If the portion of the dividend is greater than the divisor, subtracting the divisor and adding 1 to the quotient. Otherwise adding 0 to the quotient. 4. Shifting the divisor right and repeating the process until the dividend is less than the divisor. The final quotient and remainder are then output.

    Original Description:

    RTL VHDL code for 16 bit unsigned divider using long division

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    © © All Rights Reserved

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    The document describes the algorithm for 8-bit binary division. It involves: 1. Setting the quotient and remainder to 0 initially. 2. Shifting and comparing the dividend and divisor from left to right. 3. If the portion of the dividend is greater than the divisor, subtracting the divisor and adding 1 to the quotient. Otherwise adding 0 to the quotient. 4. Shifting the divisor right and repeating the process until the dividend is less than the divisor. The final quotient and remainder are then output.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    254 views10 pages

    Unsigned Divider RTL Model

    Uploaded by

    gadha
    The document describes the algorithm for 8-bit binary division. It involves: 1. Setting the quotient and remainder to 0 initially. 2. Shifting and comparing the dividend and divisor from left to right. 3. If the portion of the dividend is greater than the divisor, subtracting the divisor and adding 1 to the quotient. Otherwise adding 0 to the quotient. 4. Shifting the divisor right and repeating the process until the dividend is less than the divisor. The final quotient and remainder are then output.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 10

    Unsigned Divider

    Assignment 6 : EE224

    Name :- Yogesh Mahajan

    Roll No. :- 14D070022

    ----------------------------------------------------------------------------------------------------------------------------------------------------------------

    Set quotient to 0
    Align leftmost digits in dividend and divisor
    Repeat
    o If that portion of the dividend above the divisor is greater than or equal to the
    divisor
    Then subtract divisor from that portion of the dividend and
    Concatenate 1 to the right hand end of the quotient
    Else concatenate 0 to the right hand end of the quotient
    o Shift the divisor one place right
    Until dividend is less than the divisor
    quotient is correct, dividend is remainder
    STOP

    Division by 0 gives quotient 11111111, so 11111111 is considered as dont care state.

    rest : if(tsrt == '1') then


    init q,r = 0; areg = a; breg = b;count = 8
    goto update
    end if
    update : if(count == '0') then
    goto doneState
    else
    areg =<< 1; qreg =<< 1; rreg=<< 1; count =-1;
    goto comp
    end if
    comp : compare areg and breg
    goto sub
    sub : if(areg >= breg) then
    areg = areg - breg;
    end if
    goto update
    doneState : out breg; out done;
    goto rest

    --16 Bit Divider RTL Model


    ---Control Path-----------------------------------------------library ieee;
    use ieee.std_logic_1164.all;
    use std.textio.all;
    use ieee.numeric_std.ALL;
    entity controlPath is
    port (clk,rst : in std_logic;
    start : in std_logic;
    done : out std_logic;
    T : out std_logic_vector(4 downto 0);
    S : in std_logic_vector(1 downto 0));
    end entity;
    architecture behave of controlPath is
    type FSMstate is (rest,update,comp,sub,doneState);
    signal fsm_state : FSMstate;
    begin
    process(fsm_state,start,clk,rst,S)
    variable next_state : FSMstate;
    variable Tvar : std_logic_vector(4 downto 0);
    variable done_var : std_logic;
    begin
    if(clk'event and (clk = '1')) then
    if(rst = '1') then
    fsm_state <= rest;
    else
    fsm_state <= next_state;
    end if;
    end if;
    Tvar := (others => '0');
    done_var := '0';
    next_state := fsm_state;
    case fsm_state is
    when rest =>
    --if(start = '1') then
    next_state := update;
    Tvar(0) := '1';
    end if;

    setup all registers

    when update =>


    --- shift registers & checking shifts
    if(S(1) = '1') then -- 8 shifts done
    Tvar(4) := '1';
    -- update output in next state
    next_state := doneState;
    else
    Tvar(1) := '1';
    next_state := comp;
    end if;
    when comp =>
    -- compare if B < regD
    Tvar(2) := '1';
    next_state := sub;
    when sub =>
    next_state := update;
    if(S(0) = '1') then
    -- subtractions when B <= regD
    Tvar(3) := '1';
    end if;
    when doneState =>
    done_var := '1';
    next_state := rest;
    end case;
    T <= Tvar;
    done <= done_var;
    end process;
    end behave;
    ---------------------------------------------------------------

    --Data Path --------------------------------------------------library ieee;


    use ieee.std_logic_1164.all;
    use std.textio.all;
    use ieee.numeric_std.ALL;
    entity dataPath is
    port( clk,rst : in std_logic;
    t : in std_logic_vector(4 downto 0);
    s : out std_logic_vector(1 downto 0);
    a,b : in std_logic_vector(7 downto 0);
    quotient,remainder : out std_logic_vector(7 downto 0));
    end entity;
    architecture blahblah of dataPath is
    component mux21 is
    port ( A,B,S : in std_logic;
    O : out std_logic);
    end component;
    component shiftCount8 is

    port (A: in std_logic_vector(3 downto 0);


    B: out std_logic_vector(3 downto 0));
    end component;
    component sub8bit is
    port( A,B : in std_logic_vector(7 downto 0);
    sub : out std_logic_vector(7 downto 0));
    end component;
    component cmp8 is
    port (A,B : in std_logic_vector(7 downto 0);
    g,e,l: out std_logic);
    end component;
    component DataRegister is
    generic (data_width:integer);
    port (Din: in std_logic_vector(data_width-1 downto 0);
    Dout: out std_logic_vector(data_width-1 downto 0);
    enable,clk : in std_logic);
    end component;
    signal count0 : std_logic;
    signal count,count_in,dcrCount : std_logic_vector(3 downto 0);
    signal areg,lsa,areg_in : std_logic_vector(7 downto 0);
    signal breg,breg_in : std_logic_vector(7 downto 0);
    signal rreg,lsr,subb,rreg_in : std_logic_vector(7 downto 0);
    signal qreg,qreg_in,lsq : std_logic_vector(7 downto 0);
    signal quotient_in,remainder_in : std_logic_vector(7 downto 0);
    signal
    countEnable,aregEnable,bregEnable,rregEnable,qregEnable,resultEnable :
    std_logic;
    signal g,e,l : std_logic;
    ------------process begins------------------------------------begin
    --set operations complete------count0 <= (count(0) or count(1) or count(2) or count(3));
    muxs1 : mux21 port map ('0','1',count0,s(1));
    --cmp----------------------cmp : cmp8 port map(rreg,breg,g,e,l);
    s(0) <= not(l);
    --count register
    decr : shiftCount8 port map(count,dcrCount);
    countEnable <= (t(0) or t(1));
    count_in <= dcrCount when (t(1) = '1') else "1000"; --set count
    count_reg : DataRegister
    generic map (data_width => 4)
    port map(count_in,count,countEnable,clk);
    --areg logic----------------lsa <= areg(6 downto 0)&'0';

    aregEnable <= (t(0) or t(1));


    areg_in <= lsa when (t(1) = '1') else a;
    ar : DataRegister
    generic map(data_width => 8)
    port map(areg_in,areg,aregEnable,clk);
    --breg logic----------------bregEnable <= t(0); -- allow input to change after accept signal
    breg_in <= b;
    br : DataRegister
    generic map(data_width => 8)
    port map(breg_in,breg,bregEnable,clk);
    --rreg logic----------------rregEnable <= (t(0) or t(1) or t(3));
    sub : sub8bit port map (rreg,breg,subb);
    lsr <= rreg(6 downto 0)&areg(7);
    process(t)
    begin
    if(t(0) = '1') then
    rreg_in <= "00000000";
    elsif(t(1) = '1') then
    rreg_in <= lsr;
    elsif(t(3) = '1') then
    rreg_in <= subb;
    else
    rreg_in <= rreg;
    end if;
    end process;
    rr : DataRegister
    generic map(data_width => 8)
    port map(rreg_in,rreg,rregEnable,clk);
    --qreg logic------------------------qregEnable <= (t(0) or t(1) or t(3));
    lsq <= qreg(6 downto 0)&'0';
    process(t)
    begin
    if(t(0) = '1') then
    qreg_in <= "00000000";
    elsif(t(1) = '1') then
    qreg_in <= lsq;
    elsif(t(3) = '1') then
    qreg_in <= qreg;
    qreg_in(0) <= '1';
    else
    qreg_in <= qreg;
    end if;
    end process;

    qr : DataRegister
    generic map(data_width => 8)
    port map(qreg_in,qreg,qregEnable,clk);
    --result Logic--------resultEnable <= t(4);
    quotient_in <= qreg;
    remainder_in <= rreg;
    quoR : DataRegister
    generic map(data_width => 8)
    port map(quotient_in,quotient,resultEnable,clk);
    remR : DataRegister
    generic map(data_width => 8)
    port map(remainder_in,remainder,resultEnable,clk);
    end architecture;
    ---------------------------------------------------------------

    --8 Bit Divider RTL Model


    -----Divider--------------------------------------------------library ieee;
    use ieee.std_logic_1164.all;
    use std.textio.all;
    use ieee.numeric_std.ALL;
    entity divider8bitbit is
    port ( clk,rst : in std_logic;
    dividend,divisor : in std_logic_vector(7 downto 0);
    input_ready : in std_logic;
    divider_ready : out std_logic;
    quotient : out std_logic_vector(7 downto 0);
    remainder : out std_logic_vector(7 downto 0);
    output_ready : out std_logic;
    output_accepted : in std_logic);
    end entity;
    architecture structure of divider8bitbit is
    component controlPath is
    port ( clk,rst : in std_logic;
    input_ready : in std_logic;
    divider_ready : out std_logic := '1';
    output_ready : out std_logic;
    output_accepted : in std_logic;
    T : out std_logic_vector(4 downto 0);
    S : in std_logic_vector(1 downto 0));
    end Component;

    component dataPath is
    port( clk,rst : in std_logic;
    t : in std_logic_vector(4 downto 0);
    s : out std_logic_vector(1 downto 0);
    a,b : in std_logic_vector(7 downto 0);
    quotient,remainder : out std_logic_vector(7 downto 0));
    end component;
    signal t : std_logic_vector(4 downto 0);
    signal s : std_logic_vector(1 downto 0);
    begin
    cp : controlPath
    port
    map(clk,rst,input_ready,divider_ready,output_ready,output_accepted,t,s);
    dp : dataPath
    port map(clk,rst,t,s,dividend,divisor,quotient,remainder);
    end structure;
    ----------------------------------------------------------------Divider components--------------------------------------------shiftCounter8-----------------------------------------------library ieee;
    use ieee.std_logic_1164.all;
    entity shiftCount8 is
    port (A: in std_logic_vector(3 downto 0);
    B: out std_logic_vector(3 downto 0));
    end entity shiftCount8;
    architecture Serial of shiftCount8 is
    begin
    process(A)
    variable borrow: std_logic;
    begin
    borrow := '1';
    for I in 0 to 3 loop
    B(I) <= A(I) xor borrow;
    borrow := borrow and (not A(I));
    end loop;
    end process;
    end Serial;
    ---------------------------------------------------------------- left shifter 8 Bit ---------------------------------------library ieee;

    use ieee.std_logic_1164.all;
    entity lshift8 is
    port ( A : in std_logic_vector(7 downto 0);
    B : out std_logic_vector(7 downto 0));
    end entity;
    architecture structure of lshift8 is
    begin
    B(7 downto 1) <= A(6 downto 0);
    B(0) <= '0';
    end architecture;
    ----------------------------------------------------------------8 Bit Sub--------------------------------------------------library ieee;
    use ieee.std_logic_1164.all;
    entity sub8bit is
    port( A,B : in std_logic_vector(7 downto 0);
    sub : out std_logic_vector(7 downto 0));
    end entity;
    architecture serial of sub8bit is
    signal bbar : std_logic_vector(7 downto 0);
    begin
    bbar <= not(B);
    process(A,bbar)
    variable carry: std_logic;
    begin
    carry := '1';
    for I in 0 to 7 loop
    sub(I) <= (A(I) xor bbar(I)) xor carry;
    carry := (carry and (A(I) or bbar(I))) or (A(I) and bbar(I));
    end loop;
    end process;
    end architecture;
    --Comparator-------------------------------------------------library ieee;
    use ieee.std_logic_1164.all;
    entity cmp8 is
    port (A,B : in std_logic_vector(7 downto 0);
    g,e,l: out std_logic);
    end entity;
    architecture structure of cmp8 is

    component compBlock is
    port(gp,ep,lp : in std_logic;
    ak,bk : in std_logic;
    g,e,l : out std_logic);
    end component;
    signal gTmp,eTmp,lTmp : std_logic_vector(6 downto 0);
    begin
    cmp7 : compBlock port
    map('0','1','0',A(7),B(7),gTmp(0),eTmp(0),lTmp(0));
    cmp6 : compBlock port
    map(gTmp(0),eTmp(0),lTmp(0),A(6),B(6),gTmp(1),eTmp(1),lTmp(1));
    cmp5 : compBlock port
    map(gTmp(1),eTmp(1),lTmp(1),A(5),B(5),gTmp(2),eTmp(2),lTmp(2));
    cmp4 : compBlock port
    map(gTmp(2),eTmp(2),lTmp(2),A(4),B(4),gTmp(3),eTmp(3),lTmp(3));
    cmp3 : compBlock port
    map(gTmp(3),eTmp(3),lTmp(3),A(3),B(3),gTmp(4),eTmp(4),lTmp(4));
    cmp2 : compBlock port
    map(gTmp(4),eTmp(4),lTmp(4),A(2),B(2),gTmp(5),eTmp(5),lTmp(5));
    cmp1 : compBlock port
    map(gTmp(5),eTmp(5),lTmp(5),A(1),B(1),gTmp(6),eTmp(6),lTmp(6));
    cmp0 : compBlock port map(gTmp(6),eTmp(6),lTmp(6),A(0),B(0),g,e,l);
    end architecture;
    ---------------------------------------------------------------- Register---------------------------------------------------library ieee;
    use ieee.std_logic_1164.all;
    entity DataRegister is
    generic (data_width:integer);
    port (Din: in std_logic_vector(data_width-1 downto 0);
    Dout: out std_logic_vector(data_width-1 downto 0);
    enable,clk: in std_logic);
    end entity;
    architecture Behave of DataRegister is
    begin
    process(clk)
    begin
    if(clk'event and (clk = '1')) then
    if(enable = '1') then
    Dout <= Din;
    end if;
    end if;
    end process;
    end Behave;
    ---------------------------------------------------------------

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