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    ECE102 F11 Summary Highlights

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    ECE 102 focuses on MOS transistor characteristics and circuit concepts. Key points covered include: 1) Equations for NMOS and PMOS i-D characteristics in different operating regions. 2) The linear transfer function between signal input and output for MOS transistors, even though the overall I-V relationship is nonlinear. 3) Current mirror circuits used as current sources for biasing, allowing constant current independent of temperature and process variations. 4) Small signal modeling of MOS transistors and configurations such as common source, common gate, and differential amplifiers. 5) Frequency response analysis considers how different capacitances affect lower and upper cut-off frequencies.

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    ECE102 F11 Summary Highlights

    Uploaded by

    Lol
    157 views24 pages
    ECE 102 focuses on MOS transistor characteristics and circuit concepts. Key points covered include: 1) Equations for NMOS and PMOS i-D characteristics in different operating regions. 2) The linear transfer function between signal input and output for MOS transistors, even though the overall I-V relationship is nonlinear. 3) Current mirror circuits used as current sources for biasing, allowing constant current independent of temperature and process variations. 4) Small signal modeling of MOS transistors and configurations such as common source, common gate, and differential amplifiers. 5) Frequency response analysis considers how different capacitances affect lower and upper cut-off frequencies.

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    A pdf with some useful circuit highlights

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    ECE 102 focuses on MOS transistor characteristics and circuit concepts. Key points covered include: 1) Equations for NMOS and PMOS i-D characteristics in different operating regions. 2) The linear transfer function between signal input and output for MOS transistors, even though the overall I-V relationship is nonlinear. 3) Current mirror circuits used as current sources for biasing, allowing constant current independent of temperature and process variations. 4) Small signal modeling of MOS transistors and configurations such as common source, common gate, and differential amplifiers. 5) Frequency response analysis considers how different capacitances affect lower and upper cut-off frequencies.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    157 views24 pages

    ECE102 F11 Summary Highlights

    Uploaded by

    Lol
    ECE 102 focuses on MOS transistor characteristics and circuit concepts. Key points covered include: 1) Equations for NMOS and PMOS i-D characteristics in different operating regions. 2) The linear transfer function between signal input and output for MOS transistors, even though the overall I-V relationship is nonlinear. 3) Current mirror circuits used as current sources for biasing, allowing constant current independent of temperature and process variations. 4) Small signal modeling of MOS transistors and configurations such as common source, common gate, and differential amplifiers. 5) Frequency response analysis considers how different capacitances affect lower and upper cut-off frequencies.

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    ECE102: Summary & Highlights

    Focusing on Concepts!

    ECE 102, Fall 2011, F. Najmabadi

    MOS i-v Characteristics Equations


    NMOS

    (VOV = vGS Vt,n)

    Cut - Off :

    VOV 0

    iD = 0

    Triode :

    VOV 0 and vDS VOV

    iD = 0.5 nCox

    Saturation : VOV 0 and vDS VOV

    PMOS

    W
    2
    2VOV vDS vDS
    L
    W 2
    iD = 0.5 nCox
    VOV 1 + vDS
    L

    ]
    ]

    (VOV = vSG |Vt,p|)*

    Cut - Off :

    VOV 0

    iD = 0

    Triode :

    VOV 0 and vSD VOV

    iD = 0.5 p Cox

    Saturation : VOV 0 and vSD VOV

    W
    2
    2VOV vSD vSD
    L
    W 2
    iD = 0.5 p Cox
    VOV 1 + vSD
    L

    ]
    ]

    *Note: S&S defines |VOV |= vSG |Vt,p| and uses |VOV |in the PMOS formulas.

    The response to a combination of VGS and vgs


    (signal) can be found from the transfer function

    Response to the signal appears to be linear!

    Although the overall response is non-linear, the


    transfer function for the signal only is linear!
    vds
    Constant:
    Bias

    Signal and
    response

    vGS = VGS + vgs


    vDS = VDS + vds

    vgs

    iD = IDS + id

    Non-linear
    relationship among
    these parameters

    Linear
    relationship among
    these parameters

    Bias is the state of the system when there is no signal.

    Bias with Source Degeneration (Discrete circuits)

    Basic Arrangement

    Bias with one power supply

    Bias with two power supply

    VGS = VG RS I D

    VGS = VG RS I D

    VGS = VSS RS I D
    (KVL : 0 = RG 0 + VGS + RS I D VSS )

    Biasing in ICs
    Resistors take too much space on the chip. So, source degeneration with
    RS is NOT implemented in ICs.
    Recall that the goal of a good bias is to ensure ID and VDS that do not
    change. One can force ID to be constant using a current source.

    1) Current source forces:


    ID = I

    2) VD = VDD RD I D
    3) VGS is set by
    W
    I D = 0.5 nCox (VGS Vt ) 2
    L
    4) VS = VG VGS = VGS
    5) VDS = VD VS

    Current Mirrors (or Current Steering Circuits)


    are used as current sources for biasing ICs
    Identical MOS:
    Same Cox and Vt

    Q1 is always in saturation since

    VDS1 = VGS1 > VGS1 Vt


    VGS1 = VGS 2 = VGS
    VOV 1 = VOV 2 = VOV

    W 2
    I ref = I D1 = 0.5 nCox VOV
    L 1
    W
    I o = I D 2 = 0.5 nCox VOV2
    L 2
    I o (W / L )2
    =
    I ref (W / L )1
    Circuit works as long as Q2 is in
    saturation: VDS 2 > VOV = VGS Vt

    NMOS (or PMOS) small signal circuit model


    ig = 0 and id = g m v gs +

    id

    Input open circuit

    2 ID
    gm =
    VOV

    vds
    ro

    1
    ro
    ID

    Statement of KCL
    Two elements in parallel

    2
    2VA
    =
    >> 1
    g m ro =
    VOV VOV

    MOS Amplifier Fundamental Configurations


    (PMOS circuits are identical)

    Common Source

    Common Gate

    Av = g m (ro || RL )

    Av = g m (ro || RL )

    Common Source with RS

    Common Drain/Source Follower

    g m RL
    Av =
    1 + g m R S + RL / ro

    Av =

    g m (ro || RL )
    1 + g m (ro || RL )

    Elementary Configurations for MOS resistance


    (PMOS circuits are identical)

    ro (1 +g m R ) + R

    ro (1 +g m R )

    ro +R
    1
    R

    +
    1 + g m ro g m
    g m ro
    Output resistance
    of CS Amp with Rs

    ro

    Input resistance
    of CG Amp

    1
    1
    || ro
    gm
    gm

    Input resistance
    of CS Amp

    Diode-connected
    Transistor
    Always in saturation!

    Above configurations are for Small Signal. Typically one or both grounds
    are connected to bias voltage sources to ensure that MOS is in saturation!

    MOS as a resistor

    MOS acts as a real resistor with its


    conductivity controlled by VOV (or vGS).
    iD = g DS vDS with g DS = nCox

    W
    VOV
    L

    MOS acts as a resistor for


    signal only.
    1
    ro
    ID

    Summary of Current Mirrors


    Any circuit that
    fixes Iref

    Bias Model

    Io =

    Small Signal Model

    (W / L) 2
    I ref
    (W / L)1

    Equivalent circuit
    Signal current
    goes through
    this leg
    ( capacitor)

    Bias current
    goes through
    this leg

    Single-transistor MOS amplifiers


    with active load/current source

    NMOS CS Amp

    PMOS CS Amp

    NMOS CD Amp

    PMOS CD Amp

    Gain of a Cascode amplifier with a


    cascode current mirror/active load
    Value for the
    same gm and ro
    Cascode
    current mirror

    ro 3 (1 + g m 3 ro 4 ) + ro 4
    Cascode
    amplifier

    Av 2 = vo / v1 g m 2 (ro 2 || RL ) g m 2 ro 2

    RL1 = Ri 2 =

    Av 2 g m ro

    ro 2 + ro 3 (1 + g m 3 ro 4 ) + ro 4
    1 + g m 2 ro 2
    g m 3 ro 3 ro 4
    g m 2 ro 2

    Av1 = v1 / vi = g m1 (ro1 ||
    Av = Av1 Av 2 =

    RL1 = Ri 2 ro
    g m 3 ro 3 ro 4
    )
    g m 2 ro 2

    g m1 g m 2 g m 3 ro1ro 2 ro 3 ro 4
    g m 2 ro1ro 2 + g m 3 ro 3 ro 4

    Av1 = 0.5 g m ro
    Av = 0.5 ( g m ro ) 2

    Cascode amplifier: A two-stage, CS-CG circuit


    A high gain, Av 0.5(gmro)2 , high gain-bandwidth circuit.

    Summary of Differential Amplifiers


    Common-Mode and Differential Signal/Gain and CMRR
    Differential amplifier
    Concept of half-circuit
    Why differential amplifiers are popular
    o Large CMRR with a slight mis-match
    o Less difficult biasing
    Cascode differential amplifiers
    Differential amplifiers in ICs
    o Biasing
    o Current-source active load for two-output Amp.
    o Asymmetric active load for one-ended output

    Concept of Half Circuit


    For a symmetric circuit, differential- and common-mode
    analysis can be performed using half-circuits.

    Common Mode

    Differential Mode

    Common-Mode Half Circuit


    Common Mode circuit
    id

    id

    vo1 = vo 2
    0
    id

    vs1 = vs 2
    id

    Common Mode Half-circuit


    1. Currents about symmetry line are equal.
    2. Voltages about the symmetry line are equal (e.g., vo1 = vo2)
    3. No current crosses the symmetry line.

    Differential-Mode Half Circuit


    Differential Mode circuit
    id

    id

    vo1 = vo 2

    id

    id

    vs1 = vs 2 = 0

    Differential Mode Half-circuit


    1. Currents about the symmetry line are equal in value and opposite in sign.
    2. Voltages about the symmetry line are equal in value and opposite in sign.
    3. Voltage at the summery line is zero

    Replacing biasing resistor Rss with


    a current mirror helps in getting a high CMRR
    Small Signal

    Analyzed before
    (replace RSS with ro3)
    Current mirror is in
    the Source Circuit

    ro3 does not affect the differential gain


    ro3 is large and leads to a large CMRR
    for slightly mis-matched circuits (recall
    we wanted large Rss)

    Replacing load resistors, RD ,


    with current-source active load
    Q3 and Q4 identical
    Small
    signal

    For NMOS difference amplifier, we need PMOS load (similar to a CS amplifier) as


    Q1 should see the drain of Q3 in order to see a large R (for signal) and achieve
    a high differential gain.
    Bias current should flow into the drain of Q1 (and thus out of drain of Q3)

    Typical Frequency response of an Amplifier


    Up to now we have ignored the capacitors. To include the capacitors, we
    need to solve the circuit in the frequency domain (or use Phasors).
    o Lower cut-off frequency: fL
    o Upper cut-off frequency: fH
    o Band-width: B = fH fL

    Impact of various capacitors depend on the


    frequency of interest
    Impendence of capacitors (1/C)

    f0
    All Caps are open.
    Used this to find
    low-frequency C.

    Computing fL:
    High-f caps are open.
    Low-f caps included.

    f
    All Caps are short.
    Used to find highfrequency C.

    Mid-band:
    High-f caps are open
    Low-f caps are short.

    Computing fH :
    High-f caps are included.
    Low-f caps are short

    MOS high-frequency small signal model


    Accurate Model
    (we use this model here)

    For source connected to body


    (used by S&S)

    Generally, transistor internal capacitances are


    shown outside the transistor so that we can use
    results from the mid-band calculations.

    Summary of frequency response


    Identify which capacitors contribute to low-f and which to high-f
    Procedure (high-frequency)
    1. Include internal-capacitances of NMOS and
    simplify the circuit.
    2. Use Millers approximation for Miller
    capacitors in configurations with large (and
    negative) A.
    3. Use time-constant method to find fH
    a. Set vsig = 0
    b. Consider each capacitor separately, e.g.,
    Cj (assume others are open circuit!)
    c. Find the total resistance seen between
    the terminals of the capacitor, e.g., Rj
    (treat ground as a regular node).
    1
    2 f H

    = b1 = nj =1 R j C j

    4. Do not forget about zeros in CS and CD


    configurations.

    Procedure (low-frequency):
    1. Set vsig = 0
    2. Consider each capacitor separately, e.g., Cn
    (assume others are short circuit!)
    3. Find the total resistance seen between the
    terminals of the capacitor, e.g., Rn (treat
    ground as a regular node).
    4. The pole associated with that capacitor is
    f pn =

    1
    2 Rn Cn

    5. Lower-cut-off frequency can be found from


    fL fp1 + fp2 + fp3 +

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