Dual Digital BTSC Encoder

with Integrated DAC

AD71028
FEATURES PRODUCT OVERVIEW
2 complete independent BTSC encoders The AD71028 dual digital BTSC encoder provides two complete
Pilot tone generator digital BTSC encoder channels, including the pilot-tone
Includes subcarrier modulation generation and subcarrier mixing functions. Two built-in high
Typical 23 dB to 27 dB separation, 16 dB minimum performance DACs are provided to output the BTSC baseband
Signal bandwidth of 14 kHz composite signal. The output of the AD71028 can be connected
Phat-StereoTM algorithm for stereo image enhancement with minimal external circuitry to the input of a 4.5 MHz aural
Dialog enhancement function for playing wide dynamic FM modulator.
range video sources over built-in TV speakers
Includes L-R dual-band compressor In addition to the BTSC encoders, the AD71028 also includes a
SPI® port for control of modes and effects stereo image enhancement function, Phat Stereo, to increase the
Differential output for optimum performance sense of spaciousness available from closely spaced TV
DAC performance: 92 dB dynamic range, –92 dB THD+N loudspeakers. A dialog enhancement algorithm is also included
Output level control for setting aural carrier deviation to solve the problem of playing wide dynamic range sources
Flexible serial data port with right-justified, left-justified, over limited-performance TV speakers and amplifiers. An
I2S compatible, and DSP serial port modes extensive SPI port allows click-free parameter updates.
48-lead LQFP plastic package The AD71028 also includes ADI’s patented multibit Σ-∆ DAC
architecture. This architecture provides 92 dB SNR and THD+N
APPLICATIONS of –92 dB.
Digital set-top box BTSC encoder

FUNCTIONAL BLOCK DIAGRAM

SERIAL 3
INPUT A SERIAL
INPUT
BTSC
PLL DIVIDERS ENCODER
CORE A BTSC
CLOCK
DOUBLER DAC ENCODED
CLOCK OUTPUT A
SIGNAL
GROUP
ANALOG
BIAS
CLOCK BIAS
DOUBLER
BTSC
PLL DIVIDERS ENCODER BTSC
CORE B DAC ENCODED
3 SERIAL OUTPUT B
SERIAL INPUT
INPUT B

SPI I/O 4 CONTROL REGISTERS

04482-0-001

GROUP SPI PORT

PARAMETER RAM
AD71028

Figure 1. Functional Block Diagram

Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
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registered trademarks are the property of their respective owners. Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
AD71028

TABLE OF CONTENTS
Specifications..................................................................................... 3 Input Levels ................................................................................. 11

DAC Analog Performance........................................................... 3 Clock Relationships.................................................................... 11

BTSC Encoder Performance ....................................................... 3 SPI Port ............................................................................................ 12

Digital I/O ..................................................................................... 3 Overview ..................................................................................... 12

Power.............................................................................................. 4 SPI Address Decoding ............................................................... 12

Temperature Range ...................................................................... 4 Parameter RAM.......................................................................... 13

Digital Timing............................................................................... 4 Control Register ......................................................................... 13

Absolute Maximum Ratings............................................................ 5 Output Level Register ................................................................ 13

Pin Configuration and Functional Descriptions.......................... 6 Stereo Enhancement Register ................................................... 13

Features .............................................................................................. 8 Dialog Enhancement Register .................................................. 13

Pin Functions ................................................................................ 8 SPI Read/Write Data Formats .................................................. 14

Signal Processing ............................................................................ 10 Initialization ................................................................................ 14

Background of BTSC ................................................................. 10 Serial Data Input Port ................................................................ 14

Performance Factors .................................................................. 10 Analog Output Section .................................................................. 16

Separation Alignment ................................................................ 10 Outline Dimensions ....................................................................... 17

Phase Linearity of the External Analog Filter......................... 11 Ordering Guide .......................................................................... 17

REVISION HISTORY
Revision 0: Initial Version

Rev. 0 | Page 2 of 20
 AD71028

SPECIFICATIONS
TEST CONDITIONS, UNLESS OTHERWISE NOTED
Supply Voltages (AVDD, DVDD) 5.0 V
Ambient Temperature 25°C
Input Clock 12.288 MHz
Input Signal 1 kHz, 0 dBFS
Input Sample Rate 48 kHz
Measurement Bandwidth 20 Hz to 14 kHz
Word Width 24 Bits
Load Capacitance 50 pF
Input Voltage HI 2.4 V
Input Voltage LO 0.4 V

DAC ANALOG PERFORMANCE

Table 1.
Parameter Min Typ Max Unit
Resolution 24 Bits
Dynamic Range (20 Hz to 14 kHz, –60 dB Input) (Encoded Output, Left = Right) 85 921 dB
Total Harmonic Distortion + Noise (Encoded Output, Left = Right, 20 Hz to 14 kHz)
VIN = 0 dB –85 –921 dB
Differential Output Range (± Full Scale, Left = Right) 1.7 V p-p

1
Measurement of encoded BTSC signal, not a measurement of end-to-end system.

BTSC ENCODER PERFORMANCE

Table 2.
Parameter Min Typ Max Unit
Channel Separation1
30 Hz to 500 Hz 27 dB
500 Hz to 5 kHz 23 dB
5 kHz to 13.5 kHz 16 dB
Frequency Response1
30 Hz to 10 kHz +0.5 –1.0 dB
30 Hz to 13.5 kHz +0.5 –1.5 dB

1
These specifications are measured with a –25 dB, 1 kHz input signal.

DIGITAL I/O
Table 3.
Parameter Min Typ Max Unit
Input Voltage HI (VIH) 2.1 V
Input Voltage LO (VIL) 0.8 V
Input Leakage (IIH @ VIH = 2.4 V) 10 µA
Input Leakage (IIL @ VIL = 0.8 V) 10 µA
High Level Output Voltage (VOH) IOH = 2 mA DVDD – 0.5 V
Low Level Output Voltage (VOL) IOL = 2 mA 0.4 V

Rev. 0 | Page 3 of 20
AD71028
POWER
Table 4.
Parameter Min Typ Max Unit
Supplies
Voltage, Analog and Digital 4.5 5 5.5 V
Analog Current 31 37 mA
Digital Current 97 110 mA
Dissipation
Operation—Both Supplies 640 mW
Operation—Analog Supplies 155 mW
Operation—Digital Supplies 485 mW

TEMPERATURE RANGE
Table 5.
Parameter Min Typ Max Unit
Specifications Guaranteed 25 °C
Functionality Guaranteed 0 70 °C
Storage –55 +125 °C

DIGITAL TIMING
Table 6.
Parameter Min Typ Max Unit
tDMD MCLK Recommended Duty Cycle @ 12.288 MHz (256 × fS and 512 × fS Modes) 40 60 %
tDBL BCLK Low Pulse Width 25 ns
tDBH BCLK High Pulse Width 10 ns
tDLS LRCLK Setup 0 ns
tDLH LRCLK Hold 10 ns
tDDS SDATA Setup 0 ns
tDDH SDATA Hold 10 ns
tCCL CCLK Low Pulse Width 10 ns
tCCH CCLK High Pulse Width 10 ns
tCLS CLATCH Setup 10 ns
tCLH CLATCH Hold 20 ns
tCLD CLATCH High Pulse Width 10 ns
tCDS CDATA Setup 0 ns
tCDH CDATA Hold 10 ns
tRLP Reset LO Pulse Width 10 ns

Rev. 0 | Page 4 of 20
 AD71028

ABSOLUTE MAXIMUM RATINGS

Table 7. AD71028 Stress Ratings Table 8. Package Characteristics (48-Lead LQFP)
Parameter Min Max Unit Parameter Min Typ Max Unit
DVDD to DGND –0.3 +6 V θJA Thermal Resistance
ODVDD to DGND –0.3 +6 V [Junction-to-Ambient] 72 °C/W
AVDD to AGND –0.3 +6 V θJC Thermal Resistance
Digital Inputs DGND – 0.3 DVDD + 0.3 V [Junction-to-Case] 19.5 °C/W
Analog Inputs AGND – 0.3 AVDD + 0.3 V
AGND to DGND –0.3 +0.3 V Stresses above those listed under Absolute Maximum Ratings
Reference Voltage (AVDD + 0.3)/2 V may cause permanent damage to the device. This is a stress
Maximum Junction rating only; functional operation of the device at these or any
Temperature 125 °C other conditions above those listed in the operational sections
Storage Temperature of this specification is not implied. Exposure to absolute
Range –65 +150 °C maximum rating conditions for extended periods may affect
Soldering 300 °C device reliability.
10 sec

ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. 0 | Page 5 of 20
AD71028

PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS

CLK27_PB
CLK27_PA
MCLK_PB

MCLK_PA

FILTCAP
DIV1_PA

REFCAP
PLL_PB

PLL_PA
DGND
DVDD

NC
48 47 46 45 44 43 42 41 40 39 38 37

DIV2_PA 1 36 AGND

DIV1_PB 2 35 OUTB–

DIV2_PB 3 34 OUTB+

NC 4 33 AVDD

NC 5 32 AGND
AD71028 31 AVDD
DGND 6
TOP VIEW
DVDD 7 (Not to Scale) 30 OUTA+

ODVDD 8 29 OUTA–

NC 9 28 AGND

NC 10 27 NC

COUT 11 26 NC

CDATA 12 25 DOUBLE

13 14 15 16 17 18 19 20 21 22 23 24
DVDD
CCLK

DVDD
RESETB
DGND

SDATA_PA

SDATA_PB
CLATCH

BCLK_PA
LRCLK_PA

BCLK_PB
LRCLK_PB

04482-0-002
NC = NO CONNECT

Figure 2. 48-Lead Low Profile Quad Flat Pack (LQFP)

Table 9. Pin Function Descriptions

Pin No. Mnemonic Input/Output Description
1 DIV2_PA OUT CLK27_PA clock (Pin 40) Divided by 1125
2 DIV1_PB OUT PLL_PB Clock (Pin 46) Divided by 512 (DOUBLE = 1) or 1024 (DOUBLE = 0)
3 DIV2_PB OUT CLK27_PB Clock (Pin 41) Divided by 1125
4, 5, 9, 10, 26, 27, 39 NC No Connection
6, 16, 44 DGND Digital Ground
7, 13, 17, 45 DVDD Digital Supply for DSP Core
8 ODVDD Digital Supply for Output Buffers
11 COUT OUT SPI Readback
12 CDATA IN SPI Control Data Input
14 CCLK IN SPI Serial Bit Clock
15 CLATCH IN SPI Control Latch Signal
18 RESETB IN Reset Signal for Both Processors, Active Low
19 SDATA_PA IN Data Input to Processor A
20 BCLK_PA IN Bit Clock Signal for Serial Data Input to Processor A
21 LRCLK_PA IN Left/Right Framing Signal for Data Input to Processor A
22 SDATA_PB IN Data Input to Processor B
23 BCLK_PB IN Bit Clock Signal for Serial Data Input to Processor B
24 LRCLK_PB IN Left/Right Framing Signal for Data Input to Processor B
25 DOUBLE IN Enables Internal Clock Doubler for 12.288 MHz Input (Both Processors)
28, 32, 36 AGND Analog Ground
29 OUTA– OUT Negative Analog Output, Processor A
30 OUTA+ OUT Positive Analog Output, Processor A
31, 33 AVDD Analog Supply
34 OUTB+ OUT Positive Analog Output, Processor B
35 OUTB– OUT Negative Analog Output, Processor B
37 REFCAP IN Connection Point for 10 µF VREF Filter Capacitor
38 FILTCAP IN Connection for Noise Reduction Capacitor

Rev. 0 | Page 6 of 20
 AD71028
Pin No. Mnemonic Input/Output Description
40 CLK27_PA IN Input for 27 MHz Video Reference Clock, Processor A
41 CLK27_PB IN Input for 27 MHz Video Reference Clock, Processor B
42 PLL_PA IN Input from External PLL, Processor A
43 MCLK_PA IN Clock Input to Processor A
46 PLL_PB IN Input from External PLL, Processor B
47 MCLK_PB IN Clock Input to Processor B
48 DIV1_PA OUT PLL_PA Clock (Pin 42) Divided by 512 (DOUBLE = 1) or 1024 (DOUBLE = 0)

Rev. 0 | Page 7 of 20
AD71028

FEATURES
The AD71028 is comprised of two independent digital-input MCLK_PA, MCLK_PB
BTSC encoders. The two processors allow two completely Master clock inputs. The master clock frequency must be either
asynchronous BTSC channels to be encoded, each with its own 256 × fS or 512 × fS, where fS is the input sampling frequency. If
clock signals. Figure 1 shows the block diagram of the device. the DOUBLE pin is high, an internal clock doubler is used to
take a 256 × fS input clock and produce the 512 × fS internal
Signal processing parameters are stored in a 256-location clock required by the DSP core. If the DOUBLE pin is low, the
parameter RAM, which is initialized on power-up by an internal frequency of the input clock must be set to 512 × fS. In case
boot ROM. The values stored in the parameter RAM control all these clock signals are not available, a simple external PLL may
the filter coefficients, mixing, and dynamics processing code be used to generate the master clock signals. On-chip dividers
used in the BTSC algorithm. are provided to simplify this task.
The AD71028 has an SPI port that supports complete read/ CDATA
write capability of the parameter RAM, as well as a control port Serial data in for the SPI control port. See the SPI Port section
and several other registers that allow the various signal proces- for more information on SPI port timing.
sing parameters to be controlled. The AD71028 can run as a
COUT
standalone processor without SPI control.
Serial data output. This is used for reading back registers and
The AD71028 has a very flexible serial data input port that memory locations. It is three-stated when an SPI read is not
allows for glueless interconnection to a variety of signal sources. active. See the SPI Port section for more information on SPI
The AD71028 can be configured in left-justified, I2S, right- port timing.
justified, or DSP serial port compatible modes. It can support
CCLK
16, 20, and 24 bits in all modes. The AD71028 accepts serial
audio data in MSB first, twos complement format. SPI bit-rate clock. This pin may either run continuously or be
gated in between SPI transactions. See the SPI Port section for
The AD71028 operates from a single 5 V power supply. It is fab- more information on SPI port timing.
ricated on a single monolithic integrated circuit and is housed
CLATCH
in a 48-lead LQFP package for operation over the 0°C to 70°C
temperature range. SPI latch signal. This signal must go low at the beginning of an
SPI transaction and high at the end of a transaction. Each SPI
PIN FUNCTIONS transaction may take a different number of CCLKs to complete,
Pin names and functions are shown below. Note that pins with a depending on the address and read/write bit that are sent at the
“_PA” designation are connected to Processor A, while those beginning of the SPI transaction. Detailed SPI timing informa-
with a “_PB” designation are connected to Processor B. All input tion can be found in the SPI Port section.
pins have a logic threshold compatible with TTL input levels, RESETB
and may therefore be used in systems with 3.3 V logic. All Active-low reset signal. After RESETB transitions from low to
digital output levels are controlled by the ODVDD pin, which high, the AD71028 goes through an initialization sequence
may range from 2.7 V to 5.5 V, for compatibility with a wide where the parameter RAMs are initialized with the contents of
range of external devices. the on-board boot ROM. All SPI registers are set to 0, and the
LRCLK_PA, LRCLK_PB data RAMs are also zeroed. The initialization is complete after
Left/right clocks for framing the input data. The interpretation 1024 MCLK cycles. New values should not be written to the SPI
of the LRCLK changes according to the serial mode, set by port until the initialization is complete.
writing to the control registers. DOUBLE
BCLK_PA, BCLK_PB When this pin is set high, the internal clock doubler is turned
Serial bit clocks for clocking in the serial data. The interpreta- on so a 256 × fS MCLK can be input to the AD71028.
tion of BCLK changes according to the serial mode, which is set PLL_PA, PLL_PB
by writing to the control registers. PLL clock input pins for Processor A and Processor B. These
SDATA_PA, SDATA_PB pins are connected to an internal divide-by-1024 circuit (or
Serial data inputs to each processor. The serial format is selected divide-by-512 if DOUBLE is high). This makes it possible to use
by writing to Bits <3:0> of the control registers. an inexpensive external PLL to generate the system clock. If an
external PLL is used, this pin should also be connected to the
appropriate MCLK_PA or MCLK_PB pin.

Rev. 0 | Page 8 of 20
 AD71028
CLK27_PA, CLK27_PB DVDD
Input pins to the divide-by-1125 block. If an external PLL is Digital VDD for core. 5 V nominal.
used to generate the audio master clock, the 27 MHz video ODVDD
master clock may be applied to these pins where it is divided by
Digital VDD for all digital outputs. Variable from 2.7 V to 5.5 V.
1125 to produce a 24 kHz feedback clock to the external PLL
phase detector. DGND
DIV1_PA, DIV1_PB Digital ground.
Output of divide-by-1024 circuit. Divides the master clock AVDD
signal by 1024 (or 512 when DOUBLE is asserted). Used to Analog VDD. 5 V nominal. Bypass capacitors should be placed
interface to external PLL. close to the pins and connected directly to the analog ground
DIV2_PA, DIV2_PB plane.
Output of divide-by-1125 circuit. Divides the master-clock AGND
signal by 1125. Used to interface to external PLL. The output Analog ground.
signal is a pulse with a duration of one master clock, and should
OUTA+, OUTA–
therefore be used with edge-triggered phase detectors.
Differential analog outputs for Processor A. The nominal output
REFCAP
voltage for a 1 kHz 0 dB mono input signal is 600 mV rms. This
Analog reference voltage input. The nominal REFCAP input level may be adjusted by writing to SPI location 258.
voltage is 2.5 V; the analog gain scales directly with the voltage
OUTB+, OUTB–
on this pin. Any ac signal on this pin will cause distortion, and
therefore a large decoupling capacitor should be used to ensure Differential analog outputs for Processor B. The nominal output
that the voltage on REFCAP is clean. The input impedance of voltage for a 1 kHz 0 dB mono input signal is 600 mV rms. This
REFCAP is greater than 1 MΩ. level may be adjusted by writing to SPI location 770.
FILTCAP
Filter cap point. This pin is used to reduce the noise on an
internal biasing point in order to provide the highest
performance. It may not be necessary to connect this pin,
depending on the quality of the layout and grounding used in
the application circuit.

Rev. 0 | Page 9 of 20
AD71028

SIGNAL PROCESSING
L–R
COMPRESSOR

L 2× Fh CARRIER TO
MATRIX OSCILLATOR DAC
L+R Fh PILOT
R

04482-0-003
75µs
PRE-EMPHASIS
FILTER

Figure 3. Signal Processing Flow

BACKGROUND OF BTSC PERFORMANCE FACTORS

BTSC is the name of the standard for adding stereo audio In order to maintain good separation between left and right, it is
capability to the US television system. It is in many ways similar necessary to closely match the filtering and companding stan-
to the algorithm used for FM stereo broadcasts, with the dards set forth in the standard (FCC OET60). Even small errors
addition of a sophisticated compressor circuit to improve the can result in poor performance. The AD71028 has been pro-
signal-to-noise ratio. grammed to match these standards as accurately as possible.
Separation typically ranges from 30 dB at frequencies below
The processing of mono (L = R) signals is unchanged from the 1 kHz to 15 dB at 14 kHz. Measuring these numbers can be
original pre-BTSC system in order to maintain compatibility difficult as significant differences exist between many so-called
with non-BTSC TV receivers. The L + R signal is applied to a reference decoders, which are all implemented with analog
75 µs pre-emphasis filter, and is then applied to a 4.5 MHz FM components.
modulator, which is later added into the video signal to create a
composite video signal. SEPARATION ALIGNMENT
Stereo capability is added by taking the L–R signal, applying it The BTSC encoder outputs are all specified in terms of the
to a 2-band dynamic compressor, and then multiplying this deviation of the FM 4.5 MHz carrier. For the AD71028, a digital
signal by a carrier signal at twice the horizontal scanning rate input level of 0 dB (mono signal) should cause a carrier
(Fh), or about 2 × 15.734 kHz. This multiplication is known as deviation of ±25 kHz without the 75 µs pre-emphasis filter. In
double-sideband suppressed-carrier modulation, and it practice, the pre-emphasis filter may be left in for this adjust-
effectively translates the compressed L – R spectrum up in ment, as long as the frequency is low enough to not be affected
frequency so that it sits above the audio band (Figure 3). by the pre-emphasis filter. It is critical to maintain the proper
gain relationship between the BTSC encoder and the 4.5 MHz
In order for the receiver to recover this L – R signal, a pilot tone FM modulator. A common mistake is to assume that changing
at the horizontal rate is added to the signal. The receiver has a the gain between the BTSC encoder output and the FM
PLL that locks to this pilot and generates a signal at the carrier modulator input has the same effect as changing the audio
frequency. This signal is then used to multiply the composite input level going in to the BTSC encoder. The presence of a
BTSC-encoded signal, which translates this component back complicated 2-band nonlinear dynamics processor means that
down to baseband. The L – R signal is then applied to a 2-band the encoder output must be connected to the decoder input
expander, which is the complement to the earlier compressor (through the FM modulation/demodulation process) with a
step. Once the L + R and L – R signals are recovered, a simple known gain. If this gain is changed, the separation will
addition/subtraction circuit (sometimes referred to as the significantly suffer.
“matrix”) can be used to recover the L and R signal.
When measuring the AD71028 on the bench, it is possible to
Since the pilot tone is added at 15.734 kHz, it is necessary to use a BTSC reference decoder box, so that the FM modulation/
reduce the signal’s bandwidth so that audio signals cannot demodulation process may be skipped. These units have a
interfere with the pilot tone. In the AD71028, the bandwidth is method of adjusting the input voltage sensitivity to achieve best
limited to 14 kHz; above this frequency, the response decays separation. The output level of the AD71028 can also be
very rapidly. adjusted over a wide range using either the SPI control port or
by adjusting the values of the components used in the external
analog low-pass filter that is between the BTSC encoder output
and the input to the FM modulator.

Rev. 0 | Page 10 of 20
 AD71028
PHASE LINEARITY OF THE EXTERNAL ANALOG The AD71028 contains a clock doubler circuit that may be used
FILTER to generate an internal 512 × fS clock when the external clock is
256 × fS. The clock mode is set by connecting the DOUBLE pin
If the time alignment of the pilot to the carrier signal is not
either high or low. This pin should be tied either high or low
close to 0 degrees, a loss of separation can occur. This means
and should not be changed after power-up.
that the external analog low-pass filter should be a linear-phase
design to provide constant group delay over the range from dc The AD71028 requires a master clock at either 256 × 48 kHz
to 50 kHz. Bessel filters are recommended for this application. (12.288 MHz) when DOUBLE = 1 or 512 × 48 kHz
Figure 12 shows a recommended design for these filters. (24.576 MHz) when DOUBLE = 0. In some cases, this signal is
provided by the MPEG decoder chip itself. In other cases, only
INPUT LEVELS
the 27 MHz video clock may be available. In this case, the
The maximum input level to the AD71028 changes across AD71028 provides on-chip dividers to interface to an external
frequency. Table 10 shows the maximum allowable input level PLL such as the 74HC4046. Figure 4 shows the circuit to
for different frequencies. These values are part of the BTSC accomplish this. The 27 MHz clock is applied to the AD71028
specification and are not a function of this chip. and divided down by 1125, producing a signal at 24 kHz. The
PLL oscillator output is divided down by 512, producing a
Table 10. Maximum Input Levels to the BTSC Encoder 24 kHz output (when locked). These two signals are applied to
across Frequency the phase-comparator inputs of the external PLL. Note that the
Frequency (Hz) Maximum Input Level (dBFS) divided-down 27 MHz signal looks like a pulse with a duration
20 to 1000 0 dB of one master clock, and therefore only edge-triggered phase
1600 –1 dB detectors should be used.
2500 –3 dB
AD71028
3150 –5 dB
27MHz IN
5000 –8 dB DIVIDE-BY-1125
8000 –11 dB
12500 –15 dB 74HC4046 DIVIDE-BY-512

CLOCK RELATIONSHIPS
In an MPEG receiver architecture, all clocks are typically
generated from a 27 MHz master clock. The following integer DSP
relationships are found between the clocks, with Fh =

04482-0-004
15.734 kHz:

a) 27 MHz/Fh = 1716 = 2 × 2 × 3 × 11 × 13
Figure 4. PLL Connections for 27 MHz Master Clock
b) Fh/2 = Fcolor_subcarrier/(5 × 7 × 13)

c) 27 MHz/Fcolor_subcarrier = (5 × 7)/(2 × 2 × 2 × 3 × 11)

d) 27 MHz/48 kHz = 1125/2

Rev. 0 | Page 11 of 20
AD71028

SPI PORT
CLATCH

CCLK

04482-0-005
CDATA BYTE 0 BYTE 1 BYTE 4

Figure 5. Sample of SPI Write Format (Single-Write Mode)

CLATCH

CCLK

BYTE 0 BYTE 1 XXX

CDATA

04482-0-006
HI-Z HI-Z
COUT DATA DATA DATA

Figure 6. Sample of SPI Read Format (Single-Read Mode)

OVERVIEW COUT signal remains three-stated until a READ operation is

The AD71028 can be controlled using the SPI port. In general, requested. This allows other SPI compatible peripherals to share
there are three parameters per processor that can be controlled: the same readback line. All SPI transactions follow the same
the encoder output level, the Phat Stereo image enhancement basic format, shown in Figure 5. Figure 6 shows the read format.
algorithm, and the dialog enhancement algorithm. It is also The Wb/R bit is low for a write and high for a read operation.
possible to write new data into the parameter RAM to alter the The 10-bit address word is decoded into either a location in the
filter coefficients used in the BTSC encoding process. This is a parameter RAM or one of the SPI registers. The number of data
fairly complex topic unnecessary for normal operation of the bytes varies according to the register or memory being accessed.
chip, and the details are not included in this data sheet. Please The detailed data format diagram for continuous-mode
contact ADI if modifications to the BTSC filters are required. operation is given in the SPI Read/Write Data Formats section.
The SPI port uses a 4-wire interface consisting of CLATCH, SPI ADDRESS DECODING
CCLK, CDATA, and COUT signals. The CLATCH signal goes
low at the beginning of a transaction and high at the end of a Table 11 shows the address decoding used in the SPI port. The
transaction. The CCLK signal latches the serial input data on a SPI address space encompasses a set of registers and the param-
low-to-high transition. The CDATA signal carries the serial eter RAM. The parameter RAM is loaded on power-up from an
input data, and the COUT signal is the serial output data. The on-board boot ROM.

Table 11. SPI Port Address Decoding

SPI Address Register Name Read/Write Word Length
0–255 Parameter RAM Processor A Write: 22 Bits, Read: 22 Bits
256 SPI Control Register Processor A Write: 11 Bits, Read: N/A
257 Reserved
258 Output Level Processor A Write: 22 Bits, Read: N/A
259 Stereo Spreading Control Processor A Write: 22 Bits, Read: N/A
260 Dialog Enhancement Control Processor A Write: 22 Bits, Read: N/A
512–767 Parameter RAM Processor B Write: 22 Bits, Read: 22 Bits
768 SPI Control Register Processor B Write: 22 Bits, Read: N/A
769 Reserved
770 Output Level Processor B Write: 22 Bits, Read: N/A
771 Stereo Spreading Control Processor B Write: 22 Bits, Read: N/A
772 Dialog Enhancement Control Processor B Write: 22 Bits, Read: N/A

Rev. 0 | Page 12 of 20
 AD71028
PARAMETER RAM OUTPUT LEVEL REGISTER
The parameters for the two BTSC processors are stored in two The output level register controls the overall BTSC output level.
256-location RAM spaces. The user should not change most of Its default value is –6 dB, which outputs a 600 mV rms reference
these parameters, although editing the dynamics processing level for a 1 kHz 0 dB mono digital input signal. This value is in
curve for dialog enhancement may be useful if the curve needs 2.20 format, and –6 dB corresponds to binary
to be changed for a specific application. This is explained in the 0010000000000000000000. This register is used in conjunction
Dialog Enhancement Register section of this data sheet. with the output filter to match the output BTSC level of the
encoder with the decoder input to achieve maximum separation
CONTROL REGISTER values. This level control should not be used to control the
Control Register 1 is an 11-bit register that controls serial overall volume level of the audio signal.
modes, de-emphasis, mute, power-down, and SPI-to-memory
transfers. Table 12 documents the contents of this register. STEREO ENHANCEMENT REGISTER
This register controls ADI’s patented Phat Stereo spatial
Bits 4:5 and 8:10 are reserved and should be set to 0 at all times. enhancement algorithm. The default is all 0s, which corres-
The audio signal is muted with Bit 7 of the control register. ponds to no effect. The maximum setting is
The soft power-down bit (Bit 6) stops the internal clocks to the 0100000000000000000000, or a twos complement fractional
DSP core, but does not reset the part. The digital power con- value of 1.0. Note that the bass energy in each channel is
sumption is reduced to a low level when this bit is asserted. increased using this algorithm, which may cause some digital
Reset can only be asserted using the external reset pin. clipping on full-scale signal peaks, especially at low frequencies.

Bits 3:2 select the serial format from one of four modes. These DIALOG ENHANCEMENT REGISTER
different formats are discussed in the Initialization section of This controls the built-in dialog-enhancement algorithm, and
this data sheet. defaults to 0. The maximum setting is
0100000000000000000000, or a twos complement fractional
The word length bits (1:0) are used in right-justified serial value of 1.0. This algorithm is intended to solve the problem of
modes to determine where the MSB is located relative to the playing back high dynamic range digital audio signals over a
start of the audio frame. television’s built-in speakers. It provides an amplitude boost to
signals that are in the range where dialog signals are usually
Table 12. Control Register Contents found, while at the same time preventing loud special effects
Register Bits Function passages from overloading the speakers or amplifiers.
10 Reserved, Set to 0
The dialog enhancement control is set up as a dynamics
9 Reserved, Set to 0
processing curve with 33 locations on the curve, each spaced
8 Reserved, Set to 0
3 dB apart. There is a default dialog enhancement curve that is
7 Soft Mute (1 = Start Mute Sequence)
set at power-up, but this can be changed if a different curve is
6 Soft Power-Down (1 = Power-Down)
desired. The curve ranges from an rms input level of –87 dB on
5:4 Reserved, Set to 00
the low end to +9 dB on the high end. The value corresponding
3:2 Serial In Mode
to each point in the parameter RAM represents a gain at the
00 = I2S
appropriate input level. This gain value should range from 0
01 = Right-Justified
(–∞ dB) to +2.0 – 1 LSB (approximately +6 dB). The gain at a
10 = DSP
–87 dB input corresponds to parameter RAM location 4 on
11 = Left-Justified
Processor A and location 516 on Processor B. The table extends
1:0 Word Length
to the +9 dB input gain at locations 36 and 548 for Processors A
00 = 24 Bits
and B, respectively.
01 = 20 Bits
10 = 16 Bits
11 = 16 Bits

Rev. 0 | Page 13 of 20
AD71028
Table 13. SPI Control Register 1 Write format
Byte 0 Byte 1 Byte 2 Byte 3
00000, Wb/R, Adr [9:8] Adr [7:0] 00000, Bit [10:8] Bit [7:0]

Table 14. SPI Write Format for Parameter RAM, Output Level, Stereo Spreading and Dialog Enhancement Registers
Byte 0 Byte1 Byte 2 Byte 3 Byte 4
000000, Adr [9:8] Adr [7:0] 00, Level [21:16] Level [15:8] Level [7:0]

SPI READ/WRITE DATA FORMATS Serial Data Input Modes

The read/write formats of the SPI port are designed to be byte- Figure 7 shows the left-justified mode. LRCLK is high for the
oriented. This allows for easy programming of common micro- left channel and low for the right channel. Data is sampled on
controller chips. In order to fit into a byte-oriented format, 0s the rising edge of BCLK. The MSB is left-justified to a LRCLK
are appended to the data fields in order to extend the data-word transition with no MSB delay. The left-justified mode can accept
to the next multiple of 8 bits. For example, 22-bit words written any word length up to 24 bits.
to the SPI parameter RAM are appended with two leading zeros Figure 8 shows the I2S mode, which is the default setting.
in order to reach 24 bits (3 bytes). These zero-extended data LRCLK is low for the left channel, and the MSB is delayed from
fields are appended to a 2-byte field consisting of a read/write the edge of the LRCLK by a single BCLK period. The I2S mode
bit and a 10-bit address. The SPI port knows how many data can be used to accept any number of bits up to 24.
bytes to expect based on the address that is received in the first
2 bytes. Figure 9 shows the AD71028’s right-justified mode. LRCLK is
high for the left channel and low for the right channel. Data is
INITIALIZATION sampled on the rising edge of BCLK. The start of data is delayed
Power-Up Sequence from the LRCLK edge by 16, 12, or 8 BCLK intervals, depending
The AD71028 has a built-in power-up sequence that initializes on the selected word length. The default word length is 24 bits;
the contents of all internal RAM. During this time, the SPI other word lengths are set by writing to Bits <1:0> of the control
parameter RAM is filled with values from its associated boot register. In right-justified mode, it is assumed that there are 64
ROM. The data memories are also cleared during this time. BCLKs per frame.

The boot sequence lasts for 1024 MCLK cycles and starts on the Figure 10 shows the DSP serial port mode. LRCLK must pulse
rising edge of the RESETB pin. The user should avoid writing to high for at least one bit clock period before the MSB of the left
or reading from the SPI registers during this period of time. channel is valid, and LRCLK must pulse high again for at least
one bit clock period before the MSB of the right channel is
SERIAL DATA INPUT PORT valid. Data is sampled on the falling edge of BCLK. The DSP
The AD71028’s flexible serial data input port accepts data in serial port mode can be used with any word length up to 24 bits.
twos complement, MSB-first format. The left channel data field In this mode, it is the responsibility of the DSP to ensure that
always precedes the right channel data field. The serial mode is the left data is transmitted with the first LRCLK pulse, and that
set by using mode select bits in the SPI control register. In all synchronism is maintained from that point forward.
modes except the right-justified mode, the serial port will
accept an arbitrary number of bits up to a limit of 24 (extra bits
will not cause an error, but they will be truncated internally). In
right-justified mode, SPI control register bits are used to set the
word length to 16, 20, or 24 bits. The default on power-up is
24-bit mode. Proper operation of the right-justified mode
requires that there be exactly 64 BCLKs per audio frame.

Rev. 0 | Page 14 of 20
 AD71028
LRCLK LEFT CHANNEL RIGHT CHANNEL
BCLK

04482-0-007
SDATA MSB LSB MSB LSB

1 /FS

Figure 7. Left-Justified Mode—16 Bits to 24 Bits per Channel

LRCLK LEFT CHANNEL

RIGHT CHANNEL
BCLK

04482-0-008
SDATA MSB LSB MSB LSB

1 /FS

Figure 8. I2S Mode—16 Bits to 24 Bits per Channel

LEFT CHANNEL RIGHT CHANNEL

LRCLK
BCLK

04482-0-009
SDATA MSB LSB MSB LSB

1 /FS

Figure 9. Right-Justified Mode—16 Bits to 24 Bits per Channel

LRCLK
BCLK

04482-0-010
MSB LSB MSB LSB
SDATA
1 /FS

Figure 10. DSP Mode—16 Bits to 24 Bits per Channel

NOTES

1. DSP mode does not identify the channel.

2. LRCLK normally operates at FS; in DSP mode, LRCLK operates at 2 × FS.

3. BCLK frequency is normally 64 × LRCLK but may be operated in burst mode.

Rev. 0 | Page 15 of 20
AD71028

ANALOG OUTPUT SECTION

Figure 11 shows the block diagram of the analog output section Since the VREF input effectively multiplies the signal, care must
(one of two channels). A series of current sources is controlled be taken to ensure that no ac signals appear on this pin. This
by a digital Σ-∆ modulator. Depending on the digital code from can be accomplished by using a large decoupling capacitor in
the modulator, each current source is connected to the sum- the VREF external resistive divider circuit. If the VREF signal is
ming junction of either a positive I-to-V converter or a negative derived by dividing the 5 V analog supply, the time constant of
I-to-V converter. Two extra current sources that push instead of the divider must effectively filter any noise on the supply. If the
pull are added to set the midscale common-mode voltage. VREF signal is derived from an unregulated power amplifier
supply, the time constant must be longer because the ripple on
All current sources are derived from the VREF input pin. The the amplifier supply voltage will presumably be greater than in
gain of the AD71028 is directly proportional to the magnitude the case of the 5 V supply.
of the current sources, and therefore the gain of the AD71028 is
proportional to the voltage on the VREF pin. The nominal The AD71028 should be used with an external third-order filter
VREF voltage should be set to 2.5 V, using a simple resistive on each output channel. The circuit shown in Figure 12
divider from the analog supply. The VREF and biasing circuits combines a third-order filter and a single-ended-to-differential
are common to both DACs. converter in the same circuit. The values shown are for a
100 kHz Bessel filter. The use of a Bessel filter is important to
maintain the time alignment of the pilot to the carrier. If these
signals are not in phase, a loss of separation will occur.
IREF IREF

The outputs can also be used single-ended, with some loss of

performance; the DAC distortion may become significantly
OUT+ OUT–
poorer, although the SNR will remain quite high.
VREF IN
IREF + DIG_IN IREF – DIG_IN For best performance, a large (>10 µF) capacitor should be
BIAS connected between the FILTCAP pin and analog ground.

FROM DIGITAL
Σ–∆ MODULATOR
SWITCHED CURRENT
(DIG_IN) 3.01kΩ 270pF
04482-0-011

SOURCES 2.80kΩ
–INPUT
1.50kΩ
1nF
549Ω
OUT
Figure 11. Internal DAC Analog Architecture
2.7nF
499kΩ 2.2nF
+INPUT

04482-0-012
806Ω
1.00kΩ 820pF

Figure 12. Recommended External Analog Filter for Each Channel

Rev. 0 | Page 16 of 20
 AD71028

OUTLINE DIMENSIONS
0.75 1.60 9.00 BSC
0.60 MAX SQ
0.45
48 37
1 36

SEATING PIN 1
PLANE
10° TOP VIEW 7.00
1.45 6° (PINS DOWN) BSC SQ
1.40 2°
0.20
1.35 0.09 VIEW A
7°
3.5 ° 12 25
0° 13 24
0.15
0.05 SEATING 0.08 MAX 0.50 0.27
PLANE COPLANARITY BSC 0.22
VIEW A 0.17
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026BBC

Figure 13. 48-Lead Low Profile Quad Flatpack [LQFP]

(ST-48)
Dimensions Shown in Millimeters

ORDERING GUIDE
Model Temperature Range Package Description Package Option
AD71028JST –0°C to +70°C 48-Lead LQFP ST-48
AD71028JSTRL –0°C to +70°C 48-Lead LQFP ST-48 on 13” Reel

Rev. 0 | Page 17 of 20
AD71028

NOTES

Rev. 0 | Page 18 of 20
 AD71028

NOTES

Rev. 0 | Page 19 of 20
AD71028

NOTES

© 2004 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D04482–0–1/04(0)

Rev. 0 | Page 20 of 20