Led Driver 12 Pin

D atas he et
A S11 30
1 32 - L ED C r o s s -P le x in g Dr iv e r w i th sc r o l lin g F u n c tio n
1 General Description
2 Key Features
The AS1130 is a compact LED driver for 132 single LEDs. The
devices can be programmed via an IC compatible interface.
1MHz IC-Compatible Interface
The AS1130 offers a 12x11 LED-Matrix with 1/12 cycle rate. The
required lines to drive all 132 LEDs are reduced to 12 by using the
cross-plexing feature optimizing space on the PCB. The whole LEDMatrix driving 132 LEDs can be analog dimmed from 0 to 30mA in
256 steps (8 bit).
132 LEDs in Dot Matrix
Additionally each of the 132 LEDs can be dimmed individually with 8bit allowing 256 steps of linear dimming. To reduce CPU usage up to
6 frames can be stored with individual time delays between frames to
play small animations automatically.
8-bit Dot Correction for optimize RGB LED Operation
The AS1130 operates from 2.7V to 5.5V and features a very low
shutdown and operational current.
up to 6 Frames Memory for PWM sets
The device offers a programmable IRQ pin. Via a register it can be

set on what event (CP request, Interface time out, Error-detection,
POR, End of Frame or End of Movie) the IRO is triggered.
Minimum PCB space required
Open and Shorted LED Error Detection

Low-Power Shutdown Current
Individual 8-bit LED PWM Control
8-bit Analog Brightness Control
Programmable IRQ pin
Scroll Function
up to 36 Frames Memory for Animations
Supply Voltage Range: 2.7V to 5.5V
Available packages:
Also hardware scroll Function is implemented in the AS1130.

The device is available in an ultrasmall 20-pin WL-CSP and an easy
to solder 28-pin SSOP/TSSOP package.
- 20-pin WL-CSP
- 28-pin SSOP/TSSOP
3 Applications
Figure 1. AS1130 - Typical Application
www.ams.com/LED-Driver-ICs/AS1130
The AS1130 is ideal for dot matrix displays in mobile phones, personal electronic and toys.
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AS1130
Datasheet - P i n o u t
4 Pinout
Pin Assignments
Figure 2. Pin Assignments (Top View)
28-pin SSOP/TSSOP
20-pin WL-CSP
Pin Descriptions
Table 1. Pin Descriptions
Pin Number
28-pin
20-pin WL-CSP
SSOP / TSSOP
A3
1, 7, 14, 22, 28
Pin Name
Description
GND
Ground
Reset Input. Pull this pin to logic low to reset all control registers (set to default
values). For normal operation pull this pin to VDD.
IC Address. Connect to external resistor for IC address selection. Up to 8
devices can be connected on one bus. (see Table 6 on page 12)
Serial-Data I/O. Open drain digital I/O IC data pin.
Serial-Clock Input
Positive Supply Voltage. Connect to a +2.7V to +5.5V supply. Bypass this pin
with 10F capacitance to GND.
Synchronization Clock Input or Output. The SYNC frequency for Input and
Output is 1MHz. For SYNC_OUT the frequency can be reduced to 32kHz.
Interrupt Request. Programmable Open drain digital Output. It can be set via
an register after which event (Interface Timeout, POK, CP_Request, Error
Detection, End of Frame or End of Movie) the pin triggers an Interrupt Request.
C3
13
RSTN
D1
17
ADDR
D2
D3
16
15
SDA
SCL
B3
3, 10, 18, 19, 26
VDD
D4
12
SYNC
D5
11
IRQ
A1, A2, A4, A5,

B1, B2, B4, B5,
C1, C2, C4, C5
25, 27, 2, 4,
23, 24, 5, 6,
21, 20, 9, 8
CS0, CS1, CS6, CS7,

CS2, CS3, CS8, CS9, Sinks and Sources for 132 LEDs.
CS4, CS5, CS10, CS11
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AS1130
Datasheet - A b s o l u t e M a x i m u m R a t i n g s
5 Absolute Maximum Ratings

Stresses beyond those listed in Table 2 may cause permanent damage to the device. These are stress ratings only, and functional operation of
the device at these or any other conditions beyond those indicated in Section 6 Electrical Characteristics on page 4 is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Table 2. Absolute Maximum Ratings
Parameter
Min
Max
Units
-0.3
-0.3
7 or
VDD + 0.3
500
mA
Comments
Electrical Parameters
VDD to GND
All other pins to GND
Sink Current
Segment Current
Input Current (latch-up immunity)
-100
100
mA
100
mA
Norm: JEDEC 78
kV
Norm: MIL 883 E method 3015
Electrostatic Discharge
Electrostatic Discharge HBM
Temperature Ranges and Storage Conditions

Junction Temperature
Storage Temperature Range
+150
-55
+125
for 20-pin WL-CSP
-55
+150
for 28-pin SSOP/TSSOP

Norm IPC/JEDEC J-STD-020
The lead finish for Pb-free leaded packages
is matte tin (100% Sn).
20-pin
WL-CSP
Norm IPC/JEDEC J-STD-020
20-pin
WL-CSP
Represents an unlimited floor life time
28-pin
SSOP/
TSSOP
Represents a max. floor life time of 168h
Package Body Temperature
Humidity non-condensing
+260
85
Moisture Sensitive Level
28-pin
SSOP/
TSSOP
The reflow peak soldering temperature (body temperature) is specified according IPC/JEDEC J-STD-020 Moisture/Reflow Sensitivity
Classification for Nonhermetic Solid State Surface Mount Devices
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AS1130
Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s
6 Electrical Characteristics
VDD = 2.7V to 5.5V, typ. values are at TAMB = +25C (unless otherwise specified). All limits are guaranteed. The parameters with min and max
values are guaranteed with production tests or SQC (Statistical Quality Control) methods.
Table 3. Electrical Characteristics
Symbol
Parameter
Max
Unit
TAMB
Operating Temperature Range
-40
85
TJ
Operating Junction Temperature Range
-40
125
VDD
Operating Supply Voltage
2.7
5.5
IDD
Conditions
Operating Supply Current
Min
Typ
All current sources turned ON

@ VDD = 5.5V
340
All current sources turned OFF

@ VDD = 5.5V
0.5
mA
IDDSSD
Software Shutdown Supply Current
All digital inputs at VDD or GND

@ VDD = 5.5V
15
IDDFSD
Full Shutdown Supply Current
Pin RSTN = 0V, TAMB = +25C
0.1
360
mA
32
mA
IDIGIT
ISEG
ISEG
Digit Drive Sink Current

1
(Drive capability of all sources of one digit )

2
Segment Drive Source Current LED
VOUT = 1.8V to VDD-400mV
28
Segment Drive Current Matching LED
30
1
%
%
Device to Device Current Matching LED
VOUT = 1.8V, VDD = 3.3V
ILEAK
Leakage Output Current
All current sources OFF, VOUT = 0V,

VDD = 5.5V, TAMB = +25C
0.005
ILNR
Line Regulation
VOUT = 1.8V
0.25
%/V
0.5
ILDR
Load Regulation
VOUT = 1.8V to VDD-400mV
0.25
%/V
VDSSAT
Saturation Voltage
Current = 30mA, VDD = 3.3V
200
mV
RDSON(N)
Resistance for NMOS
0.3
VDD0.4
Open Detection Level Threshold
fOSC
Oscillator Frequency
Display Scan Rate
tRSTN
Reset Pulse Width Low
12x11 matrix
VDD0.1
770
900
mV
0.9
1.1
MHz
0.29
0.33
0.36
kHz
Short Detection Level Threshold

fREFRESH
500
ns
1. guaranteed by design
2.
I max Imin
I SEG = --------------------------- 100
I max + I min
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AS1130
Table 4. Logic Inputs/Outputs Characteristics

Symbol
IIH, IIL
Parameter
Conditions
Logic Input Current
VIN = 0V or VDD
VIH
CMOS Logic High Input Voltage
VIL
CMOS Logic Low Input Voltage
VI
CMOS Hysteresis Voltage
Min
-1
Typ
Max
1
0.7 x VDD
V
0.3 x VDD
0.3
Unit
A
V
V
VIH
Mobile Logic High Input Voltage
VIL
Mobile Logic Low Input Voltage
VI
Hysteresis Voltage
VOL(SDA)
SDA Output Low Voltage
ISINK = 3mA
0.4
VOL(IRQ)
VOL(SYNC_
IRQ Output Low Voltage
ISINK = 3mA
0.4
Sync Clock Output Low Voltage
ISINK = 1mA
0.4
Sync Clock Output High Voltage
ISOURCE = 1mA
VDD-0.4
400
pF
Max
Unit
1000
kHz
OUT)
VOH(SYNC
_OUT)
1.6
0.6
0.1
Capacitive Load for Each Bus Line
V
V
1. available on request, See Ordering Information on page 38

Table 5. IC Timing Characteristics
Symbol
Parameter
Conditions
Min
Typ
fSCL
SCL Frequency
100
tBUF
1.3
260
ns
tLOW
Bus Free Time Between STOP and START Conditions

Hold Time for Repeated
START Condition
SCL Low Period
500
ns
tHIGH
SCL High Period
260
ns
Setup Time for Repeated

START Condition
260
ns
100
ns
tHOLDSTART
tSETUPSTART
tSETUPDATA Data Setup Time

tHOLDDATA Data Hold Time
70
ns
tRISE(SCL)
SCL Rise Time
120
ns
tRISE(SCL1)
SCL Rise Time after Repeated START Condition and After

an ACK Bit
120
ns
tFALL(SCL)
SCL Fall Time
120
ns
tRISE(SDA)
SDA Rise Time
120
ns
tFALL(SDA)
SDA Fall Time
120
ns
tSETUPSTOP STOP Condition Setup Time

tSPIKESUP Pulse Width of Spike Suppressed
260
ns
6
ns
Note: The Min / Max values of the Timing Characteristics are guaranteed by design.
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AS1130
Figure 3. Timing Diagram
SDI
tBUF
tHOLDSTART
tHIGH
tHOLDSTART
tR
tLOW
tSPIKESUP
tSETUPDATA
tF
tSETUPSTOP
tSETUPSTART
SCL
STOP START
tHOLDDATA
Repeated
START
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AS1130
Datasheet - Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s
7 Typical Operating Characteristics

Figure 5. Segment Drive Current vs. Temperature
32
32
Segment Drive Source Current (mA)
Figure 4. Segment Drive Current vs. Supply Voltage
31.5
31
30.5
30
29.5
29
-45C
28.5
+25C
+85C
28
2.7
3.1
3.5
3.9
4.3
4.7
5.1
31.5
31
30.5
30
29.5
Vdd = 2.7V
29
Vdd = 3.3V
Vdd = 4.5V
28.5
Vdd = 5.5V
28
5.5
-45
-25
-5
Supply Voltage (V)
35
55
75
Figure 7. RONNMOS vs. Supply Voltage
Figure 6. Segment Drive Current vs. Output Voltage

32
0.5
Vdd = 2.7V
31.5
-45C
Vdd = 3.3V
+25C
0.4
Vdd = 4.5V
31
+85C
Vdd = 5.5V
30.5
RNMOS ()
15
Temperature (C)
30
29.5
0.3
0.2
29
0.1
28.5
28
0
1.6
2.4 2.8 3.2 3.6
4.4 4.8 5.2 5.6
2.7
3.1
Output Voltage (V)
3.5
3.9
4.3
4.7
5.1
5.5
Supply Voltage (V)
Figure 8. Open Detection Level vs. Supply Voltage
Figure 9. Short Detection Level vs. Supply Voltage
300
0.9
+25C
250
0.85
+85C
Short Detection Level (V)
Open Detection Level (mV)
-45C
200
150
100
50
0.8
0.75
0.7
-45C
0.65
+25C
+85C
0.6
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
Supply Voltage (V)
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
Supply Voltage (V)
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AS1130
Datasheet - Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s
Figure 11. CMOS Logic Input Levels vs. Temperature
3.5
3.5
Logic Input Voltage Level (V)
Figure 10. CMOS Logic Input Levels vs. Supply Voltage
3
2.5
2
1.5
1
Logic High
0.5
3
2.5
2
1.5
1
Logic High
0.5
Logic Low
Logic Low
0
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
-45
-25
-5
Supply Voltage (V)
Figure 12. MOBILE Logic Input Levels vs. Supply Voltage
35
75
1.5
0.5
Logic High
1.5
0.5
Logic High
Logic Low
Logic Low
0
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
-45
-25
Supply Voltage (V)
-5
15
35
55
75
Temperature (C)
Figure 14. Oscillator Frequency vs. Supply Voltage
Figure 15. Oscillator Frequency vs. Temperature
1.1
1.1
1.05
1.05
fOSC (kHz)
fOSC (kHz)
55
Figure 13. MOBILE Logic Input Levels vs. Temperature
15
Temperature (C)
0.95
0.95
Vdd = 2.7V
- 45C
Vdd = 3.3V
+ 25C
Vdd = 4.5V
+ 85C
Vdd = 5.5V
0.9
0.9
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
Supply Voltage (V)
-45
-25
-5
15
35
55
75
Temperature (C)
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AS1130
Datasheet - D e t a i l e d D e s c r i p t i o n
8 Detailed Description
Figure 16. AS1130 - Block Diagram
Cross-Plexing Theorem
The cross-plexing theorem is using the fact that a LED has a forward and backward direction. A LED will only glow if there is a current flowing in
forward direction. A parallel LED in backward direction will block the current flow. This effect is used in a cross-plexed matrix of LEDs.
Each CSx pin (CS0 to CS11) can be switched to VDD via the internal current source (high), to GND (low) or not connected (highZ).
The mode of operation which is controlled by an internal state machine looks like following. CS0 is switched to GND and all other CSx pins (CS1
to CS11) are controlled according to the settings in the On/Off Frame and Blink & PWM registers (see Table 7 on page 14).
Than CS1 is switched to GND and all other CSx pins (CS0 and CS2 to CS11) are controlled according to the settings in the On/Off Frame and
Blink & PWM registers.
In this manner all LEDs in the matrix are scanned and turned on/off depending on the register settings.
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AS1130
IC Interface
The AS1130 supports the IC serial bus and data transmission protocol in fast mode at 1MHz. The AS1130 operates as a slave on the IC bus.
The bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and generates the START and
STOP conditions. Connections to the bus are made via the open-drain I/O pins SCL and SDA.
Figure 17. IC Interface Initialization
1
SCL
SDA
AD2 AD1 AD0 R/W
D15 D14 D13 D12 D11 D10
D9
D8
AD2, AD1 and AD0 are defined by the pin ADDR (see IC Device Address Byte on page 12)
Figure 18. Bus Protocol
MSB
SDI
ACK from
Receiver
Slave Address
R/W
Direction Bit
ACK from
Receiver
SCL
9
ACK
START
3-7
ACK
Repeat if More Bytes Transferred
STOP or
Repeated
START
The bus protocol (as shown in Figure 18) is defined as:

- Data transfer may be initiated only when the bus is not busy.
- During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is
HIGH will be interpreted as control signals.
The bus conditions are defined as:
- Bus Not Busy. Data and clock lines remain HIGH.
- Start Data Transfer. A change in the state of the data line, from HIGH to LOW, while the clock is HIGH, defines a START condition.
- Stop Data Transfer. A change in the state of the data line, from LOW to HIGH, while the clock line is HIGH, defines the STOP condition.
- Data Valid. The state of the data line represents valid data, when, after a START condition, the data line is stable for the duration of the
HIGH period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data bytes transferred between START and STOP conditions is not limited and is determined
by the master device. The information is transferred byte-wise and each receiver acknowledges with a ninth-bit. Within the IC bus specifications a high-speed mode (3.4MHz clock rate) is defined.
- Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse that is associated with this acknowledge bit. A device that acknowledges must pull down the
SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge
clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to
enable the master to generate the STOP condition.
- Figure 18 on page 10 details how data transfer is accomplished on the IC bus. Depending upon the state of the R/W bit, two types of
data transfer are possible:
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AS1130
- Master Transmitter to Slave Receiver. The first byte transmitted by the master is the slave address, followed by a number of data bytes.
The slave returns an acknowledge bit after the slave address and each received byte.
- Slave Transmitter to Master Receiver. The first byte, the slave address, is transmitted by the master. The slave then returns an acknowledge bit. Next, a number of data bytes are transmitted by the slave to the master. The master returns an acknowledge bit after all received
bytes other than the last byte. At the end of the last received byte, a not-acknowledge is returned. The master device generates all of the
serial clock pulses and the START and STOP conditions. A transfer is ended with a STOP condition or a repeated START condition. Since
a repeated START condition is also the beginning of the next serial transfer, the bus will not be released.
The AS1130 can operate in the following slave modes:
- Slave Receiver Mode. Serial data and clock are received through SDA and SCL. After each byte is received, an acknowledge bit is transmitted. START and STOP conditions are recognized as the beginning and end of a serial transfer. Address recognition is performed by
hardware after reception of the slave address and direction bit.
- Slave Transmitter Mode. The first byte (the slave address) is received and handled as in the slave receiver mode. However, in this mode
the direction bit will indicate that the transfer direction is reversed. Serial data is transmitted on SDA by the AS1130 while the serial clock
is input on SCL. START and STOP conditions are recognized as the beginning and end of a serial transfer.
Command Byte
The AS1130 operation, (see Table 13 on page 20) is determined by a command byte (see Table 19).
Figure 19. Command Byte
MSB
LSB
A7
A6
A5
A4
A3
A2
A1
A0
Figure 20. Command and Single Data Byte received by AS1130

From Master to Slave
AS1130 Registers
From Slave to Master
Slave Address
A7
A6
R/W A
A5
A4
A3
A2
A1
A0
D7
D6
Command Byte
D5
D4
D3
D2
D1
D0
Data Byte
1 Byte
Acknowledge
from AS1130
Acknowledge
from AS1130
Acknowledge
from AS1130
Autoincrement
Memory Word
Address
Figure 21. Setting the Pointer to a Address Register to select a Data Register for a Read Operation
AS1130 Registers
Slave Address
R/W A
Acknowledge
from AS1130
A7
A6
A5
A4
A3
A2
A1
A0
Command Byte
Acknowledge
from AS1130
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AS1130
Figure 22. Reading n Bytes from AS1130

Autoincrement
Memory Word
Address

Acknowledge
from AS1130
Acknowledge
from Master
Stop reading
Not Acknowledge
from Master
n Bytes
S
R/W A
Slave Address
D7
First Data Byte
D6
D5
D4
D3
D2
D1
D0
/A
Second Data Byte
D7
D6
D5
D4
D3
D2
D1
D0
Autoincrement
to next address
AS1130 Registers
IC Device Address Byte

The address byte (see Figure 23) is the first byte received following the START condition from the master device.
Figure 23. IC Device Address Byte
address:
MSB
LSB
0*
AD2
AD1
AD0
R/W
*) can be factory set to 1
- The bit 1, 2 and 3 of the address byte are defined through the resistor @ the device select pin ADDR (see Table 6 on page 12). A
maximum of 8 devices with the same pre-set code can be connected on the same bus at one time.
- The last bit of the address byte (R/W) define the operation to be performed. When set to a 1 a read operation is selected; when set to a 0
a write operation is selected.
- IC Common address. All devices are responding on the address 0111111 if the function is enabled in the register AS1130 Config
Register (0x06) on page 25.
Following the START condition, the AS1130 monitors the IC bus, checking the device type identifier being transmitted. Upon receiving the
address code, and the R/W bit, the slave device outputs an acknowledge signal on the SDA line.
Table 6. Device Address
I2C Address
Bit
Bit Name
3:1
i2c_addr
Default
000
Access
Description
Defines the IC address of one device via an external resistor on pin ADDR
000: 1M or floating
001: 470k
010: 220k
011: 100k
100: 47k
101: 22k
110: 10k
111: 4.7k or GND
The pin ADDR is scanned after start up (POR) and defines the address for the device. The device reacts to this address until a hardware reset
(low on pin RSTN) is performed or the power-on-reset (POR) triggers again.
Note: The internal address decoder needs 5ms to identify the address and to set up the device for this address.
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AS1130
Initial Power-Up
On initial power-up, the AS1130 registers are reset to their default values, the display is blanked, and the device goes into shutdown mode. At
this time, all registers should be programmed for normal operation. To bring the device into normal operation the following sequence needs to be
performed.
Start-up sequence:
- Power-up the AS1130 (connect VDD to a source), the devices is in shutdown;
- After 5ms the address of the AS1130 is valid and the first IC command can be send.
- Define RAM Configuration; bit mem_conf in the AS1130 Config Register (see Table 20 on page 25)
- On/Off Frames
- Blink & PWM Sets
- Dot Correction, if specified
- Define Control Register (see Table 13 on page 20)
- Current Source
- Display options
- Display picture / play movie
- To light up the LEDs set the shdn bit to 1 for normal operation mode (see Table 23 on page 26).
Shutdown Mode
The AS1130 device features two different shutdown modes. A software shutdown via shutdown register (see Shutdown & Open/Short
Register Format on page 26) and a hardware shutdown via the RSTN pin.
The software shutdown disables all LEDs and stops the internal operation of the logic. A shutdown mode via the RSTN pin additionally powers
down the power-on-reset (POR) of the device. In this shutdown mode the AS1130 consumes only 100nA (typ.).
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AS1130
Datasheet - R e g i s t e r D e s c r i p t i o n
9 Register Description
Register Selection
Within this register the access to one of the RAM sections, the Dot Correction or to the Control register is selected. After one section is selected
this section is valid as long as an other section is selected.
Table 7. Register Selection Address Map
Register Section
Address
Data
HEX A7 A6 A5 A4 A3 A2 A1 A0 HEX D7 D6 D5 D4 D3 D2 D1 D0
NOP
0x00
On/Off Frame 0
0x01
On/Off Frame 1
0x02
On/Off Frame 2
0x03
....
.....
Description
No operation
On/Off Information for

each Frame (up to 36
Frames)
On/Off Frame 34
0x23
On/Off Frame 35
0x24
Blink & PWM Set 0
0x40
0x41
Blink & PWM Set 2
0x42
Blink & PWM Set 3
0x43
Blink & PWM Set 4
0x44
Blink & PWM Set 5
0x45
Dot Correction
0x80
Selection of Dot
Correction Register
Control Register
0xC0
Selection of
Control Register
Blink & PWM Set 1 0xFD
Blink & PWM

Information Sets (up to
6 sets)
Data Definition of the single frames

One frame consists of 2 datasets, the On/Off dataset and the Blink & PWM dataset. Where more On/Off frames can be linked to one PWM set.
Depending on the used PWM sets more or less On/Off frames can be stored inside the AS1130 (see Table 8).
Each On/Off Frame needs to define the used Blink & PWM dataset.
Table 8. RAM Configuration
RAM Configuration
Blink & PWM Set
On/Off Frame
On/Off Frame
with Dot Correction
35..0
34..0
1,0
29..0
28..0
2,1,0
23..0
22..0
3..0
17..0
16..0
4..0
11..0
10..0
5..0
5..0
4..0
Its necessary to define the RAM configuration before data can be written to the frame datasets. The RAM configuration is defined in the AS1130
config register (see Table 20 on page 25) via bit 2:0 and bit 4 for Dot Correction.
Note: After a first write of data to the frames, the configuration is locked in the AS1130 config register and can be changed only after a reset
of the device. A change of the RAM configuration requires to re-write the frame datasets.
Revision 1.09
14 - 39
AS1130
12x11 LED Matrix

The AS1130 is configured to control one big LED matrix.
Figure 24. AS1130 - Dot Matrix Structure
In Table 9 its described which databit represents which LED in the matrix. Per default all databits are 0, meaning no LED is on. A 1 puts the
LED on.
Each Current Segment of the LED Matrix consists of 11 LEDs, therefore 2 bytes of data are required for one Current Segment. CS0 is defined by
the two bytes with address 0x00 and 0x01 and also includes the address of the used Blink & PWM dataset for this frame.
Table 9. LEDs On/Off Frame Register Format
Segment
Address
Data
HEX
A7
A6
A5
A4
A3
A2
A1
A0
0x00
0x01
0x02
0x03
0x04
LED
27
LED
26
LED
25
LED
24
LED
23
0x05
Revision 1.09
D7 D6 D5 D4
LED LED LED LED
07
06
05
04
PWM PWM PWM X
[2]
[1]
[0]
LED LED LED LED
17
16
15
14
D3
LED
03
X
LED
13
D2
LED
02
LED
0A
LED
12
LED
1A
LED
22
LED
2A
D1
LED
01
LED
09
LED
11
LED
19
LED
21
LED
29
D0
LED
00
LED
08
LED
10
LED
18
LED
20
LED
28
15 - 39
AS1130
Table 9. LEDs On/Off Frame Register Format

Segment
Address
Data
HEX
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
0x06
LED
37
LED
36
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
LED
35
D4
LED
34
D3
LED
33
D2
D1
D0
LED
32
LED
3A
LED
31
LED
39
LED
30
LED
38
LED
47
LED
46
LED
45
LED
44
LED
43
LED
42
LED
4A
LED
41
LED
49
LED
40
LED
48
LED
57
LED
56
LED
55
LED
54
LED
53
LED
52
LED
5A
LED
51
LED
59
LED
50
LED
58
LED
67
LED
66
LED
65
LED
64
LED
63
LED
62
LED
6A
LED
61
LED
69
LED
60
LED
68
LED
77
LED
76
LED
75
LED
74
LED
73
LED
72
LED
7A
LED
71
LED
79
LED
70
LED
78
LED
87
LED
86
LED
85
LED
84
LED
83
X
LED
82
LED
8A
LED
81
LED
89
LED
80
LED
88
0x11
0x12
LED
97
LED
96
LED
95
LED
94
LED
93
LED
92
LED
91
LED
90
0x13
LED
A6
LED
A5
LED
A4
LED
A3
LED
9A
LED
A2
LED
99
LED
A1
LED
98
LED
A0
0x14
LED
A7
0x15
LED
B7
LED
B6
LED
B5
LED
B4
LED
B3
LED
AA
LED
B2
LED
A9
LED
B1
LED
A8
LED
B0
0x16
0x17
LED
BA
LED
B9
LED
B8
The Blink & PWM sets contain blink on/off and the digital PWM information for each LED in the matrix. The number of PWM datasets is flexible
according to the defined RAM configuration (see Figure 8 on page 14).
In the blink register (see Table 10) every single LED can be set to blink. The blink period is set in the display option register (see Display
Option Register Format on page 24).
Table 10. LEDs Blink Frame Register Format
Segment
Address
Data
HEX
A7
A6
A5
A4
A3
A2
A1
A0
0x00
0x01
0x02
0x03
D7
LED
07
D6
LED
06
D5
LED
05
D4
LED
04
D3
LED
03
LED
17
LED
16
LED
15
LED
14
LED
13
Revision 1.09
D2
LED
02
LED
0A
LED
12
LED
1A
D1
LED
01
LED
09
LED
11
LED
19
D0
LED
00
LED
08
LED
10
LED
18
16 - 39
AS1130
Table 10. LEDs Blink Frame Register Format

Segment
Address
Data
HEX
A7
A6
A5
A4
A3
A2
A1
A0
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
D7
LED
27
D6
LED
26
D5
LED
25
D4
LED
24
D3
LED
23
LED
37
LED
36
LED
35
LED
34
LED
33
LED
47
LED
46
LED
45
LED
44
LED
43
LED
57
LED
56
LED
55
LED
54
LED
53
LED
67
LED
66
LED
65
LED
64
LED
63
0x0D
0x0E
LED
77
LED
76
LED
75
LED
74
LED
73
0x0F
0x10
LED
87
LED
86
LED
85
LED
84
LED
83
0x11
0x12
LED
97
LED
96
LED
95
LED
94
LED
93
0x13
0x14
LED
A7
LED
A6
LED
A5
LED
A4
LED
A3
0x15
0x16
LED
B7
LED
B6
LED
B5
LED
B4
LED
B3
0x17
Revision 1.09
D2
LED
22
LED
2A
LED
32
LED
3A
D1
LED
21
LED
29
D0
LED
20
LED
28
LED
31
LED
39
LED
30
LED
38
LED
42
LED
4A
LED
41
LED
49
LED
40
LED
48
LED
52
LED
5A
LED
51
LED
59
LED
50
LED
58
LED
62
LED
6A
LED
61
LED
69
LED
60
LED
68
LED
72
LED
7A
LED
71
LED
79
LED
70
LED
78
LED
82
LED
8A
LED
81
LED
89
LED
80
LED
88
LED
92
LED
9A
LED
91
LED
99
LED
90
LED
98
LED
A2
LED
AA
LED
A1
LED
A9
LED
A0
LED
A8
LED
B2
LED
BA
LED
B1
LED
B9
LED
B0
LED
B8
17 - 39
AS1130
In the PWM register (see Table 11) the brightness of every single LED can be set via a 8bit PWM (255 steps).
Table 11. LEDs PWM Register Format
Address
Segment
LED00
LED01
LED02
LED03
LED04
LED05
LED06
LED07
LED08
LED09
LED0A
LED10
LED11
LED12
LED13
LED14
LED15
LED16
LED17
LED18
LED19
LED1A
LED20
LED21
LED22
LED23
LED24
LED25
LED26
LED27
LED28
LED29
LED2A
LED30
LED31
LED32
LED33
LED34
LED35
LED36
LED37
LED38
LED39
LED3A
HEX
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0x38
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
0x40
0x41
0x42
0x43
Data
A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
1
1
0
0
0
0
0
0
1
1
0
0
1
0
0
0
1
1
0
1
0
0
0
0
1
1
0
1
1
0
0
0
1
1
1
0
0
0
0
0
1
1
1
0
1
255 steps for intensity each single LED
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
1
0
0
1
0
0
1
0
0
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
0
0
1
0
0
1
1
1
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
1
0
0
1
0
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
0
1
1
0
0
0
0
1
0
1
1
0
1
0
0
1
0
1
1
1
0
0
0
1
0
1
1
1
1
0
0
1
1
0
0
0
0
0
0
1
1
0
0
0
1
0
0
1
1
0
0
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
0
0
0
1
1
0
1
0
1
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
1
0
0
1
1
1
0
0
0
0
0
1
1
1
0
0
1
0
0
1
1
1
0
1
0
0
0
1
1
1
0
1
1
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
0
0
1
1
1
1
1
0
0
0
1
1
1
1
1
1
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
1
0
0
0
0
1
0
0
1
0
0
0
0
1
1
Revision 1.09
18 - 39
AS1130
Table 11. LEDs PWM Register Format

Address
Segment
LED40
LED41
LED42
LED43
LED44
LED45
LED46
LED47
LED48
LED49
LED4A
LED50
LED51
LED52
LED53
LED54
LED55
LED56
LED57
LED58
LED59
LED5A
HEX
0x44
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x50
0x51
0x52
0x53
0x54
0x55
0x56
0x57
0x58
0x59
LEDA0
LEDA1
LEDA2
LEDA3
LEDA4
LEDA5
LEDA6
LEDA7
LEDA8
LEDA9
LEDA0
LEDB0
LEDB1
LEDB2
LEDB3
LEDB4
LEDB5
LEDB6
LEDB7
LEDB8
LEDB9
LEDBA
0x86
0x87
0x88
0x89
0x8A
0x8B
0x8C
0x8D
0x8E
0x8F
0x90
0x91
0x92
0x93
0x94
0x95
0x96
0x97
0x98
0x99
0x9A
0x9B
Data
A7 A6 A5 A4 A3 A2
0
1
0
0
0
1
0
1
0
0
0
1
0
1
0
0
0
1
0
1
0
0
0
1
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
1
0
0
0
1
0
1
0
0
0
1
0
1
0
0
0
1
0
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
0
1
0
1
1
0
................
1
0
0
0
0
1
1
0
0
0
0
1
1
0
0
0
1
0
1
0
0
0
1
0
1
0
0
0
1
0
1
0
0
0
1
0
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
1
1
0
0
1
0
1
1
0
0
1
0
1
1
0
0
1
0
1
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Revision 1.09
19 - 39
AS1130
Dot Correction Register

The AS1130 offers a feature to define a correction factor for the analog current for every segment. This correction factor is called Dot Correction
and is defined in the Dot Correction register (see Table 12). The Dot Correction Register is selected via data 128 on addr 253.
Table 12. Dot Correction Register Format
Segment
0
1
2
3
4
5
6
7
8
9
A
B
Address
HEX
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
A7
0
0
0
0
0
0
0
0
0
0
0
0
A6
0
0
0
0
0
0
0
0
0
0
0
0
A5
0
0
0
0
0
0
0
0
0
0
0
0
A4
0
0
0
0
0
0
0
0
0
0
0
0
Data
A3
0
0
0
0
0
0
0
0
1
1
1
1
A2
0
0
0
0
1
1
1
1
0
0
0
0
A1
0
0
1
1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
0
1
0
1
D7
D6
D5 D4 D3 D2
8 bit Dot Correction
D1
D0
Control-Registers
The AS1130 device contains 14 control-registers which are listed in Table 13. All registers are selected using a 8-bit address word, and communication is done via the serial interface. Select the Control Register via the Register Selection (see Table 7 on page 14).
The Control Register is selected via data 192 on addr 253.
Table 13. Control Register Address Map
Register Name
HEX
Register Address
A7
A6
A5
A4
A3
Register Data
A2
A1
A0
D7:D0
Picture
0x00
(see Table 14 on page 21)
Movie
0x01
Movie Mode
0x02
Frame Time / Scroll
0x03
Display Option
0x04
Current Source
0x05
AS1130 Config
0x06
Interrupt Mask
0x07
Interrupt Frame Definition
0x08
Shutdown & Open/Short
0x09
IC Interface Monitoring
0x0A
CLK Synchronization
0x0B
Interrupt Status
0x0E
AS1130 Status
0x0F
0x20
Open LED
........................
0x37

0
Revision 1.09
20 - 39
AS1130
Picture Register (0x00)

In this register it must be set if a picture is to display on the LED matrix or not. Also the address of the picture which should be displayed must be
set withi n this register. The default setting of this register is 0x00.
Table 14. Picture Register Format
0x00 Picture Register
Bit
Bit Name
blink_pic
5:0
Default
Access
R/W
All LEDs in blink mode during display picture

0: no blink
1: all LEDs blink
R/W
Display Picture
0: no picture
1: display picture
R/W
Address of Picture
000000: Frame 0
000001: Frame 1
000010: Frame 2
000011: Frame 3
000100: Frame 4
000101: Frame 5
...............
100000: Frame 32
100001: Frame 33
100010: Frame 34
100011: Frame 35
display_pic
pic_addr
000000
Bit Description
Note: The display_pic bit (bit 6 in Picture Register) has lower priority than the display_movie bit (bit 6 in Movie Register).
Movie Register (0x01)

In this register it must be set if a movie is to display on the LED matrix or not. Also the address of the first frame in the movie needs be set within
this register. The default setting of this register is 0x00.
Table 15. Movie Register Format
0x01 Movie Register
Bit
Bit Name
blink_movie
display_movie
5:0
movie_addr
Default
Access
R/W
All LEDs in blink mode during play movie

0: no blink
1: all LEDs blink
R/W
0: no movie
1: start movie
R/W
Address of first Frame in Movie

000000: Frame 0
000001: Frame 1
000010: Frame 2
000011: Frame 3
000100: Frame 4
000101: Frame 5
...............
100000: Frame 32
100001: Frame 33
100010: Frame 34
100011: Frame 35
000000
Bit Description
Note: The display_movie bit (bit 6 in Movie Register) has higher priority than the display_pic bit (bit 6 in Picture Register).
Revision 1.09
21 - 39
AS1130
Movie Mode Register (0x02)

Within this register two movie play options can be set. Per default this register is set to 0x00.
- In scroll mode a movie can stop with the last frame of the movie or scroll endless
- The number of frames to play in a movie
Table 16. Movie Mode Register Format

0x02 Movie Mode Register
Bit
Bit Name
blink_en
5:0
Default
Access
R/W
LED blink option

0: enabled
1: disabled
R/W
defines at which frame a movie stops in scroll mode

0: movie ends with 1st frame
1: movie ends with last frame
R/W
Number of frames played in a movie, starting at movie_addr defined in

Movie Register
000001: Play 2 Frames
...............
end_last
movie_frames
000000
Bit Description
1
1. Disable blink option overrides any blink definition in PWM data definition or global blink definition in picture register & movie register bit 7.
Revision 1.09
22 - 39
AS1130
Frame Time/Scroll Register (0x03)

Every single frame in a movie is displayed for a certain time before the next frame is displayed. This time can be set within this register with 4
bits. The stated values in Table 17 are typical values.
Also the scroll options are set within this register. Per default this register is set to 0x00.
Table 17. Frame Time/Scroll Register Format
0x03 Frame Time/Scroll Register
Bit
Bit Name
frame_fad
3:0
Default
Access
R/W
Fade Frame Option (not available in 5 LED block configuration)

0: no fading
1: fading of a Frame
R/W
Scroll Direction
0: scroll to right
1: scroll to left
R/W
Define block size for scrolling

0: scroll in full matrix
1: scroll in 5 LED blocks (current sources split in 2 sections, See Scroll
Function on page 31)
R/W
Scroll digits at play movie

0: no scrolling
1: scrolling digits at play movie
R/W
Delay between frame change in a movie

0000: play frame only one time
0001: 32.5ms
0010: 65ms
0011: 97.5ms
0100: 130ms
0101: 162.5ms
0110: 195ms
0111: 227.5ms
1000: 260ms
1001: 292.5ms
1010: 325ms
1011: 357.5ms
1100: 390ms
1101: 422.5ms
1110: 455ms
1111: 487.5ms
scroll_dir
block_size
Enable Scrolling
frame_delay
0000
Bit Description
Revision 1.09
23 - 39
AS1130
Display Option Register (0x04)

In this register the number of loops in a movie are defined. With the scan-limit it can be controlled how many digits are displayed in each matrix.
When all 12 digits in the matrix are displayed, the display scan rate is 430Hz (typ.). If the number of digits to display is reduced, the update frequency is increased. Per default this register is set to 0x20.
Table 18. Display Option Register Format
0x04 Display Option Register
Bit
Bit Name
7:5
loops
3:0
Default
Access
Bit Description
001
R/W
Number of loops played in one movie

000: not valid
001: 1 loop
010: 2 loops
011: 3 loops
100: 4 loops
101: 5 loops
110: 6 loops
111: play movie endless (needs to be reset to 0-6 to stop movie); for scroll
endless set bit end_last = 0
R/W
Blink period
0: 1.5s
1: 3s
R/W
Number of displayed segments in one frame (scan-limit)

0000: CS0
0001: CS0 to CS1
0010: CS0 to CS2
0011: CS0 to CS3
0100: CS0 to CS4
0101: CS0 to CS5
0110: CS0 to CS6
0111: CS0 to CS7
1000: CS0 to CS8
1001: CS0 to CS9
1010: CS0 to CS10
1011: CS0 to CS11
blink_freq
scan_limit
0000
Note: To stop a movie in play endless mode, bits D7:D5 have to be set to a value between 000 to 110.
Current Source Register (0x05)

Within this registers the current for every single LED can be set from 0mA to 30mA in 255 steps (8 bits). Per default this register is set to 0x00.
Table 19. Current Source Register Format
0x05 Current Source Register
Bit
Bit Name
7:0
current
Default
Access
00000000
R/W
Bit Description
00000000: 0mA
..........
11111111: 30mA
Revision 1.09
24 - 39
AS1130
AS1130 Config Register (0x06)

Per default this register is set to 0x00.
Table 20. AS1130 Config Register Format
0x06 AS1130 Config Register
Bit
Bit Name
low_vdd_rst
Default
Access
Bit Description
R/W
0: at the end of a movie or a display picture the low_VDD flag is not

changed
1: at the end of a movie or a display picture, the low_VDD flag is set to 0
R/W
This bit indicates the supply status

0: if low_VDD is detected, the Interrupt Status Register will be updated
accordingly and pin IRQ is triggered.
1: the low_VDD bit is directly mapped to the pin IRQ. This can be used to
control an external DC/DC Converter or Charge Pump. In this case pin IRQ
cant be used for interrupt functionality, the Interrupt Status REgister will be
updated accordingly.
R/W
This bit defines the LED open handling

0: open LEDs which are detected at LED open test, are NOT disabled
1: open LEDs which are detected at LED open test, are disabled
R/W
Analog current DotCorrection

0: disabled
1: enabled
R/W
IC Common Address
0: disabled
1: enabled (all AS1130 are reacting on the same address 0111111)
R/W
Define Memory Configuration (see Table 8 on page 14)

000: Invalid Configuration (default value)
001: RAM Configuration 1
0
6
2:0
low_vdd_stat
led_error_correction
dot_corr
common_addr
mem_conf
000
1. This configuration is locked after the first write access to ON/OFF, PWM od DotCorrection data section. Unlock can be performed only by
a reset of the device.
Interrupt Mask Register (0x07)

Table 21. Interrupt Mask Register Format
0x07 Interrupt Mask Register
Bit
Bit Name
selected_pic
Default
Access
R/W
R/W
IRQ pin triggers if the IC watchdog triggers

0: disabled
1: enabled
R/W
IRQ pin triggers if POR is active

0: disabled
1: enabled
watchdog
por
Bit Description
IRQ pin triggers if defined Frame is displayed (see Interrupt Frame
Definition Register (0x08) on page 26)
0: disabled
1: enabled
Revision 1.09
25 - 39
AS1130
Table 21. Interrupt Mask Register Format

0x07 Interrupt Mask Register
Bit
Bit Name
overtemp
Default
Access
R/W
IRQ pin triggers if the over temperature limit is reached

0: disabled
1: enabled
R/W
IRQ pin triggers if VDD is to low for used LEDs (low_VDD flag)
0: disabled
1: enabled
R/W
IRQ pin triggers if an error on the open test occurs

0: disabled
1: enabled
R/W
IRQ pin triggers if an error on the short test occurs

0: disabled
1: enabled
R/W
IRQ pin triggers if a movie is finished

0: disabled
1: enabled
low_vdd
open_err
short_err
movie_fin
Bit Description
Interrupt Frame Definition Register (0x08)

Per default this register is set to 0x3F.
Table 22. Interrupt Frame Definition Register Format
0x08 Interrupt Frame Definition Register
Bit
Bit Name
Default
Access
7:6
00
n/a
5:0
last_frame
111111
R/W
Bit Description
After this frame is displayed the last time (depending on the number of loops
played in a movie) an interrupt will be triggered.
000000: Frame 0
000001: Frame 1
000010: Frame 2
000011: Frame 3
000100: Frame 4
000101: Frame 5
..................
100000: Frame 32
100001: Frame 33
100010: Frame 34
100011: Frame 35
Shutdown & Open/Short Register (0x09)

The scan limit (0x04) defines also the number of segments for the Open/short detection.
Table 23. Shutdown & Open/Short Register Format
0x09 Shutdown & Open/Short Register
Bit
Bit Name
Default
Access
7:5
000
n/a
test_all
0
R/W
Bit Description
The LED open/short test is performed on all LED locations
0: disabled (unassembled or disabled LEDs will be detected as open)
1: enabled (unassembled LEDs will be detected as open)
Revision 1.09
26 - 39
AS1130
Table 23. Shutdown & Open/Short Register Format

0x09 Shutdown & Open/Short Register
Bit
Bit Name
auto_test
Default
Access
R/W
The automatic LED open/short test is started when

bit display_pic (0x00) or bit display_movie (0x01) is set to 1
0: disabled
1: enabled
R/W
The manual LED open/short test is started after the update of Reg0x09
0: disabled
1: enabled
R/W
0: initialise control logic (internal State machine is reset again)

1: normal operation
R/W
0: device is in shutdown mode (Outputs are turned off, internal State

machine stops)
1: normal operation
manual_test
init
shdn
Bit Description
IC Interface Monitoring Register (0x0A)

This register is used to monitor the activity on the IC bus. If a deadlock situation occurs (e.g. the bus SDA pin is pulled to low and no communication is possible) the chip will reset the IC interface and the master is able to start the communication again.
The time window for the reset of the interface of the AS1130 can be set via 7 bits from 256s to 33ms. The default setting of this register is 0xFF.
Table 24. IC Interface Monitoring Register Format
0x0A IC Interface Monitoring Register
Bit
Bit Name
Default
Access
n/a
6:1
Time out window
i2c_monitor
Bit Description
11111
R/W
Definition of the Time out window (0 to 127 => 1 to 128x256s)

0000000: 256s
........
1111111: 32.7ms
R/W
0: IC monitoring off
1: IC monitoring on
CLK Synchronization Register (0x0B)

The default setting of this register is 0x00.
Table 25. CLK Synchronization Register Format
0x0B CLK Synchronization Register
Bit
Bit Name
Default
Access
7:4
0000
n/a
3:2
clk_out
00
R/W
Bit Description
Adjustable clock out frequency
00: 1MHz
01: 500kHz
10: 125kHz
11: 32kHz
Revision 1.09
27 - 39
AS1130
Table 25. CLK Synchronization Register Format

0x0B CLK Synchronization Register
Bit
Bit Name
sync_out
Default
Access
Bit Description
The internal oscillator is used as system-clk. The selected clk frequency is
1
R/W
sync_in
available on pin D4 for synchronization. (Output)

0: disabled
1: enabled
R/W
The internal oscillator is disabled. Pin D4 is used as clk input for system-clk.
0: disabled
1: enabled
1. CLK synchronization is done via the SYNC pin. Only one option can be activated (Input or Output).
Interrupt Status Register (0x0E)

This is a read only register. Within this register the cause of an interrupt can be read out. After power up or a reset the default setting of this register is 0x20. A read out command will set this register to default and the IRQ pin will be released again.
Table 26. Interrupt Status Register Format
0x0E Interrupt Status Register
Bit
Bit Name
frame_int
i2c_int
por_int
overtemp_int
low_vdd_int
open_int
short_int
movie_int
Default
Access
Bit Description
0: no interrupt
1: defined Frame is displayed (see Interrupt Frame Definition
Register (0x08) on page 26)
0: no interrupt
1: IC watchdog reports a deadlock on the interface
0: no interrupt
1: POR was triggered
0: no interrupt
1: over temperature limit is reached
0: no interrupt
1: VDD is too low to drive requested current through the LEDs
0: no interrupt
1: error on open test
0: no interrupt
1: error on short test
0: no interrupt
1: play movie is finished
Revision 1.09
28 - 39
AS1130
AS1130 Status Register (0x0F)

This is a read only register. From this register the actual status of the AS1130 can be read out. The default setting of this register is 0x00.
Table 27. AS1130 Status Register Format
0x0F AS1130 Status Register
Bit
Bit Name
7:2
frame_on
movie_on
test_on
Default
Access
Bit Description
000000
Actual displayed frame

000000: Frame 0
000001: Frame 1
000010: Frame 2
000011: Frame 3
000100: Frame 4
000101: Frame 5
...............
100000: Frame 32
100001: Frame 33
100010: Frame 34
100011: Frame 35
0: no movie
1: movie playing
0: no test is running
1: open/short test ongoing
AS1130 Open LED Register (0x20 to 0x37)

This is a read only register. From this register the LEDs which failed with an open error can be read out. A 1 indicates LED okay, a 0 stands for
LED open. If a LED, which is physically not connected to the device is tested, the Open LED test will return a 0.
Table 28. Open LED Register Format
Segment
Address
Data
HEX
A7
A6
A5
A4
A3
A2
A1
A0
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
D7
LED
07
D6
LED
06
D5
LED
05
D4
LED
04
D3
LED
03
LED
17
LED
16
LED
15
LED
14
LED
13
LED
27
LED
26
LED
25
LED
24
LED
23
LED
37
LED
36
LED
35
LED
34
LED
33
LED
47
LED
46
LED
45
LED
44
LED
43
Revision 1.09
D2
LED
02
LED
0A
LED
12
LED
1A
LED
22
LED
2A
D1
LED
01
LED
09
LED
11
LED
19
LED
21
LED
29
D0
LED
00
LED
08
LED
10
LED
18
LED
20
LED
28
LED
32
LED
3A
LED
31
LED
39
LED
30
LED
38
LED
42
LED
4A
LED
41
LED
49
LED
40
LED
48
29 - 39
AS1130
Table 28. Open LED Register Format

Segment
Address
Data
HEX
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
0x2A
LED
57
LED
56
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
D3
D2
D1
D0
LED
55
D4
LED
54
LED
53
LED
52
LED
5A
LED
51
LED
59
LED
50
LED
58
LED
67
LED
66
LED
65
LED
64
LED
63
LED
62
LED
6A
LED
61
LED
69
LED
60
LED
68
LED
77
LED
76
LED
75
LED
74
LED
73
LED
72
LED
7A
LED
71
LED
79
LED
70
LED
78
LED
87
LED
86
LED
85
LED
84
LED
83
LED
82
LED
8A
LED
81
LED
89
LED
80
LED
88
LED
97
LED
96
LED
95
LED
94
LED
93
LED
92
LED
9A
LED
91
LED
99
LED
90
LED
98
LED
A7
LED
A6
LED
A5
LED
A4
LED
A3
0x35
LED
A2
LED
AA
LED
A1
LED
A9
LED
A0
LED
A8
0x36
LED
B7
LED
B6
LED
B5
LED
B4
LED
B3
LED
B2
LED
B1
LED
B0
0x37
LED
BA
LED
B9
LED
B8
Revision 1.09
30 - 39
AS1130
Datasheet - Ty p i c a l A p p l i c a t i o n
10 Typical Application
Scroll Function
The AS1130 offers a feature for scrolling a picture through the matrix without the need of communication via a P. The scrolling can be done in
the whole matrix (11x12) or optimized for a ticker in a 5x24 Matrix (see Figure 25).
Figure 25. LED configuration for 5LED block scroll function
CS0
CS1
CS2
CS3
CS4
CS5
CS6
CS7
CS8
CS9
CS10
CS11
00
05
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
90
95
A0
A5
B0
B5
01
06
11
16
21
26
31
36
41
46
51
56
61
66
71
76
81
86
91
96
A1
A6
B1
B6
02
07
12
17
22
27
32
37
42
47
52
57
62
67
72
77
82
87
92
97
A2
A7
B2
B7
03
08
13
18
23
28
33
38
43
48
53
58
63
68
73
78
83
88
93
98
A3
A8
B3
B8
04
09
14
19
24
29
34
39
44
49
54
59
64
69
74
79
84
89
94
99
A4
A9
B4
B9
In the movie display mode the frame is shown in the matrix at once. On the contrary in the scroll function the frame is shifted through the matrix
segment after segment (CS0 to CS1 to CS2 to CS3 ......).
Figure 26. Scrolling
Revision 1.09
31 - 39
AS1130
Figure 27. Ticker Application with 5x96 LED Matrix
Revision 1.09
32 - 39
AS1130
LED Current Calculation

The current through a LED in the matrix is set via three registers (Current Source Register, Dot Correction and PWM). The resulting current
through the single LED can be calculated as shown in the following.
First its necessary to calculate the time how long one LED will be ON.
PWM
t LEDon = -------------f OSC
(EQ 1)
Where:
tLEDon . . . . time where the LED is ON
PWM . . . value set in the register (0 - 256), (see Table 11 on page 18)
fOSC . . . frequency set in the CLK Synchronization Register, (see Table 25 on page 27)
The refresh rate is defined by the scan-limit and fOSC.

( scanlimit + 1 ) 256
tREFRESH = -----------------------------------------------------f OSC
(EQ 2)
Where:
tREFRESH . . . time needed to refresh the matrix
scan-limit . . . is set via the Display Option Register (0 - 11), (see Table 18 on page 24)
fOSC . . . frequency set in the CLK Synchronization Register, (see Table 25 on page 27)
With the LED on-time and the refresh rate an average LED ON factor can be calculated.
t LEDon
PWM
LEDon avg = ------------------------ = -----------------------------------------------------t REFRESH
( scanlimit + 1 ) 256
(EQ 3)
The resulting current is then the Segment Current (set in the Current Source Register) times the average LED ON factor.
PWM
I LEDavg = I SEG LEDon avg = I SEG -----------------------------------------------------( scanlimit + 1 ) 256
(EQ 4)
Where:
ISEG . . . Segment Current set via register (see Table 19 on page 24)
Example:
Assume that following conditions are set in the registers: PWM = 256, scan-limit = 5 (half filled matrix, 66 LEDs), ISEG = 30mA
256
I LEDavg = 30mA -------------------------------- = 5mA
( 5 + 1 ) 256
Revision 1.09
(EQ 5)
33 - 39
AS1130
Datasheet - P a c k a g e D r a w i n g s a n d M a r k i n g s
11 Package Drawings and Markings

Figure 28. 20-pin WL-CSP Marking
Figure 29. 28-pin SSOP Marking
AS1130
YYWWRZZ @
AS1130B
YYWWRZZ @
Figure 30. 28-pin TSSOP Marking
AS1130
YYWWRZZ @
Table 29. Packaging Code YYWWRZZ

YY
last two digits of the current year
WW
manufacturing week
ZZ
plant identifier
free choice / traceability code
sublot identifier
Revision 1.09
34 - 39
AS1130
Figure 31. 20-pin WL-CSP Package
Revision 1.09
35 - 39
AS1130
Figure 32. 28-pin SSOP Package
Revision 1.09
36 - 39
AS1130
Figure 33. 28-pin TSSOP Package
Revision 1.09
37 - 39
AS1130
Datasheet - O r d e r i n g I n f o r m a t i o n
12 Ordering Information
The devices are available as the standard products shown in Table 30.
Table 30. Ordering Information
Ordering Code
Marking
Logic Levels
AS1130-BSST
AS1130
CMOS
Address
0x30 - 0x37
AS1130B-BSST*
AS1130B
Mobile
AS1130C-BSST*
AS1130C
CMOS
0x38 - 0x3E
AS1130D-BSST*
AS1130D
Mobile
AS1130-BTST
AS1130
CMOS
0x30 - 0x37
AS1130B-BTST*
AS1130B
Mobile
AS1130C-BTST*
AS1130C
CMOS
AS1130D-BTST*
AS1130D
Mobile
AS1130-BWLT
AS1130
CMOS
0x38 - 0x3E
0x30 - 0x37
AS1130B-BWLT
AS1130B
Mobile
AS1130C-BWLT*
tbd
CMOS
0x38 - 0x3E
AS1130D-BWLT*
tbd
Mobile
Description
132-LED Cross-Plexing Driver with
scrolling Function
scrolling Function
scrolling Function
scrolling Function
scrolling Function
scrolling Function
scrolling Function
scrolling Function
scrolling Function
scrolling Function
scrolling Function
scrolling Function
Delivery Form
Package
Tape and Reel

Tape and Reel
28-pin SSOP
Tape and Reel

Tape and Reel
Tape and Reel
Tape and Reel
28-pin TSSOP
Tape and Reel
Tape and Reel
Tape and Reel
Tape and Reel
20-pin WL-CSP
Tape and Reel

Tape and Reel
*) on request
Note: All products are RoHS compliant and ams green.
Buy our products or get free samples online at ICdirect: http://www.ams.com/ICdirect
Technical Support is found at http://www.ams.com/Technical-Support
For further information and requests, please contact us mailto:sales@ams.com
or find your local distributor at http://www.ams.com/distributor
Revision 1.09
38 - 39
AS1130
Datasheet - O r d e r i n g I n f o r m a t i o n
Copyrights
Copyright 1997-2012, ams AG, Tobelbaderstrasse 30, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered . All rights
reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the
copyright owner.
All products and companies mentioned are trademarks or registered trademarks of their respective companies.
Disclaimer
Devices sold by ams AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. ams AG makes no
warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described
devices from patent infringement. ams AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior
to designing this product into a system, it is necessary to check with ams AG for current information. This product is intended for use in normal
commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by
ams AG for each application. For shipments of less than 100 parts the manufacturing flow might show deviations from the standard production
flow, such as test flow or test location.
The information furnished here by ams AG is believed to be correct and accurate. However, ams AG shall not be liable to recipient or any third
party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of ams AG rendering of technical or other services.
Contact Information
Headquarters
ams AG
Tobelbaderstrasse 30
A-8141 Unterpremstaetten, Austria
Tel: +43 (0) 3136 500 0
Fax: +43 (0) 3136 525 01
For Sales Offices, Distributors and Representatives, please visit:
http://www.ams.com/contact
Revision 1.09
39 - 39

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D atas he et

1MHz IC-Compatible Interface

132 LEDs in Dot Matrix

8-bit Dot Correction for optimize RGB LED Operation

up to 6 Frames Memory for PWM sets

The device offers a programmable IRQ pin. Via a register it can be

Minimum PCB space required

Open and Shorted LED Error Detection

Also hardware scroll Function is implemented in the AS1130.

3, 10, 18, 19, 26

A1, A2, A4, A5,

CS0, CS1, CS6, CS7,

5 Absolute Maximum Ratings

Norm: MIL 883 E method 3015

Temperature Ranges and Storage Conditions

for 20-pin WL-CSP

for 28-pin SSOP/TSSOP

Norm IPC/JEDEC J-STD-020

Represents an unlimited floor life time

Represents a max. floor life time of 168h

Package Body Temperature

Moisture Sensitive Level

Operating Temperature Range

Operating Junction Temperature Range

Operating Supply Voltage

Operating Supply Current

All current sources turned ON

All current sources turned OFF

Software Shutdown Supply Current

All digital inputs at VDD or GND

Full Shutdown Supply Current

Pin RSTN = 0V, TAMB = +25C

Digit Drive Sink Current

(Drive capability of all sources of one digit )

Segment Drive Source Current LED

VOUT = 1.8V to VDD-400mV

Segment Drive Current Matching LED

Device to Device Current Matching LED

VOUT = 1.8V, VDD = 3.3V

Leakage Output Current

All current sources OFF, VOUT = 0V,

VOUT = 1.8V to VDD-400mV

Current = 30mA, VDD = 3.3V

Resistance for NMOS

Open Detection Level Threshold

Reset Pulse Width Low

Short Detection Level Threshold

Table 4. Logic Inputs/Outputs Characteristics

Logic Input Current

CMOS Logic High Input Voltage

CMOS Logic Low Input Voltage

CMOS Hysteresis Voltage

Mobile Logic High Input Voltage

Mobile Logic Low Input Voltage

SDA Output Low Voltage

IRQ Output Low Voltage

Sync Clock Output Low Voltage

Sync Clock Output High Voltage

Capacitive Load for Each Bus Line

1. available on request, See Ordering Information on page 38