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Fir Filter (Verilog Code)

This document describes a digital signal processing system for audio data. It includes modules for a clock generator, audio codec interface, noise generator, and a main circuit module. The main circuit module adds noise to the left and right audio channels from the codec and outputs the noisy data back to the codec for playback.

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PraphullaPandey
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183 views

Fir Filter (Verilog Code)

This document describes a digital signal processing system for audio data. It includes modules for a clock generator, audio codec interface, noise generator, and a main circuit module. The main circuit module adds noise to the left and right audio channels from the codec and outputs the noisy data back to the codec for playback.

Uploaded by

PraphullaPandey
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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// main module FIR

module filterfir(clk,rst,x,dataout);
input [7:0]x;
input clk,rst;
output [9:0]dataout;
wire [7:0]d1,d2,d3;
wire [7:0]m1,m2,m3,m4,m5;
wire [7:0]d11,d12,d13,d14;
parameter h0=3'b101;
parameter h1=3'b100;
parameter h2=3'b011;
parameter h3=3'b010;
parameter h4=3'b001;
assign m1=x>>h0;
d_ff u2(clk,rst,x,d11);
assign m2=d11>>h1;
assign d1=m1+m2;
d_ff u4(clk,rst,d11,d12);
assign m3=d12>>h2;
assign d2=d1+m3;
d_ff u6(clk,rst,d12,d13);
assign m4=d13>>h3;
assign d3=d2+m4;
d_ff u8(clk,rst,d13,d14);
assign m5=d14>>h4;
assign dataout=d3+m5;
endmodule
module d_ff(clk,rst,d,q);// sub module d flipflop
input clk,rst;
input [7:0]d;
output [7:0]q;
reg [7:0]q;
always@(posedge clk)
begin
if(rst==1)
begin
q=0;
end
else
begin
q=d;
end
end
endmodule
module part1 (CLOCK_50, CLOCK_27, KEY, I2C_SCLK, I2C_SDAT, AUD_XCK,
AUD_DACLRCK, AUD_ADCLRCK, AUD_BCLK, AUD_ADCDAT, AUD_DACDAT);
input CLOCK_50, CLOCK_27;
input [0:0] KEY;
// I2C Audio/Video config interface
output I2C_SCLK;
inout I2C_SDAT;
// Audio CODEC
output AUD_XCK;
input AUD_DACLRCK, AUD_ADCLRCK, AUD_BCLK;
input AUD_ADCDAT;

output AUD_DACDAT;
// Local wires.
wire read_ready, write_ready, read, write;
wire [23:0] readdata_left, readdata_right;
wire [23:0] writedata_left, writedata_right;
wire reset = ~KEY[0];
/////////////////////////////////
circuit a(CLOCK_50,read_ready, write_ready, read, write,
readdata_left, readdata_right, writedata_left, writedata_right,reset);

/////////////////////////////////////////////////////////////////////////
////////
// Audio CODEC interface.
//
// The interface consists of the following wires:
// read_ready, write_ready - CODEC ready for read/write operation
// readdata_left, readdata_right - left and right channel data from the
CODEC
// read - send data from the CODEC (both channels)
// writedata_left, writedata_right - left and right channel data to the
CODEC
// write - send data to the CODEC (both channels)
// AUD_* - should connect to top-level entity I/O of the same name.
//
These signals go directly to the Audio CODEC
// I2C_* - should connect to top-level entity I/O of the same name.
//
These signals go directly to the Audio/Video Config module
/////////////////////////////////////////////////////////////////////////
////////
clock_generator my_clock_gen(
// inputs
CLOCK_27,
reset,
// outputs
AUD_XCK
);
audio_and_video_config cfg(
// Inputs
CLOCK_50,
reset,
// Bidirectionals
I2C_SDAT,
I2C_SCLK
);
audio_codec codec(
// Inputs
CLOCK_50,
reset,
read, write,
writedata_left, writedata_right,

AUD_ADCDAT,
// Bidirectionals
AUD_BCLK,
AUD_ADCLRCK,
AUD_DACLRCK,
// Outputs
read_ready, write_ready,
readdata_left, readdata_right,
AUD_DACDAT
);
endmodule
// main module FIR
module circuit(clk,read_ready, write_ready, read, write, readdata_left,
readdata_right, writedata_left, writedata_right,rst);
input signed [23:0]readdata_left,readdata_right;
input clk,rst,read_ready, write_ready;
output signed [23:0]writedata_left, writedata_right;
output
read,write;
wire [23:0] x,y,z,l,m;
noise_generator nl(clk, ~rst, z);
assign x=z+readdata_left;
assign y=z+readdata_right;

assign writedata_left=x;
assign writedata_right=y;
assign read= 1;
assign write= 1;

endmodule
//noise generator
module noise_generator(clk, enable, Q);
input clk, enable;
output [23:0] Q;
reg[2:0] counter;
always@(posedge clk)
begin
if (enable)
counter = counter + 1'b1;
end
assign Q ={{10{counter[2]}}, counter, 11'd0};
endmodule

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