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    DDI0484C Cortex m0p r0p1 TRM Parte30

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    Paolo Rossi
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    DDI0484C Cortex m0p r0p1 TRM Parte30

    Uploaded by

    Paolo Rossi
    78 views1 page
    pg 30

    Original Title

    DDI0484C Cortex m0p r0p1 Trm Parte30

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    pg 30

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    78 views1 page

    DDI0484C Cortex m0p r0p1 TRM Parte30

    Uploaded by

    Paolo Rossi
    pg 30

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 1

    Programmers Model

    3.4 Memory model


    The processor contains a bus matrix that arbitrates the processor core and optional Debug
    Access Port (DAP) memory accesses to both the external memory system and to the internal
    NVIC and debug components.

    Priority is always given to the processor to ensure that any debug accesses are as non-intrusive
    as possible. For a zero wait-state system, all debug accesses to system memory, NVIC, and
    debug resources are completely non-intrusive for typical code execution.

    The system memory map is ARMv6-M architecture compliant, and is common both to the
    debugger and processor accesses. Transactions are routed as follows:

    All accesses below 0xE0000000 or above 0xEFFFFFFF appear as AHB-Lite transactions on


    the AHB-Lite master port of the processor.

    Accesses in the range 0xE0000000 to 0xEFFFFFFF are handled within the processor and do
    not appear on the AHB-Lite master port of the processor.

    Data accesses to the AHB-Lite interface from both the debugger and the processor can be
    hardware configured to appear instead on the single-cycle I/O port.

    The processor supports only word size accesses in the range 0xE0000000 - 0xEFFFFFFF.

    Table 3-2 shows the code, data, and device suitability for each region of the default memory
    map. This is the memory map used by implementations without the optional Memory Protection
    Unit (MPU), or when an included MPU is disabled. The attributes and permissions of all
    regions, except that targeting the Cortex-M0+ NVIC and debug components, can be modified
    using an implemented MPU.

    Table 3-2 Default memory map usage

    Address range Code Data Device

    0xF0000000 - 0xFFFFFFFF No No Yes

    0xE0000000 - 0xEFFFFFFF No No Noa

    0xA0000000 - 0xDFFFFFFF No No Yes

    0x60000000 - 0x9FFFFFFF Yes Yes No

    0x40000000 - 0x5FFFFFFF No No Yes

    0x20000000 - 0x3FFFFFFF Yesb Yes No

    0x00000000 - 0x1FFFFFFF Yes Yes No

    a. Space reserved for Cortex-M0+ NVIC and debug


    components.
    b. Cortex-M1 devices implementing data
    Tightly-Coupled Memories (TCMs) in this region
    do not support code execution from the data TCM.

    Note
    Regions not marked as suitable for code behave as eXecute-Never (XN) and generate a
    HardFault exception if code attempts to execute from this location.

    See the ARMv6-M Architecture Reference Manual for more information about the memory
    model.

    ARM DDI 0484C Copyright 2012 ARM. All rights reserved. 3-8
    ID011713 Non-Confidential

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