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TMS320F28027, TMS320F28026, TMS320F28023, TMS320F28022

TMS320F28021, TMS320F28020, TMS320F280200
SPRS523K NOVEMBER 2008 REVISED JUNE 2016
TMS320F2802x Piccolo Microcontrollers

1 Device Overview
1.1
1
Features
High-Efficiency 32-Bit CPU (TMS320C28x) Three 32-Bit CPU Timers
60 MHz (16.67-ns Cycle Time) Independent 16-Bit Timer in Each Enhanced Pulse
50 MHz (20-ns Cycle Time) Width Modulator (ePWM)
40 MHz (25-ns Cycle Time) On-Chip Memory
16 16 and 32 32 MAC Operations Flash, SARAM, OTP, Boot ROM Available
16 16 Dual MAC Code-Security Module
Harvard Bus Architecture 128-Bit Security Key and Lock
Atomic Operations Protects Secure Memory Blocks
Fast Interrupt Response and Processing Prevents Firmware Reverse Engineering
Unified Memory Programming Model Serial Port Peripherals
Code-Efficient (in C/C++ and Assembly) One Serial Communications Interface (SCI)
Endianness: Little Endian Universal Asynchronous Receiver/Transmitter
(UART) Module
Low Cost for Both Device and System:
One Serial Peripheral Interface (SPI) Module
Single 3.3-V Supply
One Inter-Integrated-Circuit (I2C) Module
No Power Sequencing Requirement
Enhanced Control Peripherals
Integrated Power-on and Brown-out Resets
ePWM
Small Packaging, as Low as 38-Pin Available
High-Resolution PWM (HRPWM)
Low Power
Enhanced Capture (eCAP) Module
No Analog Support Pins
Analog-to-Digital Converter (ADC)
Clocking:
On-Chip Temperature Sensor
Two Internal Zero-Pin Oscillators
Comparator
On-Chip Crystal Oscillator and External Clock
Input Advanced Emulation Features
Watchdog Timer Module Analysis and Breakpoint Functions
Missing Clock Detection Circuitry Real-Time Debug Through Hardware
Up to 22 Individually Programmable, Multiplexed 2802x, 2802xx Packages
GPIO Pins With Input Filtering 38-Pin DA Thin Shrink Small-Outline Package
Peripheral Interrupt Expansion (PIE) Block That (TSSOP)
Supports All Peripheral Interrupts 48-Pin PT Low-Profile Quad Flatpack (LQFP)
1.2 Applications
White Goods LED Lighting
Switch Mode Power Supplies (SMPSs) Power Factor Correction
DC-DC Multiple-Output Power Supplies Sewing and Textile Machines
Solar Micro Inverters and Converters eBikes
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TMS320F28021, TMS320F28020, TMS320F280200
SPRS523K NOVEMBER 2008 REVISED JUNE 2016 www.ti.com
1.3 Description
The F2802x Piccolo family of microcontrollers provides the power of the C28x core coupled with highly
integrated control peripherals in low pin-count devices. This family is code-compatible with previous C28x-
based code, and also provides a high level of analog integration.
An internal voltage regulator allows for single-rail operation. Enhancements have been made to the
HRPWM to allow for dual-edge control (frequency modulation). Analog comparators with internal 10-bit
references have been added and can be routed directly to control the PWM outputs. The ADC converts
from 0 to 3.3-V fixed full-scale range and supports ratio-metric VREFHI/VREFLO references. The ADC
interface has been optimized for low overhead and latency.
Device Information (1)

PART NUMBER PACKAGE BODY SIZE
TMS320F28027PT LQFP (48) 7.0 mm 7.0 mm
TMS320F28026PT LQFP (48) 7.0 mm 7.0 mm
TMS320F28023PT LQFP (48) 7.0 mm 7.0 mm
TMS320F28022PT LQFP (48) 7.0 mm 7.0 mm
TMS320F28021PT LQFP (48) 7.0 mm 7.0 mm
TMS320F28020PT LQFP (48) 7.0 mm 7.0 mm
TMS320F280200PT LQFP (48) 7.0 mm 7.0 mm
TMS320F28027DA TSSOP (38) 12.5 mm 6.2 mm
(1) For more information on these devices, see Section 9, Mechanical Packaging and Orderable
Information.
2 Device Overview Copyright 20082016, Texas Instruments Incorporated

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Product Folder Links: TMS320F28027 TMS320F28026 TMS320F28023 TMS320F28022 TMS320F28021
TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
www.ti.com SPRS523K NOVEMBER 2008 REVISED JUNE 2016
1.4 Functional Block Diagram

Figure 1-1 shows the functional block diagram for the device.
Memory Bus
OTP 1K 16
Secure
M0
SARAM 1K 16
(0-wait)
M1 SARAM
SARAM 1K 16 1K/3K/4K 16 Code FLASH
(0-wait) (0-wait) Security 8K/16K/32K 16
Secure Module Secure
Boot-ROM
8K 16
(0-wait)
OTP/Flash
PSWD Wrapper
Memory Bus
TRST
TCK
COMP1OUT
GPIO TDI
32-Bit Peripheral Bus
COMP2OUT C28x TMS

MUX 32-Bit CPU
TDO GPIO
Mux
COMP1A
COMP
COMP1B
COMP2A
COMP2B PIE 3 External Interrupts
OSC1, XCLKIN
CPU Timer 0
OSC2, X1
AIO Ext, X2
CPU Timer 1
MUX PLL, LPM Wakeup
LPM, XRS
CPU Timer 2 WD
ADC
A7:0
Memory Bus
POR/
VREG
B7:0 BOR
16-Bit Peripheral Bus 32-Bit Peripheral Bus 32-Bit Peripheral Bus
SCI SPI I2C ePWM

eCAP
(4L FIFO) (4L FIFO) (4L FIFO)
HRPWM
EPWMSYNCO
EPWMSYNCI
SPISIMOx
SPISOMIx
EPWMxA
EPWMxB
SCIRXDx
SPICLKx
SCITXDx
SPISTEx
ECA Px
SDAx
SCLx
TZx
From
COMP1OUT,
COMP2OUT
GPIO MUX
Copyright 2016, Texas Instruments Incorporated

A. Not all peripheral pins are available at the same time due to multiplexing.
Figure 1-1. Functional Block Diagram
Copyright 20082016, Texas Instruments Incorporated Device Overview 3

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
Table of Contents
1 Device Overview ......................................... 1 6 Detailed Description ................................... 37
1.1 Features .............................................. 1 6.1 Overview ............................................ 37
1.2 Applications ........................................... 1 6.2 Memory Maps ...................................... 45
1.3 Description ............................................ 2 6.3 Register Maps ....................................... 53
1.4 Functional Block Diagram ........................... 3 6.4 Device Emulation Registers ......................... 54
2 Revision History ......................................... 5 6.5 VREG/BOR/POR .................................... 55
3 Device Comparison ..................................... 6 6.6 System Control ...................................... 57
3.1 Related Products ..................................... 8 6.7 Low-power Modes Block ............................ 65
4 Terminal Configuration and Functions .............. 9 6.8 Interrupts ............................................ 66
4.1 Pin Diagrams ......................................... 9 6.9 Peripherals .......................................... 71
4.2 Signal Descriptions .................................. 11 7 Applications, Implementation, and Layout ...... 123
5 Specifications ........................................... 16 7.1 TI Design or Reference Design .................... 123
5.1 Absolute Maximum Ratings ........................ 16 8 Device and Documentation Support .............. 124
5.2 ESD Ratings ........................................ 16 8.1 Getting Started ..................................... 124
5.3 Recommended Operating Conditions ............... 17 8.2 Device and Development Support Tool
5.4 Power Consumption Summary ...................... 18 Nomenclature ...................................... 124
5.5 Electrical Characteristics ............................ 23 8.3 Tools and Software ................................ 125
5.6 Thermal Resistance Characteristics ................ 24 8.4 Documentation Support ............................ 127
5.7 Thermal Design Considerations .................... 25 8.5 Related Links ...................................... 128
5.8 Emulator Connection Without Signal Buffering for 8.6 Community Resources............................. 129
the MCU ............................................. 25 8.7 Trademarks ........................................ 129
5.9 Parameter Information .............................. 26 8.8 Electrostatic Discharge Caution ................... 129
5.10 Test Load Circuit ................................... 26 8.9 Glossary............................................ 129
5.11 Power Sequencing .................................. 27 9 Mechanical Packaging and Orderable
5.12 Clock Specifications ................................. 30 Information ............................................. 130
5.13 Flash Timing ........................................ 34 9.1 Packaging Information ............................. 130
4 Table of Contents Copyright 20082016, Texas Instruments Incorporated

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
2 Revision History
Changes from October 8, 2013 to June 27, 2016 (from J Revision (October 2013) to K Revision) Page
Global: Restructured document. .................................................................................................. 1

Global: Added ESD Ratings table; Detailed Description section; Device and Documentation Support section;
and Mechanical Packaging and Orderable Information section. ............................................................... 1
Global: Added InstaSPIN-FOC devices TMS320F28027F and TMS320F28026F. See Table 3-1. ................... 1
Global: Removed "Analog MUX" table (this was Table 4-12 in SPRS523J). ............................................... 1
Global: Removed references to the Reliability Data for TMS320LF24xx and TMS320F28xx Devices Application
Report. ................................................................................................................................. 1
Section 1.1 (Features): Removed "Dynamic PLL Ratio Changes Supported" feature. ..................................... 1
Device Information: Added table. .................................................................................................. 2
Table 3-1 (Device Comparison): Changed title from "Hardware Features" to "Device Comparison". .................... 6
Table 3-1: Added InstaSPIN-FOC devices TMS320F28027F and TMS320F28026F. ..................................... 6
Table 3-1: Added footnote with reference to a list of InstaSPIN Technical Reference Manuals. ....................... 6
Table 3-1: Removed "Product status" row and associated footnote. ......................................................... 6
Section 3.1 (Related Products): Added section. ................................................................................. 8
Section 4.2 (Signal Descriptions): Updated NOTE. ............................................................................ 11
Table 4-1 (Signal Descriptions): Changed title from "Terminal Functions" to "Signal Descriptions". .................... 11
Table 4-1: Updated DESCRIPTION of X1, XRS, VREFHI, VREFLO, VDD, and VDDIO. ......................................... 11
Section 5.1 (Absolute Maximum Ratings): Added Input voltage, VIN (X1). ................................................. 16
Section 5.3 (Recommended Operating Conditions): Removed "VDDIO and VDDA should be maintained within ~0.3
V of each other" footnote. ......................................................................................................... 17
Section 5.4 (Power Consumption Summary): Changed section title from "Current Consumption" to "Power
Consumption Summary". .......................................................................................................... 18
Section 5.11 (Power Sequencing): Updated "There is no power sequencing requirement needed ..." paragraph. ... 27
Table 5-11 (Internal Zero-Pin Oscillator (INTOSC1/INTOSC2) Characteristics): Updated footnote about oscillator
accuracy. ............................................................................................................................ 32
Table 6-11 (Device Emulation Registers): Added PARTID for TMS320F28027F and TMS320F28026F devices. .... 54
Table 6-11: Added CLASSID for TMS320F28027F and TMS320F28026F devices. ...................................... 54
Table 6-11: Added REVID for silicon revision B. ............................................................................... 54
Figure 6-6 (VREG + POR + BOR + Reset Signal Connectivity): Updated figure. ......................................... 56
Section 6.6.2 (Crystal Oscillator Option): Added "The on-chip crystal oscillator X1 and X2 pins are 1.8-V level
signals ..." paragraph. .............................................................................................................. 60
Figure 6-12 (CPU-watchdog Module): Updated figure. ........................................................................ 64
Table 6-33 (SPI Master Mode External Timing (Clock Phase = 0)): Parameter 9 [tv(SPCL-SOMI)M, tv(SPCH-SOMI)M]:
Changed MIN values to 0. ......................................................................................................... 90
Table 6-34 (SPI Master Mode External Timing (Clock Phase = 1)): Parameter 11 [tv(SPCH-SOMI)M, tv(SPCL-SOMI)M]:
Table 6-35 (SPI Slave Mode External Timing (Clock Phase = 0)): Parameter 16 [tv(SPCL-SOMI)S, tv(SPCH-SOMI)S]:
Table 6-36 (SPI Slave Mode External Timing (Clock Phase = 1)): Parameter 18 [tv(SPCL-SOMI)S, tv(SPCH-SOMI)S]:
Section 6.9.10 (Pin Multiplexing): Changed title from "GPIO MUX" to "General-Purpose Input/Output (GPIO)
MUX". ............................................................................................................................... 111
Table 6-51 (Analog MUX for 48-Pin PT Package): Added table. ........................................................... 113
Table 6-52 (Analog MUX for 38-Pin DA Package): Added table. .......................................................... 114
Section 7 (Applications, Implementation, and Layout): Added section. .................................................... 123
Section 8 (Device and Documentation Support): Added section. .......................................................... 124
Section 8.1 (Getting Started): Updated links. ................................................................................. 124
Figure 8-1 (Device Nomenclature): Updated list of devices. ................................................................ 125
Section 8.3 (Tools and Software): Added section. ........................................................................... 125
Section 8.4 (Documentation Support): Updated section. .................................................................... 127
Copyright 20082016, Texas Instruments Incorporated Revision History 5

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
3 Device Comparison
Table 3-1 lists the features of the TMS320F2802x devices.
Table 3-1. Device Comparison
28027 28026
28023 28022 28021 28020 280200
FEATURE TYPE (1) 28027F (2) 28026F (2)
(50 MHz) (50 MHz) (40 MHz) (40 MHz) (40 MHz)
(60 MHz) (60 MHz)
38-Pin DA 48-Pin PT 38-Pin DA 48-Pin PT 38-Pin DA 48-Pin PT 38-Pin DA 48-Pin PT 38-Pin DA 48-Pin PT 38-Pin DA 48-Pin PT 38-Pin DA 48-Pin PT
Package Type
TSSOP LQFP TSSOP LQFP TSSOP LQFP TSSOP LQFP TSSOP LQFP TSSOP LQFP TSSOP LQFP
Instruction cycle 16.67 ns 16.67 ns 20 ns 20 ns 25 ns 25 ns 25 ns
On-chip flash (16-bit word) 32K 16K 32K 16K 32K 16K 8K
On-chip SARAM (16-bit word) 6K 6K 6K 6K 5K 3K 3K
Code security for on-chip
Yes Yes Yes Yes Yes Yes Yes
flash/SARAM/OTP blocks
Boot ROM (8K x 16) Yes Yes Yes Yes Yes Yes Yes
One-time programmable (OTP) ROM (16-
1K 1K 1K 1K 1K 1K 1K
bit word)
ePWM channels 1 8 (ePWM1/2/3/4) 8 (ePWM1/2/3/4) 8 (ePWM1/2/3/4) 8 (ePWM1/2/3/4) 8 (ePWM1/2/3/4) 8 (ePWM1/2/3/4) 8 (ePWM1/2/3/4)
eCAP inputs 0 1 1 1 1 1 1
Watchdog timer Yes Yes Yes Yes Yes Yes Yes
MSPS 4.6 4.6 3 3 2 2 2
Conversion Time 216.67 ns 216.67 ns 260 ns 260 ns 500 ns 500 ns 500 ns
12-Bit ADC Channels 3 7 13 7 13 7 13 7 13 7 13 7 13 7 13
Temperature Sensor Yes Yes Yes Yes Yes Yes Yes
Dual Sample-and-Hold Yes Yes Yes Yes Yes Yes Yes
32-Bit CPU timers 3 3 3 3 3 3 3
High-resolution ePWM Channels 1 4 (ePWM1A/2A/3A/4A) 4 (ePWM1A/2A/3A/4A) 4 (ePWM1A/2A/3A/4A) 4 (ePWM1A/2A/3A/4A)
Comparators w/ Integrated DACs 0 1 2 1 2 1 2 1 2 1 2 1 2 1 2
Inter-integrated circuit (I2C) 0 1 1 1 1 1 1 1
Serial Peripheral Interface (SPI) 1 1 1 1 1 1 1 1
Serial Communications Interface (SCI) 0 1 1 1 1 1 1 1
Digital (GPIO) 20 22 20 22 20 22 20 22 20 22 20 22 20 22
I/O pins (shared)
Analog (AIO) 6 6 6 6 6 6 6
External interrupts 3 3 3 3 3 3 3
Supply voltage (nominal) 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V
(1) A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minor differences between devices that do not affect the
basic functionality of the module. These device-specific differences are listed in the C2000 Real-Time Control Peripherals Reference Guide and in the peripheral reference guides.
(2) TMS320F28027F and TMS320F28026F are InstaSPIN-FOC-enabled MCUs. For more information, see Section 8.4 for a list of InstaSPIN Technical Reference Manuals.
6 Device Comparison Copyright 20082016, Texas Instruments Incorporated

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
Table 3-1. Device Comparison (continued)

28027 28026
28023 28022 28021 28020 280200
FEATURE TYPE (1) 28027F (2) 28026F (2)
(50 MHz) (50 MHz) (40 MHz) (40 MHz) (40 MHz)
(60 MHz) (60 MHz)
38-Pin DA 48-Pin PT 38-Pin DA 48-Pin PT 38-Pin DA 48-Pin PT 38-Pin DA 48-Pin PT 38-Pin DA 48-Pin PT 38-Pin DA 48-Pin PT 38-Pin DA 48-Pin PT
Package Type
TSSOP LQFP TSSOP LQFP TSSOP LQFP TSSOP LQFP TSSOP LQFP TSSOP LQFP TSSOP LQFP
T: 40C to 105C Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
Temperature
S: 40C to 125C Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
options
Q: 40C to 125C (3) Yes Yes Yes Yes Yes Yes Yes Yes
(3) The letter Q refers to Q100 qualification for automotive applications.
Copyright 20082016, Texas Instruments Incorporated Device Comparison 7

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
3.1 Related Products

For information about other devices in this family of products, see the following links:
The TMS320F2807x microcontroller platform is part of the Piccolo family and is suited for advanced
closed-loop control applications such as industrial drives and servo motor control; solar inverters and
converters; digital power; transportation; and power line communications. Complete development
packages for digital power and industrial drives are available as part of the powerSUITE and
DesignDRIVE initiatives.
The F2806x Piccolo family of microcontrollers (MCUs) provides the power of the C28x core and CLA
coupled with highly integrated control peripherals in low pin-count devices. This family is code-compatible
with previous C28x-based code, and also provides a high level of analog integration.
The F2805x Piccolo family of microcontrollers (MCUs) provides the power of the C28x core and CLA
coupled with highly integrated control peripherals in low pin-count devices. This family is code-compatible
with previous C28x-based code, and also provides a high level of analog integration.
The F2803x Piccolo family of microcontrollers provides the power of the C28x core and Control Law
Accelerator (CLA) coupled with highly integrated control peripherals in low pin-count devices. This family
is code-compatible with previous C28x-based code, and also provides a high level of analog integration.
8 Device Comparison Copyright 20082016, Texas Instruments Incorporated

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
4 Terminal Configuration and Functions

4.1 Pin Diagrams
Figure 4-1 shows the 48-pin PT low-profile quad flatpack (LQFP) pin assignments. Figure 4-2 shows the
38-pin DA thin shrink small-outline package (TSSOP) pin assignments.
GPIO19/XCLKIN/SPISTEA/SCIRXDA/ECAP1
GPIO33/SCLA/EPWMSYNCO/ADCSOCBO
GPIO32/SDAA/EPWMSYNCI/ADCSOCAO
GPIO1/EPWM1B/COMP1OUT
GPIO16/SPISIMOA/TZ2
GPIO17/SPISOMIA/TZ3
GPIO0/EPWM1A
VREGENZ
TEST
VDDIO
VDD
VSS
36
35
34
33
32
31
30
29
28
27
26
25
GPIO2/EPWM2A 37 24 GPIO18/SPICLKA/SCITXDA/XCLKOUT
GPIO3/EPWM2B/COMP2OUT 38 23 GPIO38/XCLKIN (TCK)
GPIO4/EPWM3A 39 22 GPIO37 (TDO)
GPIO5/EPWM3B/ECAP1 40 21 GPIO36 (TMS)
GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO 41 20 GPIO35 (TDI)
GPIO7/EPWM4B/SCIRXDA 42 19 GPIO34/COMP2OUT
VDD 43 18 ADCINB7
VSS 44 17 ADCINB6/AIO14
X1 45 16 ADCINB4/COMP2B/AIO12
X2 46 15 ADCINB3
GPIO12/TZ1/SCITXDA 47 14 ADCINB2/COMP1B/AIO10
GPIO28/SCIRXDA/SDAA/TZ2 48 13 ADCINB1
10
12
11
1
2
3
4
5
6
7
8
9
GPIO29/SCITXDA/SCLA/TZ3
TRST
XRS
ADCINA6/AIO6
ADCINA4/COMP2A/AIO4
ADCINA7
ADCINA3
ADCINA1
ADCINA2/COMP1A/AIO2
ADCINA0/VREFHI
VDDA
VSSA/VREFLO
Figure 4-1. 2802x 48-Pin PT LQFP (Top View)
Copyright 20082016, Texas Instruments Incorporated Terminal Configuration and Functions 9

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
VDD 1 38 TEST
VSS 2 37 GPIO0/EPWM1A
VREGENZ 3 36 GPIO1/EPWM1B/COMP1OUT
VDDIO 4 35 GPIO16/SPISIMOA/TZ2
GPIO2/EPWM2A 5 34 GPIO17/SPISOMIA/TZ3
GPIO3/EPWM2B 6 33 GPIO19/XCLKIN/SPISTEA/SCIRXDA/ECAP1
GPIO4/EPWM3A 7 32 GPIO18/SPICLKA/SCITXDA/XCLKOUT
GPIO5/EPWM3B/ECAP1 8 31 GPIO38/XCLKIN (TCK)
GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO 9 30 GPIO37 (TDO)
GPIO7/EPWM4B/SCIRXDA 10 29 GPIO36 (TMS)
VDD 11 28 GPIO35 (TDI)
VSS 12 27 GPIO34
GPIO12/TZ1/SCITXDA 13 26 ADCINB6/AIO14
GPIO28/SCIRXDA/SDAA/TZ2 14 25 ADCINB4/AIO12
GPIO29/SCITXDA/SCLA/TZ3 15 24 ADCINB2/COMP1B/AIO10
TRST 16 23 VSSA/VREFLO
XRS 17 22 VDDA
ADCINA6/AIO6 18 21 ADCINA0/VREFHI
ADCINA4/AIO4 19 20 ADCINA2/COMP1A/AIO2
Figure 4-2. 2802x 38-Pin DA TSSOP (Top View)
10 Terminal Configuration and Functions Copyright 20082016, Texas Instruments Incorporated

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
4.2 Signal Descriptions

Table 4-1 describes the signals. With the exception of the JTAG pins, the GPIO function is the default at
reset, unless otherwise mentioned. The peripheral signals that are listed under them are alternate
functions. Some peripheral functions may not be available in all devices. See Table 3-1 for details. Inputs
are not 5-V tolerant. All GPIO pins are I/O/Z and have an internal pullup, which can be selectively
enabled/disabled on a per-pin basis. This feature only applies to the GPIO pins. The pullups on the PWM
pins are not enabled at reset. The pullups on other GPIO pins are enabled upon reset. The AIO pins do
not have an internal pullup.
NOTE: When the on-chip VREG is used, the GPIO19, GPIO34, GPIO35, GPIO36, GPIO37, and GPIO38
pins could glitch during power up. If this is unacceptable in an application, 1.8 V could be supplied
externally. Alternatively, adding a current-limiting resistor (for example, 470 ) in series with these pins
and any external driver could be considered to limit the potential for degradation to the pin and/or external
circuitry. There is no power-sequencing requirement when using an external 1.8-V supply. However, if the
3.3-V transistors in the level-shifting output buffers of the I/O pins are powered before the 1.8-V
transistors, it is possible for the output buffers to turn on, causing a glitch to occur on the pin during power
up. To avoid this behavior, power the VDD pins before or with the VDDIO pins, ensuring that the VDD pins
have reached 0.7 V before the VDDIO pins reach 0.7 V.
Table 4-1. Signal Descriptions (1)

TERMINAL
PT DA I/O/Z DESCRIPTION
NAME
PIN # PIN #
JTAG
JTAG test reset with internal pulldown. TRST, when driven high, gives the scan
system control of the operations of the device. If this signal is not connected or driven
low, the device operates in its functional mode, and the test reset signals are ignored.
NOTE: TRST is an active high test pin and must be maintained low at all times during
TRST 2 16 I normal device operation. An external pulldown resistor is required on this pin. The
value of this resistor should be based on drive strength of the debugger pods
applicable to the design. A 2.2-k resistor generally offers adequate protection. Since
this is application-specific, it is recommended that each target board be validated for
proper operation of the debugger and the application. ()
TCK See GPIO38 I See GPIO38. JTAG test clock with internal pullup ()
See GPIO36. JTAG test-mode select (TMS) with internal pullup. This serial control
TMS See GPIO36 I
input is clocked into the TAP controller on the rising edge of TCK. ()
See GPIO35. JTAG test data input (TDI) with internal pullup. TDI is clocked into the
TDI See GPIO35 I
selected register (instruction or data) on a rising edge of TCK. ()
See GPIO37. JTAG scan out, test data output (TDO). The contents of the selected
TDO See GPIO37 O/Z register (instruction or data) are shifted out of TDO on the falling edge of TCK.
(8-mA drive)
FLASH
TEST 30 38 I/O Test Pin. Reserved for TI. Must be left unconnected.
(1) I = Input, O = Output, Z = High Impedance, OD = Open Drain, = Pullup, = Pulldown

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
Table 4-1. Signal Descriptions(1) (continued)

TERMINAL
NAME
PIN # PIN #
CLOCK
See GPIO18. Output clock derived from SYSCLKOUT. XCLKOUT is either the same
frequency, one-half the frequency, or one-fourth the frequency of SYSCLKOUT. This
is controlled by bits 1:0 (XCLKOUTDIV) in the XCLK register. At reset, XCLKOUT =
XCLKOUT See GPIO18 O/Z
SYSCLKOUT/4. The XCLKOUT signal can be turned off by setting XCLKOUTDIV
to 3. The mux control for GPIO18 must also be set to XCLKOUT for this signal to
propogate to the pin.
See GPIO19 and GPIO38. External oscillator input. Pin source for the clock is
controlled by the XCLKINSEL bit in the XCLK register, GPIO38 is the default
selection. This pin feeds a clock from an external 3.3-V oscillator. In this case, the X1
pin, if available, must be tied to GND and the on-chip crystal oscillator must be
disabled via bit 14 in the CLKCTL register. If a crystal/resonator is used, the XCLKIN
See GPIO19 and
XCLKIN I path must be disabled by bit 13 in the CLKCTL register.
GPIO38
NOTE: Designs that use the GPIO38/TCK/XCLKIN pin to supply an external clock for
normal device operation may need to incorporate some hooks to disable this path
during debug using the JTAG connector. This is to prevent contention with the TCK
signal, which is active during JTAG debug sessions. The zero-pin internal oscillators
may be used during this time to clock the device.
On-chip 1.8-V crystal-oscillator input. To use this oscillator, a quartz crystal or a
ceramic resonator must be connected across X1 and X2. In this case, the XCLKIN
X1 45 I
path must be disabled by bit 13 in the CLKCTL register. If this pin is not used, it must
be tied to GND. (I)
On-chip crystal-oscillator output. A quartz crystal or a ceramic resonator must be
X2 46 O
connected across X1 and X2. If X2 is not used, it must be left unconnected. (O)
RESET
Device Reset (in) and Watchdog Reset (out). Piccolo devices have a built-in power-on
reset (POR) and brown-out reset (BOR) circuitry. During a power-on or brown-out
condition, this pin is driven low by the device. An external circuit may also drive this
pin to assert a device reset. This pin is also driven low by the MCU when a watchdog
reset occurs. During watchdog reset, the XRS pin is driven low for the watchdog reset
duration of 512 OSCCLK cycles. A resistor between 2.2 k and 10 k should be
placed between XRS and VDDIO. If a capacitor is placed between XRS and VSS for
XRS 3 17 I/OD noise filtering, it should be 100 nF or smaller. These values will allow the watchdog to
properly drive the XRS pin to VOL within 512 OSCCLK cycles when the watchdog
reset is asserted. Regardless of the source, a device reset causes the device to
terminate execution. The program counter points to the address contained at the
location 0x3F FFC0. When reset is deactivated, execution begins at the location
designated by the program counter. The output buffer of this pin is an open-drain with
an internal pullup. () If this pin is driven by an external device, it is recommended that
an open-drain device be used.
ADC, COMPARATOR, ANALOG I/O
ADCINA7 6 I ADC Group A, Channel 7 input
ADCINA6 I ADC Group A, Channel 6 input
4 18
AIO6 I/O Digital AIO 6
COMP2A 5 19 I Comparator Input 2A (available in 48-pin device only)
COMP1A 9 20 I Comparator Input 1A
VREFHI 10 21 I ADC External Reference High only used when in ADC external reference mode. See
Section 6.9.1.1, ADC.
ADCINB7 18 I ADC Group B, Channel 7 input

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200

TERMINAL
NAME
PIN # PIN #
ADCINB6 I ADC Group B, Channel 6 input
17 26
COMP2B 16 25 I Comparator Input 2B (available in 48-pin device only)
AIO12 I/O Digital AIO12
COMP1B 14 24 I Comparator Input 1B
CPU AND I/O POWER
VDDA 11 22 Analog Power Pin. Tie with a 2.2-F capacitor (typical) close to the pin.
VSSA Analog Ground Pin
12 23
VREFLO I ADC External Reference Low (always tied to ground)
32 1 CPU and Logic Digital Power Pins. When using internal VREG, place one 1.2-F
VDD
43 11 capacitor between each VDD pin and ground. Higher value capacitors may be used.
Digital I/O Buffers and Flash Memory Power Pin. Single supply source when VREG is
VDDIO 35 4 enabled. Place a decoupling capacitor on this pin. The exact value should be
determined by the system voltage regulation solution.
33 2
VSS Digital Ground Pins
44 12
VOLTAGE REGULATOR CONTROL SIGNAL
Internal VREG Enable/Disable. Pull low to enable the internal voltage regulator
VREGENZ 34 3 I
(VREG), pull high to disable VREG.
(2)
GPIO AND PERIPHERAL SIGNALS
GPIO0 I/O/Z General-purpose input/output 0
EPWM1A O Enhanced PWM1 Output A and HRPWM channel
29 37

EPWM1B O Enhanced PWM1 Output B
28 36

COMP1OUT O Direct output of Comparator 1
EPWM2A O Enhanced PWM2 Output A and HRPWM channel
37 5

EPWM2B O Enhanced PWM2 Output B
38 6

COMP2OUT O Direct output of Comparator 2 (available in 48-pin device only)
(2) The GPIO function (shown in bold italics) is the default at reset. The peripheral signals that are listed under them are alternate functions.
For JTAG pins that have the GPIO functionality multiplexed, the input path to the GPIO block is always valid. The output path from the
GPIO block and the path to the JTAG block from a pin is enabled/disabled based on the condition of the TRST signal. See the
TMS320x2802x/TMS320F2802xx Piccolo System Control and Interrupts Reference Guide for details.
TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200

TERMINAL
NAME
PIN # PIN #
EPWM3A O Enhanced PWM3 output A and HRPWM channel
39 7

EPWM3B O Enhanced PWM3 output B
40 8

ECAP1 I/O Enhanced Capture input/output 1
EPWM4A O Enhanced PWM4 output A and HRPWM channel
41 9
EPWMSYNCI I External ePWM sync pulse input
EPWMSYNCO O External ePWM sync pulse output
EPWM4B O Enhanced PWM4 output B
42 10
SCIRXDA I SCI-A receive data

TZ1 I Trip Zone input 1
47 13
SCITXDA O SCI-A transmit data

SPISIMOA I/O SPI slave in, master out
27 35

TZ2 I Trip Zone input 2
SPISOMIA I/O SPI-A slave out, master in
26 34

TZ3 I Trip zone input 3
SPICLKA I/O SPI-A clock input/output
SCITXDA O SCI-A transmit
XCLKOUT 24 32 O/Z Output clock derived from SYSCLKOUT. XCLKOUT is either the same frequency,
one-half the frequency, or one-fourth the frequency of SYSCLKOUT. This is controlled
by bits 1:0 (XCLKOUTDIV) in the XCLK register. At reset, XCLKOUT =
SYSCLKOUT/4. The XCLKOUT signal can be turned off by setting XCLKOUTDIV
to 3. The mux control for GPIO18 must also be set to XCLKOUT for this signal to
propogate to the pin.
XCLKIN I External Oscillator Input. The path from this pin to the clock block is not gated by the
mux function of this pin. Care must be taken not to enable this path for clocking if it is
being used for the other periperhal functions
25 33
SPISTEA I/O SPI-A slave transmit enable input/output
SCIRXDA I SCI-A receive
ECAP1 I/O Enhanced Capture input/output 1
SCIRXDA I SCI receive data
48 14
SDAA I/OD I2C data open-drain bidirectional port

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200

TERMINAL
NAME
PIN # PIN #
GPIO29 I/O/Z General-purpose input/output 29.
SCITXDA O SCI transmit data
1 15
SCLA I/OD I2C clock open-drain bidirectional port
SDAA I/OD I2C data open-drain bidirectional port
31
EPWMSYNCI I Enhanced PWM external sync pulse input
ADCSOCAO O ADC start-of-conversion A
GPIO33 I/O/Z General-Purpose Input/Output 33
SCLA I/OD I2C clock open-drain bidirectional port
36
EPWMSYNCO O Enhanced PWM external synch pulse output
ADCSOCBO O ADC start-of-conversion B
COMP2OUT O Direct output of Comparator 2. COMP2OUT signal is not available in the DA package.
19 27

TDI 20 28 I JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register
(instruction or data) on a rising edge of TCK
TMS 21 29 I JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked
into the TAP controller on the rising edge of TCK.
TDO 22 30 O/Z JTAG scan out, test data output (TDO). The contents of the selected register
(instruction or data) are shifted out of TDO on the falling edge of TCK (8 mA drive)
TCK I JTAG test clock with internal pullup
23 31
XCLKIN I External Oscillator Input. The path from this pin to the clock block is not gated by the
mux function of this pin. Care must be taken to not enable this path for clocking if it is
being used for the other functions.

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
5 Specifications
5.1 Absolute Maximum Ratings (1) (2)

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VDDIO (I/O and Flash) with respect to VSS 0.3 4.6
Supply voltage V
VDD with respect to VSS 0.3 2.5
Analog voltage VDDA with respect to VSSA 0.3 4.6 V
VIN (3.3 V) 0.3 4.6
Input voltage V
VIN (X1) 0.3 2.5
Output voltage VO 0.3 4.6 V
Input clamp current IIK (VIN < 0 or VIN > VDDIO) (3) 20 20 mA
Output clamp current IOK (VO < 0 or VO > VDDIO) 20 20 mA
(4)
Junction temperature TJ 40 150 C
Storage temperature (4) Tstg 65 150 C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Section 5.3 is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to VSS, unless otherwise noted.
(3) Continuous clamp current per pin is 2 mA.
(4) Long-term high-temperature storage or extended use at maximum temperature conditions may result in a reduction of overall device life.
For additional information, see Semiconductor and IC Package Thermal Metrics.
5.2 ESD Ratings

VALUE UNIT
TMS320F2802x and TMS320F2802xF in 48-pin PT package
Human body model (HBM), per AEC Q100-002 (1) All pins 2000
All pins except corner
500
Electrostatic pins
V(ESD) V
discharge Charged device model (CDM), per AEC Q100-011 Corner pins on 48-pin PT:
1, 12, 13, 24, 25, 36, 37, 750
48
TMS320F2802x and TMS320F2802xF in 38-pin DA package
Human body model (HBM), per AEC Q100-002 (1) All pins 2000
All pins except corner
Electrostatic 500
V(ESD) pins V
discharge Charged device model (CDM), per AEC Q100-011
Corner pins on 38-pin DA:
750
1, 19, 20, 38
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
16 Specifications Copyright 20082016, Texas Instruments Incorporated

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
5.3 Recommended Operating Conditions

MIN NOM MAX UNIT
Device supply voltage, I/O, VDDIO (1) 2.97 3.3 3.63 V
Device supply voltage CPU, VDD (When internal VREG is
1.71 1.8 1.995 V
disabled and 1.8 V is supplied externally)
Supply ground, VSS 0 V
Analog supply voltage, VDDA 2.97 3.3 3.63 V
Analog ground, VSSA 0 V
28020, 28021, 280200 2 40
Device clock frequency (system clock) 28022, 28023 2 50 MHz
28026, 28027 2 60
High-level input voltage, VIH (3.3 V) 2 VDDIO + 0.3 V
Low-level input voltage, VIL (3.3 V) VSS 0.3 0.8 V
All GPIO/AIO pins 4 mA
High-level output source current, VOH = VOH(MIN), IOH
Group 2 (2) 8 mA
All GPIO/AIO pins 4 mA
Low-level output sink current, VOL = VOL(MAX), IOL (2)
Group 2 8 mA
T version 40 105
(3) S version 40 125
Junction temperature, TJ C
Q version
40 125
(Q100 Qualification)
(1) A tolerance of 10% may be used for VDDIO if the BOR is not used. See the TMS320F28027, TMS320F28026, TMS320F28023,
TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200, TMS320F280270, TMS320F280260, TMS320F280230,
TMS320F280220 Piccolo MCU Silicon Errata for more information. VDDIO tolerance is 5% if the BOR is enabled.
(2) Group 2 pins are as follows: GPIO16, GPIO17, GPIO18, GPIO19, GPIO28, GPIO29, GPIO36, GPIO37
(3) TA (Ambient temperature) is product- and application-dependent and can go up to the specified TJ max of the device. See Section 5.7,
Thermal Design Considerations.
Copyright 20082016, Texas Instruments Incorporated Specifications 17

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
5.4 Power Consumption Summary
Table 5-1. TMS320F2802x/F280200 (1) Current Consumption at 40-MHz SYSCLKOUT

VREG ENABLED VREG DISABLED
MODE TEST CONDITIONS IDDIO (2) IDDA (3) IDD IDDIO (2)
IDDA (3)
(4) (4) (4) (4) (4)

TYP MAX TYP MAX TYP MAX TYP MAX TYP MAX
The following peripheral clocks are
enabled:
ePWM1/2/3/4
eCAP1
SCI-A
SPI-A
Operational ADC
70 mA 80 mA 13 mA 18 mA 62 mA 70 mA 15 mA 18 mA 13 mA 18 mA
(Flash) I2C
COMP1/2
CPU Timer0/1/2
All PWM pins are toggled at 40 kHz.
All I/O pins are left unconnected. (5)
Code is running out of flash with 1 wait-
state.
XCLKOUT is turned off.
Flash is powered down.
IDLE XCLKOUT is turned off. 13 mA 16 mA 53 A 58 A 15 mA 17 mA 120 A 400 A 53 A 58 A
All peripheral clocks are off.
STANDBY 3 mA 6 mA 10 A 15 A 3 mA 6 mA 120 A 400 A 10 A 15 A
Peripheral clocks are off.
HALT Peripheral clocks are off. 50 A 10 A 15 A 15 A 25 A 10 A 15 A
Input clock is disabled. (6)
(1) For the TMS320F280200 device, subtract the IDD current number for eCAP (see Table 5-4) from IDD (VREG disabled)/IDDIO (VREG
enabled) current numbers shown in Table 5-1 for operational mode.
(2) IDDIO current is dependent on the electrical loading on the I/O pins.
(3) In order to realize the IDDA currents shown for IDLE, STANDBY, and HALT, clock to the ADC module must be turned off explicitly by
writing to the PCLKCR0 register.
(4) The TYP numbers are applicable over room temperature and nominal voltage.
(5) The following is done in a loop:
Data is continuously transmitted out of SPI-A and SCI-A ports.
The hardware multiplier is exercised.
Watchdog is reset.
ADC is performing continuous conversion.
COMP1/2 are continuously switching voltages.
GPIO17 is toggled.
(6) If a quartz crystal or ceramic resonator is used as the clock source, the HALT mode shuts down the on-chip crystal oscillator.

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
Table 5-2. TMS320F2802x Current Consumption at 50-MHz SYSCLKOUT

MODE TEST CONDITIONS IDDIO (1) IDDA (2) IDD IDDIO (1) IDDA (2)
TYP (3) MAX TYP (3) MAX TYP (3) MAX TYP (3) MAX TYP (3) MAX
The following peripheral clocks are
enabled:
ePWM1/2/3/4
eCAP1
SCI-A
SPI-A
Operational ADC
80 mA 90 mA 13 mA 18 mA 71 mA 80 mA 15 mA 18 mA 13 mA 18 mA
(Flash) I2C
COMP1/2
CPU Timer0/1/2
All PWM pins are toggled at 40 kHz.
All I/O pins are left unconnected. (4)
Code is running out of flash with 1 wait-
state.
IDLE XCLKOUT is turned off. 16 mA 19 mA 64 A 69 A 17 mA 20 mA 120 A 400 A 64 A 69 A
All peripheral clocks are off.
Watchdog is reset.
GPIO17 is toggled.

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
Table 5-3. TMS320F2802x Current Consumption at 60-MHz SYSCLKOUT

MODE TEST CONDITIONS IDDIO (1) IDDA (2) IDD IDDIO (1) IDDA (2)
TYP (3) MAX TYP (3) MAX TYP (3) MAX TYP (3) MAX TYP (3) MAX
The following peripheral clocks
are enabled:
ePWM1/2/3/4
eCAP1
SCI-A
SPI-A
ADC
Operational I2C 90 mA 100 mA 13 mA 18 mA 80 mA 90 mA 15 mA 18 mA 13 mA 18 mA
(Flash) COMP1/2
CPU-TIMER0/1/2
All PWM pins are toggled at
60 kHz.
All I/O pins are left
unconnected. (4)
Code is running out of flash
with 2 wait-states.
IDLE 18 mA 23 mA 75 A 80 A 19 mA 24 mA 120 A 400 A 75 A 80 A
All peripheral clocks are turned
off.
Watchdog is reset.
GPIO17 is toggled.
NOTE
The peripheral - I/O multiplexing implemented in the device prevents all available peripherals
from being used at the same time. This is because more than one peripheral function may
share an I/O pin. It is, however, possible to turn on the clocks to all the peripherals at the
same time, although such a configuration is not useful. If this is done, the current drawn by
the device will be more than the numbers specified in the current consumption tables.

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
5.4.1 Reducing Current Consumption

The 2802x/280200 devices incorporate a method to reduce the device current consumption. Since each
peripheral unit has an individual clock-enable bit, significant reduction in current consumption can be
achieved by turning off the clock to any peripheral module that is not used in a given application.
Furthermore, any one of the three low-power modes could be taken advantage of to reduce the current
consumption even further. Table 5-4 indicates the typical reduction in current consumption achieved by
turning off the clocks.
Table 5-4. Typical Current Consumption by Various

Peripherals (at 60 MHz) (1)
PERIPHERAL IDD CURRENT
MODULE (2) REDUCTION (mA)
ADC 2 (3)
I2C 3
ePWM 2
eCAP 2
SCI 2
SPI 2
COMP/DAC 1
HRPWM 3
CPU-TIMER 1
Internal zero-pin oscillator 0.5
(1) All peripheral clocks (except CPU Timer clocks) are disabled upon
reset. Writing to/reading from peripheral registers is possible only
after the peripheral clocks are turned on.
(2) For peripherals with multiple instances, the current quoted is per
module. For example, the 2 mA value quoted for ePWM is for one
ePWM module.
(3) This number represents the current drawn by the digital portion of
the ADC module. Turning off the clock to the ADC module results in
the elimination of the current drawn by the analog portion of the ADC
(IDDA) as well.
NOTE
IDDIO current consumption is reduced by 15 mA (typical) when XCLKOUT is turned off.
NOTE
The baseline IDD current (current when the core is executing a dummy loop with no
peripherals enabled) is 45 mA, typical. To arrive at the IDD current for a given application, the
current-drawn by the peripherals (enabled by that application) must be added to the baseline
IDD current.
Following are other methods to reduce power consumption further:

The flash module may be powered down if code is run off SARAM. This results in a current reduction
of 18 mA (typical) in the VDD rail and 13 mA (typical) in the VDDIO rail.
Savings in IDDIO may be realized by disabling the pullups on pins that assume an output function.

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
5.4.2 Current Consumption Graphs (VREG Enabled)
Operational Current vs Frequency
100
90
Operational Current (mA)
80
70
60
50
40
30
20
10
0
10 15 20 25 30 35 40 45 50 55 60
SYSCLKOUT (MHz)
IDDIO (m A) IDDA
Figure 5-1. Typical Operational Current Versus Frequency (F2802x/F280200)
Operational Pow er vs Frequency
450
Operational Power (mW)
400
350
300
250
200
10 15 20 25 30 35 40 45 50 55 60
SYSCLKOUT (MHz)
Figure 5-2. Typical Operational Power Versus Frequency (F2802x/F280200)

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
5.5 Electrical Characteristics (1)

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IOH = IOH MAX 2.4
VOH High-level output voltage V
IOH = 50 A VDDIO 0.2
VOL Low-level output voltage IOL = IOL MAX 0.4 V
Pin with pullup All GPIO 80 140 205
VDDIO = 3.3 V, VIN = 0 V
Input current enabled XRS pin 225 290 360
IIL A
(low level)
Pin with pulldown
VDDIO = 3.3 V, VIN = 0 V 2
enabled
Pin with pullup
VDDIO = 3.3 V, VIN = VDDIO 2
Input current enabled
IIH A
(high level) Pin with pulldown
VDDIO = 3.3 V, VIN = VDDIO 28 50 80
enabled
Output current, pullup or
IOZ VO = VDDIO or 0 V 2 A
pulldown disabled
CI Input capacitance 2 pF
VDDIO BOR trip point Falling VDDIO 2.42 2.65 3.135 V
VDDIO BOR hysteresis 35 mV
Supervisor reset release delay Time after BOR/POR/OVR event is removed to XRS
400 800 s
time release
VREG VDD output Internal VREG on 1.9 V
(1) When the on-chip VREG is used, its output is monitored by the POR/BOR circuit, which will reset the device should the core voltage
(VDD) go out of range.

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
5.6 Thermal Resistance Characteristics
5.6.1 PT Package
C/W (1) AIR FLOW (lfm) (2)
RJC Junction-to-case thermal resistance 13.6 N/A
RJB Junction-to-board thermal resistance 30.6 N/A
64 0
RJA 50.4 150
Junction-to-free air thermal resistance
(High k PCB) 48.2 250
45 500
0.56 0
0.94 150
PsiJT Junction-to-package top
1.1 250
1.38 500
30.1 0
28.7 150
PsiJB Junction-to-board
28.4 250
28 500
(1) These values are based on a JEDEC defined 2S2P system (with the exception of the Theta JC [RJC] value, which is based on a
JEDEC defined 1S0P system) and will change based on environment as well as application. For more information, see these
EIA/JEDEC standards:
JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
(2) lfm = linear feet per minute
5.6.2 DA Package
C/W (1) AIR FLOW (lfm) (2)
RJC Junction-to-case thermal resistance 12.8 N/A
RJB Junction-to-board thermal resistance 33 N/A
70.1 0
RJA 56.4 150
Junction-to-free air thermal resistance
(High k PCB) 53.9 250
50.2 500
0.34 0
0.61 150
PsiJT Junction-to-package top
0.74 250
0.98 500
32.5 0
32.1 150
PsiJB Junction-to-board
31.7 250
31.1 500
(1) These values are based on a JEDEC defined 2S2P system (with the exception of the Theta JC [RJC] value, which is based on a
JEDEC defined 1S0P system) and will change based on environment as well as application. For more information, see these
EIA/JEDEC standards:
JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
(2) lfm = linear feet per minute

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
5.7 Thermal Design Considerations

Based on the end application design and operational profile, the IDD and IDDIO currents could vary.
Systems that exceed the recommended maximum power dissipation in the end product may require
additional thermal enhancements. Ambient temperature (TA) varies with the end application and product
design. The critical factor that affects reliability and functionality is TJ, the junction temperature, not the
ambient temperature. Hence, care should be taken to keep TJ within the specified limits. Tcase should be
measured to estimate the operating junction temperature TJ. Tcase is normally measured at the center of
the package top-side surface. The thermal application report Semiconductor and IC Package Thermal
Metrics helps to understand the thermal metrics and definitions.
5.8 Emulator Connection Without Signal Buffering for the MCU

Figure 5-3 shows the connection between the MCU and JTAG header for a single-processor configuration.
If the distance between the JTAG header and the MCU is greater than 6 inches, the emulation signals
must be buffered. If the distance is less than 6 inches, buffering is typically not needed. Figure 5-3 shows
the simpler, no-buffering situation. For the pullup/pulldown resistor values, see Section 4.2, Signal
Descriptions.
6 inches or less
VDDIO VDDIO
13 5
EMU0 PD
14
EMU1
2 4
TRST TRST GND
1 6
TMS TMS GND
3 8
TDI TDI GND
7 10
TDO TDO GND
11 12
TCK TCK GND
9
TCK_RET
MCU
JTAG Header
A. See Figure 6-39 for JTAG/GPIO multiplexing.
Figure 5-3. Emulator Connection Without Signal Buffering for the MCU
NOTE
The 2802x devices do not have EMU0/EMU1 pins. For designs that have a JTAG Header
on-board, the EMU0/EMU1 pins on the header must be tied to VDDIO through a 4.7-k
(typical) resistor.

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
5.9 Parameter Information
5.9.1 Timing Parameter Symbology

Timing parameter symbols used are created in accordance with JEDEC Standard 100. To shorten the
symbols, some of the pin names and other related terminology have been abbreviated as follows:
Lowercase subscripts and their Letters and symbols and their

meanings: meanings:
a access time H High
c cycle time (period) L Low
d delay time V Valid
Unknown, changing, or don't care
f fall time X
level
h hold time Z High impedance
r rise time
su setup time
t transition time
v valid time
w pulse duration (width)
5.9.2 General Notes on Timing Parameters

All output signals from the 28x devices (including XCLKOUT) are derived from an internal clock such that
all output transitions for a given half-cycle occur with a minimum of skewing relative to each other.
The signal combinations shown in the following timing diagrams may not necessarily represent actual
cycles. For actual cycle examples, see the appropriate cycle description section of this document.
5.10 Test Load Circuit

This test load circuit is used to measure all switching characteristics provided in this document.
Tester Pin Electronics Data Sheet Timing Reference Point
42 W 3.5 nH Output
Transmission Line Under
(A)
Test
Z0 = 50 W
(B)
Device Pin
4.0 pF 1.85 pF
A. Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the
device pin.
B. The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its
transmission line effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used to
produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to
add or subtract the transmission line delay (2 ns or longer) from the data sheet timing.
Figure 5-4. 3.3-V Test Load Circuit

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
5.11 Power Sequencing

There is no power sequencing requirement needed to ensure the device is in the proper state after reset
or to prevent the I/Os from glitching during power up/down (GPIO19, GPIO3438 do not have glitch-free
I/Os). No voltage larger than a diode drop (0.7 V) above VDDIO should be applied to any digital pin prior to
powering up the device. Voltages applied to pins on an unpowered device can bias internal p-n junctions
in unintended ways and produce unpredictable results.
VDDIO, VDDA
(3.3 V)
VDD (1.8 V)
INTOSC1
tINTOSCST
X1/X2
tOSCST (B)
(A)
XCLKOUT
User-code dependent
tw(RSL1)
(D)
XRS
Address/data valid, internal boot-ROM code execution phase
Address/Data/
Control
(Internal)
td(EX) User-code execution phase
th(boot-mode)(C) User-code dependent
Boot-Mode
GPIO pins as input
Pins
Peripheral/GPIO function
Boot-ROM execution starts
Based on boot code
(E)
I/O Pins GPIO pins as input (state depends on internal PU/PD)
User-code dependent
A. Upon power up, SYSCLKOUT is OSCCLK/4. Since the XCLKOUTDIV bits in the XCLK register come up with a reset
state of 0, SYSCLKOUT is further divided by 4 before it appears at XCLKOUT. XCLKOUT = OSCCLK/16 during this
phase.
B. Boot ROM configures the DIVSEL bits for /1 operation. XCLKOUT = OSCCLK/4 during this phase. Note that
XCLKOUT will not be visible at the pin until explicitly configured by user code.
C. After reset, the boot ROM code samples Boot Mode pins. Based on the status of the Boot Mode pin, the boot code
branches to destination memory or boot code function. If boot ROM code executes after power-on conditions (in
debugger environment), the boot code execution time is based on the current SYSCLKOUT speed. The SYSCLKOUT
will be based on user environment and could be with or without PLL enabled.
D. Using the XRS pin is optional due to the on-chip power-on reset (POR) circuitry.
E. The internal pullup/pulldown will take effect when BOR is driven high.
Figure 5-5. Power-on Reset

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
Table 5-5. Reset (XRS) Timing Requirements

MIN MAX UNIT
th(boot-mode) Hold time for boot-mode pins 1000tc(SCO) cycles
tw(RSL2) Pulse duration, XRS low on warm reset 32tc(OSCCLK) cycles
Table 5-6. Reset (XRS) Switching Characteristics

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tw(RSL1) Pulse duration, XRS driven by device 600 s
Pulse duration, reset pulse generated by
tw(WDRS) 512tc(OSCCLK) cycles
watchdog
td(EX) Delay time, address/data valid after XRS high 32tc(OSCCLK) cycles
tINTOSCST Start up time, internal zero-pin oscillator 3 s
(1)
tOSCST On-chip crystal-oscillator start-up time 1 10 ms
(1) Dependent on crystal/resonator and board design.
INTOSC1
X1/X2
XCLKOUT
User-Code Dependent
tw(RSL2)
XRS
User-Code Execution Phase
td(EX)
Address/Data/
Control User-Code Execution
(Internal)
Boot-ROM Execution Starts th(boot-mode)(A)

Boot-Mode
Peripheral/GPIO Function GPIO Pins as Input Peripheral/GPIO Function
Pins
User-Code Execution Starts
I/O Pins User-Code Dependent GPIO Pins as Input (State Depends on Internal PU/PD)
User-Code Dependent
A. After reset, the Boot ROM code samples BOOT Mode pins. Based on the status of the Boot Mode pin, the boot code
branches to destination memory or boot code function. If Boot ROM code executes after power-on conditions (in
debugger environment), the Boot code execution time is based on the current SYSCLKOUT speed. The
SYSCLKOUT will be based on user environment and could be with or without PLL enabled.
Figure 5-6. Warm Reset

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
Figure 5-7 shows an example for the effect of writing into PLLCR register. In the first phase, PLLCR =
0x0004 and SYSCLKOUT = OSCCLK x 2. The PLLCR is then written with 0x0008. Right after the PLLCR
register is written, the PLL lock-up phase begins. During this phase, SYSCLKOUT = OSCCLK/2. After the
PLL lock-up is complete, SYSCLKOUT reflects the new operating frequency, OSCCLK x 4.
OSCCLK
Write to PLLCR
SYSCLKOUT
OSCCLK * 2 OSCCLK/2 OSCCLK * 4
(Current CPU (CPU frequency while PLL is stabilizing (Changed CPU frequency)
Frequency) with the desired frequency. This period
(PLL lock-up time tp) is 1 ms long.)
Figure 5-7. Example of Effect of Writing Into PLLCR Register

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
5.12 Clock Specifications
5.12.1 Device Clock Table

This section provides the timing requirements and switching characteristics for the various clock options
available on the 2802x MCUs. Table 5-7, Table 5-8, and Table 5-9 list the cycle times of various clocks.
Table 5-7. 2802x Clock Table and Nomenclature (40-MHz Devices)

MIN NOM MAX UNIT
tc(SCO), Cycle time 25 500 ns
SYSCLKOUT
Frequency 2 40 MHz
tc(LCO), Cycle time 25 100 (2) ns
LSPCLK (1) (2)
Frequency 10 40 MHz
tc(ADCCLK), Cycle time 25 ns
ADC clock
Frequency 40 MHz
(1) Lower LSPCLK will reduce device power consumption.
(2) This is the default reset value if SYSCLKOUT = 40 MHz.

MIN NOM MAX UNIT
tc(SCO), Cycle time 20 500 ns
SYSCLKOUT
Frequency 2 50 MHz
tc(LCO), Cycle time 20 80 (2) ns
LSPCLK (1)
Frequency 12.5 (2) 50 MHz
tc(ADCCLK), Cycle time 20 ns
ADC clock
Frequency 50 MHz

MIN NOM MAX UNIT
tc(SCO), Cycle time 16.67 500 ns
SYSCLKOUT
Frequency 2 60 MHz
tc(LCO), Cycle time 16.67 66.67 (2) ns
LSPCLK (1)
Frequency 15 (2) 60 MHz
tc(ADCCLK), Cycle time 16.67 ns
ADC clock
Frequency 60 MHz

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
Table 5-10. Device Clocking Requirements/Characteristics

MIN NOM MAX UNIT
On-chip oscillator (X1/X2 pins) tc(OSC), Cycle time 50 200 ns
(Crystal/Resonator) Frequency 5 20 MHz
External oscillator/clock source tc(CI), Cycle time (C8) 33.3 200 ns
(XCLKIN pin) PLL Enabled Frequency 5 30 MHz
External oscillator/clock source tc(CI), Cycle time (C8) 33.33 250 ns
(XCLKIN pin) PLL Disabled Frequency 4 30 MHz
Limp mode SYSCLKOUT
Frequency range 1 to 5 MHz
(with /2 enabled)
tc(XCO), Cycle time (C1) 66.67 2000 ns
XCLKOUT
Frequency 0.5 15 MHz
PLL lock time (1) tp 1 ms
(1) The PLLLOCKPRD register must be updated based on the number of OSCCLK cycles. If the zero-pin internal oscillators (10 MHz) are
used as the clock source, then the PLLLOCKPRD register must be written with a value of 10,000 (minimum).

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
Table 5-11. Internal Zero-Pin Oscillator (INTOSC1/INTOSC2) Characteristics

PARAMETER MIN TYP MAX UNIT
Internal zero-pin oscillator 1 (INTOSC1) (1) (2) Frequency 10 MHz
Internal zero-pin oscillator 2 (INTOSC2) (1) (2) Frequency 10 MHz
Step size (coarse trim) 55 kHz
Step size (fine trim) 14 kHz
Temperature drift (3) 3.03 4.85 kHz/C
Voltage (VDD) drift (3) 175 Hz/mV
(1) Oscillator frequency will vary over temperature, see Figure 5-8. To compensate for oscillator temperature drift, see the Oscillator
Compensation Guide and the controlSUITE example, Example_2802xOscComp.c.
(2) Frequency range ensured only when VREG is enabled, VREGENZ = VSS.
(3) Output frequency of the internal oscillators follows the direction of both the temperature gradient and voltage (VDD) gradient. For
example:
Increase in temperature will cause the output frequency to increase per the temperature coefficient.
Decrease in voltage (VDD) will cause the output frequency to decrease per the voltage coefficient.
Zero-Pin Oscillator Frequency Movement With Temperature
10.6
10.5
10.4
10.3
Output Frequency (MHz)
10.2
10.1
10
9.9
9.8
9.7
9.6
40 30 20 10 0 10 20 30 40 50 60 70 80 90 100 110 120
Typical Temperature (C)

Max
Figure 5-8. Zero-Pin Oscillator Frequency Movement With Temperature

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
5.12.2 Clock Requirements and Characteristics
Table 5-12. XCLKIN Timing Requirements - PLL Enabled

NO. MIN MAX UNIT
C9 tf(CI) Fall time, XCLKIN 6 ns
C10 tr(CI) Rise time, XCLKIN 6 ns
C11 tw(CIL) Pulse duration, XCLKIN low as a percentage of tc(OSCCLK) 45% 55%
C12 tw(CIH) Pulse duration, XCLKIN high as a percentage of tc(OSCCLK) 45% 55%
Table 5-13. XCLKIN Timing Requirements - PLL Disabled

NO. MIN MAX UNIT
Up to 20 MHz 6
C9 tf(Cl) Fall time, XCLKIN ns
20 MHz to 30 MHz 2
Up to 20 MHz 6
C10 tr(CI) Rise time, XCLKIN ns
20 MHz to 30 MHz 2
Pulse duration, XCLKIN low as a percentage of
C11 tw(CIL) 45% 55%
tc(OSCCLK)
Pulse duration, XCLKIN high as a percentage of
C12 tw(CIH) 45% 55%
tc(OSCCLK)
The possible configuration modes are shown in Table 6-16.
Table 5-14. XCLKOUT Switching Characteristics (PLL Bypassed or Enabled) (1) (2)

NO. PARAMETER MIN MAX UNIT
C3 tf(XCO) Fall time, XCLKOUT 11 ns
C4 tr(XCO) Rise time, XCLKOUT 11 ns
C5 tw(XCOL) Pulse duration, XCLKOUT low H2 H+2 ns
C6 tw(XCOH) Pulse duration, XCLKOUT high H2 H+2 ns
(1) A load of 40 pF is assumed for these parameters.
(2) H = 0.5tc(XCO)
C10
C9
C8
XCLKIN(A)
C3 C6
C1
C4
C5
XCLKOUT(B)
A. The relationship of XCLKIN to XCLKOUT depends on the divide factor chosen. The waveform relationship shown is
intended to illustrate the timing parameters only and may differ based on actual configuration.
B. XCLKOUT configured to reflect SYSCLKOUT.
Figure 5-9. Clock Timing

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
5.13 Flash Timing
Table 5-15. Flash/OTP Endurance for T Temperature Material (1)

ERASE/PROGRAM
MIN TYP MAX UNIT
TEMPERATURE
Nf Flash endurance for the array (write/erase cycles) 0C to 105C (ambient) 20000 50000 cycles
NOTP OTP endurance for the array (write cycles) 0C to 30C (ambient) 1 write
(1) Write/erase operations outside of the temperature ranges indicated are not specified and may affect the endurance numbers.
Table 5-16. Flash/OTP Endurance for S Temperature Material (1)

ERASE/PROGRAM
MIN TYP MAX UNIT
TEMPERATURE
Table 5-17. Flash/OTP Endurance for Q Temperature Material (1)

ERASE/PROGRAM
MIN TYP MAX UNIT
TEMPERATURE
Table 5-18. Flash Parameters at 60-MHz SYSCLKOUT

TEST
CONDITIONS
(1)
IDDP VDD current consumption during Erase/Program cycle VREG disabled 80
(1)
mA
IDDIOP VDDIO current consumption during Erase/Program cycle 60
(1)
IDDIOP VDDIO current consumption during Erase/Program cycle VREG enabled 120 mA
(1) Typical parameters as seen at room temperature including function call overhead, with all peripherals off. It is important to maintain a
stable power supply during the entire flash programming process. It is conceivable that device current consumption during flash
programming could be higher than normal operating conditions. The power supply used should ensure VMIN on the supply rails at all
times, as specified in the Recommended Operating Conditions of the data sheet. Any brown-out or interruption to power during
erasing/programming could potentially corrupt the password locations and lock the device permanently. Powering a target board (during
flash programming) through the USB port is not recommended, as the port may be unable to respond to the power demands placed
during the programming process.

TEST
CONDITIONS
IDDP (1) VDD current consumption during Erase/Program cycle VREG disabled 70
mA
IDDIOP (1) VDDIO current consumption during Erase/Program cycle 60
IDDIOP (1) VDDIO current consumption during Erase/Program cycle VREG enabled 110 mA

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200

TEST
CONDITIONS
(1)
IDDP VDD current consumption during Erase/Program cycle VREG disabled 60
mA
IDDIOP (1) VDDIO current consumption during Erase/Program cycle 60
IDDIOP (1) VDDIO current consumption during Erase/Program cycle VREG enabled 100 mA
Table 5-21. Flash Program/Erase Time

TEST
CONDITIONS
Program Time 16-Bit Word 50 s
8K Sector 250 ms
4K Sector 125 ms
Erase Time (1) 8K Sector 2 s
4K Sector 2 s
(1) The on-chip flash memory is in an erased state when the device is shipped from TI. As such, erasing the flash memory is not required
prior to programming, when programming the device for the first time. However, the erase operation is needed on all subsequent
programming operations.
Table 5-22. Flash/OTP Access Timing

PARAMETER MIN MAX UNIT
ta(fp) Paged Flash access time 40 ns
ta(fr) Random Flash access time 40 ns
ta(OTP) OTP access time 60 ns
Table 5-23. Flash Data Retention Duration

PARAMETER TEST CONDITIONS MIN MAX UNIT
tretention Data retention duration TJ = 55C 15 years

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
Table 5-24. Minimum Required Flash/OTP Wait-States at Different Frequencies

SYSCLKOUT SYSCLKOUT PAGE RANDOM OTP
(MHz) (ns) WAIT-STATE (1) WAIT-STATE (1) WAIT-STATE
60 16.67 2 2 3
55 18.18 2 2 3
50 20 1 1 2
45 22.22 1 1 2
40 25 1 1 2
35 28.57 1 1 2
30 33.33 1 1 1
25 40 0 1 1
(1) Random wait-state must be 1.
The equations to compute the Flash page wait-state and random wait-state in Table 5-24 are as follows:
t a( f p )
Flash Page Wait State = - 1 round up to the next highest integer
t c (SCO )
t a(f r)
Flash Random Wait State = - 1 round up to the next highest integer, or 1, whichever is larger

t c(SCO)
The equation to compute the OTP wait-state in Table 5-24 is as follows:
t a(OTP)
OTP Wait State = - 1 round up to the next highest integer, or 1, whichever is larger
t c(SCO)

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
6 Detailed Description
6.1 Overview
6.1.1 CPU
The 2802x (C28x) family is a member of the TMS320C2000 microcontroller (MCU) platform. The C28x-
based controllers have the same 32-bit fixed-point architecture as existing C28x MCUs. It is a very
efficient C/C++ engine, enabling users to develop not only their system control software in a high-level
language, but also enabling development of math algorithms using C/C++. The device is as efficient at
MCU math tasks as it is at system control tasks that typically are handled by microcontroller devices. This
efficiency removes the need for a second processor in many systems. The 32 x 32-bit MAC 64-bit
processing capabilities enable the controller to handle higher numerical resolution problems efficiently.
Add to this the fast interrupt response with automatic context save of critical registers, resulting in a device
that is capable of servicing many asynchronous events with minimal latency. The device has an 8-level-
deep protected pipeline with pipelined memory accesses. This pipelining enables it to execute at high
speeds without resorting to expensive high-speed memories. Special branch-look-ahead hardware
minimizes the latency for conditional discontinuities. Special store conditional operations further improve
performance.
6.1.2 Memory Bus (Harvard Bus Architecture)

As with many MCU-type devices, multiple busses are used to move data between the memories and
peripherals and the CPU. The memory bus architecture contains a program read bus, data read bus, and
data write bus. The program read bus consists of 22 address lines and 32 data lines. The data read and
write busses consist of 32 address lines and 32 data lines each. The 32-bit-wide data busses enable
single cycle 32-bit operations. The multiple bus architecture, commonly termed Harvard Bus, enables the
C28x to fetch an instruction, read a data value and write a data value in a single cycle. All peripherals and
memories attached to the memory bus prioritize memory accesses. Generally, the priority of memory bus
accesses can be summarized as follows:
Highest: Data Writes (Simultaneous data and program writes cannot occur on the
memory bus.)
Program Writes (Simultaneous data and program writes cannot occur on the
memory bus.)
Data Reads
Program Reads (Simultaneous program reads and fetches cannot occur on the
memory bus.)
Lowest: Fetches (Simultaneous program reads and fetches cannot occur on the
memory bus.)
6.1.3 Peripheral Bus

To enable migration of peripherals between various Texas Instruments (TI) MCU family of devices, the
devices adopt a peripheral bus standard for peripheral interconnect. The peripheral bus bridge multiplexes
the various busses that make up the processor Memory Bus into a single bus consisting of 16 address
lines and 16 or 32 data lines and associated control signals. Three versions of the peripheral bus are
supported. One version supports only 16-bit accesses (called peripheral frame 2). Another version
supports both 16- and 32-bit accesses (called peripheral frame 1).
Copyright 20082016, Texas Instruments Incorporated Detailed Description 37

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
6.1.4 Real-Time JTAG and Analysis

The devices implement the standard IEEE 1149.1 JTAG (1) interface for in-circuit based debug.
Additionally, the devices support real-time mode of operation allowing modification of the contents of
memory, peripheral, and register locations while the processor is running and executing code and
servicing interrupts. The user can also single step through non-time-critical code while enabling time-
critical interrupts to be serviced without interference. The device implements the real-time mode in
hardware within the CPU. This is a feature unique to the 28x family of devices, requiring no software
monitor. Additionally, special analysis hardware is provided that allows setting of hardware breakpoint or
data/address watch-points and generating various user-selectable break events when a match occurs.
These devices do not support boundary scan; however, IDCODE and BYPASS features are available if
the following considerations are taken into account. The IDCODE does not come by default. The user
needs to go through a sequence of SHIFT IR and SHIFT DR state of JTAG to get the IDCODE. For
BYPASS instruction, the first shifted DR value would be 1.
6.1.5 Flash
The F280200 device contains 8K x 16 of embedded flash memory, segregated into two 4K x 16 sectors.
The F28021/23/27 devices contain 32K x 16 of embedded flash memory, segregated into four 8K x 16
sectors. The F28020/22/26 devices contain 16K x 16 of embedded flash memory, segregated into four
4K x 16 sectors. All devices also contain a single 1K x 16 of OTP memory at address range 0x3D 7800
0x3D 7BFF. The user can individually erase, program, and validate a flash sector while leaving other
sectors untouched. However, it is not possible to use one sector of the flash or the OTP to execute flash
algorithms that erase/program other sectors. Special memory pipelining is provided to enable the flash
module to achieve higher performance. The flash/OTP is mapped to both program and data space;
therefore, it can be used to execute code or store data information. Addresses 0x3F 7FF0 0x3F 7FF5
are reserved for data variables and should not contain program code.
NOTE
The Flash and OTP wait-states can be configured by the application. This allows applications
running at slower frequencies to configure the flash to use fewer wait-states.
Flash effective performance can be improved by enabling the flash pipeline mode in the
Flash options register. With this mode enabled, effective performance of linear code
execution will be much faster than the raw performance indicated by the wait-state
configuration alone. The exact performance gain when using the Flash pipeline mode is
application-dependent.
For more information on the Flash options, Flash wait-state, and OTP wait-state registers,
see the TMS320x2802x/TMS320F2802xx Piccolo System Control and Interrupts Reference
Guide.
6.1.6 M0, M1 SARAMs

All devices contain these two blocks of single access memory, each 1K x 16 in size. The stack pointer
points to the beginning of block M1 on reset. The M0 and M1 blocks, like all other memory blocks on C28x
devices, are mapped to both program and data space. Hence, the user can use M0 and M1 to execute
code or for data variables. The partitioning is performed within the linker. The C28x device presents a
unified memory map to the programmer. This makes for easier programming in high-level languages.
6.1.7 L0 SARAM
The device contains up to 4K x 16 of single-access RAM. Refer to the device-specific memory map figures
in Section 6.2 to ascertain the exact size for a given device. This block is mapped to both program and
data space.
(1) IEEE Standard 1149.1-1990 Standard Test Access Port and Boundary Scan Architecture
38 Detailed Description Copyright 20082016, Texas Instruments Incorporated
TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
6.1.8 Boot ROM

The Boot ROM is factory-programmed with boot-loading software. Boot-mode signals are provided to tell
the bootloader software what boot mode to use on power up. The user can select to boot normally or to
download new software from an external connection or to select boot software that is programmed in the
internal Flash/ROM. The Boot ROM also contains standard tables, such as SIN/COS waveforms, for use
in math-related algorithms.
Table 6-1. Boot Mode Selection

MODE GPIO37/TDO GPIO34/COMP2OUT TRST MODE
3 1 1 0 GetMode
2 1 0 0 Wait (see Section 6.1.9 for description)
1 0 1 0 SCI
0 0 0 0 Parallel IO
EMU x x 1 Emulation Boot
6.1.8.1 Emulation Boot

When the emulator is connected, the GPIO37/TDO pin cannot be used for boot mode selection. In this
case, the boot ROM detects that an emulator is connected and uses the contents of two reserved SARAM
locations in the PIE vector table to determine the boot mode. If the content of either location is invalid,
then the Wait boot option is used. All boot mode options can be accessed in emulation boot.
6.1.8.2 GetMode
The default behavior of the GetMode option is to boot to flash. This behavior can be changed to another
boot option by programming two locations in the OTP. If the content of either OTP location is invalid, then
boot to flash is used. One of the following loaders can be specified: SCI, SPI, I2C, or OTP.
6.1.8.3 Peripheral Pins Used by the Bootloader

Table 6-2 shows which GPIO pins are used by each peripheral bootloader. Refer to the GPIO mux table
to see if these conflict with any of the peripherals you would like to use in your application.
Table 6-2. Peripheral Bootload Pins

BOOTLOADER PERIPHERAL LOADER PINS
SCI SCIRXDA (GPIO28)
SCITXDA (GPIO29)
Parallel Boot Data (GPIO[7:0])
28x Control (GPIO16)
Host Control (GPIO12)
SPI SPISIMOA (GPIO16)
SPISOMIA (GPIO17)
SPICLKA (GPIO18)
SPISTEA (GPIO19)
I2C SDAA (GPIO32) (1)
SCLA (GPIO33) (1)
(1) GPIO pins 32 and 33 may not be available on your device package. On these devices, this bootload
option is unavailable.

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
6.1.9 Security
The devices support high levels of security to protect the user firmware from being reverse engineered.
The security features a 128-bit password (hardcoded for 16 wait-states), which the user programs into the
flash. One code security module (CSM) is used to protect the flash/OTP and the L0/L1 SARAM blocks.
The security feature prevents unauthorized users from examining the memory contents via the JTAG port,
executing code from external memory or trying to boot-load some undesirable software that would export
the secure memory contents. To enable access to the secure blocks, the user must write the correct 128-
bit KEY value that matches the value stored in the password locations within the Flash.
In addition to the CSM, the emulation code security logic (ECSL) has been implemented to prevent
unauthorized users from stepping through secure code. Any code or data access to flash, user OTP, or L0
memory while the emulator is connected will trip the ECSL and break the emulation connection. To allow
emulation of secure code, while maintaining the CSM protection against secure memory reads, the user
must write the correct value into the lower 64 bits of the KEY register, which matches the value stored in
the lower 64 bits of the password locations within the flash. Note that dummy reads of all 128 bits of the
password in the flash must still be performed. If the lower 64 bits of the password locations are all ones
(unprogrammed), then the KEY value does not need to match.
When initially debugging a device with the password locations in flash programmed (that is, secured), the
CPU will start running and may execute an instruction that performs an access to a protected ECSL area.
If this happens, the ECSL will trip and cause the emulator connection to be cut.
The solution is to use the Wait boot option. This will sit in a loop around a software breakpoint to allow an
emulator to be connected without tripping security. The user can then exit this mode once the emulator is
connected by using one of the emulation boot options as described in the TMS320x2802x Piccolo Boot
ROM Reference Guide. Piccolo devices do not support a hardware wait-in-reset mode.
NOTE
When the code-security passwords are programmed, all addresses between 0x3F7F80
and 0x3F7FF5 cannot be used as program code or data. These locations must be
programmed to 0x0000.
If the code security feature is not used, addresses 0x3F7F80 through 0x3F7FEF may be
used for code or data. Addresses 0x3F7FF0 0x3F7FF5 are reserved for data and
should not contain program code.
The 128-bit password (at 0x3F 7FF8 0x3F 7FFF) must not be programmed to zeros. Doing
so would permanently lock the device.

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
Disclaimer
Code Security Module Disclaimer
THE CODE SECURITY MODULE (CSM) INCLUDED ON THIS DEVICE WAS DESIGNED
TO PASSWORD PROTECT THE DATA STORED IN THE ASSOCIATED MEMORY
(EITHER ROM OR FLASH) AND IS WARRANTED BY TEXAS INSTRUMENTS (TI), IN
ACCORDANCE WITH ITS STANDARD TERMS AND CONDITIONS, TO CONFORM TO
TI'S PUBLISHED SPECIFICATIONS FOR THE WARRANTY PERIOD APPLICABLE FOR
THIS DEVICE.
TI DOES NOT, HOWEVER, WARRANT OR REPRESENT THAT THE CSM CANNOT BE
COMPROMISED OR BREACHED OR THAT THE DATA STORED IN THE ASSOCIATED
MEMORY CANNOT BE ACCESSED THROUGH OTHER MEANS. MOREOVER, EXCEPT
AS SET FORTH ABOVE, TI MAKES NO WARRANTIES OR REPRESENTATIONS
CONCERNING THE CSM OR OPERATION OF THIS DEVICE, INCLUDING ANY IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
IN NO EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL, INDIRECT,
INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING IN ANY WAY
OUT OF YOUR USE OF THE CSM OR THIS DEVICE, WHETHER OR NOT TI HAS BEEN
ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE,
BUT ARE NOT LIMITED TO LOSS OF DATA, LOSS OF GOODWILL, LOSS OF USE OR
INTERRUPTION OF BUSINESS OR OTHER ECONOMIC LOSS.
6.1.10 Peripheral Interrupt Expansion (PIE) Block

The PIE block serves to multiplex numerous interrupt sources into a smaller set of interrupt inputs. The
PIE block can support up to 96 peripheral interrupts. On the F2802x, 33 of the possible 96 interrupts are
used by peripherals. The 96 interrupts are grouped into blocks of 8 and each group is fed into 1 of
12 CPU interrupt lines (INT1 to INT12). Each of the 96 interrupts is supported by its own vector stored in a
dedicated RAM block that can be overwritten by the user. The vector is automatically fetched by the CPU
on servicing the interrupt. It takes 8 CPU clock cycles to fetch the vector and save critical CPU registers.
Hence the CPU can quickly respond to interrupt events. Prioritization of interrupts is controlled in
hardware and software. Each individual interrupt can be enabled/disabled within the PIE block.
6.1.11 External Interrupts (XINT1XINT3)

The devices support three masked external interrupts (XINT1XINT3). Each of the interrupts can be
selected for negative, positive, or both negative and positive edge triggering and can also be
enabled/disabled. These interrupts also contain a 16-bit free running up counter, which is reset to zero
when a valid interrupt edge is detected. This counter can be used to accurately time stamp the interrupt.
There are no dedicated pins for the external interrupts. XINT1, XINT2, and XINT3 interrupts can accept
inputs from GPIO0GPIO31 pins.
6.1.12 Internal Zero Pin Oscillators, Oscillator, and PLL

The device can be clocked by either of the two internal zero-pin oscillators, an external oscillator, or by a
crystal attached to the on-chip oscillator circuit (48-pin devices only). A PLL is provided supporting up to
12 input-clock-scaling ratios. The PLL ratios can be changed on-the-fly in software, enabling the user to
scale back on operating frequency if lower power operation is desired. Refer to Section 5, Electrical
Specifications, for timing details. The PLL block can be set in bypass mode.
6.1.13 Watchdog
Each device contains two watchdogs: CPU-Watchdog that monitors the core and NMI-Watchdog that is a
missing clock-detect circuit. The user software must regularly reset the CPU-watchdog counter within a
certain time frame; otherwise, the CPU-watchdog generates a reset to the processor. The CPU-watchdog
can be disabled if necessary. The NMI-Watchdog engages only in case of a clock failure and can either
generate an interrupt or a device reset.
TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
6.1.14 Peripheral Clocking

The clocks to each individual peripheral can be enabled/disabled to reduce power consumption when a
peripheral is not in use. Additionally, the system clock to the serial ports (except I2C) can be scaled
relative to the CPU clock.
6.1.15 Low-power Modes

The devices are full static CMOS devices. Three low-power modes are provided:
IDLE: Place CPU in low-power mode. Peripheral clocks may be turned off selectively and
only those peripherals that need to function during IDLE are left operating. An
enabled interrupt from an active peripheral or the watchdog timer will wake the
processor from IDLE mode.
STANDBY: Turns off clock to CPU and peripherals. This mode leaves the oscillator and PLL
functional. An external interrupt event will wake the processor and the peripherals.
Execution begins on the next valid cycle after detection of the interrupt event
HALT: This mode basically shuts down the device and places it in the lowest possible power
consumption mode. If the internal zero-pin oscillators are used as the clock source,
the HALT mode turns them off, by default. To keep these oscillators from shutting
down, the INTOSCnHALTI bits in CLKCTL register may be used. The zero-pin
oscillators may thus be used to clock the CPU-watchdog in this mode. If the on-chip
crystal oscillator is used as the clock source, it is shut down in this mode. A reset or
an external signal (through a GPIO pin) or the CPU-watchdog can wake the device
from this mode.
The CPU clock (OSCCLK) and WDCLK should be from the same clock source before attempting to put
the device into HALT or STANDBY.

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
6.1.16 Peripheral Frames 0, 1, 2 (PFn)

The device segregates peripherals into three sections. The mapping of peripherals is as follows:
PF0: PIE: PIE Interrupt Enable and Control Registers Plus PIE Vector Table
Flash: Flash Waitstate Registers
Timers: CPU-Timers 0, 1, 2 Registers
CSM: Code Security Module KEY Registers
ADC: ADC Result Registers
PF1: GPIO: GPIO MUX Configuration and Control Registers
ePWM: Enhanced Pulse Width Modulator Module and Registers
eCAP: Enhanced Capture Module and Registers
Comparators: Comparator Modules
PF2: SYS: System Control Registers
SCI: Serial Communications Interface (SCI) Control and RX/TX Registers
SPI: Serial Port Interface (SPI) Control and RX/TX Registers
ADC: ADC Status, Control, and Configuration Registers
I2C: Inter-Integrated Circuit Module and Registers
XINT: External Interrupt Registers
6.1.17 General-Purpose Input/Output (GPIO) Multiplexer

Most of the peripheral signals are multiplexed with general-purpose input/output (GPIO) signals. This
enables the user to use a pin as GPIO if the peripheral signal or function is not used. On reset, GPIO pins
are configured as inputs. The user can individually program each pin for GPIO mode or peripheral signal
mode. For specific inputs, the user can also select the number of input qualification cycles. This is to filter
unwanted noise glitches. The GPIO signals can also be used to bring the device out of specific low-power
modes.
6.1.18 32-Bit CPU-Timers (0, 1, 2)

CPU-Timers 0, 1, and 2 are identical 32-bit timers with presettable periods and with 16-bit clock
prescaling. The timers have a 32-bit count-down register, which generates an interrupt when the counter
reaches zero. The counter is decremented at the CPU clock speed divided by the prescale value setting.
When the counter reaches zero, it is automatically reloaded with a 32-bit period value.
CPU-Timer 0 is for general use and is connected to the PIE block. CPU-Timer 1 is also for general use
and can be connected to INT13 of the CPU. CPU-Timer 2 is reserved for DSP/BIOS. It is connected to
INT14 of the CPU. If DSP/BIOS is not being used, CPU-Timer 2 is available for general use.
CPU-Timer 2 can be clocked by any one of the following:
SYSCLKOUT (default)
Internal zero-pin oscillator 1 (INTOSC1)
Internal zero-pin oscillator 2 (INTOSC2)
External clock source

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
6.1.19 Control Peripherals

The devices support the following peripherals that are used for embedded control and communication:
ePWM: The enhanced PWM peripheral supports independent/complementary PWM

generation, adjustable dead-band generation for leading/trailing edges,
latched/cycle-by-cycle trip mechanism. Some of the PWM pins support the
HRPWM high resolution duty and period features. The type 1 module found on
2802x devices also supports increased dead-band resolution, enhanced SOC and
interrupt generation, and advanced triggering including trip functions based on
comparator outputs.
eCAP: The enhanced capture peripheral uses a 32-bit time base and registers up to four
programmable events in continuous/one-shot capture modes.
This peripheral can also be configured to generate an auxiliary PWM signal.
ADC: The ADC block is a 12-bit converter. It has up to 13 single-ended channels pinned
out, depending on the device. It contains two sample-and-hold units for
simultaneous sampling.
Comparator: Each comparator block consists of one analog comparator along with an internal
10-bit reference for supplying one input of the comparator.
6.1.20 Serial Port Peripherals

The devices support the following serial communication peripherals:
SPI: The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream
of programmed length (one to sixteen bits) to be shifted into and out of the device
at a programmable bit-transfer rate. Normally, the SPI is used for communications
between the MCU and external peripherals or another processor. Typical
applications include external I/O or peripheral expansion through devices such as
shift registers, display drivers, and ADCs. Multidevice communications are
supported by the master/slave operation of the SPI. The SPI contains a 4-level
receive and transmit FIFO for reducing interrupt servicing overhead.
SCI: The serial communications interface is a two-wire asynchronous serial port,
commonly known as UART. The SCI contains a 4-level receive and transmit FIFO
for reducing interrupt servicing overhead.
I2C: The inter-integrated circuit (I2C) module provides an interface between a MCU
and other devices compliant with Philips Semiconductors Inter-IC bus ( I2C-bus)
specification version 2.1 and connected by way of an I2C-bus. External
components attached to this 2-wire serial bus can transmit/receive up to 8-bit data
to/from the MCU through the I2C module. The I2C contains a 4-level receive and
transmit FIFO for reducing interrupt servicing overhead.

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
6.2 Memory Maps

In Figure 6-1, Figure 6-2, Figure 6-3, Figure 6-4, and Figure 6-5, the following apply:
Memory blocks are not to scale.
Peripheral Frame 0, Peripheral Frame 1 and Peripheral Frame 2 memory maps are restricted to data
memory only. A user program cannot access these memory maps in program space.
Protected means the order of Write-followed-by-Read operations is preserved rather than the pipeline
order.
Certain memory ranges are EALLOW protected against spurious writes after configuration.
Locations 0x3D7C80 0x3D7CC0 contain the internal oscillator and ADC calibration routines. These
locations are not programmable by the user.

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
Data Space Prog Space

0x00 0000 M0 Vector RAM (Enabled if VMAP = 0)
0x00 0040 M0 SARAM (1K x 16, 0-Wait)
0x00 0400 M1 SARAM (1K x 16, 0-Wait)
0x00 0800 Peripheral Frame 0
0x00 0D00
PIE Vector - RAM
(256 x 16)
(Enabled if Reserved
VMAP = 1,
ENPIE = 1)
0x00 0E00 Peripheral Frame 0

0x00 2000 Reserved
0x00 6000
Peripheral Frame 1
(4K x 16, Protected)
Reserved
0x00 7000
Peripheral Frame 2
0x00 8000
L0 SARAM (4K x 16)
(0-Wait, Secure Zone + ECSL, Dual Mapped)
0x00 9000 Reserved

0x3D 7800 User OTP (1K x 16, Secure Zone + ECSL)
0x3D 7C00
Reserved
0x3D 7C80
Calibration Data
0x3D 7CC0
Get_mode function
0x3D 7CE0
Reserved
0x3D 7E80
Calibration Data
0x3D 7EB0
Reserved
0x3D 7FFF
PARTID
0x3D 8000
Reserved
0x3F 0000
FLASH
(32K x 16, 4 Sectors, Secure Zone + ECSL)
0x3F 7FF8 128-Bit Password

0x3F 8000
L0 SARAM (4K x 16)
0x3F 9000 Reserved

0x3F E000 Boot ROM (8K x 16, 0-Wait)
0x3F FFC0 Vector (32 Vectors, Enabled if VMAP = 1)
A. Memory locations 0x3D 7E800x3D 7EAF are reserved in TMX/TMP silicon.
Figure 6-1. 28023/28027 Memory Map

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200

0x00 0040 M0 SARAM (1K x 16, 0-Wait)
0x00 0400 M1 SARAM (1K x 16, 0-Wait)
0x00 0D00
PIE Vector - RAM
(256 x 16)
VMAP = 1,
ENPIE = 1)

0x00 2000 Reserved
0x00 6000
Peripheral Frame 1
Reserved
0x00 7000
Peripheral Frame 2
0x00 8000
L0 SARAM (4K x 16)
0x00 9000 Reserved

0x3D 7C00 Reserved
0x3D 7C80
Calibration Data
0x3D 7CC0
Get_mode function
0x3D 7CE0
Reserved
0x3D 7E80
Calibration Data
0x3D 7EB0
Reserved
0x3D 7FFF
PARTID
0x3D 8000
Reserved
0x3F 4000
FLASH

0x3F 8000
L0 SARAM (4K x 16)
0x3F 9000 Reserved

Figure 6-2. 28022/28026 Memory Map

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200

0x00 0040 M0 SARAM (1K x 16, 0-Wait)
0x00 0400 M1 SARAM (1K x 16, 0-Wait)
0x00 0D00
PIE Vector - RAM
(256 x 16)
VMAP = 1,
ENPIE = 1)

0x00 2000 Reserved
0x00 6000
Peripheral Frame 1
Reserved
0x00 7000
Peripheral Frame 2
0x00 8000
L0 SARAM (3K x 16)
0x00 8C00 Reserved

0x3D 7C00
Reserved
0x3D 7C80
Calibration Data
0x3D 7CC0
Get_mode function
0x3D 7CE0
Reserved
0x3D 7E80
Calibration Data
0x3D 7EB0
Reserved
0x3D 7FFF
PARTID
0x3D 8000
Reserved
0x3F 0000
FLASH

0x3F 8000
L0 SARAM (3K x 16)
0x3F 8C00 Reserved

Figure 6-3. 28021 Memory Map

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200

0x00 0040 M0 SARAM (1K x 16, 0-Wait)
0x00 0400 M1 SARAM (1K x 16, 0-Wait)
0x00 0D00
PIE Vector - RAM
(256 x 16)
VMAP = 1,
ENPIE = 1)

0x00 2000 Reserved
0x00 6000
Peripheral Frame 1
Reserved
0x00 7000
Peripheral Frame 2
0x00 8000
L0 SARAM (1K x 16)
0x00 8400 Reserved

0x3D 7C00
Reserved
0x3D 7C80
Calibration Data
0x3D 7CC0
Get_mode function
0x3D 7CE0
Reserved
0x3D 7E80
Calibration Data
0x3D 7EB0
Reserved
0x3D 7FFF
PARTID
0x3D 8000
Reserved
0x3F 4000
FLASH

0x3F 8000
L0 SARAM (1K x 16)
0x3F 8400 Reserved


TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200

0x00 0040 M0 SARAM (1K x 16, 0-Wait)
0x00 0400 M1 SARAM (1K x 16, 0-Wait)
0x00 0D00
PIE Vector - RAM
(256 x 16)
VMAP = 1,
ENPIE = 1)

0x00 2000 Reserved
0x00 6000
Peripheral Frame 1
Reserved
0x00 7000
Peripheral Frame 2
0x00 8000
L0 SARAM (1K x 16)
0x00 8400 Reserved

0x3D 7C00 Reserved
0x3D 7C80
Calibration Data
0x3D 7CC0
Get_mode function
0x3D 7CE0
Reserved
0x3D 7E80
Calibration Data
0x3D 7EB0
Reserved
0x3D 7FFF
PARTID
0x3D 8000
Reserved
0x3F 6000
FLASH

0x3F 8000
L0 SARAM (1K x 16)
0x3F 8400 Reserved

0x3F FFC0
Vector (32 Vectors, Enabled if VMAP = 1)

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
Table 6-3. Addresses of Flash Sectors in F28021/28023/28027

ADDRESS RANGE PROGRAM AND DATA SPACE
0x3F 0000 0x3F 1FFF Sector D (8K x 16)
0x3F 2000 0x3F 3FFF Sector C (8K x 16)
0x3F 4000 0x3F 5FFF Sector B (8K x 16)
0x3F 6000 0x3F 7F7F Sector A (8K x 16)
Program to 0x0000 when using the
0x3F 7F80 0x3F 7FF5
Code Security Module
Boot-to-Flash Entry Point
0x3F 7FF6 0x3F 7FF7
(program branch instruction here)
Security Password (128-Bit)
0x3F 7FF8 0x3F 7FFF
(Do not program to all zeros)
Table 6-4. Addresses of Flash Sectors in F28020/28022/28026

0x3F 4000 0x3F 4FFF Sector D (4K x 16)
0x3F 5000 0x3F 5FFF Sector C (4K x 16)
0x3F 7F80 0x3F 7FF5
0x3F 7FF6 0x3F 7FF7
0x3F 7FF8 0x3F 7FFF
Table 6-5. Addresses of Flash Sectors in F280200

0x3F 7F80 0x3F 7FF5
0x3F 7FF6 0x3F 7FF7
0x3F 7FF8 0x3F 7FFF
NOTE
When the code-security passwords are programmed, all addresses between 0x3F 7F80
and 0x3F 7FF5 cannot be used as program code or data. These locations must be
programmed to 0x0000.
If the code security feature is not used, addresses 0x3F 7F80 through 0x3F 7FEF may
be used for code or data. Addresses 0x3F 7FF0 0x3F 7FF5 are reserved for data and
should not contain program code.
Table 6-6 shows how to handle these memory locations.

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
Table 6-6. Impact of Using the Code Security Module

FLASH
ADDRESS
CODE SECURITY ENABLED CODE SECURITY DISABLED
0x3F 7F80 0x3F 7FEF Application code and data
Fill with 0x0000
0x3F 7FF0 0x3F 7FF5 Reserved for data only
Peripheral Frame 1 and Peripheral Frame 2 are grouped together to enable these blocks to be write/read
peripheral block protected. The protected mode makes sure that all accesses to these blocks happen as
written. Because of the pipeline, a write immediately followed by a read to different memory locations, will
appear in reverse order on the memory bus of the CPU. This can cause problems in certain peripheral
applications where the user expected the write to occur first (as written). The CPU supports a block
protection mode where a region of memory can be protected so that operations occur as written (the
penalty is extra cycles are added to align the operations). This mode is programmable and by default, it
protects the selected zones.
The wait-states for the various spaces in the memory map area are listed in Table 6-7.
Table 6-7. Wait-states

AREA WAIT-STATES (CPU) COMMENTS
M0 and M1 SARAMs 0-wait Fixed
Peripheral Frame 0 0-wait
Peripheral Frame 1 0-wait (writes) Cycles can be extended by peripheral generated ready.
2-wait (reads) Back-to-back write operations to Peripheral Frame 1 registers will incur
a 1-cycle stall (1-cycle delay).
Peripheral Frame 2 0-wait (writes) Fixed. Cycles cannot be extended by the peripheral.
2-wait (reads)
L0 SARAM 0-wait data and program Assumes no CPU conflicts
OTP Programmable Programmed via the Flash registers.
1-wait minimum 1-wait is minimum number of wait states allowed.
FLASH Programmable Programmed via the Flash registers.
0-wait Paged min
1-wait Random min
Random Paged
FLASH Password 16-wait fixed Wait states of password locations are fixed.
Boot-ROM 0-wait

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
6.3 Register Maps

The devices contain three peripheral register spaces. The spaces are categorized as follows:
Peripheral Frame 0: These are peripherals that are mapped directly to the CPU memory bus.
See Table 6-8.
Peripheral Frame 1: These are peripherals that are mapped to the 32-bit peripheral bus. See
Table 6-9.
Peripheral Frame 2: These are peripherals that are mapped to the 16-bit peripheral bus. See
Table 6-10.
Table 6-8. Peripheral Frame 0 Registers (1)

NAME ADDRESS RANGE SIZE (16) EALLOW PROTECTED (2)
Device Emulation Registers 0x00 0880 0x00 0984 261 Yes
System Power Control Registers 0x00 0985 0x00 0987 3 Yes
(3)
FLASH Registers 0x00 0A80 0x00 0ADF 96 Yes
Code Security Module Registers 0x00 0AE0 0x00 0AEF 16 Yes
ADC registers (0 wait read only) 0x00 0B00 0x00 0B0F 16 No
CPUTIMER0/1/2 Registers 0x00 0C00 0x00 0C3F 64 No
PIE Registers 0x00 0CE0 0x00 0CFF 32 No
PIE Vector Table 0x00 0D00 0x00 0DFF 256 No
(1) Registers in Frame 0 support 16-bit and 32-bit accesses.
(2) If registers are EALLOW protected, then writes cannot be performed until the EALLOW instruction is executed. The EDIS instruction
disables writes to prevent stray code or pointers from corrupting register contents.
(3) The Flash Registers are also protected by the Code Security Module (CSM).
Table 6-9. Peripheral Frame 1 Registers

NAME ADDRESS RANGE SIZE (16) EALLOW PROTECTED
(1)
Comparator 1 registers 0x00 6400 0x00 641F 32
(1)
Comparator 2 registers 0x00 6420 0x00 643F 32
(1)
ePWM1 + HRPWM1 registers 0x00 6800 0x00 683F 64
(1)
ePWM2 + HRPWM2 registers 0x00 6840 0x00 687F 64
(1)
ePWM3 + HRPWM3 registers 0x00 6880 0x00 68BF 64
(1)
ePWM4 + HRPWM4 registers 0x00 68C0 0x00 68FF 64
eCAP1 registers 0x00 6A00 0x00 6A1F 32 No
(1)
GPIO registers 0x00 6F80 0x00 6FFF 128
(1) Some registers are EALLOW protected. See the module reference guide for more information.
Table 6-10. Peripheral Frame 2 Registers

NAME ADDRESS RANGE SIZE (16) EALLOW PROTECTED
System Control Registers 0x00 7010 0x00 702F 32 Yes
SPI-A Registers 0x00 7040 0x00 704F 16 No
SCI-A Registers 0x00 7050 0x00 705F 16 No
NMI Watchdog Interrupt Registers 0x00 7060 0x00 706F 16 Yes
External Interrupt Registers 0x00 7070 0x00 707F 16 Yes
(1)
ADC Registers 0x00 7100 0x00 717F 128
(1)
I2C-A Registers 0x00 7900 0x00 793F 64
(1) Some registers are EALLOW protected. See the module reference guide for more information.

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
6.4 Device Emulation Registers

These registers are used to control the protection mode of the C28x CPU and to monitor some critical
device signals. The registers are defined in Table 6-11 .
Table 6-11. Device Emulation Registers

ADDRESS EALLOW
NAME SIZE (x16) DESCRIPTION
RANGE PROTECTED
0x0880
DEVICECNF 2 Device Configuration Register Yes
0x0881
PARTID 0x3D 7FFF 1 Part ID Register TMS320F280200PT 0x00C1
TMS320F280200DA 0x00C0
TMS320F28027PT 0x00CF
TMS320F28027DA 0x00CE
TMS320F28027FPT 0x00CF
TMS320F28027FDA 0x00CE
TMS320F28026PT 0x00C7
TMS320F28026DA 0x00C6
TMS320F28026FPT 0x00C7
No
TMS320F28026FDA 0x00C6
TMS320F28023PT 0x00CD
TMS320F28023DA 0x00CC
TMS320F28022PT 0x00C5
TMS320F28022DA 0x00C4
TMS320F28021PT 0x00CB
TMS320F28021DA 0x00CA
TMS320F28020PT 0x00C3
TMS320F28020DA 0x00C2
CLASSID 0x0882 1 Class ID Register TMS320F280200PT/DA 0x00C7
TMS320F28027PT/DA 0x00CF
TMS320F28027FPT/DA 0x00CF
TMS320F28026PT/DA 0x00C7
TMS320F28026FPT/DA 0x00C7 No
REVID 0x0883 1 Revision ID 0x0000 - Silicon Rev. 0 - TMS
Register
0x0001 - Silicon Rev. A - TMS No
0x0002 - Silicon Rev. B - TMS

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
6.5 VREG/BOR/POR
Although the core and I/O circuitry operate on two different voltages, these devices have an on-chip
voltage regulator (VREG) to generate the VDD voltage from the VDDIO supply. This eliminates the cost and
space of a second external regulator on an application board. Additionally, internal power-on reset (POR)
and brown-out reset (BOR) circuits monitor both the VDD and VDDIO rails during power-up and run mode.
6.5.1 On-chip Voltage Regulator (VREG)

A linear regulator generates the core voltage (VDD) from the VDDIO supply. Therefore, although capacitors
are required on each VDD pin to stabilize the generated voltage, power need not be supplied to these pins
to operate the device. Conversely, the VREG can be disabled, should power or redundancy be the
primary concern of the application.
6.5.1.1 Using the On-chip VREG

To utilize the on-chip VREG, the VREGENZ pin should be tied low and the appropriate recommended
operating voltage should be supplied to the VDDIO and VDDA pins. In this case, the VDD voltage needed by
the core logic will be generated by the VREG. Each VDD pin requires on the order of 1.2 F (minimum)
capacitance for proper regulation of the VREG. These capacitors should be located as close as possible
to the VDD pins.
6.5.1.2 Disabling the On-chip VREG

To conserve power, it is also possible to disable the on-chip VREG and supply the core logic voltage to
the VDD pins with a more efficient external regulator. To enable this option, the VREGENZ pin must be tied
high.

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
6.5.2 On-chip Power-On Reset (POR) and Brown-Out Reset (BOR) Circuit
Two on-chip supervisory circuits, the power-on reset (POR) and the brown-out reset (BOR) remove the
burden of monitoring the VDD and VDDIO supply rails from the application board. The purpose of the POR is
to create a clean reset throughout the device during the entire power-up procedure. The trip point is a
looser, lower trip point than the BOR, which watches for dips in the VDD or VDDIO rail during device
operation. The POR function is present on both VDD and VDDIO rails at all times. After initial device power-
up, the BOR function is present on VDDIO at all times, and on VDD when the internal VREG is enabled
(VREGENZ pin is tied low). Both functions tie the XRS pin low when one of the voltages is below their
respective trip point. Additionally, when the internal voltage regulator is enabled, an over-voltage
protection circuit will tie XRS low if the VDD rail rises above its trip point. See Section 5 for the various trip
points as well as the delay time for the device to release the XRS pin after the under/over-voltage
condition is removed. Figure 6-6 shows the VREG, POR, and BOR. To disable both the VDD and VDDIO
BOR functions, a bit is provided in the BORCFG register. Refer to the TMS320x2802x/TMS320F2802xx
Piccolo System Control and Interrupts Reference Guide for details.
In
I/O Pin
Out
(Force Hi-Z When High)
DIR (0 = Input, 1 = Output)
Internal SYSRS
Weak PU
Deglitch SYSCLKOUT
Filter
WDRST Sync RS
C28
Core
MCLKRS
JTAG
TCK
PLL Detect
XRS
+ Logic
Pin
Clocking
Logic
VREGHALT
(A)
WDRST
PBRS
(B) POR/BOR On-Chip
Generating Voltage
Module VREGENZ
Regulator
(VREG)
A. WDRST is the reset signal from the CPU-watchdog.

B. PBRS is the reset signal from the POR/BOR module.
Figure 6-6. VREG + POR + BOR + Reset Signal Connectivity

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
6.6 System Control

This section describes the oscillator and clocking mechanisms, the watchdog function and the low power
modes.
Table 6-12. PLL, Clocking, Watchdog, and Low-Power Mode Registers

NAME ADDRESS SIZE (x16) DESCRIPTION (1)
BORCFG 0x00 0985 1 BOR Configuration Register
XCLK 0x00 7010 1 XCLKOUT Control
PLLSTS 0x00 7011 1 PLL Status Register
CLKCTL 0x00 7012 1 Clock Control Register
PLLLOCKPRD 0x00 7013 1 PLL Lock Period
INTOSC1TRIM 0x00 7014 1 Internal Oscillator 1 Trim Register
INTOSC2TRIM 0x00 7016 1 Internal Oscillator 2 Trim Register
LOSPCP 0x00 701B 1 Low-Speed Peripheral Clock Prescaler Register
PCLKCR0 0x00 701C 1 Peripheral Clock Control Register 0
PCLKCR1 0x00 701D 1 Peripheral Clock Control Register 1
LPMCR0 0x00 701E 1 Low Power Mode Control Register 0
PCLKCR3 0x00 7020 1 Peripheral Clock Control Register 3
PLLCR 0x00 7021 1 PLL Control Register
SCSR 0x00 7022 1 System Control and Status Register
WDCNTR 0x00 7023 1 Watchdog Counter Register
WDKEY 0x00 7025 1 Watchdog Reset Key Register
WDCR 0x00 7029 1 Watchdog Control Register
(1) All registers in this table are EALLOW protected.

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
Figure 6-7 shows the various clock domains that are discussed. Figure 6-8 shows the various clock
sources (both internal and external) that can provide a clock for device operation.
PCLKCR0/1/3 LOSPCP SYSCLKOUT

(System Ctrl Regs) (System Ctrl Regs) C28x Core CLKIN
Clock Enables LSPCLK
Peripheral
I/O SPI-A, SCI-A
Registers PF2
Clock Enables
Peripheral
I/O eCAP1
Registers PF1
GPIO Clock Enables
Mux
Peripheral
I/O ePWM1/.../4
Registers PF1
Clock Enables
Peripheral
I/O I2C-A
Registers PF2
Clock Enables
ADC PF2
16 Ch 12-Bit ADC Registers
Analog PF0
GPIO
Mux Clock Enables
COMP
6 COMP1/2
Registers PF1
A. CLKIN is the clock into the CPU. It is passed out of the CPU as SYSCLKOUT (that is, CLKIN is the same frequency
as SYSCLKOUT).
Figure 6-7. Clock and Reset Domains

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
CLKCTL[WDCLKSRCSEL]
Internal 0
(A) OSC1CLK
INTOSC1TRIM Reg OSC 1
(10 MHz) OSCCLKSRC1 WDCLK
CPU-Watchdog
(OSC1CLK on XRS reset)
OSCE
1
CLKCTL[INTOSC1OFF]
1 = Turn OSC Off
CLKCTL[INTOSC1HALT] CLKCTL[OSCCLKSRCSEL]
WAKEOSC
1 = Ignore HALT
0
Internal OSC2CLK
(A)
INTOSC2TRIM Reg OSC 2 OSCCLK PLL
(10 MHz) (B)
(OSC1CLK on XRS reset) Missing-Clock-Detect Circuit
1
OSCE
CLKCTL[TRM2CLKPRESCALE]
CLKCTL[TMR2CLKSRCSEL]
1 = Turn OSC Off

10
CLKCTL[INTOSC2OFF] Prescale SYNC
11 /1, /2, /4, Edge
/8, /16 Detect 01, 10, 11
1 = Ignore HALT 1 01 CPUTMR2CLK
CLKCTL[INTOSC2HALT] 00
SYSCLKOUT
OSCCLKSRC2
0
XCLK[XCLKINSEL] 0 = GPIO38 CLKCTL[OSCCLKSRC2SEL]
1 = GPIO19
CLKCTL[XCLKINOFF]
0 1
XCLKIN GPIO19
or 0
GPIO38
XCLKIN
X1
EXTCLK
(Crystal)
XTAL OSC WAKEOSC
X2 (Oscillators enabled when this signal is high)
CLKCTL[XTALOSCOFF] 0 = OSC on (default on reset)

1 = Turn OSC off
A. Register loaded from TI OTP-based calibration function.
B. See Section 6.6.4 for details on missing clock detection.
Figure 6-8. Clock Tree

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
6.6.1 Internal Zero Pin Oscillators

The F2802x devices contain two independent internal zero pin oscillators. By default both oscillators are
turned on at power up, and internal oscillator 1 is the default clock source at this time. For power savings,
unused oscillators may be powered down by the user. The center frequency of these oscillators is
determined by their respective oscillator trim registers, written to in the calibration routine as part of the
boot ROM execution. See Section 5, Electrical Specifications, for more information on these oscillators.
6.6.2 Crystal Oscillator Option

The on-chip crystal oscillator X1 and X2 pins are 1.8-V level signals and must never have 3.3-V level
signals applied to them. If a system 3.3-V external oscillator is to be used as a clock source, it should be
connected to the XCLKIN pin only. The X1 pin is not intended to be used as a single-ended clock input, it
should be used with X2 and a crystal.
The typical specifications for the external quartz crystal (fundamental mode, parallel resonant) are listed in
Table 6-13. Furthermore, ESR range = 30 to 150 .
Table 6-13. Typical Specifications for External Quartz Crystal (1)

FREQUENCY (MHz) Rd () CL1 (pF) CL2 (pF)
5 2200 18 18
10 470 15 15
15 0 15 15
20 0 12 12
(1) Cshunt should be less than or equal to 5 pF.
XCLKIN/GPIO19/38 X1 X2
Turn off Rd
XCLKIN path
in CLKCTL
register
CL1 Crystal CL2
A. X1/X2 pins are available in 48-pin package only.

Figure 6-9. Using the On-chip Crystal Oscillator
NOTE
1. CL1 and CL2 are the total capacitance of the circuit board and components excluding the
IC and crystal. The value is usually approximately twice the value of the crystal's load
capacitance.
2. The load capacitance of the crystal is described in the crystal specifications of the
manufacturers.
3. TI recommends that customers have the resonator/crystal vendor characterize the
operation of their device with the MCU chip. The resonator/crystal vendor has the
equipment and expertise to tune the tank circuit. The vendor can also advise the
customer regarding the proper tank component values that will produce proper start up
and stability over the entire operating range.

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
XCLKIN/GPIO19/38 X1 X2
External Clock Signal NC

(Toggling 0VDDIO)
Figure 6-10. Using a 3.3-V External Oscillator
6.6.3 PLL-Based Clock Module

The devices have an on-chip, PLL-based clock module. This module provides all the necessary clocking
signals for the device, as well as control for low-power mode entry. The PLL has a 4-bit ratio control
PLLCR[DIV] to select different CPU clock rates. The watchdog module should be disabled before writing
to the PLLCR register. It can be re-enabled (if need be) after the PLL module has stabilized, which takes
1 ms. The input clock and PLLCR[DIV] bits should be chosen in such a way that the output frequency of
the PLL (VCOCLK) is at least 50 MHz.
Table 6-14. PLL Settings

SYSCLKOUT (CLKIN)
PLLCR[DIV] VALUE (1) (2)
(3)
PLLSTS[DIVSEL] = 0 or 1 PLLSTS[DIVSEL] = 2 PLLSTS[DIVSEL] = 3
0000 (PLL bypass) OSCCLK/4 (Default) (1) OSCCLK/2 OSCCLK
0001 (OSCCLK * 1)/4 (OSCCLK * 1)/2 (OSCCLK * 1)/1
(1) The PLL control register (PLLCR) and PLL Status Register (PLLSTS) are reset to their default state by the XRS signal or a watchdog
reset only. A reset issued by the debugger or the missing clock detect logic has no effect.
(2) This register is EALLOW protected. See the TMS320x2802x/TMS320F2802xx Piccolo System Control and Interrupts Reference Guide
for more information.
(3) By default, PLLSTS[DIVSEL] is configured for /4. (The boot ROM changes this to /1.) PLLSTS[DIVSEL] must be 0 before writing to the
PLLCR and should be changed only after PLLSTS[PLLLOCKS] = 1.
Table 6-15. CLKIN Divide Options

PLLSTS [DIVSEL] CLKIN DIVIDE
0 /4
1 /4
2 /2
3 /1

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
The PLL-based clock module provides four modes of operation:

INTOSC1 (Internal Zero-pin Oscillator 1): This is the on-chip internal oscillator 1. This can provide
the clock for the Watchdog block, core and CPU-Timer 2
INTOSC2 (Internal Zero-pin Oscillator 2): This is the on-chip internal oscillator 2. This can provide
the clock for the Watchdog block, core and CPU-Timer 2. Both INTOSC1 and INTOSC2 can be
independently chosen for the Watchdog block, core and CPU-Timer 2.
Crystal/Resonator Operation: The on-chip (crystal) oscillator enables the use of an external
crystal/resonator attached to the device to provide the time base. The crystal/resonator is connected to
the X1/X2 pins. Some devices may not have the X1/X2 pins. See Table 4-1 for details.
External Clock Source Operation: If the on-chip (crystal) oscillator is not used, this mode allows it to
be bypassed. The device clocks are generated from an external clock source input on the XCLKIN pin.
Note that the XCLKIN is multiplexed with GPIO19 or GPIO38 pin. The XCLKIN input can be selected
as GPIO19 or GPIO38 via the XCLKINSEL bit in XCLK register. The CLKCTL[XCLKINOFF] bit
disables this clock input (forced low). If the clock source is not used or the respective pins are used as
GPIOs, the user should disable at boot time.
Before changing clock sources, ensure that the target clock is present. If a clock is not present, then that
clock source must be disabled (using the CLKCTL register) before switching clocks.
Table 6-16. Possible PLL Configuration Modes

CLKIN AND
PLL MODE REMARKS PLLSTS[DIVSEL]
SYSCLKOUT
Invoked by the user setting the PLLOFF bit in the PLLSTS register. The PLL block
is disabled in this mode. This can be useful to reduce system noise and for low 0, 1 OSCCLK/4
PLL Off power operation. The PLLCR register must first be set to 0x0000 (PLL Bypass) 2 OSCCLK/2
before entering this mode. The CPU clock (CLKIN) is derived directly from the 3 OSCCLK/1
input clock on either X1/X2, X1 or XCLKIN.
PLL Bypass is the default PLL configuration upon power-up or after an external
0, 1 OSCCLK/4
reset (XRS). This mode is selected when the PLLCR register is set to 0x0000 or
PLL Bypass 2 OSCCLK/2
while the PLL locks to a new frequency after the PLLCR register has been
3 OSCCLK/1
modified. In this mode, the PLL itself is bypassed but the PLL is not turned off.
0, 1 OSCCLK * n/4
Achieved by writing a nonzero value n into the PLLCR register. Upon writing to the
PLL Enable 2 OSCCLK * n/2
PLLCR the device will switch to PLL Bypass mode until the PLL locks.
3 OSCCLK * n/1
6.6.4 Loss of Input Clock (NMI Watchdog Function)

The 2802x devices may be clocked from either one of the internal zero-pin oscillators
(INTOSC1/INTOSC2), the on-chip crystal oscillator, or from an external clock input. Regardless of the
clock source, in PLL-enabled and PLL-bypass mode, if the input clock to the PLL vanishes, the PLL will
issue a limp-mode clock at its output. This limp-mode clock continues to clock the CPU and peripherals at
a typical frequency of 15 MHz.
When the limp mode is activated, a CLOCKFAIL signal is generated that is latched as an NMI interrupt.
Depending on how the NMIRESETSEL bit has been configured, a reset to the device can be fired
immediately or the NMI watchdog counter can issue a reset when it overflows. In addition to this, the
Missing Clock Status (MCLKSTS) bit is set. The NMI interrupt could be used by the application to detect
the input clock failure and initiate necessary corrective action such as switching over to an alternative
clock source (if available) or initiate a shut-down procedure for the system.
If the software does not respond to the clock-fail condition, the NMI watchdog triggers a reset after a
preprogrammed time interval. Figure 6-11 shows the interrupt mechanisms involved.

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
NMIFLG[NMINT]
NMIFLGCLR[NMINT] Clear
Latch
Set Clear
XRS
Generate NMIFLG[CLOCKFAIL]
Interrupt 1 0
Clear NMIFLGCLR[CLOCKFAIL]
NMINT Pulse
When 0 Latch CLOCKFAIL
SYNC?
Input = 1
Clear Set SYSCLKOUT
NMICFG[CLOCKFAIL]
NMIFLGFRC[CLOCKFAIL]
XRS
SYSCLKOUT
SYSRS
NMIWDPRD[15:0]
NMI Watchdog NMIRS See System
NMIWDCNT[15:0] Control Section
Figure 6-11. NMI-watchdog
6.6.5 CPU-Watchdog Module

The CPU-watchdog module on the 2802x device is similar to the one used on the 281x/280x/283xx
devices. This module generates an output pulse, 512 oscillator clocks wide (OSCCLK), whenever the 8-bit
watchdog up counter has reached its maximum value. To prevent this, the user must disable the counter
or the software must periodically write a 0x55 + 0xAA sequence into the watchdog key register that resets
the watchdog counter. Figure 6-12 shows the various functional blocks within the watchdog module.
Normally, when the input clocks are present, the CPU-watchdog counter decrements to initiate a CPU-
watchdog reset or WDINT interrupt. However, when the external input clock fails, the CPU-watchdog
counter stops decrementing (that is, the watchdog counter does not change with the limp-mode clock).
NOTE
The CPU-watchdog is different from the NMI watchdog. It is the legacy watchdog that is
present in all 28x devices.
NOTE
Applications in which the correct CPU operating frequency is absolutely critical should
implement a mechanism by which the MCU will be held in reset, should the input clocks ever
fail. For example, an R-C circuit may be used to trigger the XRS pin of the MCU, should the
capacitor ever get fully charged. An I/O pin may be used to discharge the capacitor on a
periodic basis to prevent it from getting fully charged. Such a circuit would also help in
detecting failure of the flash memory.

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
WDCR (WDPS[2:0]) WDCR (WDDIS)
WDCNTR(7:0)
WDCLK Watchdog WDCLK 8-Bit

/512 Watchdog
Prescaler
Counter
CLR
Clear Counter
Internal
Pullup
WDKEY(7:0)
Generate WDRST
Watchdog Output Pulse WDINT
55 + AA Good K ey (512 OSCCLKs)
Key Detector
XRS
Core-reset Bad
WDCHK SCSR (WDENINT)
Key
WDCR (WDCHK[2:0])
1 0 1
WDRST(A)
A. The WDRST signal is driven low for 512 OSCCLK cycles.
Figure 6-12. CPU-watchdog Module
The WDINT signal enables the watchdog to be used as a wakeup from IDLE/STANDBY mode.
In STANDBY mode, all peripherals are turned off on the device. The only peripheral that remains
functional is the CPU-watchdog. This module will run off OSCCLK. The WDINT signal is fed to the LPM
block so that it can wake the device from STANDBY (if enabled). See Section 6.7, Low-power Modes
Block, for more details.
In IDLE mode, the WDINT signal can generate an interrupt to the CPU, via the PIE, to take the CPU out of
IDLE mode.
In HALT mode, the CPU-watchdog can be used to wake up the device through a device reset.

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
6.7 Low-power Modes Block

Table 6-17 summarizes the various modes.
Table 6-17. Low-power Modes

MODE LPMCR0(1:0) OSCCLK CLKIN SYSCLKOUT EXIT (1)
XRS, CPU-watchdog interrupt, any
IDLE 00 On On On
enabled interrupt
On XRS, CPU-watchdog interrupt, GPIO
STANDBY 01 Off Off
(CPU-watchdog still running) Port A signal, debugger (2)
Off
(on-chip crystal oscillator and
XRS, GPIO Port A signal, debugger (2),
HALT (3) 1X PLL turned off, zero-pin oscillator Off Off
CPU-watchdog
and CPU-watchdog state
dependent on user code.)
(1) The Exit column lists which signals or under what conditions the low power mode is exited. A low signal, on any of the signals, exits the
low power condition. This signal must be kept low long enough for an interrupt to be recognized by the device. Otherwise, the low-power
mode will not be exited and the device will go back into the indicated low power mode.
(2) The JTAG port can still function even if the CPU clock (CLKIN) is turned off.
(3) The WDCLK must be active for the device to go into HALT mode.
The various low-power modes operate as follows:
IDLE Mode: This mode is exited by any enabled interrupt that is recognized by the
processor. The LPM block performs no tasks during this mode as long as
the LPMCR0(LPM) bits are set to 0,0.
STANDBY Mode: Any GPIO port A signal (GPIO[31:0]) can wake the device from STANDBY
mode. The user must select which signal(s) will wake the device in the
GPIOLPMSEL register. The selected signal(s) are also qualified by the
OSCCLK before waking the device. The number of OSCCLKs is specified in
the LPMCR0 register.
HALT Mode: CPU-watchdog, XRS, and any GPIO port A signal (GPIO[31:0]) can wake
the device from HALT mode. The user selects the signal in the
GPIOLPMSEL register.
NOTE
The low-power modes do not affect the state of the output pins (PWM pins included). They
will be in whatever state the code left them in when the IDLE instruction was executed. See
the TMS320x2802x/TMS320F2802xx Piccolo System Control and Interrupts Reference
Guide for more details.

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
6.8 Interrupts
Figure 6-13 shows how the various interrupt sources are multiplexed.
Peripherals
2
(SPI, SCI, ePWM, I C, HRPWM, eCAP, ADC)
WDINT
WAKEINT Watchdog
Sync LPMINT
Low-Power Modes
SYSCLKOUT
XINT1
MUX
XINT1
Interrupt Control
XINT1CR(15:0)
XINT2CTR(15:0)
Up to 96 Interrupts GPIOXINT1SEL(4:0)
XINT2SOC
INT1 ADC
PIE
to XINT2
MUX
INT12 Interrupt Control XINT2
XINT2CR(15:0)
C28 XINT3CTR(15:0)
Core GPIOXINT2SEL(4:0)
GPIO0.int
XINT3
MUX
XINT3 GPIO
Interrupt Control
MUX
XINT3CR(15:0)
GPIO31.int
XINT3CTR(15:0)
GPIOXINT3SEL(4:0)
TINT0
CPU TIMER 0
INT13 TINT1
CPU TIMER 1
INT14 TINT2
CPU TIMER 2
CPUTMR2CLK
CLOCKFAIL System Control

NMI NMI interrupt with watchdog function
NMIRS (See the System
(See the NMI Watchdog section.)
Control section.)
Figure 6-13. External and PIE Interrupt Sources

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
Eight PIE block interrupts are grouped into one CPU interrupt. In total, 12 CPU interrupt groups, with
8 interrupts per group equals 96 possible interrupts. Table 6-18 shows the interrupts used by 2802x
devices.
The TRAP #VectorNumber instruction transfers program control to the interrupt service routine
corresponding to the vector specified. TRAP #0 attempts to transfer program control to the address
pointed to by the reset vector. The PIE vector table does not, however, include a reset vector. Therefore,
TRAP #0 should not be used when the PIE is enabled. Doing so will result in undefined behavior.
When the PIE is enabled, TRAP #1 through TRAP #12 will transfer program control to the interrupt service
routine corresponding to the first vector within the PIE group. For example: TRAP #1 fetches the vector
from INT1.1, TRAP #2 fetches the vector from INT2.1, and so forth.
IFR[12:1] IER[12:1] INTM
INT1
INT2
1
MUX CPU
0
INT11
INT12 Global
(Flag) (Enable) Enable
INTx.1
INTx.2
INTx.3 From
INTx INTx.4 Peripherals
MUX INTx.5 or
External
INTx.6
Interrupts
INTx.7
PIEACKx INTx.8
(Enable) (Flag)
(Enable/Flag)
PIEIERx[8:1] PIEIFRx[8:1]
Figure 6-14. Multiplexing of Interrupts Using the PIE Block

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
Table 6-18. PIE MUXed Peripheral Interrupt Vector Table (1)
INTx.8 INTx.7 INTx.6 INTx.5 INTx.4 INTx.3 INTx.2 INTx.1

INT1.y WAKEINT TINT0 ADCINT9 XINT2 XINT1 Reserved ADCINT2 ADCINT1
(LPM/WD) (TIMER 0) (ADC) Ext. int. 2 Ext. int. 1 (ADC) (ADC)
0xD4E 0xD4C 0xD4A 0xD48 0xD46 0xD44 0xD42 0xD40
INT2.y Reserved Reserved Reserved Reserved EPWM4_TZINT EPWM3_TZINT EPWM2_TZINT EPWM1_TZINT
(ePWM4) (ePWM3) (ePWM2) (ePWM1)
INT3.y Reserved Reserved Reserved Reserved EPWM4_INT EPWM3_INT EPWM2_INT EPWM1_INT
(ePWM4) (ePWM3) (ePWM2) (ePWM1)
INT4.y Reserved Reserved Reserved Reserved Reserved Reserved Reserved ECAP1_INT
(eCAP1)
INT5.y Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

INT6.y Reserved Reserved Reserved Reserved Reserved Reserved SPITXINTA SPIRXINTA
(SPI-A) (SPI-A)

0xDAE 0xDAC 0xDAA 0xDA8 0xDA6 0xDA4 0xDA2 0xDA0
INT8.y Reserved Reserved Reserved Reserved Reserved Reserved I2CINT2A I2CINT1A
(I2C-A) (I2C-A)
0xDBE 0xDBC 0xDBA 0xDB8 0xDB6 0xDB4 0xDB2 0xDB0
INT9.y Reserved Reserved Reserved Reserved Reserved Reserved SCITXINTA SCIRXINTA
(SCI-A) (SCI-A)
0xDCE 0xDCC 0xDCA 0xDC8 0xDC6 0xDC4 0xDC2 0xDC0
INT10.y ADCINT8 ADCINT7 ADCINT6 ADCINT5 ADCINT4 ADCINT3 ADCINT2 ADCINT1
(ADC) (ADC) (ADC) (ADC) (ADC) (ADC) (ADC) (ADC)
0xDDE 0xDDC 0xDDA 0xDD8 0xDD6 0xDD4 0xDD2 0xDD0

0xDEE 0xDEC 0xDEA 0xDE8 0xDE6 0xDE4 0xDE2 0xDE0
INT12.y Reserved Reserved Reserved Reserved Reserved Reserved Reserved XINT3
Ext. Int. 3
0xDFE 0xDFC 0xDFA 0xDF8 0xDF6 0xDF4 0xDF2 0xDF0
(1) Out of 96 possible interrupts, some interrupts are not used. These interrupts are reserved for future devices. These interrupts can be
used as software interrupts if they are enabled at the PIEIFRx level, provided none of the interrupts within the group is being used by a
peripheral. Otherwise, interrupts coming in from peripherals may be lost by accidentally clearing their flag while modifying the PIEIFR.
To summarize, there are two safe cases when the reserved interrupts could be used as software interrupts:
No peripheral within the group is asserting interrupts.
No peripheral interrupts are assigned to the group (for example, PIE groups 5, 7, or 11) .

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
Table 6-19. PIE Configuration and Control Registers

NAME ADDRESS SIZE (x16) DESCRIPTION (1)
PIECTRL 0x0CE0 1 PIE, Control Register
PIEACK 0x0CE1 1 PIE, Acknowledge Register
PIEIER1 0x0CE2 1 PIE, INT1 Group Enable Register
PIEIFR1 0x0CE3 1 PIE, INT1 Group Flag Register
PIEIER5 0x0CEA 1 PIE, INT5 Group Enable Register
PIEIFR5 0x0CEB 1 PIE, INT5 Group Flag Register
PIEIER6 0x0CEC 1 PIE, INT6 Group Enable Register
PIEIFR6 0x0CED 1 PIE, INT6 Group Flag Register
PIEIER7 0x0CEE 1 PIE, INT7 Group Enable Register
PIEIFR7 0x0CEF 1 PIE, INT7 Group Flag Register
PIEIER8 0x0CF0 1 PIE, INT8 Group Enable Register
PIEIFR8 0x0CF1 1 PIE, INT8 Group Flag Register
Reserved 0x0CFA 6 Reserved
0x0CFF
(1) The PIE configuration and control registers are not protected by EALLOW mode. The PIE vector table
is protected.

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
6.8.1 External Interrupts
Table 6-20. External Interrupt Registers

NAME ADDRESS SIZE (x16) DESCRIPTION
XINT1CR 0x00 7070 1 XINT1 configuration register
XINT1CTR 0x00 7078 1 XINT1 counter register
XINT2CTR 0x00 7079 1 XINT2 counter register
XINT3CTR 0x00 707A 1 XINT3 counter register
Each external interrupt can be enabled/disabled or qualified using positive, negative, or both positive and
negative edge. For more information, see the TMS320x2802x/TMS320F2802xx Piccolo System Control
and Interrupts Reference Guide.
6.8.1.1 External Interrupt Electrical Data/Timing
Table 6-21. External Interrupt Timing Requirements (1)

MIN MAX UNIT
(2)
Synchronous 1tc(SCO) cycles
tw(INT) Pulse duration, INT input low/high
With qualifier 1tc(SCO) + tw(IQSW) cycles
(1) For an explanation of the input qualifier parameters, see Table 6-54.
(2) This timing is applicable to any GPIO pin configured for ADCSOC functionality.
Table 6-22. External Interrupt Switching Characteristics (1)

td(INT) Delay time, INT low/high to interrupt-vector fetch tw(IQSW) + 12tc(SCO) cycles
tw(INT)
XINT1, XINT2, XINT3
td(INT)
Address bus
Interrupt Vector
(internal)
Figure 6-15. External Interrupt Timing

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
6.9 Peripherals
6.9.1 Analog Block

A 12-bit ADC core is implemented that has different timings than the 12-bit ADC used on F280x/F2833x.
The ADC wrapper is modified to incorporate the new timings and also other enhancements to improve the
timing control of start of conversions. Figure 6-16 shows the interaction of the analog module with the rest
of the F2802x system.
For more information on the ADC, see the TMS320x2802x, 2803x Piccolo Analog-to-Digital Converter
(ADC) and Comparator Reference Guide.
38-Pin 48-Pin (3.3 V) VDDA

(Agnd) VSSA
VDDA VDDA VREFLO
VREFLO VREFLO
Tied To Tied To Interface Reference
VSSA VSSA Diff
VREFHI VREFHI
Tied To Tied To VREFHI
A0 A0 A0
B0
A1
A1
A2 A2
B1
A3
A2 COMP1OUT
A4 A4 AIO2 10-Bit Comp1
AIO10 DAC
B2
Simultaneous Sampling Channels
A6 A6
A7 A3 ADC
B3
B1 A4 COMP2OUT
AIO4 10-Bit Comp2
B2 B2 AIO12 DAC
B4 (See Note A)
B3
B4 B4
B5
B6 B6 Temperature Sensor
B7 A5
Signal Pinout A6
AIO6
AIO14
B6
A7
B7
A. Comparator 2 is only available on the 48-pin PT package.
Figure 6-16. Analog Pin Configurations

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
6.9.1.1 Analog-to-Digital Converter (ADC)
6.9.1.1.1 Features
The core of the ADC contains a single 12-bit converter fed by two sample-and-hold circuits. The sample-
and-hold circuits can be sampled simultaneously or sequentially. These, in turn, are fed by a total of up to
13 analog input channels. The converter can be configured to run with an internal bandgap reference to
create true-voltage based conversions or with a pair of external voltage references (VREFHI/VREFLO) to
create ratiometric-based conversions.
Contrary to previous ADC types, this ADC is not sequencer-based. It is easy for the user to create a
series of conversions from a single trigger. However, the basic principle of operation is centered around
the configurations of individual conversions, called SOCs, or Start-Of-Conversions.
Functions of the ADC module include:
12-bit ADC core with built-in dual sample-and-hold (S/H)
Simultaneous sampling or sequential sampling modes
Full range analog input: 0 V to 3.3 V fixed, or VREFHI/VREFLO ratiometric. The digital value of the input
analog voltage is derived by:
Internal Reference (VREFLO = VSSA. VREFHI must not exceed VDDA when using either internal or
external reference modes.)
Digital Value = 0, when input 0 V
Input Analog Voltage - VREFLO

Digital Value = 4096 when 0 V < input < 3.3 V
3.3
Digital Value = 4095, when input 3.3 V

External Reference (VREFHI/VREFLO connected to external references. VREFHI must not exceed VDDA
when using either internal or external reference modes.)
Digital Value = 0, when input 0 V
Input Analog Voltage - VREFLO

Digital Value = 4096 when 0 V < input < VREFHI
VREFHI - VREFLO
Digital Value = 4095, when input VREFHI

Up to 16-channel, multiplexed inputs
16 SOCs, configurable for trigger, sample window, and channel
16 result registers (individually addressable) to store conversion values
Multiple trigger sources
S/W software immediate start
ePWM 14
GPIO XINT2
CPU Timers 0/1/2
ADCINT1/2
9 flexible PIE interrupts, can configure interrupt request after any conversion

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
Table 6-23. ADC Configuration and Control Registers

SIZE EALLOW
REGISTER NAME ADDRESS DESCRIPTION
(x16) PROTECTED
ADCCTL1 0x7100 1 Yes Control 1 Register
ADCCTL2 0x7101 1 Yes Control 2 Register
ADCINTFLG 0x7104 1 No Interrupt Flag Register
ADCINTFLGCLR 0x7105 1 No Interrupt Flag Clear Register
ADCINTOVF 0x7106 1 No Interrupt Overflow Register
ADCINTOVFCLR 0x7107 1 No Interrupt Overflow Clear Register
INTSEL1N2 0x7108 1 Yes Interrupt 1 and 2 Selection Register
INTSEL3N4 0x7109 1 Yes Interrupt 3 and 4 Selection Register
INTSEL5N6 0x710A 1 Yes Interrupt 5 and 6 Selection Register
INTSEL7N8 0x710B 1 Yes Interrupt 7 and 8 Selection Register
INTSEL9N10 0x710C 1 Yes Interrupt 9 Selection Register (reserved Interrupt 10 Selection)
SOCPRICTL 0x7110 1 Yes SOC Priority Control Register
ADCSAMPLEMODE 0x7112 1 Yes Sampling Mode Register
ADCINTSOCSEL1 0x7114 1 Yes Interrupt SOC Selection 1 Register (for 8 channels)
ADCINTSOCSEL2 0x7115 1 Yes Interrupt SOC Selection 2 Register (for 8 channels)
ADCSOCFLG1 0x7118 1 No SOC Flag 1 Register (for 16 channels)
ADCSOCFRC1 0x711A 1 No SOC Force 1 Register (for 16 channels)
ADCSOCOVF1 0x711C 1 No SOC Overflow 1 Register (for 16 channels)
ADCSOCOVFCLR1 0x711E 1 No SOC Overflow Clear 1 Register (for 16 channels)
ADCSOC0CTL to 0x7120 1 Yes SOC0 Control Register to SOC15 Control Register
ADCSOC15CTL 0x712F
ADCREFTRIM 0x7140 1 Yes Reference Trim Register
ADCOFFTRIM 0x7141 1 Yes Offset Trim Register
COMPHYSTCTL 0x714C 1 Yes Comparator Hysteresis Control Register
ADCREV 0x714F 1 No Revision Register
Table 6-24. ADC Result Registers (Mapped to PF0)

SIZE EALLOW
REGISTER NAME ADDRESS DESCRIPTION
(x16) PROTECTED
ADCRESULT0 to 0xB00 1 No ADC Result 0 Register to ADC Result 15 Register
ADCRESULT15 0xB0F

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
0-Wait
Result PF0 (CPU)
Registers
PF2 (CPU)
SYSCLKOUT
ADCENCLK
ADCINT 1
PIE
ADCINT 9
ADC TINT 0
AIO ADC ADCTRIG 1 CPUTIMER 0
Core TINT 1
MUX Channels ADCTRIG 2 CPUTIMER 1
12-Bit
TINT 2
ADCTRIG 3 CPUTIMER 2
XINT 2SOC
ADCTRIG 4 XINT 2
SOCA 1
ADCTRIG 5
SOCB 1 ePWM 1
ADCTRIG 6
SOCA 2
ADCTRIG 7
SOCB 2 ePWM 2
ADCTRIG 8
SOCA 3
ADCTRIG 9
SOCB 3 ePWM 3
ADCTRIG 10
SOCA 4
ADCTRIG 11
SOCB 4 ePWM 4
ADCTRIG 12
Figure 6-17. ADC Connections
ADC Connections if the ADC is Not Used

It is recommended that the connections for the analog power pins be kept, even if the ADC is not used.
Following is a summary of how the ADC pins should be connected, if the ADC is not used in an
application:
VDDA Connect to VDDIO
VSSA Connect to VSS
VREFLO Connect to VSS
ADCINAn, ADCINBn, VREFHI Connect to VSSA
When the ADC module is used in an application, unused ADC input pins should be connected to analog
ground (VSSA).
NOTE: Unused ADCIN pins that are multiplexed with AIO function should not be directly connected to
analog ground. They should be grounded through a 1-k resistor. This is to prevent an errant code from
configuring these pins as AIO outputs and driving grounded pins to a logic-high state.
When the ADC is not used, be sure that the clock to the ADC module is not turned on to realize power
savings.

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
6.9.1.1.2 ADC Start-of-Conversion Electrical Data/Timing
Table 6-25. External ADC Start-of-Conversion Switching Characteristics

tw(ADCSOCL) Pulse duration, ADCSOCxO low 32tc(HCO) cycles
tw(ADCSOCL)
ADCSOCAO
or
ADCSOCBO
Figure 6-18. ADCSOCAO or ADCSOCBO Timing

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
6.9.1.1.3 On-Chip Analog-to-Digital Converter (ADC) Electrical Data/Timing
Table 6-26. ADC Electrical Characteristics

DC SPECIFICATIONS
Resolution 12 Bits
ADC clock 60-MHz device 0.001 60 MHz
Sample Window 28027/26/23/22 7 64 ADC
28021/20/200 14 64 Clocks
ACCURACY
INL (Integral nonlinearity) at ADC Clock 30 MHz (1) 4 4 LSB
DNL (Differential nonlinearity) at ADC Clock 30 MHz,
1 1 LSB
no missing codes
(2)
Offset error Executing Device_Cal
20 0 20
function
LSB
Executing periodic self-
4 0 4
recalibration (3)
Overall gain error with internal reference 60 60 LSB
Overall gain error with external reference 40 40 LSB
Channel-to-channel offset variation 4 4 LSB
Channel-to-channel gain variation 4 4 LSB
ADC temperature coefficient with internal reference 50 ppm/C
ADC temperature coefficient with external reference 20 ppm/C
VREFLO 100 A
VREFHI 100 A
ANALOG INPUT
Analog input voltage with internal reference 0 3.3 V
Analog input voltage with external reference VREFLO VREFHI V
VREFLO input voltage (4) VSSA VSSA V
(5)
VREFHI input voltage with VREFLO = VSSA 1.98 VDDA V
Input capacitance 5 pF
Input leakage current 5 A
(1) INL will degrade when the ADC input voltage goes above VDDA.
(2) 1 LSB has the weighted value of full-scale range (FSR)/4096. FSR is 3.3 V with internal reference and VREFHI - VREFLO for external
reference.
(3) Periodic self-recalibration will remove system-level and temperature dependencies on the ADC zero offset error. This can be performed
as needed in the application without sacrificing an ADC channel by using the procedure listed in the "ADC Zero Offset Calibration"
section of the TMS320x2802x, 2803x Piccolo Analog-to-Digital Converter (ADC) and Comparator Reference Guide.
(4) VREFLO is always connected to VSSA.
(5) VREFHI must not exceed VDDA when using either internal or external reference modes. Since VREFHI is tied to ADCINA0, the input signal
on ADCINA0 must not exceed VDDA.

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
Table 6-27. ADC Power Modes

ADC OPERATING MODE CONDITIONS IDDA UNITS
ADC Clock Enabled
Bandgap On (ADCBGPWD = 1)
Mode A Operating Mode 13 mA
Reference On (ADCREFPWD = 1)
ADC Powered Up (ADCPWDN = 1)
ADC Clock Enabled
Mode B Quick Wake Mode 4 mA
ADC Clock Enabled
Mode C Comparator-Only Mode 1.5 mA
ADC Clock Enabled
Mode D Off Mode 0.075 mA
6.9.1.1.3.1 Internal Temperature Sensor
Table 6-28. Temperature Sensor Coefficient

PARAMETER (1) MIN TYP MAX UNIT
TSLOPE Degrees C of temperature movement per measured ADC LSB change
0.18 (2) (3) C/LSB
of the temperature sensor
TOFFSET ADC output at 0C of the temperature sensor 1750 LSB
(1) The temperature sensor slope and offset are given in terms of ADC LSBs using the internal reference of the ADC. Values must be
adjusted accordingly in external reference mode to the external reference voltage.
(2) ADC temperature coeffieicient is accounted for in this specification
(3) Output of the temperature sensor (in terms of LSBs) is sign-consistent with the direction of the temperature movement. Increasing
temperatures will give increasing ADC values relative to an initial value; decreasing temperatures will give decreasing ADC values
relative to an initial value.
6.9.1.1.3.2 ADC Power-Up Control Bit Timing
Table 6-29. ADC Power-Up Delays

PARAMETER (1) MIN MAX UNIT
td(PWD) Delay time for the ADC to be stable after power up 1 ms
(1) Timings maintain compatibility to the ADC module. The 2802x ADC supports driving all 3 bits at the same time td(PWD) ms before first
conversion.
ADCPWDN/
ADCBGPWD/
ADCREFPWD/
ADCENABLE td(PWD)
Request for ADC
Conversion
Figure 6-19. ADC Conversion Timing

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
Ron Switch
Rs ADCIN 3.4 kW
Source Cp Ch
ac
Signal 5 pF 1.6 pF
28x DSP
Typical Values of the Input Circuit Components:
Switch Resistance (Ron): 3.4 k W

Sampling Capacitor (Ch): 1.6 pF
Parasitic Capacitance (Cp): 5 pF
Source Resistance (Rs): 50 W
Figure 6-20. ADC Input Impedance Model

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
6.9.1.1.3.3 ADC Sequential and Simultaneous Timings
Analog Input
SOC0 Sample SOC1 Sample SOC2 Sample
Window Window Window
0 2 9 15 22 24 37
ADCCLK
ADCCTL 1.INTPULSEPOS
ADCSOCFLG 1.SOC0
ADCSOCFLG 1.SOC1
ADCSOCFLG 1.SOC2
S/H Window Pulse to Core SOC0 SOC1 SOC2
ADCRESULT 0 2 ADCCLKs Result 0 Latched
ADCRESULT 1
EOC0 Pulse
EOC1 Pulse
ADCINTFLG .ADCINTx
Minimum Conversion 0
1 ADCCLK
7 ADCCLKs 13 ADC Clocks
6 Minimum Conversion 1
ADCCLKs 7 ADCCLKs 13 ADC Clocks
Figure 6-21. Timing Example for Sequential Mode / Late Interrupt Pulse

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
Analog Input
SOC0 Sample SOC1 Sample SOC2 Sample
Window Window Window
0 2 9 15 22 24 37
ADCCLK
ADCCTL1.INTPULSEPOS
ADCSOCFLG 1.SOC0
ADCSOCFLG 1.SOC1
ADCSOCFLG 1.SOC2
S/H Window Pulse to Core SOC0 SOC1 SOC2
ADCRESULT 0 Result 0 Latched
ADCRESULT 1
EOC0 Pulse
EOC1 Pulse
EOC2 Pulse
ADCINTFLG .ADCINTx
Minimum Conversion 0
2 ADCCLKs
7 ADCCLKs 13 ADC Clocks
6 Minimum Conversion 1
Figure 6-22. Timing Example for Sequential Mode / Early Interrupt Pulse

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
Analog Input A
SOC0 Sample SOC2 Sample
A Window A Window
Analog Input B
B Window B Window
0 2 9 22 24 37 50
ADCCLK
ADCCTL1.INTPULSEPOS
ADCSOCFLG 1.SOC0
ADCSOCFLG 1.SOC1
ADCSOCFLG 1.SOC2
S/H Window Pulse to Core SOC0 (A/B) SOC2 (A/B)
ADCRESULT 0 2 ADCCLKs Result 0 (A) Latched
ADCRESULT 1 Result 0 (B) Latched
ADCRESULT 2
EOC0 Pulse
EOC1 Pulse 1 ADCCLK
EOC2 Pulse
ADCINTFLG .ADCINTx
Minimum Conversion 0 (A) Conversion 0 (B)

2 ADCCLKs
7 ADCCLKs 13 ADC Clocks 13 ADC Clocks
19 Minimum Conversion 1 (A)

Figure 6-23. Timing Example for Simultaneous Mode / Late Interrupt Pulse

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
Analog Input A
A Window A Window
Analog Input B
B Window B Window
0 2 9 22 24 37 50
ADCCLK
ADCCTL1.INTPULSEPOS
ADCSOCFLG1.SOC0
ADCSOCFLG1.SOC1
ADCSOCFLG1.SOC2
S/H Window Pulse to Core SOC0 (A/B) SOC2 (A/B)
ADCRESULT 0 2 ADCCLKs Result 0 (A) Latched
ADCRESULT 1 Result 0 (B) Latched
ADCRESULT 2
EOC0 Pulse
EOC1 Pulse
EOC2 Pulse
ADCINTFLG.ADCINTx
Minimum Conversion 0 (A) Conversion 0 (B)

2 ADCCLKs
7 ADCCLKs 13 ADC Clocks 13 ADC Clocks
19 Minimum Conversion 1 (A)
Figure 6-24. Timing Example for Simultaneous Mode / Early Interrupt Pulse

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
6.9.1.2 ADC MUX
To COMPy A or B input
To ADC Channel X
Logic implemented in GPIO MUX block

AIOx Pin
AIOxIN SYSCLK
1
AIOxINE AIODAT Reg

SYNC (Read)
AIODAT Reg
(Latch)
AIOMUX 1 Reg
AIOSET,
0 = Output)
AIOCLEAR,
(1 = Input,
AIOxDIR
AIOTOGGLE
Regs
AIODIR Reg
1 (Latch)
(0 = Input, 1 = Output)
0 0
Figure 6-25. AIOx Pin Multiplexing
The ADC channel and Comparator functions are always available. The digital I/O function is available only
when the respective bit in the AIOMUX1 register is 0. In this mode, reading the AIODAT register reflects
the actual pin state.
The digital I/O function is disabled when the respective bit in the AIOMUX1 register is 1. In this mode,
reading the AIODAT register reflects the output latch of the AIODAT register and the input digital I/O buffer
is disabled to prevent analog signals from generating noise.
On reset, the digital function is disabled. If the pin is used as an analog input, users should keep the AIO
function disabled for that pin.

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
6.9.1.3 Comparator Block

Figure 6-26 shows the interaction of the Comparator modules with the rest of the system.
COMP x A
+
COMP x B COMP
- GPIO TZ1/2/3
MUX
COMP x
+
DAC x ePWM
AIO Wrapper
MUX
COMPxOUT
DAC
Core
10-Bit
Figure 6-26. Comparator Block Diagram
Table 6-30. Comparator Control Registers

COMP1 COMP2 SIZE EALLOW
REGISTER NAME DESCRIPTION
ADDRESS ADDRESS (1) (x16) PROTECTED
COMPCTL 0x6400 0x6420 1 Yes Comparator Control Register
COMPSTS 0x6402 0x6422 1 No Comparator Status Register
DACCTL 0x6404 0x6424 1 Yes DAC Control Register
DACVAL 0x6406 0x6426 1 No DAC Value Register
RAMPMAXREF_ACTIVE Ramp Generator Maximum
0x6408 0x6428 1 No
Reference (Active) Register
RAMPMAXREF_SHDW Ramp Generator Maximum
0x640A 0x642A 1 No
Reference (Shadow) Register
RAMPDECVAL_ACTIVE Ramp Generator Decrement Value
0x640C 0x642C 1 No
(Active) Register
RAMPDECVAL_SHDW Ramp Generator Decrement Value
0x640E 0x642E 1 No
(Shadow) Register
RAMPSTS 0x6410 0x6430 1 No Ramp Generator Status Register
(1) Comparator 2 is only available on the 48-pin PT package.

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
6.9.1.3.1 On-Chip Comparator/DAC Electrical Data/Timing
Table 6-31. Electrical Characteristics of the Comparator/DAC

PARAMETER MIN TYP MAX UNITS
Comparator
Comparator Input Range VSSA VDDA V
Comparator response time to PWM Trip Zone (Async) 30 ns
Input Offset 5 mV
(1)
Input Hysteresis 35 mV
DAC
DAC Output Range VSSA VDDA V
DAC resolution 10 bits
DAC settling time See Figure 6-27
DAC Gain 1.5%
DAC Offset 10 mV
Monotonic Yes
INL 3 LSB
(1) Hysteresis on the comparator inputs is achieved with a Schmidt trigger configuration. This results in an effective 100-k feedback
resistance between the output of the comparator and the noninverting input of the comparator. There is an option to disable the
hysteresis and, with it, the feedback resistance; see the TMS320x2802x, 2803x Piccolo Analog-to-Digital Converter (ADC) and
Comparator Reference Guide for more information on this option if needed in your system.
1100
1000
900
800
700
Settling Time (ns)
600
500
400
300
200
100
0
0 50 100 150 200 250 300 350 400 450 500
DAC Step Size (Codes)
DAC Accuracy 15 Codes 7 Codes 3 Codes 1 Code
Figure 6-27. DAC Settling Time

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
6.9.2 Detailed Descriptions

Integral Nonlinearity
Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero through full
scale. The point used as zero occurs one-half LSB before the first code transition. The full-scale point is
defined as level one-half LSB beyond the last code transition. The deviation is measured from the center
of each particular code to the true straight line between these two points.
Differential Nonlinearity
An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal
value. A differential nonlinearity error of less than 1 LSB ensures no missing codes.
Zero Offset
The major carry transition should occur when the analog input is at zero volts. Zero error is defined as the
deviation of the actual transition from that point.
Gain Error
The first code transition should occur at an analog value one-half LSB above negative full scale. The last
transition should occur at an analog value one and one-half LSB below the nominal full scale. Gain error is
the deviation of the actual difference between first and last code transitions and the ideal difference
between first and last code transitions.
Signal-to-Noise Ratio + Distortion (SINAD)
SINAD is the ratio of the rms value of the measured input signal to the rms sum of all other spectral
components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is
expressed in decibels.
Effective Number of Bits (ENOB)
For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula,
(SINAD - 1.76)
N=
6.02 it is possible to get a measure of performance expressed as N, the effective number of
bits. Thus, effective number of bits for a device for sine wave inputs at a given input frequency can be
calculated directly from its measured SINAD.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first nine harmonic components to the rms value of the measured
input signal and is expressed as a percentage or in decibels.
Spurious Free Dynamic Range (SFDR)
SFDR is the difference in dB between the rms amplitude of the input signal and the peak spurious signal.

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
6.9.3 Serial Peripheral Interface (SPI) Module

The device includes the four-pin serial peripheral interface (SPI) module. One SPI module (SPI-A) is
available. The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of
programmed length (one to sixteen bits) to be shifted into and out of the device at a programmable bit-
transfer rate. Normally, the SPI is used for communications between the MCU and external peripherals or
another processor. Typical applications include external I/O or peripheral expansion through devices such
as shift registers, display drivers, and ADCs. Multidevice communications are supported by the
master/slave operation of the SPI.
The SPI module features include:
Four external pins:
SPISOMI: SPI slave-output/master-input pin
SPISIMO: SPI slave-input/master-output pin
SPISTE: SPI slave transmit-enable pin
SPICLK: SPI serial-clock pin
NOTE: All four pins can be used as GPIO if the SPI module is not used.
Two operational modes: master and slave
Baud rate: 125 different programmable rates.
LSPCLK
Baud rate = when SPIBRR = 3 to 127
(SPIBRR + 1)
LSPCLK
Baud rate = when SPIBRR = 0, 1, 2
4
Data word length: one to sixteen data bits
Four clocking schemes (controlled by clock polarity and clock phase bits) include:
Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the SPICLK
signal and receives data on the rising edge of the SPICLK signal.
Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the falling edge
of the SPICLK signal and receives data on the falling edge of the SPICLK signal.
Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the SPICLK
signal and receives data on the falling edge of the SPICLK signal.
Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the falling
edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.
Simultaneous receive and transmit operation (transmit function can be disabled in software)
Transmitter and receiver operations are accomplished through either interrupt-driven or polled algorithms.
Nine SPI module control registers: Located in control register frame beginning at address 7040h.
NOTE
All registers in this module are 16-bit registers that are connected to Peripheral Frame 2.
When a register is accessed, the register data is in the lower byte (70), and the upper byte
(158) is read as zeros. Writing to the upper byte has no effect.
Enhanced feature:
4-level transmit/receive FIFO
Delayed transmit control
Bi-directional 3 wire SPI mode support

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
The SPI port operation is configured and controlled by the registers listed in Table 6-32.
Table 6-32. SPI-A Registers

NAME ADDRESS SIZE (x16) EALLOW PROTECTED DESCRIPTION (1)
SPICCR 0x7040 1 No SPI-A Configuration Control Register
SPICTL 0x7041 1 No SPI-A Operation Control Register
SPISTS 0x7042 1 No SPI-A Status Register
SPIBRR 0x7044 1 No SPI-A Baud Rate Register
SPIRXEMU 0x7046 1 No SPI-A Receive Emulation Buffer Register
SPIRXBUF 0x7047 1 No SPI-A Serial Input Buffer Register
SPITXBUF 0x7048 1 No SPI-A Serial Output Buffer Register
SPIDAT 0x7049 1 No SPI-A Serial Data Register
SPIFFTX 0x704A 1 No SPI-A FIFO Transmit Register
SPIFFRX 0x704B 1 No SPI-A FIFO Receive Register
SPIFFCT 0x704C 1 No SPI-A FIFO Control Register
SPIPRI 0x704F 1 No SPI-A Priority Control Register
(1) Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined
results.
For more information on the SPI, see the TMS320x2802x, 2803x Piccolo Serial Peripheral Interface (SPI)
Reference Guide.

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
Figure 6-28 is a block diagram of the SPI in slave mode.
SPIFFENA
Receiver Overrun
SPIFFTX.14 Overrun Flag INT ENA
RX FIFO Registers SPISTS.7

SPICTL.4
SPIRXBUF
RX FIFO _0
RX FIFO _1
----- SPIINT
RX FIFO Interrupt
RX FIFO _3 RX Interrupt
Logic
16
SPIRXBUF SPIFFOVF
Buffer Register FLAG
SPIFFRX.15 To CPU
TX FIFO Registers
SPITXBUF
TX FIFO _3 TX Interrupt
----- TX FIFO Interrupt Logic
TX FIFO _1
SPITX
TX FIFO _0
SPI INT
16 16 ENA
SPI INT FLAG
SPITXBUF SPISTS.6
Buffer Register
SPICTL.0
TRIWIRE
16 SPIPRI.0
M M
SPIDAT S TW
Data Register S SW1 SPISIMO
M TW
SPIDAT.15 - 0 M
TW
S
S SW2 SPISOMI
Talk
SPICTL.1
SPISTE
State Control
Master/Slave
SPI Char SPICCR.3 - 0 SPICTL.2

S
SW3
3 2 1 0
Clock Clock
M
SPI Bit Rate S Polarity Phase
LSPCLK SPIBRR.6 - 0 SPICCR.6 SPICTL.3 SPICLK

6 5 4 3 2 1 0 M
A. SPISTE is driven low by the master for a slave device.
Figure 6-28. SPI Module Block Diagram (Slave Mode)

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
6.9.3.1 SPI Master Mode Electrical Data/Timing

Table 6-33 lists the master mode timing (clock phase = 0) and Table 6-34 lists the timing (clock phase = 1). Figure 6-29 and Figure 6-30 show the
timing waveforms.
Table 6-33. SPI Master Mode External Timing (Clock Phase = 0) (1) (2) (3) (4) (5)
SPI WHEN (SPIBRR + 1) IS EVEN OR SPI WHEN (SPIBRR + 1) IS ODD
NO. SPIBRR = 0 OR 2 AND SPIBRR > 3 UNIT
MIN MAX MIN MAX
1 tc(SPC)M Cycle time, SPICLK 4tc(LCO) 128tc(LCO) 5tc(LCO) 127tc(LCO) ns
Pulse duration, SPICLK high
tw(SPCH)M 0.5tc(SPC)M 10 0.5tc(SPC)M 0.5tc(SPC)M 0.5tc(LCO) 10 0.5tc(SPC)M 0.5tc(LCO)
(clock polarity = 0)
2 ns
Pulse duration, SPICLK low
tw(SPCL)M 0.5tc(SPC)M 10 0.5tc(SPC)M 0.5tc(SPC)M 0.5tc(LCO) 10 0.5tc(SPC)M 0.5tc(LCO)
tw(SPCL)M 0.5tc(SPC)M 10 0.5tc(SPC)M 0.5tc(SPC)M + 0.5tc(LCO) 10 0.5tc(SPC)M + 0.5tc(LCO)
3 ns
tw(SPCH)M 0.5tc(SPC)M 10 0.5tc(SPC)M 0.5tc(SPC)M + 0.5tc(LCO) 10 0.5tc(SPC)M + 0.5tc(LCO)
Delay time, SPICLK high to SPISIMO
td(SPCH-SIMO)M 10 10
valid (clock polarity = 0)
4 ns
Delay time, SPICLK low to SPISIMO
td(SPCL-SIMO)M 10 10
valid (clock polarity = 1)
Valid time, SPISIMO data valid after
tv(SPCL-SIMO)M 0.5tc(SPC)M 10 0.5tc(SPC)M + 0.5tc(LCO) 10
SPICLK low (clock polarity = 0)
5 ns
tv(SPCH-SIMO)M 0.5tc(SPC)M 10 0.5tc(SPC)M + 0.5tc(LCO) 10
SPICLK high (clock polarity = 1)
Setup time, SPISOMI before SPICLK
tsu(SOMI-SPCL)M 26 26
low (clock polarity = 0)
8 ns
Setup time, SPISOMI before SPICLK
tsu(SOMI-SPCH)M 26 26
high (clock polarity = 1)
Valid time, SPISOMI data valid after
tv(SPCL-SOMI)M 0 0
9 ns
tv(SPCH-SOMI)M 0 0
(1) The MASTER / SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is cleared.
(2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR +1)
(3) tc(LCO) = LSPCLK cycle time
(4) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 15-MHz MAX, master mode receive 10-MHz MAX
Slave mode transmit 10-MHz MAX, slave mode receive 10-MHz MAX.
(5) The active edge of the SPICLK signal referenced is controlled by the clock polarity bit (SPICCR.6).

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
SPICLK
SPICLK
4
5
SPISIMO Master Out Data Is Valid
Master In Data
SPISOMI
Must Be Valid
(A)
SPISTE
A. In the master mode, SPISTE goes active 0.5tc(SPC) (minimum) before valid SPI clock edge. On the trailing end of the
word, the SPISTE will go inactive 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit, except that SPISTE
stays active between back-to-back transmit words in both FIFO and non-FIFO modes.
Figure 6-29. SPI Master Mode External Timing (Clock Phase = 0)

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
Table 6-34. SPI Master Mode External Timing (Clock Phase = 1) (1) (2) (3) (4) (5)
SPI WHEN (SPIBRR + 1) IS EVEN SPI WHEN (SPIBRR + 1) IS ODD
NO. OR SPIBRR = 0 OR 2 AND SPIBRR > 3 UNIT
MIN MAX MIN MAX
1 tc(SPC)M Cycle time, SPICLK 4tc(LCO) 128tc(LCO) 5tc(LCO) 127tc(LCO) ns
tw(SPCH)M 0.5tc(SPC)M 10 0.5tc(SPC)M 0.5tc(SPC)M 0.5tc (LCO) 10 0.5tc(SPC)M 0.5tc(LCO)
2 ns
tw(SPCL))M 0.5tc(SPC)M 10 0.5tc(SPC)M 0.5tc(SPC)M 0.5tc (LCO) 10 0.5tc(SPC)M 0.5tc(LCO
tw(SPCL)M 0.5tc(SPC)M 10 0.5tc(SPC)M 0.5tc(SPC)M + 0.5tc(LCO) 10 0.5tc(SPC)M + 0.5tc(LCO)
3 ns
tw(SPCH)M 0.5tc(SPC)M 10 0.5tc(SPC)M 0.5tc(SPC)M + 0.5tc(LCO) 10 0.5tc(SPC)M + 0.5tc(LCO)
Setup time, SPISIMO data valid
tsu(SIMO-SPCH)M before SPICLK high 0.5tc(SPC)M 10 0.5tc(SPC)M 10
6 ns
Setup time, SPISIMO data valid
tsu(SIMO-SPCL)M before SPICLK low 0.5tc(SPC)M 10 0.5tc(SPC)M 10
tv(SPCH-SIMO)M 0.5tc(SPC)M 10 0.5tc(SPC)M 10
7 ns
tv(SPCL-SIMO)M 0.5tc(SPC)M 10 0.5tc(SPC)M 10
Setup time, SPISOMI before
tsu(SOMI-SPCH)M 26 26
10 ns
Setup time, SPISOMI before
tsu(SOMI-SPCL)M 26 26
tv(SPCH-SOMI)M 0 0
11 ns
tv(SPCL-SOMI)M 0 0
(1) The MASTER/SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is set.
(2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
1
SPICLK
2
SPICLK
6
7
SPISIMO Master out data Is valid Data Valid
10
11
Master in data
SPISOMI
must be valid
SPISTE(A)
A. In the master mode, SPISTE goes active 0.5tc(SPC) (minimum) before valid SPI clock edge. On the trailing end of the word, the SPISTE will go inactive 0.5tc(SPC) after
the receiving edge (SPICLK) of the last data bit, except that SPISTE stays active between back-to-back transmit words in both FIFO and non-FIFO modes.
Figure 6-30. SPI Master Mode External Timing (Clock Phase = 1)

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
6.9.3.2 SPI Slave Mode Electrical Data/Timing

Table 6-35 lists the slave mode external timing (clock phase = 0) and Table 6-36 (clock phase = 1).
Figure 6-31 and Figure 6-32 show the timing waveforms.
Table 6-35. SPI Slave Mode External Timing (Clock Phase = 0) (1) (2) (3) (4) (5)
NO. MIN MAX UNIT
12 tc(SPC)S Cycle time, SPICLK 4tc(LCO) ns
tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 0) 0.5tc(SPC)S 10 0.5tc(SPC)S
13 ns
tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 1) 0.5tc(SPC)S 10 0.5tc(SPC)S
14 ns
td(SPCH-SOMI)S Delay time, SPICLK high to SPISOMI valid (clock polarity = 0) 21
15 ns
td(SPCL-SOMI)S Delay time, SPICLK low to SPISOMI valid (clock polarity = 1) 21
tv(SPCL-SOMI)S Valid time, SPISOMI data valid after SPICLK low (clock polarity = 0) 0
16 ns
tv(SPCH-SOMI)S Valid time, SPISOMI data valid after SPICLK high (clock polarity = 1) 0
tsu(SIMO-SPCL)S Setup time, SPISIMO before SPICLK low (clock polarity = 0) 26
19 ns
tsu(SIMO-SPCH)S Setup time, SPISIMO before SPICLK high (clock polarity = 1) 26
tv(SPCL-SIMO)S Valid time, SPISIMO data valid after SPICLK low (clock polarity = 0) 0.5tc(SPC)S 10
20 ns
tv(SPCH-SIMO)S Valid time, SPISIMO data valid after SPICLK high (clock polarity = 1) 0.5tc(SPC)S 10
(1) The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.
12
SPICLK
13
14
SPICLK
15
16
SPISOMI SPISOMI data Is valid
19
20
SPISIMO data
SPISIMO must be valid
SPISTE(A)
A. In the slave mode, the SPISTE signal should be asserted low at least 0.5tc(SPC) (minimum) before the valid SPI clock
edge and remain low for at least 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit.
Figure 6-31. SPI Slave Mode External Timing (Clock Phase = 0)

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
Table 6-36. SPI Slave Mode External Timing (Clock Phase = 1) (1) (2) (3) (4)
NO. MIN MAX UNIT
12 tc(SPC)S Cycle time, SPICLK 8tc(LCO) ns
13 ns
14 ns
tsu(SOMI-SPCH)S Setup time, SPISOMI before SPICLK high (clock polarity = 0) 0.125tc(SPC)S
17 ns
tsu(SOMI-SPCL)S Setup time, SPISOMI before SPICLK low (clock polarity = 1) 0.125tc(SPC)S
Valid time, SPISOMI data valid after SPICLK low
tv(SPCL-SOMI)S 0
18 ns
Valid time, SPISOMI data valid after SPICLK high
tv(SPCH-SOMI)S 0
tsu(SIMO-SPCH)S Setup time, SPISIMO before SPICLK high (clock polarity = 0) 26
21 ns
tsu(SIMO-SPCL)S Setup time, SPISIMO before SPICLK low (clock polarity = 1) 26
Valid time, SPISIMO data valid after SPICLK high
tv(SPCH-SIMO)S 0.5tc(SPC)S 10
22 ns
Valid time, SPISIMO data valid after SPICLK low
tv(SPCL-SIMO)S 0.5tc(SPC)S 10
(1) The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.
12
SPICLK
13
14
SPICLK
17
18
SPISOMI SPISOMI data is valid Data Valid
21
22
SPISIMO data
SPISIMO
must be valid
SPISTE(A)
A. In the slave mode, the SPISTE signal should be asserted low at least 0.5tc(SPC) before the valid SPI clock edge and
remain low for at least 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit.
Figure 6-32. SPI Slave Mode External Timing (Clock Phase = 1)

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
6.9.4 Serial Communications Interface (SCI) Module

The devices include one serial communications interface (SCI) module (SCI-A). The SCI module supports
digital communications between the CPU and other asynchronous peripherals that use the standard
nonreturn-to-zero (NRZ) format. The SCI receiver and transmitter are double-buffered, and each has its
own separate enable and interrupt bits. Both can be operated independently or simultaneously in the full-
duplex mode. To ensure data integrity, the SCI checks received data for break detection, parity, overrun,
and framing errors. The bit rate is programmable to over 65000 different speeds through a 16-bit baud-
select register.
Features of each SCI module include:
Two external pins:
SCITXD: SCI transmit-output pin
SCIRXD: SCI receive-input pin
NOTE: Both pins can be used as GPIO if not used for SCI.
Baud rate programmable to 64K different rates:
LSPCLK
Baud rate = when BRR 0
(BRR + 1) * 8
LSPCLK
Baud rate = when BRR = 0
16
Data-word format
One start bit
Data-word length programmable from one to eight bits
Optional even/odd/no parity bit
One or two stop bits
Four error-detection flags: parity, overrun, framing, and break detection
Two wake-up multiprocessor modes: idle-line and address bit
Half- or full-duplex operation
Double-buffered receive and transmit functions
Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms with status
flags.
Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and TX EMPTY flag
(transmitter-shift register is empty)
Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag (break
condition occurred), and RX ERROR flag (monitoring four interrupt conditions)
Separate enable bits for transmitter and receiver interrupts (except BRKDT)
NRZ (nonreturn-to-zero) format
NOTE
All registers in this module are 8-bit registers that are connected to Peripheral Frame 2.
When a register is accessed, the register data is in the lower byte (70), and the upper byte
(158) is read as zeros. Writing to the upper byte has no effect.
Enhanced features:
Auto baud-detect hardware logic
4-level transmit/receive FIFO

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
The SCI port operation is configured and controlled by the registers listed in Table 6-37.
Table 6-37. SCI-A Registers (1)

EALLOW
PROTECTED
SCICCRA 0x7050 1 No SCI-A Communications Control Register
SCICTL1A 0x7051 1 No SCI-A Control Register 1
SCIHBAUDA 0x7052 1 No SCI-A Baud Register, High Bits
SCILBAUDA 0x7053 1 No SCI-A Baud Register, Low Bits
SCICTL2A 0x7054 1 No SCI-A Control Register 2
SCIRXSTA 0x7055 1 No SCI-A Receive Status Register
SCIRXEMUA 0x7056 1 No SCI-A Receive Emulation Data Buffer Register
SCIRXBUFA 0x7057 1 No SCI-A Receive Data Buffer Register
SCITXBUFA 0x7059 1 No SCI-A Transmit Data Buffer Register
(2)
SCIFFTXA 0x705A 1 No SCI-A FIFO Transmit Register
SCIFFRXA (2) 0x705B 1 No SCI-A FIFO Receive Register
SCIFFCTA (2) 0x705C 1 No SCI-A FIFO Control Register
SCIPRIA 0x705F 1 No SCI-A Priority Control Register
(1) Registers in this table are mapped to Peripheral Frame 2 space. This space only allows 16-bit accesses. 32-bit accesses produce
undefined results.
(2) These registers are new registers for the FIFO mode.

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
For more information on the SCI, see the TMS320x2802x, 2803x Piccolo Serial Communications Interface
(SCI) Reference Guide.
Figure 6-33 shows the SCI module block diagram.
SCICTL1.1
Frame Format and Mode SCITXD
SCITXD
TXSHF
Parity Register TXENA
TX EMPTY
Even/Odd Enable
8 SCICTL2.6
SCICCR.6 SCICCR.5
TXRDY TX INT ENA
Transmitter-Data
Buffer Register SCICTL2.7
TXWAKE SCICTL2.0
SCICTL1.3 8 TX FIFO
TX FIFO _0 Interrupts TXINT
1 TX Interrupt
TX FIFO _1
Logic
----- To CPU
TX FIFO _3
WUT SCITXBUF.7-0 SCI TX Interrupt select logic
TX FIFO registers
SCIFFENA AutoBaud Detect logic
SCIFFTX.14
SCIHBAUD. 15 - 8
SCIRXD
Baud Rate RXSHF
Register SCIRXD
MSbyte
Register RXWAKE
LSPCLK SCIRXST.1
SCILBAUD. 7 - 0 RXENA
Baud Rate 8 SCICTL1.0

LSbyte SCICTL2.1
Register Receive Data
Buffer register
RXRDY RX/BK INT ENA
SCIRXBUF.7-0
SCIRXST.6
8
RX FIFO _3 BRKDT
----- RX FIFO
SCIRXST.5
RX FIFO_1
Interrupts
RX FIFO _0
RX Interrupt
RXINT
SCIRXBUF.7-0 Logic
RX FIFO registers To CPU
RXFFOVF
SCIRXST.7 SCIRXST.4 - 2
SCIFFRX.15
RX Error FE OE PE
RX Error
RX ERR INT ENA
SCI RX Interrupt select logic
SCICTL1.6
Figure 6-33. Serial Communications Interface (SCI) Module Block Diagram

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
6.9.5 Inter-Integrated Circuit (I2C)

The device contains one I2C Serial Port. Figure 6-34 shows how the I2C peripheral module interfaces
within the device.
The I2C module has the following features:
Compliance with the Philips Semiconductors I2C-bus specification (version 2.1):
Support for 1-bit to 8-bit format transfers
7-bit and 10-bit addressing modes
General call
START byte mode
Support for multiple master-transmitters and slave-receivers
Support for multiple slave-transmitters and master-receivers
Combined master transmit/receive and receive/transmit mode
Data transfer rate of from 10 kbps up to 400 kbps (I2C Fast-mode rate)
One 4-word receive FIFO and one 4-word transmit FIFO
One interrupt that can be used by the CPU. This interrupt can be generated as a result of one of the
following conditions:
Transmit-data ready
Receive-data ready
Register-access ready
No-acknowledgment received
Arbitration lost
Stop condition detected
Addressed as slave
An additional interrupt that can be used by the CPU when in FIFO mode
Module enable/disable capability
Free data format mode
For more information on the I2C, see the TMS320x2802x, 2803x Piccolo Inter-Integrated Circuit (I2C)
Module Reference Guide.

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
2
I C Module
I2CXSR I2CDXR
TX FIFO
SDA FIFO Interrupt to
CPU/PIE
RX FIFO
Peripheral Bus
I2CRSR I2CDRR
Control/Status
Registers CPU
Clock
SCL Synchronizer
Prescaler
Noise Filters
Interrupt to
I2C INT
CPU/PIE
Arbitrator
A. The I2C registers are accessed at the SYSCLKOUT rate. The internal timing and signal waveforms of the I2C port are
also at the SYSCLKOUT rate.
B. The clock enable bit (I2CAENCLK) in the PCLKCRO register turns off the clock to the I2C port for low power
operation. Upon reset, I2CAENCLK is clear, which indicates the peripheral internal clocks are off.
Figure 6-34. I2C Peripheral Module Interfaces
The registers in Table 6-38 configure and control the I2C port operation.
Table 6-38. I2C-A Registers

EALLOW
NAME ADDRESS DESCRIPTION
PROTECTED
I2COAR 0x7900 No I2C own address register
I2CIER 0x7901 No I2C interrupt enable register
I2CSTR 0x7902 No I2C status register
I2CCLKL 0x7903 No I2C clock low-time divider register
I2CCLKH 0x7904 No I2C clock high-time divider register
I2CCNT 0x7905 No I2C data count register
I2CDRR 0x7906 No I2C data receive register
I2CSAR 0x7907 No I2C slave address register
I2CDXR 0x7908 No I2C data transmit register
I2CMDR 0x7909 No I2C mode register
I2CISRC 0x790A No I2C interrupt source register
I2CPSC 0x790C No I2C prescaler register
I2CFFTX 0x7920 No I2C FIFO transmit register
I2CFFRX 0x7921 No I2C FIFO receive register
I2CRSR No I2C receive shift register (not accessible to the CPU)
I2CXSR No I2C transmit shift register (not accessible to the CPU)

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
6.9.5.1 I2C Electrical Data/Timing
Table 6-39. I2C Timing

TEST CONDITIONS MIN MAX UNIT
I2C clock module frequency is between
7 MHz and 12 MHz and I2C prescaler and
fSCL SCL clock frequency 400 kHz
clock divider registers are configured
appropriately
vil Low level input voltage 0.3 VDDIO V
Vih High level input voltage 0.7 VDDIO V
Vhys Input hysteresis 0.05 VDDIO V
Vol Low level output voltage 3 mA sink current 0 0.4 V
tLOW Low period of SCL clock 1.3 s
appropriately
tHIGH High period of SCL clock 0.6 s
appropriately
Input current with an input voltage
lI 10 10 A
between 0.1 VDDIO and 0.9 VDDIO MAX
6.9.6 Enhanced PWM Modules (ePWM1/2/3/4)

The devices contain up to four enhanced PWM Modules (ePWM). Figure 6-35 shows a block diagram of
multiple ePWM modules. Figure 6-36 shows the signal interconnections with the ePWM. See the
TMS320x2802x, 2803x Piccolo Enhanced Pulse Width Modulator (ePWM) Module Reference Guide for
more details.
Table 6-40 shows the complete ePWM register set per module.

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
EPWMSYNCI
EPWM1SYNCI
EPWM1TZINT EPWM1B
ePWM1 TZ1 to TZ3
EPWM1INT
Module
EPWM2TZINT
PIE EPWM2INT CLOCKFAIL
TZ5
EPWMxTZINT EMUSTOP
TZ6
EPWMxINT
EPWM1ENCLK
TBCLKSYNC
eCAPI
EPWM1SYNCO
EPWM1SYNCO
EPWM2SYNCI TZ1 to TZ3

COMPOUT1
COMPOUT2 EPWM2B
ePWM2
Module
COMP CLOCKFAIL
TZ5 EPWM1A
EMUSTOP H
TZ6 EPWM2A
R
EPWM2ENCLK P
W
TBCLKSYNC EPWMxA
M
G
EPWM2SYNCO P
I
Peripheral Bus
M
SOCA1 U
ADC
SOCB1 X
SOCA2
SOCB2 EPWMxSYNCI EPWMxB
SOCAx ePWMx TZ1 to TZ3

SOCBx Module
CLOCKFAIL
TZ5
EMUSTOP
TZ6
EPWMxENCLK
TBCLKSYNC
System Control
C28x CPU
SOCA1
SOCA2 Pulse Stretch ADCSOCAO
SPCAx (32 SYSCLKOUT Cycles, Active-Low Output)
SOCB1
SOCB2 Pulse Stretch ADCSOCBO
SPCBx (32 SYSCLKOUT Cycles, Active-Low Output)
Figure 6-35. ePWM

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
Table 6-40. ePWM Control and Status Registers

SIZE (x16) /
NAME ePWM1 ePWM2 ePWM3 ePWM4 DESCRIPTION
#SHADOW
TBCTL 0x6800 0x6840 0x6880 0x68C0 1/0 Time Base Control Register
TBSTS 0x6801 0x6841 0x6881 0x68C1 1/0 Time Base Status Register
TBPHSHR 0x6802 0x6842 0x6882 0x68C2 1/0 Time Base Phase HRPWM Register
TBPHS 0x6803 0x6843 0x6883 0x68C3 1/0 Time Base Phase Register
TBCTR 0x6804 0x6844 0x6884 0x68C4 1/0 Time Base Counter Register
TBPRD 0x6805 0x6845 0x6885 0x68C5 1/1 Time Base Period Register Set
TBPRDHR 0x6806 0x6846 0x6886 0x68C6 1/1 Time Base Period High Resolution Register (1)
CMPCTL 0x6807 0x6847 0x6887 0x68C7 1/0 Counter Compare Control Register
CMPAHR 0x6808 0x6848 0x6888 0x68C8 1/1 Time Base Compare A HRPWM Register
CMPA 0x6809 0x6849 0x6889 0x68C9 1/1 Counter Compare A Register Set
CMPB 0x680A 0x684A 0x688A 0x68CA 1/1 Counter Compare B Register Set
AQCTLA 0x680B 0x684B 0x688B 0x68CB 1/0 Action Qualifier Control Register For Output A
AQCTLB 0x680C 0x684C 0x688C 0x68CC 1/0 Action Qualifier Control Register For Output B
AQSFRC 0x680D 0x684D 0x688D 0x68CD 1/0 Action Qualifier Software Force Register
AQCSFRC 0x680E 0x684E 0x688E 0x68CE 1/1 Action Qualifier Continuous S/W Force Register Set
DBCTL 0x680F 0x684F 0x688F 0x68CF 1/1 Dead-Band Generator Control Register
DBRED 0x6810 0x6850 0x6890 0x68D0 1/0 Dead-Band Generator Rising Edge Delay Count Register
DBFED 0x6811 0x6851 0x6891 0x68D1 1/0 Dead-Band Generator Falling Edge Delay Count Register
TZSEL 0x6812 0x6852 0x6892 0x68D2 1/0 Trip Zone Select Register (1)
TZDCSEL 0x6813 0x6853 0x6893 0x98D3 1/0 Trip Zone Digital Compare Register
TZCTL 0x6814 0x6854 0x6894 0x68D4 1/0 Trip Zone Control Register (1)
TZEINT 0x6815 0x6855 0x6895 0x68D5 1/0 Trip Zone Enable Interrupt Register (1)
(1)
TZFLG 0x6816 0x6856 0x6896 0x68D6 1/0 Trip Zone Flag Register
TZCLR 0x6817 0x6857 0x6897 0x68D7 1/0 Trip Zone Clear Register (1)
TZFRC 0x6818 0x6858 0x6898 0x68D8 1/0 Trip Zone Force Register (1)
ETSEL 0x6819 0x6859 0x6899 0x68D9 1/0 Event Trigger Selection Register
ETPS 0x681A 0x685A 0x689A 0x68DA 1/0 Event Trigger Prescale Register
ETFLG 0x681B 0x685B 0x689B 0x68DB 1/0 Event Trigger Flag Register
ETCLR 0x681C 0x685C 0x689C 0x68DC 1/0 Event Trigger Clear Register
ETFRC 0x681D 0x685D 0x689D 0x68DD 1/0 Event Trigger Force Register
PCCTL 0x681E 0x685E 0x689E 0x68DE 1/0 PWM Chopper Control Register
HRCNFG 0x6820 0x6860 0x68A0 0x68E0 1/0 HRPWM Configuration Register (1)
(1) Registers that are EALLOW protected.

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
Table 6-40. ePWM Control and Status Registers (continued)

SIZE (x16) /
NAME ePWM1 ePWM2 ePWM3 ePWM4 DESCRIPTION
#SHADOW
HRPWR 0x6821 - - - 1/0 HRPWM Power Register
HRMSTEP 0x6826 - - - 1/0 HRPWM MEP Step Register
HRPCTL 0x6828 0x6868 0x68A8 0x68E8 1/0 High resolution Period Control Register (1)
(2)
TBPRDHRM 0x682A 0x686A 0x68AA 0x68EA 1/W Time Base Period HRPWM Register Mirror
TBPRDM 0x682B 0x686B 0x68AB 0x68EB 1 / W (2) Time Base Period Register Mirror
CMPAHRM 0x682C 0x686C 0x68AC 0x68EC 1 / W (2) Compare A HRPWM Register Mirror
(2)
CMPAM 0x682D 0x686D 0x68AD 0x68ED 1/W Compare A Register Mirror
(1)
DCTRIPSEL 0x6830 0x6870 0x68B0 0x68F0 1/0 Digital Compare Trip Select Register
DCACTL 0x6831 0x6871 0x68B1 0x68F1 1/0 Digital Compare A Control Register (1)
DCBCTL 0x6832 0x6872 0x68B2 0x68F2 1/0 Digital Compare B Control Register (1)
DCFCTL 0x6833 0x6873 0x68B3 0x68F3 1/0 Digital Compare Filter Control Register (1)
DCCAPCT 0x6834 0x6874 0x68B4 0x68F4 1/0 Digital Compare Capture Control Register (1)
DCFOFFSET 0x6835 0x6875 0x68B5 0x68F5 1/1 Digital Compare Filter Offset Register
DCFOFFSETCNT 0x6836 0x6876 0x68B6 0x68F6 1/0 Digital Compare Filter Offset Counter Register
DCFWINDOW 0x6837 0x6877 0x68B7 0x68F7 1/0 Digital Compare Filter Window Register
DCFWINDOWCNT 0x6838 0x6878 0x68B8 0x68F8 1/0 Digital Compare Filter Window Counter Register
DCCAP 0x6839 0x6879 0x68B9 0x68F9 1/1 Digital Compare Counter Capture Register
(2) W = Write to shadow register

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
Time-Base (TB)
CTR=ZERO Sync
TBPRD Shadow (24) In/Out
CTR=CMPB Select EPWMxSYNCO
TBPRDHR (8)
TBPRD Active (24) Disabled Mux
8
CTR=PRD
TBCTL[PHSEN] TBCTL[SYNCOSEL]
EPWMxSYNCI
Counter DCAEVT1.sync
Up/Down DCBEVT1.sync
TBCTL[SWFSYNC]
(16 Bit)
(Software Forced
CTR=ZERO Sync)
TCBNT
Active (16) CTR_Dir CTR=PRD
CTR=ZERO
TBPHSHR (8) CTR=PRD or ZERO EPWMxINT
16 8 CTR=CMPA Event
Trigger EPWMxSOCA
Phase CTR=CMPB
TBPHS Active (24) and
Control CTR_Dir EPWMxSOCB
Interrupt
(A) (ET)
DCAEVT1.soc EPWMxSOCA
(A) ADC
DCBEVT1.soc EPWMxSOCB
Action
Qualifier
CTR=CMPA (AQ)
CMPAHR (8)
16
High-resolution PWM (HRPWM)
CMPA Active (24)
CMPA Shadow (24) EPWMA EPWMxA
Dead PWM Trip

CTR=CMPB Chopper Zone
Band
(DB) (PC) (TZ)
16
CMPB Active (16) EPWMB EPWMxB

CMPB Shadow (16) EPWMxTZINT
TZ1 to TZ3
CTR=ZERO EMUSTOP
DCAEVT1.inter CLOCKFAIL
DCBEVT1.inter (A)
DCAEVT1.force
DCAEVT2.inter (A)
DCBEVT2.inter DCAEVT2.force
(A)
DCBEVT1.force
(A)
DCBEVT2.force
A. These events are generated by the Type 1 ePWM digital compare (DC) submodule based on the levels of
the COMPxOUT and TZ signals.
Figure 6-36. ePWM Sub-Modules Showing Critical Internal Signal Interconnections

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
6.9.6.1 ePWM Electrical Data/Timing

PWM refers to PWM outputs on ePWM14. Table 6-41 shows the PWM timing requirements and Table 6-
42, switching characteristics.
Table 6-41. ePWM Timing Requirements (1)

MIN MAX UNIT
Asynchronous 2tc(SCO) cycles
tw(SYCIN) Sync input pulse width Synchronous 2tc(SCO) cycles
With input qualifier 1tc(SCO) + tw(IQSW) cycles
Table 6-42. ePWM Switching Characteristics

tw(PWM) Pulse duration, PWMx output high/low 33.33 ns
tw(SYNCOUT) Sync output pulse width 8tc(SCO) cycles
Delay time, trip input active to PWM forced high
td(PWM)tza no pin load 25 ns
Delay time, trip input active to PWM forced low
td(TZ-PWM)HZ Delay time, trip input active to PWM Hi-Z 20 ns
6.9.6.2 Trip-Zone Input Timing
Table 6-43. Trip-Zone Input Timing Requirements (1)

MIN MAX UNIT
Asynchronous 2tc(TBCLK) cycles
tw(TZ) Pulse duration, TZx input low Synchronous 2tc(TBCLK) cycles
With input qualifier 2tc(TBCLK) + tw(IQSW) cycles
SYSCLK
tw(TZ)
(A)
TZ
td(TZ-PWM)HZ
(B)
PWM
A. TZ - TZ1, TZ2, TZ3

B. PWM refers to all the PWM pins in the device. The state of the PWM pins after TZ is taken high depends on the PWM
recovery software.
Figure 6-37. PWM Hi-Z Characteristics

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
6.9.7 High-Resolution PWM (HRPWM)

This module combines multiple delay lines in a single module and a simplified calibration system by using
a dedicated calibration delay line. For each ePWM module there is one HR delay line.
The HRPWM module offers PWM resolution (time granularity) that is significantly better than what can be
achieved using conventionally derived digital PWM methods. The key points for the HRPWM module are:
Significantly extends the time resolution capabilities of conventionally derived digital PWM
This capability can be utilized in both single edge (duty cycle and phase-shift control) as well as dual
edge control for frequency/period modulation.
Finer time granularity control or edge positioning is controlled via extensions to the Compare A and
Phase registers of the ePWM module.
HRPWM capabilities, when available on a particular device, are offered only on the A signal path of an
ePWM module (that is, on the EPWMxA output). EPWMxB output has conventional PWM capabilities.
NOTE
The minimum SYSCLKOUT frequency allowed for HRPWM is 50 MHz.
NOTE
When dual-edge high-resolution is enabled (high-resolution period mode), the PWMxB output
is not available for use.
6.9.7.1 HRPWM Electrical Data/Timing

Table 6-44 shows the high-resolution PWM switching characteristics.
Table 6-44. High-Resolution PWM Characteristics at SYSCLKOUT = 50 MHz (1)60 MHz

Micro Edge Positioning (MEP) step size (2) 150 310 ps
(1) The HRPWM operates at a minimum SYSCLKOUT frequency of 50 MHz. Below 50 MHz, with device process variation, the MEP step
size may decrease under cold temperature and high core voltage conditions to such a point that 255 MEP steps will not span an entire
SYSCLKOUT cycle.
(2) Maximum MEP step size is based on worst-case process, maximum temperature and minimum voltage. MEP step size will increase
with low voltage and high temperature and decrease with voltage and cold temperature.
Applications that use the HRPWM feature should use MEP Scale Factor Optimizer (SFO) estimation software functions. See the TI
software libraries for details of using SFO function in end applications. SFO functions help to estimate the number of MEP steps per
SYSCLKOUT period dynamically while the HRPWM is in operation.

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
6.9.8 Enhanced Capture Module (eCAP1)

The device contains an enhanced capture (eCAP) module. Figure 6-38 shows a functional block diagram
of a module.
CTRPHS
(phase register32 bit) APWM mode
SYNC
SYNCIn
OVF CTR_OVF
TSCTR CTR [031]
SYNCOut PWM
(counter32 bit) Deltamode PRD [031] compare
RST
logic
CMP [031]
32
CTR [031] CTR=PRD

CTR=CMP
32
PRD [031]
eCAPx
MODE SELECT
32 CAP1 LD1 Polarity
LD
(APRD active) select
APRD 32
shadow CMP [031]
32
32 CAP2 LD2 Polarity

LD
(ACMP active) select
Event Event
32 ACMP
qualifier
shadow Prescale
32 Polarity
CAP3 LD3 select
LD
(APRD shadow)
32 CAP4 LD4
LD Polarity
(ACMP shadow) select
4
Capture events 4
CEVT[1:4]
Interrupt Continuous /
to PIE Trigger Oneshot
and CTR_OVF Capture Control
Flag
CTR=PRD
control
CTR=CMP
Figure 6-38. eCAP Functional Block Diagram
The eCAP module is clocked at the SYSCLKOUT rate.

The clock enable bits (ECAP1 ENCLK) in the PCLKCR1 register turn off the eCAP module individually (for
low power operation). Upon reset, ECAP1ENCLK is set to low, indicating that the peripheral clock is off.

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
Table 6-45. eCAP Control and Status Registers

NAME eCAP1 SIZE (x16) EALLOW PROTECTED DESCRIPTION
TSCTR 0x6A00 2 Time-Stamp Counter
CTRPHS 0x6A02 2 Counter Phase Offset Value Register
CAP1 0x6A04 2 Capture 1 Register
CAP4 0x6A0A 2 Capture 4 Register
Reserved 0x6A0C 0x6A12 8 Reserved
ECCTL1 0x6A14 1 Capture Control Register 1
ECCTL2 0x6A15 1 Capture Control Register 2
ECEINT 0x6A16 1 Capture Interrupt Enable Register
ECFLG 0x6A17 1 Capture Interrupt Flag Register
ECCLR 0x6A18 1 Capture Interrupt Clear Register
ECFRC 0x6A19 1 Capture Interrupt Force Register
Reserved 0x6A1A 0x6A1F 6 Reserved
For more information on the eCAP, see the TMS320F2802x, 2803x Piccolo Enhanced Capture (eCAP)
Module Reference Guide.
6.9.8.1 eCAP Electrical Data/Timing

Table 6-46 shows the eCAP timing requirement and Table 6-47 shows the eCAP switching characteristics.
Table 6-46. Enhanced Capture (eCAP) Timing Requirement (1)

MIN MAX UNIT
Asynchronous 2tc(SCO) cycles
tw(CAP) Capture input pulse width Synchronous 2tc(SCO) cycles
With input qualifier 1tc(SCO) + tw(IQSW) cycles
Table 6-47. eCAP Switching Characteristics

tw(APWM) Pulse duration, APWMx output high/low 20 ns

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
6.9.9 JTAG Port

On the 2802x device, the JTAG port is reduced to 5 pins (TRST, TCK, TDI, TMS, TDO). TCK, TDI, TMS
and TDO pins are also GPIO pins. The TRST signal selects either JTAG or GPIO operating mode for the
pins in Figure 6-39. During emulation/debug, the GPIO function of these pins are not available. If the
GPIO38/TCK/XCLKIN pin is used to provide an external clock, an alternate clock source should be used
to clock the device during emulation/debug since this pin will be needed for the TCK function.
NOTE
In 2802x devices, the JTAG pins may also be used as GPIO pins. Care should be taken in
the board design to ensure that the circuitry connected to these pins do not affect the
emulation capabilities of the JTAG pin function. Any circuitry connected to these pins should
not prevent the emulator from driving (or being driven by) the JTAG pins for successful
debug.
TRST = 0: JTAG Disabled (GPIO Mode)

TRST = 1: JTAG Mode
TRST
TRST
XCLKIN
GPIO38_in
TCK
TCK/GPIO38
GPIO38_out
C28x
Core
GPIO37_in
TDO
TDO/GPIO37 1
0 GPIO37_out
GPIO36_in
1
TMS
TMS/GPIO36
GPIO36_out 1 0
GPIO35_in
1
TDI
TDI/GPIO35
GPIO35_out 1 0
Figure 6-39. JTAG/GPIO Multiplexing

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
6.9.10 General-Purpose Input/Output (GPIO) MUX

The GPIO MUX can multiplex up to three independent peripheral signals on a single GPIO pin in addition
to providing individual pin bit-banging I/O capability.
The device supports 22 GPIO pins. The GPIO control and data registers are mapped to Peripheral
Frame 1 to enable 32-bit operations on the registers (along with 16-bit operations). Table 6-48 shows the
GPIO register mapping.
Table 6-48. GPIO Registers

GPIO CONTROL REGISTERS (EALLOW PROTECTED)
GPACTRL 0x6F80 2 GPIO A Control Register (GPIO0 to 31)
GPAQSEL1 0x6F82 2 GPIO A Qualifier Select 1 Register (GPIO0 to 15)
GPAQSEL2 0x6F84 2 GPIO A Qualifier Select 2 Register (GPIO16 to 31)
GPAMUX1 0x6F86 2 GPIO A MUX 1 Register (GPIO0 to 15)
GPAMUX2 0x6F88 2 GPIO A MUX 2 Register (GPIO16 to 31)
GPADIR 0x6F8A 2 GPIO A Direction Register (GPIO0 to 31)
GPAPUD 0x6F8C 2 GPIO A Pull Up Disable Register (GPIO0 to 31)
GPBCTRL 0x6F90 2 GPIO B Control Register (GPIO32 to 38)
GPBQSEL1 0x6F92 2 GPIO B Qualifier Select 1 Register (GPIO32 to 38)
GPBMUX1 0x6F96 2 GPIO B MUX 1 Register (GPIO32 to 38)
GPBDIR 0x6F9A 2 GPIO B Direction Register (GPIO32 to 38)
GPBPUD 0x6F9C 2 GPIO B Pull Up Disable Register (GPIO32 to 38)
AIOMUX1 0x6FB6 2 Analog, I/O mux 1 register (AIO0 to AIO15)
AIODIR 0x6FBA 2 Analog, I/O Direction Register (AIO0 to AIO15)
GPIO DATA REGISTERS (NOT EALLOW PROTECTED)
GPADAT 0x6FC0 2 GPIO A Data Register (GPIO0 to 31)
GPASET 0x6FC2 2 GPIO A Data Set Register (GPIO0 to 31)
GPACLEAR 0x6FC4 2 GPIO A Data Clear Register (GPIO0 to 31)
GPATOGGLE 0x6FC6 2 GPIO A Data Toggle Register (GPIO0 to 31)
GPBDAT 0x6FC8 2 GPIO B Data Register (GPIO32 to 38)
GPBSET 0x6FCA 2 GPIO B Data Set Register (GPIO32 to 38)
GPBCLEAR 0x6FCC 2 GPIO B Data Clear Register (GPIO32 to 38)
GPBTOGGLE 0x6FCE 2 GPIO B Data Toggle Register (GPIO32 to 38)
AIODAT 0x6FD8 2 Analog I/O Data Register (AIO0 to AIO15)
AIOSET 0x6FDA 2 Analog I/O Data Set Register (AIO0 to AIO15)
AIOCLEAR 0x6FDC 2 Analog I/O Data Clear Register (AIO0 to AIO15)
AIOTOGGLE 0x6FDE 2 Analog I/O Data Toggle Register (AIO0 to AIO15)
GPIO INTERRUPT AND LOW POWER MODES SELECT REGISTERS (EALLOW PROTECTED)
GPIOXINT1SEL 0x6FE0 1 XINT1 GPIO Input Select Register (GPIO0 to 31)
GPIOLPMSEL 0x6FE8 2 LPM GPIO Select Register (GPIO0 to 31)
NOTE
There is a two-SYSCLKOUT cycle delay from when the write to the GPxMUXn/AIOMUXn
and GPxQSELn registers occurs to when the action is valid.

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
Table 6-49. GPIOA MUX (1) (2)

DEFAULT AT RESET
PERIPHERAL PERIPHERAL PERIPHERAL
PRIMARY I/O
SELECTION 1 SELECTION 2 SELECTION 3
FUNCTION
GPAMUX1 REGISTER
(GPAMUX1 BITS = 00) (GPAMUX1 BITS = 01) (GPAMUX1 BITS = 10) (GPAMUX1 BITS = 11)
BITS
1-0 GPIO0 EPWM1A (O) Reserved Reserved
3-2 GPIO1 EPWM1B (O) Reserved COMP1OUT (O)
7-6 GPIO3 EPWM2B (O) Reserved COMP2OUT (3) (O)
11-10 GPIO5 EPWM3B (O) Reserved ECAP1 (I/O)
13-12 GPIO6 EPWM4A (O) EPWMSYNCI (I) EPWMSYNCO (O)
15-14 GPIO7 EPWM4B (O) SCIRXDA (I) Reserved
17-16 Reserved Reserved Reserved Reserved
25-24 GPIO12 TZ1 (I) SCITXDA (O) Reserved
GPAMUX2 REGISTER
(GPAMUX2 BITS = 00) (GPAMUX2 BITS = 01) (GPAMUX2 BITS = 10) (GPAMUX2 BITS = 11)
BITS
1-0 GPIO16 SPISIMOA (I/O) Reserved TZ2 (I)
3-2 GPIO17 SPISOMIA (I/O) Reserved TZ3 (I)
5-4 GPIO18 SPICLKA (I/O) SCITXDA (O) XCLKOUT (O)
7-6 GPIO19/XCLKIN SPISTEA (I/O) SCIRXDA (I) ECAP1 (I/O)
25-24 GPIO28 SCIRXDA (I) SDAA (I/OD) TZ2 (I)
27-26 GPIO29 SCITXDA (O) SCLA (I/OD) TZ3 (I)
(1) The word reserved means that there is no peripheral assigned to this GPxMUX1/2 register setting. Should it be selected, the state of the
pin will be undefined and the pin may be driven. This selection is a reserved configuration for future expansion.
(2) I = Input, O = Output, OD = Open Drain
(3) These functions are not available in the 38-pin package.

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
Table 6-50. GPIOB MUX (1)

DEFAULT AT RESET PERIPHERAL PERIPHERAL PERIPHERAL
PRIMARY I/O FUNCTION SELECTION 1 SELECTION 2 SELECTION 3
GPBMUX1 REGISTER
(GPBMUX1 BITS = 00) (GPBMUX1 BITS = 01) (GPBMUX1 BITS = 10) (GPBMUX1 BITS = 11)
BITS
1-0 GPIO32 (2) SDAA (2) (I/OD) EPWMSYNCI (2) (I) ADCSOCAO (2)
(O)
(2) (2) (2) (2)
3-2 GPIO33 SCLA (I/OD) EPWMSYNCO (O) ADCSOCBO (O)
5-4 GPIO34 COMP2OUT (O) Reserved Reserved
7-6 GPIO35 (TDI) Reserved Reserved Reserved
9-8 GPIO36 (TMS) Reserved Reserved Reserved
11-10 GPIO37 (TDO) Reserved Reserved Reserved
13-12 GPIO38/XCLKIN (TCK) Reserved Reserved Reserved
(1) I = Input, O = Output, OD = Open Drain
(2) These pins are not available in the 38-pin package.
Table 6-51. Analog MUX for 48-Pin PT Package (1)

DEFAULT AT RESET
PERIPHERAL SELECTION 2 AND
AIOx AND PERIPHERAL SELECTION 1
PERIPHERAL SELECTION 3
AIOMUX1 REGISTER BITS AIOMUX1 BITS = 0,x AIOMUX1 BITS = 1,x
1-0 ADCINA0 (I), VREFHI (I) ADCINA0 (I), VREFHI (I)
3-2 ADCINA1 (I) ADCINA1 (I)
5-4 AIO2 (I/O) ADCINA2 (I), COMP1A (I)
11-10
13-12 AIO6 (I/O) ADCINA6 (I)
17-16
19-18 ADCINB1 (I) ADCINB1 (I)
21-20 AIO10 (I/O) ADCINB2 (I), COMP1B (I)
27-26
29-28 AIO14 (I/O) ADCINB6 (I)
(1) I = Input, O = Output

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
Table 6-52. Analog MUX for 38-Pin DA Package (1)

DEFAULT AT RESET
PERIPHERAL SELECTION 2 AND
AIOx AND PERIPHERAL SELECTION 1
PERIPHERAL SELECTION 3
AIOMUX1 REGISTER BITS AIOMUX1 BITS = 0,x AIOMUX1 BITS = 1,x
1-0 ADCINA0 (I), VREFHI (I) ADCINA0 (I), VREFHI (I)
3-2
7-6
11-10
15-14
17-16
19-18
23-22
27-26
31-30
(1) I = Input, O = Output
The user can select the type of input qualification for each GPIO pin via the GPxQSEL1/2 registers from
four choices:
Synchronization To SYSCLKOUT Only (GPxQSEL1/2 = 0, 0): This is the default mode of all GPIO pins
at reset and it simply synchronizes the input signal to the system clock (SYSCLKOUT).
Qualification Using Sampling Window (GPxQSEL1/2 = 0, 1 and 1, 0): In this mode the input signal,
after synchronization to the system clock (SYSCLKOUT), is qualified by a specified number of cycles
before the input is allowed to change.
The sampling period is specified by the QUALPRD bits in the GPxCTRL register and is configurable in
groups of 8 signals. It specifies a multiple of SYSCLKOUT cycles for sampling the input signal. The
sampling window is either 3-samples or 6-samples wide and the output is only changed when ALL
samples are the same (all 0s or all 1s) as shown in Figure 4-18 (for 6 sample mode).
No Synchronization (GPxQSEL1/2 = 1,1): This mode is used for peripherals where synchronization is
not required (synchronization is performed within the peripheral).
Due to the multilevel multiplexing that is required on the device, there may be cases where a peripheral
input signal can be mapped to more then one GPIO pin. Also, when an input signal is not selected, the
input signal will default to either a 0 or 1 state, depending on the peripheral.

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
GPIOXINT1SEL
GPIOLMPSEL GPIOXINT2SEL
LPMCR0 GPIOXINT3SEL
Low P ower External Interrupt PIE

Modes Block MUX
Asynchronous
path GPxDAT (read)
GPxQSEL1/2
GPxCTRL
GPxPUD 00 N/C
01 Peripheral 1 Input
Input
Internal
Qualification
Pullup 10 Peripheral 2 Input
11 Peripheral 3 Input
Asynchronous path GPxTOGGLE
GPIOx pin GPxCLEAR
GPxSET
00 GPxDAT (latch)
01 Peripheral 1 Output
High Impedance
Output Control
00 GPxDIR (latch)
0 = Input, 1 = Output 01 Peripheral 1 Output Enable
10 Peripheral 2 Output Enable
XRS
11 Peripheral 3 Output Enable
= Default at Reset
GPxMUX1/2
A. x stands for the port, either A or B. For example, GPxDIR refers to either the GPADIR and GPBDIR register
depending on the particular GPIO pin selected.
B. GPxDAT latch/read are accessed at the same memory location.
C. This is a generic GPIO MUX block diagram. Not all options may be applicable for all GPIO pins. See the
TMS320x2802x/TMS320F2802xx Piccolo System Control and Interrupts Reference Guide for pin-specific variations.
Figure 6-40. GPIO Multiplexing

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
6.9.10.1 GPIO Electrical Data/Timing
6.9.10.1.1 GPIO - Output Timing
Table 6-53. General-Purpose Output Switching Characteristics

tr(GPO) Rise time, GPIO switching low to high All GPIOs 13 (1) ns
(1)
tf(GPO) Fall time, GPIO switching high to low All GPIOs 13 ns
tfGPO Toggling frequency 15 MHz
(1) Rise time and fall time vary with electrical loading on I/O pins. Values given in Table 6-53 are applicable for a 40-pF load on I/O pins.
GPIO
t r(GPO)
t f(GPO)
Figure 6-41. General-Purpose Output Timing

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
6.9.10.1.2 GPIO - Input Timing
Table 6-54. General-Purpose Input Timing Requirements

MIN MAX UNIT
QUALPRD = 0 1tc(SCO) cycles
tw(SP) Sampling period
QUALPRD 0 2tc(SCO) * QUALPRD cycles
tw(IQSW) Input qualifier sampling window tw(SP) * (n (1) 1) cycles
(2)
Synchronous mode 2tc(SCO) cycles
tw(GPI) Pulse duration, GPIO low/high
With input qualifier tw(IQSW) + tw(SP) + 1tc(SCO) cycles
(1) "n" represents the number of qualification samples as defined by GPxQSELn register.
(2) For tw(GPI), pulse width is measured from VIL to VIL for an active low signal and VIH to VIH for an active high signal.
(A)
GPIO Signal GPxQSELn = 1,0 (6 samples)
1 1 0 0 0 0 0 0 0 1 0 0 0 1 1 1 1 1 1 1 1 1
tw(SP) Sampling Period determined

(B)
by GPxCTRL[QUALPRD]
tw(IQSW)
(C)
Sampling Window [(SYSCLKOUT cycle * 2 * QUALPRD) * 5 ]
SYSCLKOUT
QUALPRD = 1
(SYSCLKOUT/2)
(D)
Output From
Qualifier
A. This glitch will be ignored by the input qualifier. The QUALPRD bit field specifies the qualification sampling period. It
can vary from 00 to 0xFF. If QUALPRD = 00, then the sampling period is 1 SYSCLKOUT cycle. For any other value
"n", the qualification sampling period in 2n SYSCLKOUT cycles (that is, at every 2n SYSCLKOUT cycles, the GPIO
pin will be sampled).
B. The qualification period selected via the GPxCTRL register applies to groups of 8 GPIO pins.
C. The qualification block can take either three or six samples. The GPxQSELn Register selects which sample mode is
used.
D. In the example shown, for the qualifier to detect the change, the input should be stable for 10 SYSCLKOUT cycles or
greater. In other words, the inputs should be stable for (5 x QUALPRD x 2) SYSCLKOUT cycles. This would ensure
5 sampling periods for detection to occur. Since external signals are driven asynchronously, an 13-SYSCLKOUT-wide
pulse ensures reliable recognition.
Figure 6-42. Sampling Mode

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
6.9.10.1.3 Sampling Window Width for Input Signals

The following section summarizes the sampling window width for input signals for various input qualifier
configurations.
Sampling frequency denotes how often a signal is sampled with respect to SYSCLKOUT.
Sampling frequency = SYSCLKOUT/(2 * QUALPRD), if QUALPRD 0
Sampling frequency = SYSCLKOUT, if QUALPRD = 0
Sampling period = SYSCLKOUT cycle x 2 x QUALPRD, if QUALPRD 0
In the above equations, SYSCLKOUT cycle indicates the time period of SYSCLKOUT.
Sampling period = SYSCLKOUT cycle, if QUALPRD = 0
In a given sampling window, either 3 or 6 samples of the input signal are taken to determine the validity of
the signal. This is determined by the value written to GPxQSELn register.
Case 1:
Qualification using 3 samples
Sampling window width = (SYSCLKOUT cycle x 2 x QUALPRD) x 2, if QUALPRD 0
Sampling window width = (SYSCLKOUT cycle) x 2, if QUALPRD = 0
Case 2:
Qualification using 6 samples
Sampling window width = (SYSCLKOUT cycle x 2 x QUALPRD) x 5, if QUALPRD 0
Sampling window width = (SYSCLKOUT cycle) x 5, if QUALPRD = 0
SYSCLK
GPIOxn
tw(GPI)
Figure 6-43. General-Purpose Input Timing
VDDIO
> 1 MS
2 pF
VSS VSS
Figure 6-44. Input Resistance Model for a GPIO Pin With an Internal Pullup

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
6.9.10.1.4 Low-Power Mode Wakeup Timing

Table 6-55 shows the timing requirements, Table 6-56 shows the switching characteristics, and Figure 6-
45 shows the timing diagram for IDLE mode.
Table 6-55. IDLE Mode Timing Requirements (1)

MIN MAX UNIT
Without input qualifier 2tc(SCO)
tw(WAKE-INT) Pulse duration, external wake-up signal cycles
With input qualifier 5tc(SCO) + tw(IQSW)
Table 6-56. IDLE Mode Switching Characteristics (1)

(2)
Delay time, external wake signal to program execution resume cycles
Wake-up from Flash Without input qualifier 20tc(SCO)
cycles
Flash module in active state With input qualifier 20tc(SCO) + tw(IQSW)
td(WAKE-IDLE) Wake-up from Flash Without input qualifier 1050tc(SCO)
cycles
Flash module in sleep state With input qualifier 1050tc(SCO) + tw(IQSW)
Wake-up from SARAM cycles
With input qualifier 20tc(SCO) + tw(IQSW)
(2) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. execution of an ISR (triggered
by the wake-up) signal involves additional latency.
td(WAKEIDLE)
Address/Data
(internal)
XCLKOUT
tw(WAKEINT)
(A)(B)
WAKE INT
A. WAKE INT can be any enabled interrupt, WDINT or XRS.

B. From the time the IDLE instruction is executed to place the device into low-power mode (LPM), wakeup should not be
initiated until at least 4 OSCCLK cycles have elapsed.
Figure 6-45. IDLE Entry and Exit Timing

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
Table 6-57. STANDBY Mode Timing Requirements

MIN MAX UNIT
Pulse duration, external Without input qualification 3tc(OSCCLK)
tw(WAKE-INT) cycles
wake-up signal With input qualification (1) (2 + QUALSTDBY) * tc(OSCCLK)
(1) QUALSTDBY is a 6-bit field in the LPMCR0 register.
Table 6-58. STANDBY Mode Switching Characteristics

Delay time, IDLE instruction
td(IDLE-XCOL) 32tc(SCO) 45tc(SCO) cycles
executed to XCLKOUT low
Delay time, external wake signal to program execution
cycles
resume (1)
Wake up from flash Without input qualifier 100tc(SCO)
cycles
Flash module in active state With input qualifier 100tc(SCO) + tw(WAKE-INT)
td(WAKE-STBY)
Wake up from flash Without input qualifier 1125tc(SCO)
cycles
Flash module in sleep state With input qualifier 1125tc(SCO) + tw(WAKE-INT)
Wake up from SARAM cycles
With input qualifier 100tc(SCO) + tw(WAKE-INT)
(1) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. execution of an ISR (triggered
by the wake up signal) involves additional latency.

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
(A) (C) (F)

(B) (D)(E) (G)
Device STANDBY STANDBY Normal Execution

Status
Flushing Pipeline
Wake-up
(H)
Signal
tw(WAKE-INT)
td(WAKE-STBY)
X1/X2 or
XCLKIN
XCLKOUT
td(IDLEXCOL)
A. IDLE instruction is executed to put the device into STANDBY mode.
B. The PLL block responds to the STANDBY signal. SYSCLKOUT is held for the number of cycles indicated below
before being turned off:
16 cycles, when DIVSEL = 00 or 01
32 cycles, when DIVSEL = 10
This delay enables the CPU pipeline and any other pending operations to flush properly.
C. Clock to the peripherals are turned off. However, the PLL and watchdog are not shut down. The device is now in
STANDBY mode.
D. The external wake-up signal is driven active.
E. The wake-up signal fed to a GPIO pin to wake up the device must meet the minimum pulse width requirement.
Furthermore, this signal must be free of glitches. If a noisy signal is fed to a GPIO pin, the wake-up behavior of the
device will not be deterministic and the device may not exit low-power mode for subsequent wake-up pulses.
F. After a latency period, the STANDBY mode is exited.
G. Normal execution resumes. The device will respond to the interrupt (if enabled).
H. From the time the IDLE instruction is executed to place the device into low-power mode (LPM), wakeup should not be
Figure 6-46. STANDBY Entry and Exit Timing Diagram
Table 6-59. HALT Mode Timing Requirements

MIN MAX UNIT
tw(WAKE-GPIO) Pulse duration, GPIO wake-up signal toscst + 2tc(OSCCLK) cycles
tw(WAKE-XRS) Pulse duration, XRS wakeup signal toscst + 8tc(OSCCLK) cycles
Table 6-60. HALT Mode Switching Characteristics

td(IDLE-XCOL) Delay time, IDLE instruction executed to XCLKOUT low 32tc(SCO) 45tc(SCO) cycles
tp PLL lock-up time 1 ms
Delay time, PLL lock to program execution resume
Wake up from flash 1125tc(SCO) cycles
td(WAKE-HALT) Flash module in sleep state
Wake up from SARAM 35tc(SCO) cycles

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
(A) (C) (F) (H)

(B) (D)(E) (G)
Device
HALT HALT
Status
Flushing Pipeline PLL Lock-up Time Normal

Wake-up Latency Execution
(I)
GPIOn
td(WAKEHALT )
tw(WAKE-GPIO)
tp
X1/X2 or
XCLKIN
Oscillator Start-up Time
XCLKOUT
td(IDLEXCOL)
A. IDLE instruction is executed to put the device into HALT mode.

B. The PLL block responds to the HALT signal. SYSCLKOUT is held for the number of cycles indicated below before
oscillator is turned off and the CLKIN to the core is stopped:
16 cycles, when DIVSEL = 00 or 01
This delay enables the CPU pipeline and any other pending operations to flush properly.
C. Clocks to the peripherals are turned off and the PLL is shut down. If a quartz crystal or ceramic resonator is used as
the clock source, the internal oscillator is shut down as well. The device is now in HALT mode and consumes
absolute minimum power. It is possible to keep the zero-pin internal oscillators (INTOSC1 and INTOSC2) and the
watchdog alive in HALT mode. This is done by writing to the appropriate bits in the CLKCTL register.
D. When the GPIOn pin (used to bring the device out of HALT) is driven low, the oscillator is turned on and the oscillator
wake-up sequence is initiated. The GPIO pin should be driven high only after the oscillator has stabilized. This
enables the provision of a clean clock signal during the PLL lock sequence. Since the falling edge of the GPIO pin
asynchronously begins the wakeup procedure, care should be taken to maintain a low noise environment prior to
entering and during HALT mode.
E. The wake-up signal fed to a GPIO pin to wake up the device must meet the minimum pulse width requirement.
Furthermore, this signal must be free of glitches. If a noisy signal is fed to a GPIO pin, the wake-up behavior of the
device will not be deterministic and the device may not exit low-power mode for subsequent wake-up pulses.
F. Once the oscillator has stabilized, the PLL lock sequence is initiated, which takes 1 ms.
G. When CLKIN to the core is enabled, the device will respond to the interrupt (if enabled), after a latency. The HALT
mode is now exited.
H. Normal operation resumes.
I. From the time the IDLE instruction is executed to place the device into low-power mode (LPM), wakeup should not be
Figure 6-47. HALT Wake-Up Using GPIOn

TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
7 Applications, Implementation, and Layout
NOTE
Information in the following sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TIs customers are responsible for
determining suitability of components for their purposes. Customers should validate and test
their design implementation to confirm system functionality.
7.1 TI Design or Reference Design

TI Designs Reference Design Library is a robust reference design library spanning analog, embedded
processor and connectivity. Created by TI experts to help you jump start your system design, all TI
Designs include schematic or block diagrams, BOMs, and design files to speed your time to market.
Search and download designs at ti.com/tidesigns.
36V, 32A Power Stage for BLDC Motor with Cycle by Cycle Stall Current Limiter
This reference design is a power stage for brushless motors in battery-powered garden and power tools
rated up to 1 kW, operating from a 10-cell lithium-ion battery with a voltage range from 36 V to 42 V. The
design uses 60-V, N-channel NexFET technology featuring a very low drain-to-source resistance
(RDS_ON) of 1.8 m in a SON5x6 SMD package, which results in a very small PCB form factor of
57 mm 59 mm. The 3-phase gate-driver is used to drive a 3-phase MOSFET bridge, which can operate
from 6 V to 60 V and supports programmable gate current with a maximum setting of 2.3-A sink/1.7-A
source. The C2000 Piccolo LaunchPad Development Kit (LAUNCHXL-F28027) is used with this
power stage, and 120-degree trapezoidal control of BLDC motor with Hall sensors is implemented in
software. The cycle-by-cycle current limit feature in the gate-driver protects the board from excessive
current that is caused during motor stalls, by limiting the maximum current allowed in the power stage to a
safe level.
Single-Ended Signal Conditioning Circuit for Current and Voltage Measurement Using Fluxgate Sensors
This design provides a 4-channel signal conditioning solution for single-ended SAR ADCs integrated into a
microcontroller measuring motor current using fluxgate sensors. Also provided is an alternative
measurement circuit with external SAR ADCs as well as circuits for high-speed overcurrent and earth fault
detection. Proper signal conditioning improves noise immunity on critical current measurements in motor
drives. This reference design can help increase the effective resolution of the analog-to-digital conversion,
improving motor drive efficiency.
Copyright 20082016, Texas Instruments Incorporated Applications, Implementation, and Layout 123
TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
8 Device and Documentation Support

8.1 Getting Started
Key links include:
1. Getting Started with C2000 Real-time Control MCUs
2. Motor Drive and Control
3. Digital Power
4. Tools & Software for Performance MCUs
8.2 Device and Development Support Tool Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
TMS320 MCU devices and support tools. Each TMS320 MCU commercial family member has one of
three prefixes: TMX, TMP, or TMS (for example, TMS320F28023). Texas Instruments recommends two of
three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent
evolutionary stages of product development from engineering prototypes (TMX/TMDX) through fully
qualified production devices/tools (TMS/TMDS).
Device development evolutionary flow:
TMX Experimental device that is not necessarily representative of the final device's electrical
specifications
TMP Final silicon die that conforms to the device's electrical specifications but has not
completed quality and reliability verification
TMS Fully qualified production device
Support tool development evolutionary flow:
TMDX Development-support product that has not yet completed Texas Instruments internal
qualification testing
TMDS Fully qualified development-support product
TMX and TMP devices and TMDX development-support tools are shipped against the following
disclaimer:
"Developmental product is intended for internal evaluation purposes."
TMS devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard
production devices. Texas Instruments recommends that these devices not be used in any production
system because their expected end-use failure rate still is undefined. Only qualified production devices are
to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
package type (for example, PT) and temperature range (for example, S). Figure 8-1 provides a legend for
reading the complete device name for any family member.
For device part numbers and further ordering information, see the TI website (www.ti.com) or contact your
TI sales representative.
For additional description of the device nomenclature markings on the die, see the TMS320F28027,
TMS320F28026, TMS320F28023, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200,
TMS320F280270, TMS320F280260, TMS320F280230, TMS320F280220 Piccolo MCU Silicon Errata.
124 Device and Documentation Support Copyright 20082016, Texas Instruments Incorporated
TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
TMS 320 F 28023 PT S
PREFIX TEMPERATURE RANGE

TMX = experimental device T = 40C to 105C
TMP = prototype device S = 40C to 125C
TMS = qualified device
Q = 40C to 125C
(Q refers to Q100 qualification for automotive applications.)
DEVICE FAMILY PACKAGE TYPE

320 = TMS320 MCU Family 48-Pin PT Low-Profile Quad Flatpack (LQFP)
38-Pin DA Thin Shrink Small-Outline Package (TSSOP)
DEVICE
TECHNOLOGY 28027 28027F
F = Flash 28026 28026F
28023
28022
28021
28020
280200
A. For more information on peripheral, temperature, and package availability for a specific device, see Table 3-1.
Figure 8-1. Device Nomenclature
8.3 Tools and Software

TI offers an extensive line of development tools. Some of the tools and software to evaluate the
performance of the device, generate code, and develop solutions are listed below. To view all available
tools and software for C2000 real-time control MCUs, visit the Tools & software for C2000 real-time
control MCUs page.
Development Tools
Code Composer Studio (CCS) Integrated Development Environment (IDE) for C2000 Microcontrollers
Code Composer Studio is an integrated development environment (IDE) that supports TI's Microcontroller
and Embedded Processors portfolio. CCS comprises a suite of tools used to develop and debug
embedded applications. It includes an optimizing C/C++ compiler, source code editor, project build
environment, debugger, profiler, and many other features. The intuitive IDE provides a single user
interface taking you through each step of the application development flow. Familiar tools and interfaces
allow users to get started faster than ever before. CCS combines the advantages of the Eclipse software
framework with advanced embedded debug capabilities from TI resulting in a compelling feature-rich
development environment for embedded developers.
C2000 Piccolo LaunchPad
The C2000 Piccolo LaunchPad is an inexpensive, modular, and fun evaluation platform, enabling you to
dive into real-time, closed-loop control development with Texas Instruments C2000 32-bit microcontroller
family. This platform provides a great starting point for development of many common power electronics
applications, including motor control, digital power supplies, solar inverters, digital LED lighting, precision
sensing, and more.
To view all available C2000 LaunchPad development kits and BoosterPack plug-in modules, visit the
C2000 LaunchPad site.
Software Tools
powerSUITE - Digital Power Supply Design Software Tools for C2000 MCUs
powerSUITE is a suite of digital power supply design software tools for Texas Instruments' C2000 real-
time microcontroller (MCU) family. powerSUITE helps power supply engineers drastically reduce
development time as they design digitally-controlled power supplies based on C2000 real-time control
MCUs.
Copyright 20082016, Texas Instruments Incorporated Device and Documentation Support 125
TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
Training
InstaSPIN-FOC LaunchPad and BoosterPack
This six-part series provides information about the C2000 InstaSPIN-FOC Motor Control LaunchPad
Development Kit and BoosterPack Plug-in Module.
The InstaSPIN-FOC enabled C2000 Piccolo LaunchPad is an inexpensive evaluation platform designed to
help you leap right into the world of sensorless motor control using the InstaSPIN-FOC solution.
Part 1: Introduction and Overview
Part 2: Identifying Your Motor
Part 3: Zero Speed, Low Speed, & Tuning
Part 4: Accelerations & Speed Reversals with Texas Instruments
Part 5: High, Higher, Highest Speeds with Texas Instruments
BOOSTXL-DRV8301 BoosterPack with Texas Instruments
C2000 Architecture and Peripherals
The C2000 family of microcontrollers contains a unique mix of innovative and cutting-edge peripherals
along with a very capable C28x core. This video goes over the core architecture and every peripheral
offered on C2000 devices.
TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
8.4 Documentation Support

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the
upper right corner, click on Alert me to register and receive a weekly digest of any product information that
has changed. For change details, review the revision history included in any revised document.
The current documentation that describes the processor, related peripherals, and other technical collateral
is listed below.
Errata
TMS320F28027, TMS320F28026, TMS320F28023, TMS320F28022, TMS320F28021, TMS320F28020,
TMS320F280200, TMS320F280270, TMS320F280260, TMS320F280230, TMS320F280220 Piccolo MCU
Silicon Errata describes known advisories on silicon and provides workarounds.
InstaSPIN Technical Reference Manuals
InstaSPIN-FOC and InstaSPIN-MOTION User's Guide describes the InstaSPIN-FOC and InstaSPIN-
MOTION devices.
TMS320F28026F, TMS320F28027F InstaSPIN-FOC Software Technical Reference Manual describes
the TMS320F28026F and TMS320F28027F InstaSPIN-FOC software.
CPU User's Guides
TMS320C28x CPU and Instruction Set Reference Guide describes the central processing unit (CPU) and
the assembly language instructions of the TMS320C28x fixed-point digital signal processors (DSPs). This
reference guide also describes emulation features available on these DSPs.
Peripheral Guides
TMS320F2802x/TMS320F2802xx Piccolo System Control and Interrupts Reference Guide describes the
various interrupts and system control features of the 2802x microcontrollers (MCUs).
C2000 Real-Time Control Peripherals Reference Guide describes the peripheral reference guides of the
28x digital signal processors (DSPs).
TMS320x2802x Piccolo Boot ROM Reference Guide describes the purpose and features of the boot
loader (factory-programmed boot-loading software) and provides examples of code. It also describes other
contents of the device on-chip boot ROM and identifies where all of the information is located within that
memory.
TMS320x2802x, 2803x Piccolo Analog-to-Digital Converter (ADC) and Comparator Reference Guide
describes how to configure and use the on-chip ADC module, which is a 12-bit pipelined ADC.
TMS320x2802x, 2803x Piccolo Enhanced Pulse Width Modulator (ePWM) Module Reference Guide
describes the main areas of the enhanced pulse width modulator that include digital motor control, switch
mode power supply control, UPS (uninterruptible power supplies), and other forms of power conversion.
TMS320x2802x, 2803x Piccolo High Resolution Pulse Width Modulator (HRPWM) Reference Guide
describes the operation of the high-resolution extension to the pulse width modulator (HRPWM).
TMS320x2802x, 2803x Piccolo Serial Communications Interface (SCI) Reference Guide describes how to
use the SCI.
TMS320F2802x, 2803x Piccolo Enhanced Capture (eCAP) Module Reference Guide describes the
enhanced capture module. It includes the module description and registers.
TMS320x2802x, 2803x Piccolo Serial Peripheral Interface (SPI) Reference Guide describes the SPI - a
high-speed synchronous serial input/output (I/O) port - that allows a serial bit stream of programmed
length (one to sixteen bits) to be shifted into and out of the device at a programmed bit-transfer rate.
TMS320x2802x, 2803x Piccolo Inter-Integrated Circuit (I2C) Module Reference Guide describes the
features and operation of the inter-integrated circuit (I2C) module.
TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
Tools Guides
TMS320C28x Assembly Language Tools v15.12.0.LTS User's Guide describes the assembly language
tools (assembler and other tools used to develop assembly language code), assembler directives, macros,
common object file format, and symbolic debugging directives for the TMS320C28x device.
TMS320C28x Optimizing C/C++ Compiler v15.12.0.LTS User's Guide describes the TMS320C28x C/C++
compiler. This compiler accepts ANSI standard C/C++ source code and produces TMS320 DSP assembly
language source code for the TMS320C28x device.
TMS320C28x Instruction Set Simulator Technical Overview describes the simulator, available within the
Code Composer Studio for TMS320C2000 IDE, that simulates the instruction set of the C28x core.
Application Reports
Semiconductor Packing Methodology describes the packing methodologies employed to prepare
semiconductor devices for shipment to end users.
Calculating Useful Lifetimes of Embedded Processors provides a methodology for calculating the useful
lifetime of TI embedded processors (EPs) under power when used in electronic systems. It is aimed at
general engineers who wish to determine if the reliability of the TI EP meets the end system reliability
requirement.
Semiconductor and IC Package Thermal Metrics describes traditional and new thermal metrics and puts
their application in perspective with respect to system-level junction temperature estimation.
Oscillator Compensation Guide describes a factory supplied method for compensating the Piccolo internal
oscillators for frequency drift caused by temperature.
8.5 Related Links

The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 8-1. Related Links

TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY
DOCUMENTS SOFTWARE COMMUNITY
TMS320F28027 Click here Click here Click here Click here Click here
TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
8.6 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI E2E Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster
collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge,
explore ideas and help solve problems with fellow engineers.
TI Embedded Processors Wiki Texas Instruments Embedded Processors Wiki. Established to help
developers get started with Embedded Processors from Texas Instruments and to foster
innovation and growth of general knowledge about the hardware and software surrounding
these devices.
8.7 Trademarks
Piccolo, controlSUITE, TMS320C2000, NexFET, C2000, LaunchPad, TMS320, E2E are trademarks of
Texas Instruments.
I2C-bus is a registered trademark of NXP B.V. Corporation.
All other trademarks are the property of their respective owners.
8.8 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
8.9 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
TMS320F28020 TMS320F280200
TMS320F28021, TMS320F28020, TMS320F280200
9 Mechanical Packaging and Orderable Information

9.1 Packaging Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and
revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
130 Mechanical Packaging and Orderable Information Copyright 20082016, Texas Instruments Incorporated
TMS320F28020 TMS320F280200
MECHANICAL DATA
MTQF003A OCTOBER 1994 REVISED DECEMBER 1996
PT (S-PQFP-G48) PLASTIC QUAD FLATPACK
0,27
0,50 0,08 M
0,17
36 25
37 24
48 13
0,13 NOM
1 12
5,50 TYP
7,20
SQ
6,80 Gage Plane
9,20
SQ
8,80
0,25
1,45 0,05 MIN 0 7
1,35
0,75
Seating Plane 0,45
1,60 MAX 0,10
4040052 / C 11/96
NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
D. This may also be a thermally enhanced plastic package with leads conected to the die pads.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265 1

PACKAGE OPTION ADDENDUM
www.ti.com 22-Aug-2016
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
TMP320F28027PTA OBSOLETE LQFP PT 48 TBD Call TI Call TI -40 to 85

TMS320F280200DAS ACTIVE TSSOP DA 38 40 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 F280200DAS
& no Sb/Br) S320
TMS320F280200DAT ACTIVE TSSOP DA 38 40 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 105 F280200DAT
& no Sb/Br) S320
TMS320F280200PTT ACTIVE LQFP PT 48 250 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 105 S320 980
& no Sb/Br) F280200PTT
& no Sb/Br) S320
& no Sb/Br) S320
TMS320F28020PTS ACTIVE LQFP PT 48 250 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 S320 980
& no Sb/Br) F28020PTS
& no Sb/Br) S320
& no Sb/Br) S320
TMS320F28022DAQ ACTIVE TSSOP DA 38 40 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 F28022DAQ
& no Sb/Br) S320
TMS320F28022DAQR ACTIVE TSSOP DA 38 2000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR F28022DAQ
& no Sb/Br) S320
& no Sb/Br) S320
& no Sb/Br) S320
TMS320F28022PTQ ACTIVE LQFP PT 48 250 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 S320 980
& no Sb/Br) F28022PTQ
Addendum-Page 1
(1) Drawing Qty (2) (6) (3) (4/5)
& no Sb/Br) S320
& no Sb/Br) S320
& no Sb/Br) S320
& no Sb/Br) S320
& no Sb/Br) S320
& no Sb/Br) S320
TMS320F28026DATR ACTIVE TSSOP DA 38 2000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 105 F28026DAT
& no Sb/Br) S320
TMS320F28026FPTQ ACTIVE LQFP PT 48 250 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 S320F 980
& no Sb/Br) 28026FPTQ
TMS320F28026FPTT ACTIVE LQFP PT 48 250 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 105 S320 980
& no Sb/Br) F28026FPTT
& no Sb/Br) S320
Addendum-Page 2
(1) Drawing Qty (2) (6) (3) (4/5)
& no Sb/Br) S320
& no Sb/Br) S320
TMS320F28027DATR ACTIVE TSSOP DA 38 2000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 105 F28027DAT
& no Sb/Br) S320
TMS320F28027FPTQ ACTIVE LQFP PT 48 250 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 S320 980
& no Sb/Br) F28027FPTQ
TMS320F28027FPTT ACTIVE LQFP PT 48 250 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 105 S320 980
& no Sb/Br) F28027FPTT
TMS320F28027PTQR ACTIVE LQFP PT 48 1000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR S320 980
TMS320F28027PTR ACTIVE LQFP PT 48 1000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 105 S320 980
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
Addendum-Page 3
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 4
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
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TMS320F28027, TMS320F28026, TMS320F28023, TMS320F28022

SPRS523K NOVEMBER 2008 REVISED JUNE 2016

TMS320F2802x Piccolo Microcontrollers

SPRS523K NOVEMBER 2008 REVISED JUNE 2016 www.ti.com

Device Information (1)

2 Device Overview Copyright 20082016, Texas Instruments Incorporated

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1.4 Functional Block Diagram

COMP2OUT C28x TMS

16-Bit Peripheral Bus 32-Bit Peripheral Bus 32-Bit Peripheral Bus

SCI SPI I2C ePWM

Copyright 2016, Texas Instruments Incorporated

Figure 1-1. Functional Block Diagram

Copyright 20082016, Texas Instruments Incorporated Device Overview 3

SPRS523K NOVEMBER 2008 REVISED JUNE 2016 www.ti.com

4 Table of Contents Copyright 20082016, Texas Instruments Incorporated

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Global: Restructured document. .................................................................................................. 1

Copyright 20082016, Texas Instruments Incorporated Revision History 5

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Table 3-1. Device Comparison

6 Device Comparison Copyright 20082016, Texas Instruments Incorporated

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Table 3-1. Device Comparison (continued)

(3) The letter Q refers to Q100 qualification for automotive applications.

Copyright 20082016, Texas Instruments Incorporated Device Comparison 7

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3.1 Related Products

8 Device Comparison Copyright 20082016, Texas Instruments Incorporated

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4 Terminal Configuration and Functions

Figure 4-1. 2802x 48-Pin PT LQFP (Top View)

Copyright 20082016, Texas Instruments Incorporated Terminal Configuration and Functions 9

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Figure 4-2. 2802x 38-Pin DA TSSOP (Top View)

10 Terminal Configuration and Functions Copyright 20082016, Texas Instruments Incorporated

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4.2 Signal Descriptions

Table 4-1. Signal Descriptions (1)

Copyright 20082016, Texas Instruments Incorporated Terminal Configuration and Functions 11

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Table 4-1. Signal Descriptions(1) (continued)

12 Terminal Configuration and Functions Copyright 20082016, Texas Instruments Incorporated

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Table 4-1. Signal Descriptions(1) (continued)

SPRS523K NOVEMBER 2008 REVISED JUNE 2016 www.ti.com

Table 4-1. Signal Descriptions(1) (continued)

14 Terminal Configuration and Functions Copyright 20082016, Texas Instruments Incorporated

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Table 4-1. Signal Descriptions(1) (continued)

Copyright 20082016, Texas Instruments Incorporated Terminal Configuration and Functions 15

SPRS523K NOVEMBER 2008 REVISED JUNE 2016 www.ti.com

5.1 Absolute Maximum Ratings (1) (2)

5.2 ESD Ratings

16 Specifications Copyright 20082016, Texas Instruments Incorporated

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5.3 Recommended Operating Conditions