Lecture 9

Lecture 9
ARM Instruction Set

(& ARM Based Microcontrollers)
1
In this lecture
ARM Instruction Set

ARM Based Microcontrollers
2
Load-Store Instructions
Transfer data between memory and processor
registers
Three types :
Single-register transfer
Multiple-register transfer
Swap
3
Single Register Data Transfer
Used for moving a single data item
Several types:
LDR STR Word
LDRB STRB Byte
LDRH STRH Halfword
LDRSB Signed byte load
LDRSH Signed halfword load
Syntax:
LDR{<cond>}{<size>} Rd, <address>
STR{<cond>}{<size>} Rd, <address>
4
Single Register Data Transfercntd
Addressing Modes:
Preindexed with write back
E.g. LDR r0, [r1,#4]! (r0 [r1+4]) then r1 = r1+4)
Preindexed addressing
E.g. LDR r0, [r1,#4] (r0 [r1+4], r1 does not change)
Postindexed addressing
E.g. LDR r0, [r1], #4 (r0[r1] then r1 = r1 +4)
5
Multiple Register Data Transfer
Syntax:
<LDM|STM>{<cond>}<addressing_mode> Rb{!}, <register list>
Rb = Base register
Four addressing modes:

LDMIA / STMIA (Load multiple/ store multiple, increment after)
E.g. LDMIA r0, {r1-r3} (r1[r0], r2[r0+4], r3[r0+8])
LDMIB / STMIB increment before
E.g. LDMIB r0, {r1-r3} (r1[r0+4], r2[r0+8], r3[r0+12])
LDMDA / STMDA decrement after
E.g. LDMDA r0, {r1-r3} (r3[r0], r2[r0-4], r1[r0-8])
LDMDB / STMDB decrement before
E.g. LDMDB r0, {r1-r3} (r3[r0-4], r2[r0-8], r1[r0-12])
6
Software Interrupt Instruction(SWI)
31 28 27 24 23 0
Cond 1 1 1 1 SWI number (ignored by processor)
Condition Field
Causes a software interrupt exception
The SWI handler can examine the SWI number to decide
what operation has been requested
By using the SWI mechanism, an operating system can
implement a set of privileged operations which applications
running in user mode can request
Syntax:
SWI{<cond>} <SWI number>
7
Branch instructions
Branch : B{<cond>} label
Label is a 24 bit offset
The processor core shifts the offset field left by 2 positions, sign-
extends it and adds it to the PC (PCPC+(offset<<2))
This gives 32 Mbyte range
Branch with Link : BL{<cond>} subroutine_label
Similar to Branch, but overrides LR (link register) with a return address
It can be used to call subroutines. To return from the subroutine restore
the value of PC from LR
E.g. BL subroutine ; branch to subroutine, LRPC+4

subroutine:
<subroutine code>
MOV PC, LR ; restore PC (return)
8
Thumb
Thumb is a 16-bit instruction set
Optimized for code density from C code (~65% of ARM code size)
Improved performance from narrow memory
Subset of the functionality of the ARM instruction set
31 0
ADDS r2,r2,#1
32-bit ARM Instruction
For most instructions generated by compiler:
Conditional execution is not used
Source and destination registers identical
Constants are of limited size
Inline barrel shifter not used
15 0
ADD r2,#1
16-bit Thumb Instruction
9
ARM Based Microcontrollers
(LPC2148)
10
LPC2148
Based on ARM7TDMI-S
512KB on-chip flash memory (non-
volatile memory)
32KB on-chip SRAM
Several peripherals
Up to 60MHz CPU clock
Operating voltage range: 3.0V-3.6V
64 pins
11
LPC2148 Block Diagram
The microcontroller can be seen as an ARM based system
Peripherals
32KB 512KB
GPIO
SRAM FLASH
A/D Converters
D/A Converters
PWM ARM7 Local Bus
Capture/Compare
Real Time Clock
UART
APB
Interrupt
ARM7TDMI-S AHB Controller
SPI
I2 C
USB
12
LPC2148 Block Diagramcntd
Flash memory
Non-volatile
Used to store code and data
Can be programed using JTAG interface using In System Programming
(ISP), or by means of In Application Programming (IAP)
Minimum of 100,000 erase/write cycles
Static RAM
Volatile
Can be used to store code and data
Peripherals (Input/Outpt)
Each peripheral has registers used to communicate with the ARM core
13
Memory Mapping
The microcontroller has a 4GB address space (PC is 32 bits)
Peripheral registers are also addressed as memory locations
4GB AHB Peripherals 0xFFFFFFFF
0xF000000
APB Peripherals
3.5GB 0xE000000
0x40007FFF
32KB SRAM
0x40000000
1GB
0x0007FFFF
512kB Flash
0.0GB 0x00000000
14
Peripherals
Peripherals are controlled by writing into or reading from the
appropriate registers
Which registers to write to or to read from are given on the
device (LPC2148) datasheet /user manual
E.g. LPC2148 has two General Purpose I/O (GPIO) ports

(PORT0 and PORT1)
To configure a pin on PORT0 as an input or as an output, write

appropriate values to register IO0DIR (address of 0xE0028008)
To set (make logical 1) a pin on PORT0, set the appropriate bit on
register IO0SET (address 0xE0028004)
To read the value of a pin on PORT0, read appropriate bit on register
IO0PIN (address of 0xE0028000)
15
Hardware and Software Tools for Labs
LPC2148 Education Board

IAR for ARM
Proteus
16
More Readings
ARM System Developers Guide (chapters 3)
LPC214x User Manual
17

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Lecture 9

ARM Instruction Set

ARM Instruction Set

Four addressing modes:

Cond 1 1 1 1 SWI number (ignored by processor)

4GB AHB Peripherals 0xFFFFFFFF

E.g. LPC2148 has two General Purpose I/O (GPIO) ports

To configure a pin on PORT0 as an input or as an output, write

LPC2148 Education Board

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