Applied Electronics II: Chapter 1: Feedback Amplifiers

Applied Electronics II
Chapter 1: Feedback Amplifiers
School of Electrical and Computer Engineering

Addis Ababa Institute of Technology
Addis Ababa University
Daniel D./Abel G.
March 7,2016
Chapter 1: Feedback Amplifiers (AAIT) Chapter One March 7,2016 1 / 45

Overview
Overview
1 Overview
2 Types of Feedback
3 The General Feedback Structure
Basic Feedback Amplifier
4 Feedback Topologies
5 Properties of Negative Feedback
Gain Desensitivity
Noise/Interference Reduction
Reduction of Nonlinear Distortion
Control of Impedance level & Bandwidth Extension
6 Analysis of Feedback Amplifiers
Voltage-Series (Voltage Amplifier) Feedback
Method of Analysiis of Feedback Amplifiers
Current-Series (Transconductance Amplifier) Feedback
Current-Shunt (Current Amplifier) Feedback
Voltage-Shunt (Transresistance Amplifier) Feedback
7 Exercise
Types of Feedback
Type of Feeedback
Most physical systems incorporate some form of feedback. Feedback can

be broadly classified as:
1 Posittive Feedback
A portion of the output signal is added to the input. Positve feedback
is used in the design of oscillator and a number of other applications
(will be discussed in Chapter 4 and 5).
2 Negative Feedback
A portion of the output signal is subtracted from the input signal.The
basic idea of negative feedback is to trade off gain for other desirable
properties listed below
Desensitize the gain
Reduce nonlinear distortion
Reduce the effect of noise
Control the input and output resistances
Extend the bandwidth of the amplifier.

Types of Feedback
Negeative Feedback
Example
Introducing resistor at the emitter of BJT common-emitter circuits
stabilizes the Q-point against variation transistor parameters.
Solution Apply KCL at B-E loop
V+ VBB = IB RB + VBE (on) + IE RE + V

RC IC
Assuming active-mode of operation
IB + IE = (1 + )IB and IC = IB
VBB VCE
RB +
As IC increases(due to in T, ageing ), the
VBE - -
voltage drop across RE increase thus
RE IE opposing the base-emitter voltage.
V-
The General Feedback Structure

Figure 1 show the basic structure of a feedback amplifier, where each of
the quantities x can represent either a voltage or a current signal.
Figure: 1 General structure of the feedback amplifier, the quantities x represent

either voltage or current signals.
The relationship between the quantities x is
xo = Axi
xf = xo
xi = xs xf
Feedback Systems
Thus xo = A(xs xo )
The gain with feedback ,Af
xo A
Af = =
xs 1 + A
The open-loop gain, A represents the transfer gain of the basic amplifier
without feedback. Implicit in the description is that the source, the load,
and the feedback network do not load the basic amplifier. That is, the
gain A does not depend on any of these three networks.In practice this will
not be the case.
if |Af | < |A| the feed back is negative or degenerative
if |Af | > |A| the feed back is positive or regenerative
If, as is the case in many circuits, the loop gain A is large, A 1, then
it follows that
1
Af u

The General Feedback Structure Basic Feedback Amplifier

A basic representation of feedback amplifier is show in the Figure below
Ii I Io = IL
Comparato + Basic + +
Signal Sampling
r or Mixer Vi Amplifier, V Vo RL
Source - -
Network -
Network gain A
If
Feedback
Network b
Signal Source : This block is a voltage source Vs with a series resistor

Rs (Thvenins equivalent circuit) or a current source Is with a
parallel resistor Rs (Nortons equivalent circuit)
Feedback Network : Usually a passive two-port network with reverse
transmission
Sampling Network : Sampling blocks are shown below
Sampler Sampler
A RL A RL
b b
Figure: (a) Voltage or node sampling Figure: (b) Current or loop sampling
(a) Output voltage is sampled by connecting the feedback

network in shunt across the output.
(b) Output current is sampled by connecting the feedback
network in series with the output.

Comparator or Mixer Network : Two types a series (loop) and shunt

(node). A differential amplifier is often used as mixer.
Series Shunt
Source Source
Mixer Mixer
+ Ii
Rs Rs
Vi A Is A
Vs
-
If
+
Vf b b
-
Figure: (a) Series Mixing Figure: (b) Shunt Mixing

Basic Amplifier : A could be used to represent

V
Vi = AV , Voltage gain
I
Ii = AI , Current gain
I
Vi = GM , Transconductance
V
Ii = RM , Transresistance
They are gain of the basic amplifier without feedback

Feedback Topologies
Feedback Topologies
There are four basic feedback topologies, based on the parameters to be

amplified (voltage or current)and the output parameter (voltage or
current). They are described by the type of connection at the input and
output of the circuit.
(a) Voltage-Series (Series-Shunt) or Voltage Amplifier
(b) Current-Shunt (Shunt-Series) or Current Amplifier
(c) Current-Series (Series-Series) or Transconductance Amplifier
(d) Voltage-Shunt (Shunt-Shunt) or Transeresistance Amplifier

Feedback Topologies
Feedback Topologies
Figure: (a) Series-Shunt Figure: (c) Series-Series
Figure: (b) Shunt-Series Figure: (d) Shunt-Shunt

Properties of Negative Feedback Gain Desensitivity
Gain Desensitivity
Variation in the circuit gain as a result of change in transistor parameters
is reduced by negative feedback
From the previous slides the gain with feedback,Af is given as
xo A
Af = =
xs 1 + A
Assuming is constant and taking the derivative of Af with respect to A,
dAf 1 A 1 dA
= = or dAf =
dA 1 + A (1 + A)2 (1 + A)2 (1 + A)2
Dividing both sides the gain with feedback yields

dA
dAf (1+A)2 1 dA
= A
=
Af 1+A
1 + A A

Properties of Negative Feedback Gain Desensitivity
Gain Desensitivity
Hence the percentage change in Af (due to variations in some circuit

parameter) is smaller than the percentage change in A by a factor equal to
the amount of feedback. For this reason, the amount of feedback, 1 + A,
is also known as the desensitivity factor.
Example
The open-loop gain of an amplifier is A = 5 104 V /V exhibits a gain
change of 25% as the operating temperature changes. Calculate the
percentage change if the closed loop gain Af = 50V /V .
dAf 1 dA A dA Af dA 50
= = = = 25%
Af 1 + A A A(1 + A) A A A 5 104
dAf
= 0.025%
Af

Properties of Negative Feedback Noise/Interference Reduction
Noise/Interference Reduction
Under certain condition feedback amplifiers can be used to reduce
noise/interference.
This can be achieved if a preamplifer which is (relatively)
noise/interference-free precessed the noise/interference-prone
amplifier
Under such conditions the Signal-to-Noise ratio can be improved (
compare to noise/interference-prone amplifier without feedback) by
the factor of the preamplifier gain

Properties of Negative Feedback Reduction of Nonlinear Distortion
Reduction of Nonlinear Distortion
Distortion in the output is due to application of large amplitude input

signal applied beyond the linear region of operation.
Negative feedback can be implemented to reduce nonlinear distortion
by a factor of 1 + A.
Assuming that the open-loop gain A 1, the gain with feedback
A 1
Af = u
1 + A
It implies that Af is independent of the nonlinear properties of the
transistors used in the basic amplifier.
Since the feedback network usually consists of passive components,
which usually can be chosen to be as accurate as one wishes.

Properties of Negative Feedback Control of Impedance level & Bandwidth Extension
Control of Impedance level & Bandwidth Extension
Control of Impedance level: The input and output impedance can be

increased or decreased with the proper type of negative
feedback circuit.
Bandwidth Extension : The improvement in frequency response and
bandwidth extension (Chapter 3)
The advantage of negative feedback is at the cost of gain. Under certain
circumstance, a negative feedback amplifier may become unstable and
break into oscillation.

Analysis of Feedback Amplifiers
Fundamental Assumtions
Some fundamental assumptions are taken in order to analyze the four
feedback configurations.
Input is transmitted through the amplifier only, not through the
feedback.
The feedback signal transmitted feedback network only, not through
the amplifier.
is independent of the load and source impedance.
Ii Ro Io
+ +
+
Vs +
Vi Ri AvoVi Vo RL

- -
- Vf +
Rif Rof Rof
+ +
Vo Vo
-
Figure: Ideal structure of a Voltage-Series feedback amplifier

Analysis of Feedback Amplifiers Voltage-Series (Voltage Amplifier) Feedback

Avo represents the open circuit voltage gain taking Rs into account
Input Impedance: The input impedance with feedback is
Vs
Rif =
Ii
Also,
RL
Vs = Ii Ri + Vf = Ii Ri + Vo and Vo = Avo Vi
Ro + RL
let Av = Avo RoR+R

L
L
, where Av is the voltage gain without feedback taking
the RL into account then
Vs = Ii Ri + Av Vi = Ii Ri + Av Ii Ri
VS
Rif = = Ri (1 + Av )
Ii

Ro Ix
+
+
Vi Ri AvoVi + V
Vf x
+

Vo
Figure: Ideal structure of a Voltage-Series feedback amplifier
Output Impedance: To find Rof must remove the external signal (set
Vs = 0 or Is = 0), let RL = , impress a voltage Vx across the output
terminals and calculate the current Ix delivered by the test voltage Vx
Vx Avo Vi
Ix =
Ro
Since Vi = Vx
Vx Ro
Rof = =
Ix 1 + Avo

0
The output resistance with feedback Rof which includes RL as part of the
amplifier is Rof k RL
Ro RL
0 Rof RL Rof + RL
Rof = =
Rof + RL RL
1 + Avo
Ro + RL
0
Taking Ro = Ro k RL
0
0 Ro
Rof =
1 + Av
Voltage gain with feedback: Avf taking the load into account.
Ro + RL
Vs = Vi + Vo = Vo + Vo
Avo RL


Manipulating the equation
RL
Avo
Vo Ro + RL
Avf = =
Vs RL
1 + Avo
Ro + RL
The voltage gain with feedback without the load Avfo is
Vo Avo
Avfo = =
Vs 1 + Avo
In conclusion
Input Impedance: increased by a factor 1 + Av
output Impedance: decreased by a factor 1 + Av
Voltage Gain: decreased by a factor 1 + Av

In practical case
In practical case, feedback network will not be ideal VCVS.
Actually, it is resistive and will load the amplifier.
Source and load resistances will affect A, Ri , and Ro .
Source and load resistances should be lumped with basic amplifier.
Expressed as two-port network.
How To Solve
1. Identify the feedback network
2. Its loading effect at the input is obtained by short circuiting its port 2
(because it is connected in shunt with the output).
3. The loading effect at the output is obtained by open-circuiting port 1
of the feedback network (because it is connected in series with the
input)
4. The gain without feedback A is determined
5. The feed back gain is determined

Figure: Finding the A circuit and for the Voltage-Series feedback amplifier.

Analysis of Feedback Amplifiers Method of Analysiis of Feedback Amplifiers

Steps
1. Identify if the mixing or comparison is series or shunt
a) Series mixing : If the feedback signal subtracts from the externally
applied signal as a voltage
b) Shunt mixing : If the feedback signal subtracts from the applied
excitation signal as a current.
2. Identify the sampled signal as series or shunt
a) Voltage sampling : Set Vo = 0(RL = 0. If Xf becomes zero, we have
voltage sampling.
b) Current sampling : Set Io = 0(RL = . If Xf becomes zero, we have
current sampling.
3. The amplifier without feedback but taking the feedback network
loading into account
1) Find the input circuit.
a) Set Vo = 0 for voltage sampling.
b) Set Io = 0 for current sampling.


2) Find the output circuit.
a) Set Vi = 0 for shunt comparison so that no feedback current enters the
amplifier input.
b) Set Io = 0 for series comparison so that no feedback voltage reaches
the amplifier input.
4. Find the feedback network .
5. Calculate ,A,Ri and Ro .
6. Calculate the closed loop Af , Rif , Rof .


Example
Analyze the amplifier to obtain its voltage gain Vo /Vs , input resistance
Rin , and output resistance Rout . Find numerical values for case
gm1 = gm2 = 4mA/V , RD1 = RD2 = 10k and R2 = k. For simplicity,
neglect ro of each of Q1 and Q2 .
The next step is identifying the A and
circuit
RD2
RD1 We identify the feedback network as
Vo
Q2
the voltage divider of (R1 , R2 )
R2
Q1
Rout
+
Vs +
+ V
R2
Vf R1 o
Rin R1
-

Example (Continued)
The A circuit is Calculating A1 and A2
Vd1 = 0 id1 RD1

RD2
RD1
Vo
Vi = Vgs1 + id1 (R1 k R2 )
Vd1 Q2 R2 Vd1 id1 RD1
A1 = =
+ Q1 Vi Vgs1 + id1 (R1 k R2 )
R1 Rout
RD1
Vi A1 =
1/gm1 + (R1 k R2 )
- R1 R2
Ri gm1 RD1
A1 =
1 + gm1 (R1 k R2 )

Example (continued)
From A circuit we have
Vo = 0 id2 (RD2 k (R1 + R2 )) and Vgs2 = Vd1
Vo id2 (RD2 k (R1 + R2 ))

A2 = = = gm2 (RD2 k (R1 + R2 ))
Vd1 Vgs2
The open loop gain is
Vo gm1 gm2 RD1 [RD2 k (R1 + R2 )]

A= = A1 A2 =
Vi 1 + gm1 (R1 k R2 )
When evaluated
4 4 10[10 k (1 + 9)]
A= = 173.913 V /V
1 + 4(1 k 9)

Example (continued)
from circuit we have
R1 1
= = = 0.1 V /V
R1 + R2 1+9
The closed loop gain
Vo A 173.913
= Af = = = 9.45 V /V
Vs 1 + A 1 + 173.913 0.1
The input resistance is infinite because it is the input resistance of
MOSFET.
The output resistance is
Ro RD2 k (R1 + R2 ) 10 k (1 + 9)
Rout = Rf = = = = 271.87
1 + A 1 + A 1 + 173.913 0.1
Analysis of Feedback Amplifiers Current-Series (Transconductance Amplifier) Feedback

Ii Io
+ +
Vs + Vi Ri Ro
GmVi Vo RL
- -
- Vf +
Rif Rof Rof
+
Io Io
Input Impedance:
Vs Ro
Rif = ; Vs = Ii Ri + Io ; Io = Gm Vi
Ii Ro + RL
Ii Ri + Gm Ii Ri RoR+R
o
L
Ro
Rif = = Ri (1 + Gm )
Ii Ro + RL

Gm = Io /Vi is the short-circuit transconductance, and
GM = Gm Ro /(Ro + RL ) is the transconductance without feedback taking
the load into account.
Rif = Ri (1 + GM )
Output Impedance: calculated by short-circuiting the source and replacing
the source with a voltage source Vx with a current of Ix
Vx
Ix = Gm Vi and Vi = Ix
Ro
Vx Ro (Ix + Gm Ix )
=Rof = = Ro (1 + Gm )
Ix Ix
The output impedance taking the load as part of the amplifier is:
0 1 + Gm
Rof = (Rof k RL ) = (Ro k RL )
1 + GM

Figure: Finding the A circuit and for the Current-Series feedback amplifier.


Example
Calculate the closed loop voltage gain, output resistance and input resistance for
the circuit below. The output is taken from emitter current of Q3 . The values of
RC 1 = 9k, RC 2 = 5k, RC 3 = 600, RE 1 = 100, RE 3 = 100 and
RF = 640. Assume that the bias circuit, which is not shown, establishes
IC 1 = 0.6mA, IC 2 = 1mA, and IC 3 = 4mA. Also assume that for all three
transistors, hfe = 100 and ro = .
The circuit.
RC3
RF
RC2 Vo +
Vf RE1 RE3 Io
RC1 Q3
Q2
-
Io
Vf [(RF + RE 1 ) k RE 2 ]Io RFR+R
E1
E1
Q1 = =
+ Io Io
RF
Vs
RE 1 RE 2
- RE1 RE3 = = 11.9
RF + RE 1 + R E 2


Example (continued)
The A circuit. When A 1
1 1
RC3 Af u = = 84mA/V
11.9
RC2 Vo
Q3 lets check by determining each transistor
RC1
gain
Q2
Ro Vc1 ic (RC 1 k r2 )
A1 = =
Q1 Io Vi ie (re1 + [RE 1 k (RE 3 + RF )])
RF RF
Vi + (RC 1 k r2 )
A1 =
RE1 RE3 RE1 RE3 (re1 + [RE 1 k (RE 3 + RF )])
Ri Since Q1 is biased at 0.6mA ,re1 = 41.7.
Q2 is biased at 1mA; thus r2 = hfe /gm2
evaluating A1
A1 = 14.92V /V

Example (continued)
The gain of Q2
Vc2 ic [RC 2 k (hfe + 1)[re3 + (RE 3 k (RF + RE 1 ))]]

A2 = =
Vb2 Vb2
A2 = gm2 [RC 2 k (hfe + 1)[re3 + (RE 3 k (RF + RE 1 ))]]

re3 = 25/4 = 6.25 and substituting the other values
A2 = 131.2V /V
The gain of Q3
Io Ie3 1
A3 = = =
Vc2 Vb3 re3 + (RE 3 k (RF + RE 1 ))
when evaluated
A3 = 10.6mA/V

Example (continued)
The gain without feedback
A = A1 A2 A3 = 14.92 131.2 10.6 103 = 20.7A/V
The gain with feedback

A 20.7
Af = = = 83.7mA/V
1 + A 1 + 20.7 11.9
We can note that it is very close to approximate value. The input resistance
Rin = Rif = Ri (1 + A)
Ri = (hfe + 1)[re1 + (RE 1 k (RF + RE 2 ))] = 13.65k

Rif = 13.65(1 + 20.7 11.9) = 3.38M

Example (continued)
The output resistance
Rof = Ro = Ri (1 + A)
RC 2
Ro = [RE 3 k (RF + RE 1 )] + re3 +
hfe + 1
When evaluated Ro = 143.9
Rof = 143.9(1 + 20.7 11.9) = 35.6k

Analysis of Feedback Amplifiers Current-Shunt (Current Amplifier) Feedback
Ii Io
+ +
Is Vi Ri Ro Vo RL
AiIi
- -
Rof Rof
Rif
Io Io
Ai is the short-circuit current gain taking Rs into account

Input Resistance:
Ro
Is = Ii + Io ; Io = Ai Ii
RL + Ro
taking AI = Ai (Ro /(Ro + RL )), where AI is current gain without feedback
taking the load into account.

Vi Ri Ii Ri
Rif = = =
Is Ii + AI Ii 1 + AI
Output Resistance: making Is = 0 and replacing the load with a source
Vx
Ix = Ai Ii ; Ii = If = Io = Ix
Ro
Vx Vx
Ix = Ai Ix ; = Ix (1 + Ai )
Ro Ro
Vx
Rof = = Ro (1 + Ai )
Ix
The output resistance with load
0 1 + Ai
Rof = Rof k RL = (Ro k RL )
1 + AI


Figure: Finding the A circuit and for the Current-Shunt feedback amplifier.

Analysis of Feedback Amplifiers Voltage-Shunt (Transresistance Amplifier) Feedback

Ii Io
+ +
+ Ro
Is Vi Ri Vo RL
RmIi
- -
Rof Rof
Rif
Vo
Rm is the open-circuit transresistance gain taking Rs into account

Input Resistance:
RL
Is = Ii + Vo ; Vo = Rm Ii
RL + Ro
taking RM = Rm (RL /(Ro + RL )), where RM is transresistance gain
without feedback taking the load into account.

Vi Vi Ri
Rif = = =
Is Ii + RM Ii 1 + RM
Output Resistance: making Is = 0 and replacing the load with a source
Vx Rm Ii
Ix = ; Ii = If = Vo = Vx
Ro
Vx + Rm Vx Vx Ix
Ix = ; =
Ro Ro (1 + Rm )
Vx Ro
Rof = =
Ix 1 + Ai
The output resistance with load
0 Ro k RL
Rof = Rof k RL =
1 + RM


Figure: Finding the A circuit and for the Voltage-Shunt feedback amplifier.

Exercise
Exercise
The following questions in the text book are exercises to be done for the
tutorial session.
10.36
10.52
10.57
10.65

Chapter 2: Differential Amplifier

Daniel D./Abel G.
April 4, 2016
Chapter 2: Differential Amplifier (AAIT) Chapter Two April 4, 2016 1 / 29

Overview
1 Introduction
2 The MOS Differential Pair
Operation with a Common-Mode Input Voltage
Operation with a Differential Input Voltage
Large-Signal Operation
3 Small-Signal Operation of the MOS Differential Pair
Differential Gain
The Differential Half-Circuit
The Differential Amplifier with Current-Source Loads
Cascode Differential Amplifier
Common-Mode Gain and Common-Rejection ratio (CMRR)
Differential versus Single-Ended Output
Current Source, Biasing Techniques
4 Exercise

Introduction
Introduction
The purpose of a differential amplifier is to amplify the difference
between two signals.
The differential-pair of differential-amplifier configuration is widely
used in IC circuit design.
One example is input stage of op-amp.
Another example is emitter-coupled logic (ECL).
Technology was invented in 1940s for use in vacuum tubes the basic
differential-amplifier configuration was later implemented with
discrete bipolar transistors.
However, the configuration became most useful with invention of
modern transistor / MOS technologies.
V1 Differntial
Vo
Amplifier
V2

The MOS Differential Pair
The MOS Differential Pair

Two matched transistors (Q1 and Q2 ) joined and biased by a constant
current source I. MOSFETs should not enter triode region of operation.
Figure: The basic MOS differential-pair configuration.

The MOS Differential Pair Operation with a Common-Mode Input Voltage

Consider case when two gate terminals are joined together.
Connected to a common-mode voltage (VCM ).
vG 1 = vG 2 = VCM
Q1 and Q2 are matched.
Current I will divide equally between the two transistors.
ID1 = ID2 = I /2, VS = VCM VGS
where VGS is the gate-to-source voltage.


Neglecting channel-length modulation, VGS and I /2 are related by
I 1 0W
= kn (VGS Vt )2
2 2 L
in terms of the overdrive voltage VOV ,
s
I 1 0W 2 1 W
= kn VOV or VOV =
2 2 L kn0 L
The voltage at each drain will be

I
vD1 = vD2 = VDD RD
2
As long as Q1 and Q2 remain in the saturation region, the current I will
divide equally and the voltages at the drains will not change. Thus the
differential pair does not respond to (i.e., it rejects) common-mode input
signals.
An important specification of a differential amplifier is its input

common-mode range.This is the range of VCM over which the
differential pair operates properly.
The highest value of VCM is limited by the requirement that Q1 and Q2
remain in saturation, which means vDS VOV
I
max(VCM ) = Vt + VDD RD
2
The lowest value of VCM is determined by the need to allow for a sufficient
voltage across the current source I for it to operate properly. If a voltage
VCS is needed across the current source, then
min(VCM ) = VSS + VCS + Vt + VOV

The MOS Differential Pair Operation with a Differential Input Voltage

If vid is applied to Q1 and Q2 is grounded, following conditions apply:
vid = vGS1 vGS2 > 0
iD1 > iD2
if vid is positive, vGS1 will be greater than vGS2 and hence iD1 will be
greater than vD2 and the difference output voltage (vD2 vD1 ) will
be positive.


The differential pair responds to difference-mode or differential input
signals by providing a corresponding differential output signal between the
two drains.
To find the vid that causes the entire bias current I to flow in one of the
two transistors.
vGS1 reaches the value that corresponds to iD1 = I ,
vGS2 is reduced to a value equal to the threshold voltage Vt , at
which point vS = Vt .
The vGS1 can be found as

1 0 W
I =
kn (vGS1 Vt )2
2 L
q
vGS1 = Vt + 2I /kn0 (W /L) = Vt + 2VOV

The corresponding max(vid ) is
max(vid )= vGS1 + vS

max(vid )= Vt + 2VOV Vt = 2VOV
To steer the current completely
to one side of the pair, a difference input
voltage vid of at least 2VOV (4VT for bipolar) is needed.

The MOS Differential Pair Large-Signal Operation
Objective is to derive expressions for drain current iD1 and iD2 in terms of
differential signal vid = vG 1 vG 2 .
Assumption taken
Differential pair is perfectly matched
Channel-length Modulation is Neglected ( = 0)
The circuit maintains Q1 and Q2 in the saturation region of operation
at all times.
Load Independence
Step 1 Expression drain currents for Q1 and Q2 .
1 0W 1 0W
iD1 = kn (vGS1 Vt )2 and iD2 = kn (vGS2 Vt )2
2 L 2 L
Step 2 Take the square roots of both sides of both
r r
p 1 0W p 1 0W
iD1 = k (vGS1 Vt ) and iD2 = k (vGS2 Vt )
2 n L 2 n L
Step 3 (vGS1 vGS2 = vG 1 vG 2 = vid ) Subtract and perform appropriate
substitution . r
p p 1 0W
iD1 iD2 = k vid
2 n L
Step 4 Squaring both sides and substituting for iD1 + iD2 = I
p 1 0W
2 iD1 iD2 = I kn vid2
2 L
Step 5 Replacing iD2 = I iD1 , squaring
q both sides and solving the
0 W

quadratic and substituting VOV = I / kn L
s
vid /2 2

I I vid
iD1 = + 1
2 VOV 2 VOV
s
vid /2 2

I I vid
iD2 = 1
2 VOV 2 VOV
The Transfer characteristics are nonlinear due to the term involving vid2
Figure: Normalized plots of the currents in a MOSFET differential pair.

Since Linear amplification is desirable vid will be as small as possible. For
a given value of VOV , the only option is to keep vid /2 much smaller than
VOV .
The approximation is

I I vid I I vid
iD1 u + and iD2 u
2 VOV 2 2 VOV 2
Figure: The linear range of operation of the MOS differential pair can be
extended by operating the transistor at a higher value of VOV .
Small-Signal Operation of the MOS Differential Pair
Small-Signal Operation of the MOS Differential Pair
Figure: Small-signal analysis of MOS deferential amplifier.

Small-Signal Operation of the MOS Differential Pair Differential Gain
Differential Gain
From Figure (a) vG 1 = VCM + 12 vid and vG 2 = VCM 21 vid causes a
virtual signal ground to appear on the common-source (common-emitter)
connection
where VCM denotes a common-mode dc voltage
where vid denotes a differential input applied complementarily (or balanced)
Also note that each of Q1 and Q2 is biased at a dc current of I /2 and is
operating at an overdrive voltage VOV .
Assuming vid /2 VOV , the drain current will be

I vid I vid
id1 = and id2 =
VOV 2 VOV 2
The transconductance of MOSFET is
2ID 2(I /2) I
gm = = =
VOV VOV VOV
Combining the equations
v v
id id
id1 = gm and id2 = gm
2 2
Small-Signal Operation of the MOS Differential Pair Differential Gain
Differential Gain
The output can be taken between the drain and the ground,refereed as
single-ended outputs vo1 and vo2 .
v v
id id
vo1 = id1 RD = gm RD and vo2 = id2 RD = gm RD
2 2
The output can e taken between the two drain terminals, refereed as
differential output vod
vod = vo2 vo1 = gm vid RD
The differential gain

vod
= gm RD Av =
vid
When the output resistance of the MOSFET is taken into account
vod
Av = = gm [RD k ro ]
vid
Small-Signal Operation of the MOS Differential Pair The Differential Half-Circuit
The Differential Half-Circuit
The performance can be determined by considering only half the circuit

since the circuit is symmetrical and balanced. It is easier for analysis.
Q1 is biased at I /2 and is
operating at VOV .
This circuit may be used to
determine the differential
voltage gain of the differential
amplifier
Av = gm [RD k ro ]
Figure: Half-circuit of the differential amplifier.

Small-Signal Operation of the MOS Differential Pair The Differential Amplifier with Current-Source Loads
The Differential Amplifier with Current-Source Loads

To obtain higher gain, the passive resistances (RD ) can be replaced with current
sources. The current sources are realized with PMOS and biased to conduct I /2.
Av = gm1 [ro1 k ro3 ]

Small-Signal Operation of the MOS Differential Pair Cascode Differential Amplifier
Cascode Differential Amplifier

Gain can be increased via cascode configuration.
The differential Gain
Av = gm1 [Ron k Rop ]
where
Ron = [gm3 ro3 ]ro1
Rop = [gm5 ro5 ]ro7

Small-Signal Operation of the MOS Differential Pair Common-Mode Gain and Common-Rejection ratio (CMRR)
Common-Mode Gain and CMRR


In practice there is no ideal current source or symmetrical matching.
Non-ideal current source: Assuming the current source have a finite
output resistance RSS , and a small common-mode signal vicm is add on
VCM . In the ideal case the drain voltage will not change or the
common-mode gain is zero.
since RSS is very large we can assume Q1 and Q2 are operate at a bias current of
I/2.
i vicm
vicm = + 2iRSS and i=
gm 1/gm + 2RSS
The drain voltage
RD
vo1 = vo2 = RD i = vicm
1/gm + 2RSS
since 2RSS 1/gm
vo1 vo2 RD
= u
vicm vicm 2RSS

vo1 and vo2 are corrupted by vicm ,still common-mode signal is rejected
vod = vo2 vo1 = 0
Effect of RD Mismatch:Assume Q1 load is RD and Q2 load is
(RD + RD ). The drain voltage
RD RD + RD
vo1 u vicm and vo u vicm
2RSS 2RSS
Thus
RD
vod = vo2 vo1 = vicm
2RSS
The common-mode gain

vod RD RD RD
Acm = = =
vicm 2RSS 2RSS RD
Mismatch in the drain resistances causes the differential amplifier to
have a finite common-mode gain.

Common-mode rejection ratio (CMRR)
|Ad |
CMMR =
|Acm |
CMMR for drain resistance mismatch of RD

2gm RSS
CMMR =
RD /RD
For high CMMR RSS

Effect of gm Mismatch: Assume gm1 = gm + 21 gm , gm2 = gm 12 gm
from the figure on the next slide

1 1 gm2
i1 = i2 and i1 + i2 = i1 1 +
gm1 gm2 gm1



gm2
vicm = i1 /gm1 + (i1 + i2 )RSS = i1 /gm1 + i1 1 + RSS
gm1
rearranging to expressi1 and i2 in terms of vicm
gm1 vicm gm2 vicm
i1 = and i2 =
1 + (gm1 + gm2 )RSS 1 + (gm1 + gm2 )RSS
The differential output voltage vod = vo2 vo1 = i2 RD + i1 RD
(gm1 gm2 )RD gm RD
vod = vicm = vicm
1 + (gm1 + gm2 )RSS 1 + 2gm RSS
The common-mode gain

gm RD RD gm
Av = u
1 + 2gm RSS 2RSS gm
The corresponding CMMR
gm
CMMR = (2gm RSS )/( )
gm
Small-Signal Operation of the MOS Differential Pair Differential versus Single-Ended Output
Differential versus Single-Ended Output
Differential Output:
It decreases the common-mode gain and increases the common-mode
rejection ratio (CMRR) dramatically
It increases the differential gain by a factor of 2 (6 dB) because the
output is the difference between two voltages of equal magnitude and
opposite sign.
Single-Ended Output:
Needed to connect it to an off-chip load.
Advantage of Differential Amplifier:
The differential transmission of the signal on the chip also minimizes
its susceptibility to corruption with noise and interference.
Enables us to bias the amplifier and to couple amplifier stages
together without the need for bypass and coupling capacitors.

Small-Signal Operation of the MOS Differential Pair Current Source, Biasing Techniques
Current Source, Biasing Techniques

The current source is implemented using a current mirror. Q3 and Q4 is
the current mirror implementation.

Exercise
Exercise
The following questions in the text book are exercises to be done for the
tutorial session.
8.1
8.6
8.17
8.21
8.25
Reading Assignment
BJT Differential Amplifier

Chapter 3: Operational Amplifier

Part 1- Op Amp Basics

Daniel D./Abel G.
April 14, 2016
Chapter 3: Operational Amplifier Part 1- Op Amp Basics (AAIT)

Chapter Three April 14, 2016 1 / 45
Overview
1 Introduction
2 The Ideal Op Amp
The Op Amp Terminals
Function and Characteristics of the Ideal Op Amp
3 The Inverting Configuration
Closed-Loop Gain
Effect of Finite Open-Loop Gain
Input and Output Resistances
An Important Application - The Weighted Summer
4 The Noninverting Configuration
The Closed-Loop Gain
Application - The Voltage Follower
5 Difference Amplifiers
A Single-Op-Amp Difference Amplifier
The Instrumentation Amplifier
6 Integrators and Differentiators
Introduction
Introduction
The operational amplifier (Op amps) have been in use for a long
time, their initial applications being primarily in the areas of analog
computation and sophisticated instrumentation.
Early op amps were constructed from discrete components (vacuum
tubes and then transistors, and resistors).
The introduction of integrated circuit (IC) reduced the cost and
improved the performance.
One of the reasons for the popularity of the op amp is its versatility.
IC op amp has characteristics that closely approach the assumed ideal.

The Ideal Op Amp The Op Amp Terminals
The Op Amp Terminals

From a signal point of view the op amp has three terminals: two input
terminals (1 and 2) and one output terminal (3).
Most IC op amps require two dc power supplies, as shown in two
terminals, 4 and 5, are brought out of the op-amp package and connected
to a positive voltage VCC and a negative voltage VEE , respectively.
Some times other terminals can include terminals for frequency
compensation and terminals for offset nulling.

The Ideal Op Amp Function and Characteristics of the Ideal Op Amp
Op amp is designed to sense the difference between the voltage signals

applied at its two input terminals and multiply this by a number A.
v3 = A(v2 v1 )
Characteristics of the Ideal Op Amp

Infinite input impedance
Zero output impedance
Zero common-mode gain or, equivalently, infinite common-mode
rejection
Infinite open-loop gain A
Infinite bandwidth
Question: But, is an amplifier with infinite gain of any use?


An amplifiers input is composed of two components
differential input (vId ) - is difference between inputs at inverting and
non-inverting terminals
vId = v2 v1
common-mode input (vIcm ) - is input present at both terminals

1
vIcm = (v2 + v1 )
2
The input signals v1 and v2
v1 = vIcm vId /2 and v2 = vIcm + vId /2
Similarly, two components of gain exist

differential gain (A) - gain applied to differential input ONLY
common-mode gain (Acm ) - gain applied to common-mode input ONLY
Figure: Input signals in terms of

Figure: Equivalent circuit of the ideal op differential and common-mode
amp. components.

The Inverting Configuration
The Inverting Configuration

Op amps are not used alone; rather, the op amp is connected to passive
components in a feedback circuit.
There are two such basic circuit configurations employing an op amp and
two resistors: the inverting configuration and the noninverting
configuration
Figure: The inverting closed-loop configuration.

The Inverting Configuration Closed-Loop Gain
Closed-Loop Gain
Assuming an ideal op amp. How to analyze closed-loop gain for inverting
configuration of an ideal op-amp?
Step 1 Begin at the output terminal
Step 2 If vo is finite , then the voltage between the op-amp input terminals
should be negligibly small and ideally zero.
vo
v2 v1 = = 0 , because A is
A
A virtual short circuit between v1 and v2 .

A virtual ground exist at v1 .
Step 3 Define current in to inverting input (i1 ).
vI v1 vI 0 vI
i1 = = =
R1 R1 R1
Step 4 Determine where this current flows?
The Inverting Configuration Closed-Loop Gain
Closed-Loop Gain
It cannot go into the op amp, since infinite input impedance draws zero
current. i1 will have to flow through R2 to the low-impedance terminal 3.
Step 5 Define vo in terms of current flowing across R2 .
vI R2 R2
vo = v1 i1 R2 = 0 R2 = vI G =
R1 R1 R1

The Inverting Configuration Effect of Finite Open-Loop Gain

How does the gain expression change if open loop gain (A) is not assumed
to be infinite?
One must employ analysis similar to the previous.
The voltage at v1 becomes
vo vo
v2 v1 = v1 =
A A
The current i1 becomes
vI v1 vI + vAo
i1 = =
R1 R1
The output voltage vo becomes
R2
!
vo vI + vAo 1+ R1 R2
vo = v1 i1 R2 = R2 vo 1+ = v1
A R1 A R1

The Inverting Configuration Effect of Finite Open-Loop Gain

The Gain will be
vo R /R
GA< = = 2 1
vi 1 + R2 /R1
1+
A
Figure: Analysis of the inverting configuration taking into account the finite
open-loop gain of the op amp.

The Inverting Configuration Input and Output Resistances

The Input Resistance is
vi vi vi
=Ri = = = R1
ii (vi v1 )/R1 vi /R1
For a Voltage amplification Ri must be large. Then the gain would be
reduced, so such configuration suffers from low Ri . Consider the following
circuit and find the expression of the closed loop gain

The Inverting Configuration Input and Output Resistances
The closed loop gain

vo R2 R4 R4
= 1+ +
vi R1 R2 R3
It can be seen a higher Ri can be achieved without compromising the

closed loop gain.
Since the output of the inverting configuration is taken at the terminals of
the ideal voltage source A(v2 v1 ), it follows that the output resistance of
the closed-loop amplifier is zero.
Ro = 0

The Inverting Configuration An Important Application - The Weighted Summer
An Important Application - The Weighted Summer

Weighted Summer - is a closed-loop amplifier configuration which provides
an output voltage which is weighted sum of the inputs.

The Noninverting Configuration
The Noninverting Configuration

The input signal vI is applied directly to the positive input terminal of the
op amp while one terminal of R1 is connected to ground.
Then the polarity / phase of the output is same as input.
Figure: The noninverting configuration.

The Noninverting Configuration The Closed-Loop Gain
The Closed-Loop Gain
For an ideal case the closed-loop gain by using the previous methods.
vo R2
=1+
vi R1
Figure: The noninverting configuration.

The Noninverting Configuration Effect of Finite Open-Loop Gain

Assuming the op amp to be ideal except for having a finite open-loop gain
A. The closed-loop gain
vo 1 + R2 /R1
GA< = =
vi 1 + R2 /R1
1+
A
For
R2
A1+
R1
the closed-loop gain can be approximated by the ideal value.
The percentage error in G resulting from the finite op-amp gain A as
1 + R2 /R1
Percentage gain error =
A + 1 + (R2 /R1 )
The input impedance Ri of this closed-loop amplifier is ideally infinite,
since no current flows into the positive input terminal of the op amp. The
output is taken at the terminals of the ideal voltage source thus the output
impedance Ro of the noninverting configuration is zero.
The Noninverting Configuration Application - The Voltage Follower
The Voltage Follower

The property of high input impedance is a very desirable feature of
the noninverting configuration.
It enables using this circuit as a buffer amplifier to connect a source
with a high impedance to a low-impedance load. Buffer amplifier is
not required to provide any voltage gain
This circuit is commonly referred to as a voltage follower, since the
output follows the input.
Figure: a) The unity-gain buffer or follower amplifier. (b) Its equivalent circuit
model.
Difference Amplifiers
A difference amplifier is one that responds to the difference between the
two signals applied at its input and ideally rejects signals that are common
to the two inputs.
Ideally, the amp will amplify only the differential signal (vId ) and
reject completely the common-mode input signal (vIcm ). However, a
practical circuit will behave as below
vo = Ad vId + Acm vIcm
The efficacy of a differential amplifier is measured by the degree of its
rejection of common-mode signals in preference to differential signals.
|Ad |
CMRR = 20 log
Acm
Question: The op amp is itself a difference amplifier; why not just use an
op amp?
A difference amplifier is one that responds to the difference between the
two signals applied at its input and ideally rejects signals that are common
to the two inputs.
Ideally, the amp will amplify only the differential signal (vId ) and
reject completely the common-mode input signal (vIcm ). However, a
practical circuit will behave as below
vo = Ad vId + Acm vIcm
The efficacy of a differential amplifier is measured by the degree of its
rejection of common-mode signals in preference to differential signals.
|Ad |
CMRR = 20 log
Acm
Question: The op amp is itself a difference amplifier; why not just use an
op amp? very high (ideally infinite) gain of the op amp
Difference Amplifiers A Single-Op-Amp Difference Amplifier

Analyzing the difference amplifier below using superposition.

R2 R4 R2
vo1 = vI 1 vo2 = 1+ vI 2
R1 R3 + R4 R1
We have to make the two gain magnitudes equal in order to reject
common-mode signals.

R2 R4 R2
= 1+
R1 R3 + R4 R1
R2 /R1 R4 R4 /R3
= =
1 + R2 /R1 R3 + R4 1 + R4 /R3
The condition is obtained when
R2 R4
=
R1 R3
Assuming the condition is satisfied, the output voltage
R2
vo = (vI 2 vI 1 )
R1
In addition to rejecting common-mode signals, a difference amplifier is
usually required to have a high input resistance. Assuming R4 = R2 and
R3 = R1 and applying a differential input.
vId = R1 iI + 0 + R1 iI
Thus
vId
RId = = 2R1
iI
Note that if the amplifier is required to have a large differential gain (R2 /R1 ),
then R1 of necessity will be relatively small and the input resistance will be
correspondingly low, a drawback of this circuit.
Another drawback of the circuit is that it is not easy to vary the differential gain
of the amplifier.
Difference Amplifiers The Instrumentation Amplifier

The low-input-resistance problem can be solved by using voltage followers
to buffer the two input terminals. But why not get some voltage gain.
Solution: using a Noninverting Op Amp.


The output vo
R4 R2
vo = 1+ (vI 2 vI 1 )
R3 R1
The Advantages are
very high input resistance
high differential gain
symmetric gain (assuming that A1 and A2 are matched)
The Disadvantage
Ad and Acm are equal in first stage - meaning that the common-mode
and differential inputs are amplified with equal gain
need for matching - if two op amps which comprise stage 1 are not
perfectly matched, one will see unintended effects
The Solution is to disconnect the two resistors (R1 ) connected to node X
from ground and connecting them together.
For a differential input applied the gain would remain the same. For a common
mode input voltage vIcm an equal voltage appears at the negative input terminals
of A1 and A2 , causing the current through 2R1 to be zero. Thus vo1 and vo2 will
be equal to the input. Thus the first stage no longer amplifies vIcm .
Integrators and Differentiators The Inverting Integrator
The Inverting Integrator

By placing a capacitor in the feedback path and a resistor at the input, we obtain
the circuit of below. We shall now show that this circuit realizes the mathematical
operation of integration. Let the input be a time-varying function vI (t).
The transient description

Zt
1
vO (t) = vI (t)dt vO (t0 )
CR
0
The steady-state description
Vo (s) 1
=
Vi (s) sCR
Thus the integrator transfer function has magnitude of 1/CR and phase
= +90
This configuration also known as a Miller integrator has a disadvantage.
At = 0, the magnitude of the integrator transfer function is infinite.
This indicates that at dc the op amp is operating with an open loop.
Solution: By placing a very large resistor in parallel with the capacitor,
negative feedback is employed to make dc gain finite.

The integrator transfer function becomes

Vo (s) RF /R
=
Vi (s) 1 + sCRF
The lower the value we select for RF , the higher the corner frequency will be and
the more nonideal the integrator becomes. Thus selecting a value for RF presents
the designer with a trade-off between dc performance and signal performance.
Integrators and Differentiators The Op-Amp Differentiator
The Op-Amp Differentiator

Interchanging the location of the capacitor and the resistor of the integrator
circuit results in the circuit which performs the mathematical function of
differentiation.
The transient description

dvI (t)
vO (t) = CR
dt
Integrators and Differentiators The Op-Amp Differentiator
The Op-Amp Differentiator
The steady-state description
Vo (s)
= sCR
Vi (s)
Thus the integrator transfer function has magnitude of CR and phase

= 90
This configuration as a differentiator has a disadvantage.
Differentiator acts as noise amplifier, exhibiting large changes in
output from small (but fast) changes in input. As such, it is rarely
used in practice.
When the circuit is used, it is usually necessary to connect a small-valued
resistor in series with the capacitor. This modification, unfortunately, turns
the circuit into a nonideal differentiator.

DC Imperfections Offset Voltage
Offset Voltage
Now we consider some of the important nonideal properties of the op amp.
What happens If the two input terminals of the op amp are tied together and
connected to ground.
Ideally since vid = 0, we expect vO = 0
In practice a finite dc voltage exists at the output.

Offset Voltage
The causes of VOS is unavoidable mismatches in the differential stage of
the op amp. It is impossible to perfectly match all transistors.
General-purpose op amps exhibit VOS in the range of 1 mV to 5 mV. Also,
the value of VOS depends on temperature.
Analysis to determine the effect of the op-amp VOS on their performance is

the same for both inverting and the noninverting amplifier configurations.

R2
VO = VOS 1 +
R1
Offset Voltage
How to reduced Offset Voltage
offset nulling terminals A variable resistor (if properly set) may be used to reduce
the asymmetry present and, in turn, reduce offset.
capacitive coupling A series capacitor placed between the source and op amp may
be used to reduce offset, although it will also filter out dc signals.

DC Imperfections Input Bias and Offset Currents
Input Bias and Offset Currents

In order for the op amp to operate, its two input terminals have to be
supplied with dc currents, termed the input bias currents, IB .
IB1 + IB2
IB =
2
IOS = |IB1 IB2 |
input offset currents, IOS - the difference between bias current at both
terminals.
The resulting output voltage
VO = IB1 R2 u IB R2


To reduce the value of the output dc voltage due to the input bias currents,
logically it is R2 but higher R2 needed for gain.
The solution is introducing a resistance R3 in series with the noninverting input.
The output voltage when calculated

VO = IB2 R3 + R2 (IB1 IB2 R3 /R1 )
Assuming IB1 = IB2 = IB
VO = IB [R2 R3 (1 + R2 /R1 )]

Thus we can reduce VO to zero by selecting R3 such that
R2 R1 R2
R3 = =
1 + R2 /R1 R1 + R2
We conclude that to minimize the effect of the input bias currents, one
should place in the positive lead a resistance equal to the equivalent dc
resistance seen by the inverting terminal.
This is the case for op amps constructed using bipolar junction transistors
(BJTs). Those using MOSFETs in the first (input) stage do not draw an
appreciable input bias current; nevertheless, the input terminals should
have continuous dc paths to ground.
Frequency Response Frequency Dependence of the Open-Loop Gain
Frequency Dependence of the Open-Loop Gain

The differential open-loop gain A of an op amp is not infinite; rather, it is finite
and decreases with frequency.
It is high at dc, but falls off at a rather low frequency.
Internal compensation - is the presence of internal passive components
(caps) which cause op-amp to demonstrate STC low-pass response.
Frequency compensation - is the process of modifying the open-loop gain to
increase stability.
Figure: Open-loop gain of a general-purpose internally compensated op amp.

Frequency Response Frequency Dependence of the Open-Loop Gain
Frequency Dependence of the Open-Loop Gain
The gain of an internally compensated op-amp may be expressed as shown

below
A0
The transfer function in Laplace domain: A(s) =
1 + s/b
A0
The transfer function in Frequency domain: A() =
1 + /b
A0 b
The transfer function for high frequnecy: A()

A0 b t
Magnitude gain for high frequnecy: |A()| =

Unity gain occurs at t t = A0 b

Frequency Response Frequency Response of Closed-Loop Amplifiers
Frequency Response of Closed-Loop Amplifiers

The effect of limited op-amp gain and bandwidth on the closed-loop
transfer functions of the inverting configurations.
Step 1 Define closed-loop gain of an inverting amplifier with finite
open-loop gain (A)
Vo R2 /R1
=
Vi 1 + (1 + R2 /R1 )/A
Step 2 Insert frequency-dependent description of A
Vo R2 /R1 R2 /R1
= =
Vi 1 + R2 /R1 1 + 1+R2 /R1
+ s 1+R2 /R1
1+ A0 b A0
A0
1 + s/b
Step 3 Assume A0 1 + R2 /R1
Vo R2 /R1
=
Vi 1 + s(1+R
t
2 /R1 )

Frequency Response Frequency Response of Closed-Loop Amplifiers
By using the same methods the effect of limited op-amp gain and
bandwidth on the closed-loop transfer functions of the noninverting
configurations.
Vo 1 + R2 /R1
=
Vi 1 + s(1+R
t
2 /R1 )
3dB frequency - is the frequency at which the amplifier gain is attenuated

3dB from maximum (aka. dc value).
t
3dB =
1 + R2 /R1

Large-Signal Operation of Op Amps

The following are limitations on the performance of op-amp circuits when
large output signals are present.
1 Output Voltage Saturation
Op amps operate linearly over a limited range of output voltages. If
supply voltage +/- 15V is vO will saturate around +/- 13V.
2 Output Current Limits
Another limitation on the operation of op amps is that their output
current is limited to a specified maximum. If the circuit requires a larger
current, the op-amp output voltage will saturate at the level
corresponding to the maximum allowed output current.
3 Slew Rate
Slew Rate is the maximum rate of change possible at the output of a
real op amp.
dvo
SR = max
dt

If slew rate is less than rate of change of input it becomes problematic.
Slewing occurs because the bandwidth of the op-amp is limited, so the
output at very high frequencies is attenuated.


4 Full-Power Bandwidth
Op-amp slew-rate limiting can cause nonlinear distortion in sinusoidal
waveforms.
Assume a unity-gain follower with a sine-wave input
vI = Vi sin t
The rate of change
dvI
= Vi cos t
dt
Now if Vi exceeds the slew rate of the op amp, the output waveform
will be distorted in the manner shown.

Full-power bandwidth (fM ) is the frequency at which an output sinusoid

with amplitude equal to the rated output voltage of the op amp begins to
show distortion due to slew-rate limiting.
SR
SR = M VoMax fM =
2VoMax
Maximum output voltage (VoMax ) - is equal to (AvI ).

Output sinusoids of amplitudes smaller than VoMax will show slewrate
distortion at frequencies higher than fM
At a frequency higher than fM , the maximum amplitude of the
undistorted output sinusoid is

M
Vo = VoMax


Chapter 3: Operational Amplifier

Part 2- CMOS Op Amp

Daniel D./Abel G.
May 1, 2016
Chapter 3: Operational Amplifier Part 2- CMOS Op Amp (AAIT)

Chapter Three May 1, 2016 1 / 12
Overview I
1 Introduction
2 Categorization of CMOS Op Amps
3 The Two Stage CMOS Op Amp

The Circuit
Characteristics
The Folded-Cascode CMOS Op Amp
4 OPA313
Description
Features
Application

Introduction
Introduction
The CMOS op-amp circuits considered find application primarily in

the design of analog and mixed-signal VLSI circuits.
Because these op amps are usually designed with a specific
application in mind, they can be optimized to meet a subset of the
list of desired specifications, such as high dc gain, wide bandwidth, or
large output-signal swing.
Since many CMOS op amps are utilized with an IC, the load on their
outputs are usually small capacitances.
As a result, internal CMOS op amps do not need to have low output
resistances, and their design rarely incorporates an output stage.
Internal CMOS op amps do not need input clamping diodes for gate
protection and thus do not suffer from the leakage effects of such
diodes.

Categorization of CMOS Op Amps
Categorization of CMOS Op Amps

The Two Stage CMOS Op Amp
The Two Stage CMOS Op Amp

This simple but elegant circuit has become a classic and is used in a
variety of forms in the design of VLSI systems.

The Two Stage CMOS Op Amp The Circuit
The Circuit
The circuit consists of two gain stages
1 First Stage
Formed by the differential pair Q1 -Q2 together with its current mirror
load Q3 -Q4 .
Differential-amplifier circuit provides a voltage gain in the range of 20
V/V to 60 V/V.
Also provides a reasonable common-mode rejection ratio (CMRR).
The differential pair is biased by current source Q5 , which is a current
mirror output.
The current mirror is fed by a reference current IREF .
2 Second Stage
Consists of the common-source transistor Q6 and its current-source
load Q7 .
Provides a gain of 50 V/V to 80 V/V.
It takes part in the process of frequency compensating the op amp.
This is implemented using a compensation capacitance CC .

The Two Stage CMOS Op Amp Characteristics
Characteristics
The CMOS op-amp circuit can exhibit a systematic output dc offset
voltage. It can be eliminated by sizing the transistors.
(W /L)6 (W /L)7
=2
(W /L)4 (W /L)5
The common-mode range
VSS + VOV 3 + Vtn |Vtp | VICM VDD |Vtp | |VOV 1 | |VOV 5 |
The extent of output swing.
VSS + VOV 6 O VDD |VOV 7 |
The overall dc voltage gain.
A = A1 A2 = gm1 (ro2 k ro4 )gm6 (ro6 k ro7 )
The output resistance.
Ro = ro6 k ro7
The Two Stage CMOS Op Amp Characteristics
Characteristics
Since Op amps are used with negative feedback , stability is paramount.
To achieve stability the phase of the gain should not be near 180 degrees
when the magnitude gain is unity.
This is the purpose of the dominant capacitance CC .
Figure: Small-signal equivalent circuit for the op amp.
The Capacitances are C1 = Cgd2 + Cdb2 + Cgd4 + Cdb4 + Cgs6 and

C2 = Cdb6 + Cdb7 + Cgd7 + CL

OPA313 Description
Description
Manufacturer Texas Instruments

The OPA313 family of single-, dual-, and quad-channel op amps
represents a new generation of low-cost, general purpose, micro-power
operational amplifiers.
Rail-to-rail input and output swings
Low quiescent current (50A, typ)
A wide bandwidth of 1 MHz

very low noise (25nV / Hz at 1 kHz)
very attractive for a variety of battery-powered applications that
require a good balance between cost and performance.
The low input bias current supports those op amps to be used in
applications with megaohm source impedances.

OPA313 Features
Features
Wide Supply Range: 1.8V to 5.5V

Low Noise: 25nV / Hz at 1 kHz
Gain Bandwidth: 1MHz
Low Input Bias Current: 0.2pA
Low Offset Voltage: 0.5mV
Unity-Gain Stable
Internal RF/EMI Filter
Extended Temperature Range:400 to 1250

OPA313 Application
Application
Battery-Powered Instruments:
Consumer, Industrial, Medical
Notebooks, Portable Media Players
Sensor Signal Conditioning:
Loop-Powered
Notebooks, Portable Media Players
Wireless Sensors:
Home Security
Remote Sensing
Wireless Metering

Chapter 4: Wave shaping and Waveform Generators

Daniel D./Abel G.
May 25, 2016
Chapter 4: Wave shaping and Waveform Generators (AAIT)Chapter Three May 25, 2016 1 / 34
Overview
1 Introduction
2 Basic Principles of Sinusoidal Oscillators
The Oscillator Feedback Loop
The Oscillation Criterion
Nonlinear Amplitude Control
3 Op AmpRC Oscillator Circuits
The Wien-Bridge Oscillator
The Phase-Shift Oscillator
4 Multivibrators
Bistable Multivibrators
Application of the Bistable Circuit as a Comparator
Astable Multivibrator
Generation of Square Waveforms
Generation of Triangular Waveforms
Monostable Multivibrator
Generation of a Standardized Pulse
Introduction
Introduction
Standard waveforms for example, sinusoidal, square, triangular, or

pulse are required in computer, control systems, communication
systems, test and measurement systems.
A circuit that produces periodic wave forms at its output with out an
input is refereed as Oscillator.
Oscillator can be classified as
1 Linear Oscillators 2 Non-linear Oscillators

1 RC oscillators 1 Multivibrators
Wien Bridge bistable
Phase-Shift monostable
2 LC oscillators astable
Hartley
Colpitts
Crystal
Basic Principles of Sinusoidal Oscillators The Oscillator Feedback Loop

The basic structure of a sinusoidal oscillator consists of an amplifier and a
frequency-selective network connected in a positive-feedback loop.
Although no input signal will be present in an actual oscillator circuit,

we include an input signal here to help explain the principle of
operation.
The gain-with-feedback is given by
A(s)
Af (s) =
1 A(s)(s)
Basic Principles of Sinusoidal Oscillators The Oscillation Criterion
The loop gain of the circuit
L(s) = A(s)(s)
The characteristic equation thus becomes
1 L(s) = 0
If at a specific frequency f0 the loop gain A is equal to unity
L(0 ) = A(0 )(0 ) = 1
That is, at this frequency the circuit will provide sinusoidal oscillations
for zero input signal.
At f0 the phase of the loop gain should be zero and the magnitude of
the loop gain should be unity. This is known as the Barkhausen
criterion.
Basic Principles of Sinusoidal Oscillators Nonlinear Amplitude Control

The parameters of any physical system cannot be maintained
constant for any length of time.
As a result, even if A = 1 and = 0 is achieved then the
temperature changes and A becomes slightly less than
unity(oscillation will cease) or slightly grater(oscillations will grow in
amplitude).
It is evident a mechanism is needed to force A remain equal to unity
at the desired value of output amplitude.
A nonlinear circuit for gain control achieves the task and have the
following function.
First, to ensure that oscillations will start, designs the circuit such that
A is slightly greater than unity.
When the amplitude reaches the desired level, the nonlinear network
comes into action and causes the loop gain to be reduced to exactly
unity.
If, for some reason, the loop gain is reduced below unity, the nonlinear
network comes into action and causes the loop gain to be increase to
exactly unity.
The gain control can be implemented using a Limiter Circuit. The figure
below is a popular limiter circuit frequently employed for the control of
op-amp oscillators.
To understand how the circuit operates.

Lets consider first the case of a small (close to zero) input signal vI and a
small output voltage vO
vA is positive and vB is negative.
Both diodes D1 and D2 will be off.
All input current flows through the feed back resistor.
vO = (Rf /R1 )vI
This is the linear portion of the limiter transfer characteristic in the

previous figure.
Let us use superposition to find the voltages at nodes A and B.
R3 R2
vA = V + vO
R2 + R3 R2 + R3
R4 R5
vB = V + vO
R4 + R5 R4 + R5
As vI goes positive
vO goes negative
vB will become more negative, thus keeping D2 off.
vA becomes less positive.
If we continue to increase vI further.
A negative value of vO will be reached at which vA becomes -0.7 V or
so and diode D1 conducts.
Using the constant voltage-drop model for D1 and denote the voltage drop
VD . The value of vO at which D1 conducts is the negative limiting level
L .
R3 R3
L = V VD 1 +
R2 R2
vI can be found by dividing L by the limiter gain Rf /R1 .
If vI is increased beyond this value, more current is injected into D1 , and
vA remains at approximately VD .
Thus R3 appears in effect in parallel with Rf which is ((Rf k R3 )/R1 )
slope of the transfer function.
The transfer characteristic for negative vI can be found in a manner

identical to the previous.

R4 R4
L+ = V + VD 1 +
R5 R5
The slope of the transfer characteristic in the positive limiting region is
(Rf k R4 )/R1 .
Removing Rf altogether results in the transfer characteristic, which is that
of a comparator
That is, the circuit compares
vI with the comparator
reference value of 0 V : vI > 0
results in vo L , and vI < 0
yields vo L+ .
Op AmpRC Oscillator Circuits The Wien-Bridge Oscillator

A Wien-bridge oscillator without the nonlinear gain-control network.
The Loop Gain.

R2 Zp
L(s) = A(s)(s) = 1 +
R 1 Zp + Zs
Where
R 1 + sRC
Zp = Zs =
1 + sRC sC
Thus
1 + R2 /R1 1 + R2 /R1
L(s) = Zs
=
1 + Zp 3 + sCR + 1/sCR
1 + R2 /R1
L() =
3 + (CR 1/CR)
The phase of the loop gain will be zero at frequency
0 = 0 CR 1/0 CR
That is 0 = 1/CR
To obtain sustained oscillations at this frequency, one should set the
magnitude of the loop gain to unity. This can be achieved by selecting
R2 /R1 = 2
To ensure that oscillations will start, one chooses R2 /R1 slightly greater
than 2
Figure: A Wien-bridge oscillator with a limiter used for amplitude control.

Op AmpRC Oscillator Circuits The Phase-Shift Oscillator

The basic structure of the phase-shift oscillator consists of a negative gain
amplifier (K) with a three-section (third-order) RC ladder network in the feedback.
Figure: A phase-shift oscillator.
The circuit will oscillate at the frequency for which the phase shift of the RC
network is .
For oscillations to be sustained, the value of K = mag [1/(RCnetwork)] at
the oscillation frequency.
Figure: practical phase-shift oscillator with a limiter for amplitude stabilization.

Diodes D1 and D2 and resistors R1 , R2 , R3 , and R4 for amplitude
stabilization.
To start oscillations, Rf has to be made slightly greater than the minimum
required value
Multivibrators Bistable Multivibrators
Bistable Multivibrators are circuits that has two stable state and move between
states when appropriately triggered.
Figure: A positive-feedback loop capable of bistable operation.
Assume that the electrical noise causes a small positive increment in the voltage
v+ .
The incremental signal will be amplified by A.
Much greater signal will appear at the output voltage vO .
The voltage divider will feed a fraction of the output signal back to
the positive-input terminal of the op amp.
If A > 1, as is usually the case, the fed-back signal will be greater
than the original increment in v+ .
This regenerative process continues until op amp saturates at the
positive-saturation output level, L+ .
When this happens, v+ becomes L+ R1 /(R1 + R2 ).
This is one of the two stable states of the circuit.
Had we assumed the equally probable situation of a negative increment.
The op amp would saturate in the negative direction.
vO = L and v+ = L R1 /(R1 + R2 )
This is the other stable state.
Also note that the circuit cannot exist in the state for which v+ = 0 and
vO = 0 for any length of time. This is a state of unstable equilibrium(also
known as a metastable state).
Transfer Characteristics of the Bistable Circuit
To derive the transfer characteristics.

Assume vO is at L+ level.
v+ = L+ .
vI is increased from 0 V. nothing happens until it reaches L+ = VTH
When vI > L+ then vO goes negative.
The regenerative process takes place until vO = L and v+ = L .
Increasing vI further has no effect.
Next consider what happens as vI is decreased.
Since now v+ = L , the circuit remains in the negative-saturation
state until vI = L .
As vI < L goes below this value the regenerative action takes place
vO = L and v+ = L
Bistable Circuit as a Comparator

The comparator is used for detecting the level of an input signal relative to a
preset threshold value.
This is noninverting configuration.

by using superposition.
R2 R1
v+ = vI + vO
R2 + R 1 R2 + R 1
Assuming the output voltage at vO = L+ .

To make a state change vO = L+ , v+ = 0, vI = VTL .
VTL = L+ (R1 /R2 )
To change from negative state to positive.
VTH = L (R1 /R2 )
The difference between VTL . and VTH is the Hysteresis.
By using limiter circuits to make the output more precise.
R should be chosen to yield the current required for the proper

operation of the zener diodes.
L+ = VZ1 + VD
L = (VZ2 + VD )
thus VTH = L (R1 /R2 ) = (VZ2 + VD )(R1 /R2 )
thus VTL = L+ (R1 /R2 ) = (VZ1 + VD )(R1 /R2 )
Assuming the zener diodes are identical The hysteresis will be
2(VZ + VD )(R1 /R2 )
Multivibrators Astable Multivibrator

A square waveform can be generated by arranging for a bistable multivibrator to
switch states periodically. This can be done by connecting the bistable
multivibrator with an RC circuit in a feedback loop
How the circuit operates

1 let the output of the bistable multivibrator be L+ .
2 The voltage at the positive input terminal will be v+ = L+ .
3 The voltage across C,v , will rise exponentially toward L+ with a
time constant = CR.
4 This will continue until v = VTH = L+ .
5 Any further the input seen by the op amp will be negative then
vO = L+ .
6 As a result, v+ = L .
7 The capacitor will then start discharging, and its voltage, v , will
decrease exponentially toward L .
8 This new state will prevail until v reaches the negative threshold
VTL = L .
9 Then the bistable multivibrator switches to the positive-output state.
Expression
A capacitor C that is charging or discharging through a resistance R
toward a final voltage V has a voltage v (t)
v (t) = V (V V0+ )e t/
where V0+ is the voltage at t = 0+ and = CR is the time constant.
The period T of the square wave can be found as follows.

During the charging interval T1 the voltage v ,
v = L+ (L+ L )e t/
where = CR Substituting v = L+ at t = T1 gives
1 (L /L+ )
T1 = ln
1
Similarly, during the discharge interval T2
1 (L+ /L )
T2 = ln
1
The period T = T1 + T2 where L+ = L
1+
T = 2 ln
1
Square-wave generator can be made to have variable frequency by

switching different capacitors C and by continuously adjusting R.
Also, the waveform across C can be made almost triangular by using
a small value for the parameter .
However, triangular waveforms of superior linearity can be easily
generated using the scheme discussed next.

The exponential waveforms generated in the astable circuit can be changed to
triangular by replacing the low-pass RC circuit with an integrator.
The integrator causes linear charging and discharging of the capacitor,

thus providing a triangular waveform.
How the circuit operates.
1 Let the output of the bistable circuit be at L+ .
2 A current equal L+ /R to will flow into the resistor R and through
capacitor C .
3 Causes the output of the integrator to linearly decrease with a slope
of L+ /CR.
4 This will continue until the integrator output reaches the lower
threshold VTL of the bistable circuit.
5 The output becomes negative and equal to L .
6 The current through R and C will reverse direction, and its value will
become equal to |L |/R.
7 The integrator output will start to increase linearly with a positive
slope equal to |L |/CR.
8 This will continue until the integrator output voltage reaches VTH .
The period T of the square and triangular waveforms

During the interval T1 .
VTH VTL L+
=
T1 CR
from which we obtain
VTH VTL
T1 = CR
L+
VTH VTL L
=
T2 CR
VTH VTL
T2 = CR
L
Thus to obtain symmetrical square waves we design the bistable circuit to have
L+ = L .
Multivibrators Monostable Multivibrator

In some applications the need arises for a pulse of known height and width
generated in response to a trigger signal. Such a standardized pulse can be
generated by the monostable multivibrator.
The circuit is an augmented form of the astable circuit.

A clamping diode D1 is added across the capacitor C1 .
Trigger circuit composed of capacitor C2 , resistor R4 , and diode D2 is
connected to the noninverting input terminal of the op amp.
1 In the stable state, which prevails in the absence of the triggering
signal, the output of the op amp is at L+ .
2 D1 is conducting through R3 and thus clamping the voltage vB to one
diode drop above ground.
3 R4 R1 , so that diode D2 will be conducting a very small current
and the voltage vc (R1 /(R1 + R2 ))L+ .
4 The stable state is maintained because L+ is greater than VD1 .
5 Now consider the application of a negative-going step at the trigger
input.
6 D2 conducts heavily and pulls node C down.
7 If the trigger signal is of sufficient height to cause vC to go below vB ,
the op amp will see a net negative input voltage and its output will
switch to L .
8 This in turn will cause vC to go negative to L .

9 D2 will then cut off, thus isolating the circuit from any further
changes at the trigger input terminal.
10 The negative voltage at A causes D1 to cut off, and C1 begins to
discharge exponentially toward L .
11 The monostable multivibrator is now in its quasi-stable state.
12 When vB goes below the voltage at node C , op-amp output switches
back to L+ and the voltage at node C goes back to L+ .
13 Capacitor C1 then charges toward L+ until diode D1 turns on and the
circuit returns to its stable state.
The duration T of the output pulse is determined from the exponential
waveform of vB ,
vB = L (L VD1 )e t/C1 R3
by substituting vB (T ) = L ,
L = L (L VD1 )e T /C1 R3
Rearranging
VD1 L
T = C1 R3 ln
L L
For VD1 |L |, this equation can be approximated by

1
T C1 R3 ln
1
Chapter 4: Wave shaping and Waveform Generators

Daniel D./Abel G.
May 25, 2016
Overview
1 Introduction
2 Basic Principles of Sinusoidal Oscillators
The Oscillation Criterion
3 Op AmpRC Oscillator Circuits
4 Multivibrators
Application of the Bistable Circuit as a Comparator
Astable Multivibrator
Monostable Multivibrator
Introduction
Introduction
Standard waveforms for example, sinusoidal, square, triangular, or

pulse are required in computer, control systems, communication
systems, test and measurement systems.
A circuit that produces periodic wave forms at its output with out an
input is refereed as Oscillator.
Oscillator can be classified as
1 Linear Oscillators 2 Non-linear Oscillators

1 RC oscillators 1 Multivibrators
Wien Bridge bistable
Phase-Shift monostable
2 LC oscillators astable
Hartley
Colpitts
Crystal
Basic Principles of Sinusoidal Oscillators The Oscillator Feedback Loop

The basic structure of a sinusoidal oscillator consists of an amplifier and a
frequency-selective network connected in a positive-feedback loop.
Although no input signal will be present in an actual oscillator circuit,

we include an input signal here to help explain the principle of
operation.
The gain-with-feedback is given by
A(s)
Af (s) =
1 A(s)(s)
Basic Principles of Sinusoidal Oscillators The Oscillation Criterion
The loop gain of the circuit
L(s) = A(s)(s)
The characteristic equation thus becomes
1 L(s) = 0
If at a specific frequency f0 the loop gain A is equal to unity
L(0 ) = A(0 )(0 ) = 1
That is, at this frequency the circuit will provide sinusoidal oscillations
for zero input signal.
At f0 the phase of the loop gain should be zero and the magnitude of
the loop gain should be unity. This is known as the Barkhausen
criterion.

The parameters of any physical system cannot be maintained
constant for any length of time.
As a result, even if A = 1 and = 0 is achieved then the
temperature changes and A becomes slightly less than
unity(oscillation will cease) or slightly grater(oscillations will grow in
amplitude).
It is evident a mechanism is needed to force A remain equal to unity
at the desired value of output amplitude.
A nonlinear circuit for gain control achieves the task and have the
following function.
First, to ensure that oscillations will start, designs the circuit such that
A is slightly greater than unity.
When the amplitude reaches the desired level, the nonlinear network
comes into action and causes the loop gain to be reduced to exactly
unity.
If, for some reason, the loop gain is reduced below unity, the nonlinear
network comes into action and causes the loop gain to be increase to
exactly unity.
The gain control can be implemented using a Limiter Circuit. The figure
below is a popular limiter circuit frequently employed for the control of
op-amp oscillators.
To understand how the circuit operates.

Lets consider first the case of a small (close to zero) input signal vI and a
small output voltage vO
vA is positive and vB is negative.
Both diodes D1 and D2 will be off.
All input current flows through the feed back resistor.
vO = (Rf /R1 )vI
This is the linear portion of the limiter transfer characteristic in the

previous figure.
Let us use superposition to find the voltages at nodes A and B.
R3 R2
vA = V + vO
R2 + R3 R2 + R3
R4 R5
vB = V + vO
R4 + R5 R4 + R5
As vI goes positive
vO goes negative
vB will become more negative, thus keeping D2 off.
vA becomes less positive.
If we continue to increase vI further.
A negative value of vO will be reached at which vA becomes -0.7 V or
so and diode D1 conducts.
Using the constant voltage-drop model for D1 and denote the voltage drop
VD . The value of vO at which D1 conducts is the negative limiting level
L .
R3 R3
L = V VD 1 +
R2 R2
vI can be found by dividing L by the limiter gain Rf /R1 .
If vI is increased beyond this value, more current is injected into D1 , and
vA remains at approximately VD .
Thus R3 appears in effect in parallel with Rf which is ((Rf k R3 )/R1 )
slope of the transfer function.
The transfer characteristic for negative vI can be found in a manner

identical to the previous.

R4 R4
L+ = V + VD 1 +
R5 R5
The slope of the transfer characteristic in the positive limiting region is
(Rf k R4 )/R1 .
Removing Rf altogether results in the transfer characteristic, which is that
of a comparator
That is, the circuit compares
vI with the comparator
reference value of 0 V : vI > 0
results in vo L , and vI < 0
yields vo L+ .

A Wien-bridge oscillator without the nonlinear gain-control network.
The Loop Gain.

R2 Zp
L(s) = A(s)(s) = 1 +
R 1 Zp + Zs
Where
R 1 + sRC
Zp = Zs =
1 + sRC sC
Thus
1 + R2 /R1 1 + R2 /R1
L(s) = Zs
=
1 + Zp 3 + sCR + 1/sCR
1 + R2 /R1
L() =
3 + (CR 1/CR)
The phase of the loop gain will be zero at frequency
0 = 0 CR 1/0 CR
That is 0 = 1/CR
To obtain sustained oscillations at this frequency, one should set the
magnitude of the loop gain to unity. This can be achieved by selecting
R2 /R1 = 2
To ensure that oscillations will start, one chooses R2 /R1 slightly greater
than 2
Figure: A Wien-bridge oscillator with a limiter used for amplitude control.


The basic structure of the phase-shift oscillator consists of a negative gain
amplifier (K) with a three-section (third-order) RC ladder network in the feedback.
Figure: A phase-shift oscillator.
The circuit will oscillate at the frequency for which the phase shift of the RC
network is .
For oscillations to be sustained, the value of K = mag [1/(RCnetwork)] at
the oscillation frequency.
Figure: practical phase-shift oscillator with a limiter for amplitude stabilization.

Diodes D1 and D2 and resistors R1 , R2 , R3 , and R4 for amplitude
stabilization.
To start oscillations, Rf has to be made slightly greater than the minimum
required value
Bistable Multivibrators are circuits that has two stable state and move between
states when appropriately triggered.
Figure: A positive-feedback loop capable of bistable operation.
Assume that the electrical noise causes a small positive increment in the voltage
v+ .
The incremental signal will be amplified by A.
Much greater signal will appear at the output voltage vO .
The voltage divider will feed a fraction of the output signal back to
the positive-input terminal of the op amp.
If A > 1, as is usually the case, the fed-back signal will be greater
than the original increment in v+ .
This regenerative process continues until op amp saturates at the
positive-saturation output level, L+ .
When this happens, v+ becomes L+ R1 /(R1 + R2 ).
This is one of the two stable states of the circuit.
Had we assumed the equally probable situation of a negative increment.
The op amp would saturate in the negative direction.
vO = L and v+ = L R1 /(R1 + R2 )
This is the other stable state.
Also note that the circuit cannot exist in the state for which v+ = 0 and
vO = 0 for any length of time. This is a state of unstable equilibrium(also
known as a metastable state).
Transfer Characteristics of the Bistable Circuit
To derive the transfer characteristics.

Assume vO is at L+ level.
v+ = L+ .
vI is increased from 0 V. nothing happens until it reaches L+ = VTH
When vI > L+ then vO goes negative.
The regenerative process takes place until vO = L and v+ = L .
Increasing vI further has no effect.
Next consider what happens as vI is decreased.
Since now v+ = L , the circuit remains in the negative-saturation
state until vI = L .
As vI < L goes below this value the regenerative action takes place
vO = L and v+ = L
Bistable Circuit as a Comparator

The comparator is used for detecting the level of an input signal relative to a
preset threshold value.
This is noninverting configuration.

by using superposition.
R2 R1
v+ = vI + vO
R2 + R 1 R2 + R 1
Assuming the output voltage at vO = L+ .

To make a state change vO = L+ , v+ = 0, vI = VTL .
VTL = L+ (R1 /R2 )
To change from negative state to positive.
VTH = L (R1 /R2 )
The difference between VTL . and VTH is the Hysteresis.
By using limiter circuits to make the output more precise.
R should be chosen to yield the current required for the proper

operation of the zener diodes.
L+ = VZ1 + VD
L = (VZ2 + VD )
thus VTH = L (R1 /R2 ) = (VZ2 + VD )(R1 /R2 )
thus VTL = L+ (R1 /R2 ) = (VZ1 + VD )(R1 /R2 )
Assuming the zener diodes are identical The hysteresis will be
2(VZ + VD )(R1 /R2 )

A square waveform can be generated by arranging for a bistable multivibrator to
switch states periodically. This can be done by connecting the bistable
multivibrator with an RC circuit in a feedback loop
How the circuit operates

1 let the output of the bistable multivibrator be L+ .
2 The voltage at the positive input terminal will be v+ = L+ .
3 The voltage across C,v , will rise exponentially toward L+ with a
time constant = CR.
4 This will continue until v = VTH = L+ .
5 Any further the input seen by the op amp will be negative then
vO = L+ .
6 As a result, v+ = L .
7 The capacitor will then start discharging, and its voltage, v , will
decrease exponentially toward L .
8 This new state will prevail until v reaches the negative threshold
VTL = L .
9 Then the bistable multivibrator switches to the positive-output state.
Expression
A capacitor C that is charging or discharging through a resistance R
toward a final voltage V has a voltage v (t)
v (t) = V (V V0+ )e t/
where V0+ is the voltage at t = 0+ and = CR is the time constant.
The period T of the square wave can be found as follows.

During the charging interval T1 the voltage v ,
v = L+ (L+ L )e t/
where = CR Substituting v = L+ at t = T1 gives
1 (L /L+ )
T1 = ln
1
Similarly, during the discharge interval T2
1 (L+ /L )
T2 = ln
1
The period T = T1 + T2 where L+ = L
1+
T = 2 ln
1
Square-wave generator can be made to have variable frequency by

switching different capacitors C and by continuously adjusting R.
Also, the waveform across C can be made almost triangular by using
a small value for the parameter .
However, triangular waveforms of superior linearity can be easily
generated using the scheme discussed next.

The exponential waveforms generated in the astable circuit can be changed to
triangular by replacing the low-pass RC circuit with an integrator.
The integrator causes linear charging and discharging of the capacitor,

thus providing a triangular waveform.
1 Let the output of the bistable circuit be at L+ .
2 A current equal L+ /R to will flow into the resistor R and through
capacitor C .
3 Causes the output of the integrator to linearly decrease with a slope
of L+ /CR.
4 This will continue until the integrator output reaches the lower
threshold VTL of the bistable circuit.
5 The output becomes negative and equal to L .
6 The current through R and C will reverse direction, and its value will
become equal to |L |/R.
7 The integrator output will start to increase linearly with a positive
slope equal to |L |/CR.
8 This will continue until the integrator output voltage reaches VTH .
The period T of the square and triangular waveforms

VTH VTL L+
=
T1 CR
VTH VTL
T1 = CR
L+
VTH VTL L
=
T2 CR
VTH VTL
T2 = CR
L
Thus to obtain symmetrical square waves we design the bistable circuit to have
L+ = L .

In some applications the need arises for a pulse of known height and width
generated in response to a trigger signal. Such a standardized pulse can be
generated by the monostable multivibrator.
The circuit is an augmented form of the astable circuit.

A clamping diode D1 is added across the capacitor C1 .
Trigger circuit composed of capacitor C2 , resistor R4 , and diode D2 is
connected to the noninverting input terminal of the op amp.
1 In the stable state, which prevails in the absence of the triggering
signal, the output of the op amp is at L+ .
2 D1 is conducting through R3 and thus clamping the voltage vB to one
diode drop above ground.
3 R4 R1 , so that diode D2 will be conducting a very small current
and the voltage vc (R1 /(R1 + R2 ))L+ .
4 The stable state is maintained because L+ is greater than VD1 .
5 Now consider the application of a negative-going step at the trigger
input.
6 D2 conducts heavily and pulls node C down.
7 If the trigger signal is of sufficient height to cause vC to go below vB ,
the op amp will see a net negative input voltage and its output will
switch to L .
8 This in turn will cause vC to go negative to L .

9 D2 will then cut off, thus isolating the circuit from any further
changes at the trigger input terminal.
10 The negative voltage at A causes D1 to cut off, and C1 begins to
discharge exponentially toward L .
11 The monostable multivibrator is now in its quasi-stable state.
12 When vB goes below the voltage at node C , op-amp output switches
back to L+ and the voltage at node C goes back to L+ .
13 Capacitor C1 then charges toward L+ until diode D1 turns on and the
circuit returns to its stable state.
The duration T of the output pulse is determined from the exponential
waveform of vB ,
vB = L (L VD1 )e t/C1 R3
by substituting vB (T ) = L ,
L = L (L VD1 )e T /C1 R3
Rearranging
VD1 L
T = C1 R3 ln
L L
For VD1 |L |, this equation can be approximated by

1
T C1 R3 ln
1

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Applied Electronics II

Chapter 1: Feedback Amplifiers

School of Electrical and Computer Engineering

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Most physical systems incorporate some form of feedback. Feedback can

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V+ VBB = IB RB + VBE (on) + IE RE + V

The General Feedback Structure

Figure: 1 General structure of the feedback amplifier, the quantities x represent

Basic Feedback Amplifier

Signal Source : This block is a voltage source Vs with a series resistor

Basic Feedback Amplifier

Sampling Network : Sampling blocks are shown below

(a) Output voltage is sampled by connecting the feedback

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Basic Feedback Amplifier

Comparator or Mixer Network : Two types a series (loop) and shunt

Figure: (a) Series Mixing Figure: (b) Shunt Mixing

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Basic Feedback Amplifier

Basic Amplifier : A could be used to represent

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There are four basic feedback topologies, based on the parameters to be

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Figure: (a) Series-Shunt Figure: (c) Series-Series

Figure: (b) Shunt-Series Figure: (d) Shunt-Shunt

Dividing both sides the gain with feedback yields

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Hence the percentage change in Af (due to variations in some circuit

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Reduction of Nonlinear Distortion

Distortion in the output is due to application of large amplitude input

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Control of Impedance level & Bandwidth Extension

Control of Impedance level: The input and output impedance can be

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Figure: Ideal structure of a Voltage-Series feedback amplifier

Voltage-Series (Voltage Amplifier) Feedback

let Av = Avo RoR+R

Voltage-Series (Voltage Amplifier) Feedback

Voltage-Series (Voltage Amplifier) Feedback

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Voltage-Series (Voltage Amplifier) Feedback

Voltage-Series (Voltage Amplifier) Feedback

Voltage-Series (Voltage Amplifier) Feedback

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Method of Analysiis of Feedback Amplifiers

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Method of Analysiis of Feedback Amplifiers

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Voltage-Series (Voltage Amplifier) Feedback

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Voltage-Series (Voltage Amplifier) Feedback

Vd1 = 0 id1 RD1

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Voltage-Series (Voltage Amplifier) Feedback

Vo = 0 id2 (RD2 k (R1 + R2 )) and Vgs2 = Vd1