A20 Datasheet v1.5 20150510

A20
Datasheet
Revision 1.5
Apr 06 , 2015
Copyright 2015 Allwinner Technology Co., Ltd. All Rights Reserved.

A20
Declaration
THIS A20 DATASHEET IS THE ORIGINAL WORK AND COPYRIGHTED PROPERTY OF ALLWINNER
TECHNOLOGY (ALLWINNER). REPRODUCTION IN WHOLE OR IN PART MUST OBTAIN THE WRITTEN
APPROVAL OF ALLWINNER AND GIVE CLEAR ACKNOWLEDGEMENT TO THE COPYRIGHT OWNER.
THE INFORMATION FURNISHED BY ALLWINNER IS BELIEVED TO BE ACCURATE AND RELIABLE.

ALLWINNER RESERVES THE RIGHT TO MAKE CHANGES IN CIRCUIT DESIGN AND/OR SPECIFICA-
TIONS AT ANY TIME WITHOUT NOTICE. ALLWINNER DOES NOT ASSUME ANY RESPONSIBILITY AND
LIABILITY FOR ITS USE. NOR FOR ANY INFRINGEMENTS OF PATENTS OR OTHER RIGHTS OF THE
THIRD PARTIES WHICH MAY RESULT FROM ITS USE. NO LICENSE IS GRANTED BY IMPLICATION OR
OTHERWISE UNDER ANY PATENT OR PATENT RIGHTS OF ALLWINNER. THIS DATASHEET NEITHER
STATES NOR IMPLIES WARRANTY OF ANY KIND, INCLUDING FITNESS FOR ANY PARTICULAR AP-
PLICATION.
THIRD PARTY LICENCES MAY BE REQUIRED TO IMPLEMENT THE SOLUTION/PRODUCT. CUSTOM-

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DEMNITY OR OTHER OBLIGATIONS WITH RESPECT TO MATTERS COVERED UNDER ANY REQUIRED
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Copyright 2015 Allwinner Technology Co., Ltd. All Rights Reserved.
Allwinner Technology Co., Ltd.

No.9 Technology Road 2,High-Tech Zone
Zhuhai, Guangdong Province, China
Contact Us: service@allwinnertech.com

Home Page: www.allwinnertech.com
A20 Datasheet ( Revision 1.5 ) Copyright 2015 Allwinner Technology Co., Ltd. All Rights Reserved. Page 2
A20
Revision History
Revision Date Description

1.0 Feb 27, 2013 Initial version
1.1 March 21, 2013 Revize the logo
1.2 May 10, 2013 Revize VDD-RTC to 1.3V
1.3 Oct 16, 2013 Modify the recommended operating condition section
1.4 Dec 30, 2013 Add TJ and JC
1.5 Apr 06, 2015 Modify the power up and down sequence
A20
Table of Contents
CHAPTER 1 OVERVIEW................. 4
CHAPTER 2FEATURES................................ 5
CHAPTER 3 BLOCK DIAGRAM................... 10
CHAPTER 4 PIN DESCRIPTION................. 11

4.1. PIN CHARACTERISTICS.................. 11
4.2. GPIO MULTIPLEXING FUNCTIONS................. 20
4.3. DETAILED PIN/SIGNAL DESCRIPTION.......... 24
4.4. POWER SIGNAL DESCRIPTION..................... 29
CHAPTER 5 ELECTRICAL CHARACTERISTICS.... 31

5.1. ABSOLUTE MAXIMUM RATINGS............................................................................. 31
5.2. RECOMMENDED OPERATING CONDITIONS....................................................... 31
5.3. DC ELECTRICAL CHARACTERISTICS.................................................................................. 32
5.4. OSCILLATOR ELECTRICAL CHARACTERISTICS...................................................................... 32
5.4.1. 24MHZ OSCILLATOR CHARACTERISTICS 32
5.4.2. 32768HZ OSCILLATOR CHARACTERISTICS 33
5.5. POWER UP/DOWN SEQUENCE 33
CHAPTER 6 PIN ASSIGNMENT 35

6.1. PIN MAP35
6.2. PACKAGE DIMENSION 36
Overview
1 OVERVIEW
Allwinner A20 processor is a dual-core ARM Cortex-A7 mobile application solution designed for tablet and smart
TV applications.
A20 is based on a dual-core ARM Cortex-A7 CPU architecture, and integrates the powerful ARM Mali400 MP2
GPU, delivering a reliable system performance as well as good game compatibility. Besides,A20 supports 2160p
video decoding and H.264 HP 1080p video encoding.
Additionally, A20 processor features a wide range of interfaces and connectivity, including 4-CH CVBS in, 4-CH
CVBS out, HDMI with HDCP, VGA, LVDS/RGB LCD, SATA, USB, and GMAC, etc. More importantly, A20 proces-
sor is pin-compatible with its predecessor A10, which greatly simplifies the product design process and makes the
upgrade of a design much easier.
Features
2 FEATURES
Dual-Core CPU SDRAM

Dual Cortex-A7 Support
DDR3/DDR3L/DDR2
ARMv7
ISA standard ARM instruction set Support
32-bit bus width
Thumb-2
Support
2GB address space
Jazeller
RCT
NEON
Advanced SIMD NAND Flash
VFPv4
floating point Comply
to ONFI 2.3 and Toggle 1.0
Hardware
virtualization support Support
64 bits ECC per 512 bytes or 1024 bytes
Large
Physical Address Extensions(LPAE) Support
8bits data bus width
JTAG
debug Support
1K/2K/4K/8K/16K page size
One
general timer for individual CPU Support
up to 8 CE and 2 RB
32KB
Instruction and 32KB Data L1 Cache for Support
system boot from NAND flash
individual CPU Support
SLC/MLC NAND and EF-NAND
Support
SDR/DDR NAND interface
Graphic Engine
3D SD/MMC Interface
Mali400
MP2 GPU Comply
with eMMC standard specification V4.3
Support
OpenGL ES 2.0 / OpenVG 1.1 standard Comply
with SD physical layer specification V2.0
2D Comply
with SDIO card specification V2.0
Support
BLT and ROP2/3/4 Support
1/4/8 bits bus width
Support
90 /180 /270 rotation Support
HS/DS/SDR12/SDR25 bus mode
Support
mirror/ alpha (plane and pixel alpha) / Support
eMMC mandatory and alternative boot
color key operations
Format
conversion: ARGB 8888/4444/1555, Support
four independent SD/MMC/SDIO
RGB565, MONO 1/2/4/8bpp, Palette 1/2/4/8bpp controllers
(input only), YUV 444/422/420 Support
SDSC/SDHC/SDXC/MMC/ RS-MMC card
Support
eMMC/iNand Flash
Memory Support
1GB/2GB/4GB/8GB/16GB/32GB/64GB
/128GB SD/MMC card
Internal BROM
Support
SDIO interrupt detection
Support
system boot from NAND Flash, SPI Nor
Flash (SPI0), SD Card/TF card (SDC0/2) Support
descriptor-based internal DMA controller
for efficient scatter and gather operations
Support
system code download through USB
OTG (USB0)
Features
System Resources Alpha

blending
Timer Thumb
generation
6
timers: clock source can be switched over 4x2
scaling ratio from 1/16 to 64 arbitrary non-
24M/32K for all timers, and external signals can be integer ratio
used as clock source for Timer4/5
Two
33-bit AVS counters
Display Engine
Watchdog
to generate reset signal or interrupt
Four moveable and size-adjustable layers, each
Real
time counter for second, minute, hour, day, layer size up to 8192x8192 pixels
month, and year
Ultra-Scaling engine
8-tap
scale filter in horizontal and 4 tap in vertical
High Speed Timer Source
image size from 8x4 to 8192x8192
4
channels resolution and destination image size from 8x4 to
Clock
source is fixed to AHB, and the pre-scale 8192x8192 resolution
ranges from 1 to 16 Support multiple image input formats
56-bit
counter that can be separated to 24-bit high mono
1/2/4/8 bpp
register and 32-bit low register palette
1/2/4/8 bpp
6/24/32
bpp color
DMA YUV444/420/422/411

16
channels Support alpha blending/color key/gamma/harware
Support
data width of 8/32 bits cursor/sprite
Support
linear and IO address modes Output color correction: luminance/hue/saturation,
etc
Support de-interlace
CCU Video enhancement: lum peaking/DCTi/black and
8PLLs,
a main 24MHz oscillator, an on-chip RC white level extension
oscillator and a 32768Hz oscillator (optional) 3D input/output format conversion and display
GIC Video Output

Support
16 SGIs, 16 PPIs, and 128 SPIs
HDMI 1.4 transmitter with HDCP
Support
ARM architecture security extensions LVDS/Sync RGB/CPU LCD interface up to
Support
ARM architecture virtualization extensions 1920x1200 resolution
Support
uniprocessor and multiprocessor Support 4-channel CVBS, or 2-channel S-video, or
environments 1-channel YPbPr/VGA (YPbPr/VGA up to 1080p)
Support two-channel independent display
Video Engine (Phoenix 3.0)

Video Decoding Video Input
Support
picture size up to 3840x2160 Support TV decoder: 4-ch analog CVBS or 1-ch
YPbPr(480i/576i/480p/576p) signal input
Support
decoding speed up to 1080p@60fps
Dual CMOS sensor parallel interfaces that support
Supported
formats: Mpeg1/2, Mpeg4 SP/ASP
YUV format only
GMC, H.263 including Sorenson Spark, H.264 BP/
CSI0
up to 1080p@30fps
MP/HP, VP6/8, AVS jizun, Jpeg/Mjpeg, etc.
CSI1
up to 720p@30fps
Video Encoding
Support BT656 interface
H.264
HP up to 1080p@30fps
Support 24-bit YUV444/RGB interface
Jpeg
baseline: picture size up to 4080x4080
Features
Analog Audio Output GMAC
Stereo audio DAC Comply

with the IEEE 802.3-2002 standard
Stereo capless headphone drivers Programmable

frame length to support Standard
Up or Jumbo Ethernet frames with size up to 16KB
to 100dB SNR during DAC playback
Support
10/100/1000Mbps data transfer rates
Support
8KHz~192KHz DAC sample rate
RGMII interface to communicate with an external
One low-noise analog microphone bias
Gigabit PHY
Dedicated headphone outputs
Support
10/100Mbps MII PHY interface
Two mixers to meet different requirements
Output
mixer for LINEINL/R, FMINL/R, MIC1/2
and Stereo DAC output Digital Audio In/Out
ADC
record mixer for LINEINL/R, FMINL/R, One
I2S compliant audio interface, supporting
MIC1/2 and Stereo DAC output 8-channel and 2-channel input
One
PCM, supporting linear sample(8-bit or 16-
bit), 8-bit u-law and A-law companded sample
Analog Audio Input One
AC97 audio codec, supporting 2-channel and
Support four analog audio inputs 6-channel audio data output
Two
microphone inputs
Differential
or stereo line-in input
Transport Stream Controller
Stereo
FM-in input Support
both SPI and SSI
Stereo audio ADC Speed
up to 150Mbps for both SPI and SSI
96dBA
SNR
Support
32-channel PID filter
Support
8KHz ~ 48KHz ADC sample rate
Support
hardware PCR packet detect
RTP Open-Drain TWI

12-bit SAR ADC Up
to 5 TWIs compliant with TWI protocol
Dual touch detection
Sampling frequency up to 2MHz
Smart Card Reader
One
smart card reader controller supporting ISO/
Connectivity IEC 7816-3 and EMV2000 specifications
USB2.0 DRD Support
synchronous and any other non-ISO 7816
Support
High-Speed (HS, 480-Mbps), Full- and non-EMV cards
Speed (FS, 12-Mbps), and Low-Speed (LS, 1.5-
Mbps) in Host mode
SPI
Support
High-Speed (HS, 480-Mbps), Full- Master/Slave
configurable
Speed (FS, 12-Mbps) in Device mode
Up
to 4 independent SPI controllers: SPI0 with
Support
up to 5 user-configurable endpoints for one CS signal for system boot, SPI1/2/3 each with
Bulk , Isochronous, Control and Interrupt two CS signals
USB EHCI/OHCI UART

Two
EHCI/OHCI-compliant hosts Up
to 8 UART controllers:UART0 with two wires
for debug tools, UART1 with 8 wires, UART2/3
EMAC each with 4 wires, and others each with 2 wires
Support
10/100Mbps MII data transfer rate
Features
PS2
Security System
Two
PS2 compliant to IBM PS2 and AT-
Security System
compatible keyboard and mouse interface
Support
AES, DES, 3DES, SHA-1, MD5
Dual-role
controller: a PS2 host or a PS2 device
Support
ECB/CBC modes for AES/DES/3DES
128-bit,
192-bit and 256-bit key size for AES
IR
160-bit
hardware PRNG with 192-bit seed
Two
IR controllers supporting CIR, MIR and FIR
Security JTAG
modes
SATA Power Management

One
SATA Host controller Flexible PLL clock generator and OSC for 32KHz
Support
SATA 1.5Gb/s and SATA 3.0Gb/s Flexible clock gate
Support DVFS for CPU frequency and voltage ad-
Comply
with SATA spec 2.6
justment
Support
external SATA(eSATA)
Support standby mode (only DDR+RTC-Domain
power exist)
CAN
One
CAN bus controller
Package
Support
the CAN2.0 A/B protocol specification
FBGA 441 balls,0.80mm ball pitch, 19x19x1.4mm
Programmable
data rate up to 1Mbps
Keypad
One
keypad matrix interface up to 8 rows and 8
colums
Interrupt
for key press or key release
Internal
debouncing filter to prevent switching
noises
LRADC
6-bit
resolution
Voltage
input range between 0V to 2V
PWM
2
PWM outputs
Support
cycle mode and pulse mode
The
pre-scale is from 1 to 64
Block Diagram
3 BLOCK DIAGRAM
Pin Description
4 PIN DESCRIPTION
4.1. PIN CHARACTERISTICS

Following table describes the A20 pin characteristics from seven aspects: BALL#, Pin Name, Default
Function1, Type2, Reset State3, Default Pull Up/Down4, and Buffer Strength5.
Default Default Pull Buffer
BALL# Pin Name Type Reset State
Function Up/Down Strength (mA)
SDRAM
AC7 SDQ0 DRAM I/O Z - -
AB5 SDQ3 DRAM I/O Z - -
AA1 SDQ8 DRAM I/O Z - -
Y1 SDQ10 DRAM I/O Z - -
W2 SDQ13 DRAM I/O Z - -
Y2 SDQ15 DRAM I/O Z - -
T2 SDQ16 DRAM I/O Z - -
N2 SDQ17 DRAM I/O Z - -
U2 SDQ18 DRAM I/O Z - -
P1 SDQ19 DRAM I/O Z - -
T1 SDQ20 DRAM I/O Z - -
U1 SDQ21 DRAM I/O Z - -
N1 SDQ22 DRAM I/O Z - -
Note:
1 Default function defines the default function of each pin, especially for pins with multiplexing functions;
2 There are five pin types here: O for output, I for input, I/O for input/output, A for analog,P for power and G for
ground;
3 Reset state defines the state of the terminal at reset: Z for high-impedance.
4 Default Pull up/down defines the presence of an internal pull up or pull down resistor. Unless otherwise speci-
fied, the pin is default to be floating, and can be configured as pull up or pull down;
5 Buffer strength defines the driver strength of the associated output buffer. It is tested in the condition that VCC=
3.3V, strength=MAX;
Pin Description

M2 SDQ23 DRAM I/O Z - -
J1 SDQ24 DRAM I/O Z - -
L1 SDQ25 DRAM I/O Z - -
H1 SDQ26 DRAM I/O Z - -
K2 SDQ27 DRAM I/O Z - -
L2 SDQ28 DRAM I/O Z - -
G2 SDQ29 DRAM I/O Z - -
M1 SDQ30 DRAM I/O Z - -
H2 SDQ31 DRAM I/O Z - -
H3/H4/Y5/AA8 SVREF DRAM P - -
AB6 SDQS0 DRAM I/O Z - -
AC5 SDQS0B DRAM I/O Z - -
AC6 SDQM0 DRAM O Z - -
AB1 SDQS1 DRAM I/O Z - -
AA2 SDQS1B DRAM I/O Z - -
W1 SDQM1 DRAM O Z - -
R2 SDQM2 DRAM O Z - -
R1 SDQS2 DRAM I/O Z - -
P2 SDQS2B DRAM I/O Z - -
K1 SDQS3 DRAM I/O Z - -
J2 SDQS3B DRAM I/O Z - -
G1 SDQM3 DRAM O Z - -
V2 SCKB DRAM O Z - -
V1 SCK DRAM O Z - -
J4 SCK1 DRAM O Z - -
J3 SCK1B DRAM O Z
N3 SCKE DRAM O Z - -
W4 SA0 DRAM O Z - -
R4 SA1 DRAM O Z - -
U4 SA2 DRAM O Z - -
M4 SA3 DRAM O Z - -
Y4 SA4 DRAM O Z - -
N4 SA5 DRAM O Z - -
V4 SA6 DRAM O Z - -
M3 SA7 DRAM O Z - -
AA3 SA8 DRAM O Z - -
P4 SA9 DRAM O Z - -
L3 SA10 DRAM O Z - -
W3 SA11 DRAM O Z - -
P3 SA12 DRAM O Z - -
Y3 SA13 DRAM O Z - -
R3 SA14 DRAM O Z - -
AA4 SA15 DRAM O Z
K3 SBA0 DRAM O Z - -
L4 SBA1 DRAM O Z - -
K4 SBA2 DRAM O Z - -
T3 SWE DRAM O Z - -
U3 SCAS DRAM O Z - -
T4 SRAS DRAM O Z - -
V3 SCS DRAM O Z - -
Pin Description

AA5 SODT DRAM O Z - -
AA7 SZQ DRAM A Z - -
AA6 SRST DRAM O Z - -
N8 SADBG DRAM A Z - -
P8 SDDBG0 DRAM A Z - -
R8 SADBG1 DRAM A Z - -
M8/N9/P9 VDD-DLL POWER P - - -
G5/H5/L5/W5/
W6/W7/M5/R5/ VCC-DRAM POWER P - - -
T5/Y6
GPIO A
D5 PA0 GPIO I/O Z NO PULL 20
E5 PA1 GPIO I/O Z NO PULL 20
C13 PA17 GPIO I/O Z NO PULL 20
H10/J10 VCC-PA POWER P - - -
GPIO B
A15 PB0 GPIO I/O Z NO PULL 20
B15 PB1 GPIO I/O Z NO PULL 20
C12 PB9 GPIO I/O Z NO PULL 20
Pin Description

GPIO C
M23 PC0 GPIO I/O Z NO PULL 20
M22 PC1 GPIO I/O Z NO PULL 20
L23 PC2 GPIO I/O Z NO PULL 20
L22 PC3 GPIO I/O Z PULL UP 20
K23 PC4 GPIO I/O Z PULL UP 20
K22 PC5 GPIO I/O Z NO PULL 20
J23 PC6 GPIO I/O Z PULL UP 20
J22 PC7 GPIO I/O Z PULL UP 20
H23 PC8 GPIO I/O Z NO PULL 20
G23 PC10 GPIO I/O Z NO PULL 20
M21 PC16 GPIO I/O Z PULL DOWN 20
F23 PC17 GPIO I/O Z PULL UP 20
F22 PC18 GPIO I/O Z PULL UP 20
L21 PC19 GPIO I/O Z NO PULL 20
K21 PC20 GPIO I/O Z NO PULL 20
J21 PC21 GPIO I/O Z NO PULL 20
J20 PC22 GPIO I/O Z NO PULL 20
G19 PC23 GPIO I/O Z PULL UP 20
F21 PC24 GPIO I/O Z NO PULL 20
H19/J19 VCC-PC POWER P - - -
GPIO D
AB15 PD0 GPIO I/O Z NO PULL 20
AC15 PD1 GPIO I/O Z NO PULL 20
Y15 PD10 GPIO I/O Z NO PULL 20
AA15 PD11 GPIO I/O Z NO PULL 20
Pin Description

GPIO E
E23 PE0 GPIO I/O Z NO PULL 20
E22 PE1 GPIO I/O Z NO PULL 20
D23 PE2 GPIO I/O Z NO PULL 20
D22 PE3 GPIO I/O Z NO PULL 20
C23 PE4 GPIO I/O Z NO PULL 20
C22 PE5 GPIO I/O Z NO PULL 20
B23 PE6 GPIO I/O Z NO PULL 20
A23 PE8 GPIO I/O Z NO PULL 20
F19 VCC-PE POWER P - - -
GPIO F
M20 PF0 GPIO I/O Z NO PULL 20
M19 PF1 GPIO I/O Z NO PULL 20
L20 PF2 GPIO I/O Z NO PULL 20
L19 PF3 GPIO I/O Z NO PULL 20
K20 PF4 GPIO I/O Z NO PULL 20
K19 PF5 GPIO I/O Z NO PULL 20
N19 VCC-PF POWER P - - -
GPIO G
F20 PG0 GPIO I/O Z NO PULL 20
E21 PG1 GPIO I/O Z NO PULL 20
D21 PG3 GPIO I/O Z NO PULL 20
C21 PG5 GPIO I/O Z NO PULL 20
E18 VCC-PG POWER P - - -
GPIO H
A6 PH0 GPIO I/O Z NO PULL 20
B6 PH1 GPIO I/O Z NO PULL 20
C6 PH2 GPIO I/O Z NO PULL 20
Pin Description

D4 PH9 GPIO I/O Z NO PULL 20
E1 PH22 GPIO I/O Z NO PULL 20
F3 PH26 GPIO I/O Z NO PULL 20
F4 PH27 GPIO I/O Z NO PULL 20
GPIO I
A20 PI0 GPIO I/O Z NO PULL 20
B20 PI1 GPIO I/O Z NO PULL 20
C17 PI10 GPIO I/O Z NO PULL 20
D17 PI11 GPIO I/O Z NO PULL 20
E17 PI16 GPIO I/O Z NO PULL 20
SYSTEM CONTROL
W8 BOOTSEL - I H PULL UP -
Pin Description

T10 JTAGSEL - I H PULL UP -
H16 TEST - I L PULL DOWN -
F5 NMI# - I Z NO PULL
C14 RESET# - I Z NO PULL
USB
N20 DM0 - A - - -
N21 DP0 - A - - -
P20 DM1 - A - - -
P21 DP1 - A - - -
L16/L15 VCC-USB - P - - -
K16 VDD-USB - P - - -
R20 DM2 - A - - -
R21 DP2 - A - - -
SATA
T20 SATA-TXP - A - - -
T21 SATA-TXM - A - - -
U20 SATA-RXM - A - - -
U21 SATA-RXP - A - - -
V21 REXT-SATA - A - - -
M15/M16 VDD-SATA - P - - -
N15/N16 VDD25-SATA - P - - -
P19 SATA-CLKM - A - - -
R19 SATA-CLKP - A - - -
TP
Y22 TPX1 - A - - -
AA22 TPX2 - A - - -
Y23 TPY1 - A - - -
AA23 TPY2 - A - - -
AUDIO CODEC
AC23 MICOUTN - A - - -
AC22 MICOUTP - A - - -
Y21 FMINR - A - - -
Y20 FMINL - A - - -
AA21 VMIC - P - - -
AC21 MICIN2 - A - - -
AC20 MICIN1 - A - - -
W20 VRA1 - A - - -
V20 VRA2 - A - - -
T19 AVCC - P - - -
W21 VRP - A - - -
AB21 LINEINR - A - - -
AB20 LINEINL - A - - -
U19 AGND - G - - -
W19 HPR - A - - -
Y19 HPL - A - - -
V19 GND-HP - G - - -
AA19 HPCOM - A
AA20 HPCOMFB - A - - -
AC19 HPBP - P - - -
AB19 VCCHP - P - - -
Pin Description

LRADC
AB23 LRADC0 - A - - -
AB22 LRADC1 - A - - -
TV-OUT
AC16 TVOUT0 - A - - -
AB16 TVOUT1 - A - - -
AC17 TVOUT2 - A - - -
AB17 TVOUT3 - A - - -
W15 VCC-TVOUT - P - - -
TV-IN
AC18 TVIN0 - A - - -
AB18 TVIN1 - A - - -
AA17 TVIN2 - A - - -
Y17 TVIN3 - A - - -
W16 VCC-TVIN - P - - -
W17 VCC25-TVIN - P - - -
AA16 VRP-TVIN - A - - -
Y16 VRN-TVIN - A - - -
HDMI
V23 HTX0P - A - - -
V22 HTX0N - A - - -
U23 HTX1P - A - - -
U22 HTX1N - A - - -
T23 HTX2P - A - - -
T22 HTX2N - A - - -
W23 HTXCP - A - - -
W22 HTXCN - A - - -
T13 VCC-HDMI - P - - -
R23 HSCL - I/O - - -
R22 HSDA - I/O - - -
P22 HHPD - I/O - - -
P23 HCEC - I/O - - -
T14 HVREG1 - A - - -
CLOCK
F1 X32KI - A - - -
F2 X32KO - A - - -
K8 VDD-RTC - P - - -
N23 X24MI - A - - -
N22 X24MO - A
R15 PLLVREG A
P16 VCC-PLL - P
T15 PLLTEST - A
T16 PLLDV - A
POWER
J12/J13/H11/
VDD-CPU - P - - -
H12/H13/H14
T8/R9/R10/L8/
L9/K9/K10/K15/ VDD-SYS - P - - -
J15/J16
Pin Description

J5/K5/N5/P5/U5/
V5/Y7/Y8/G3/G4/
L10/L11/L12/L13/
L14/K11/K12/
K13/K14J11/M9/
M10/M11/M12/
M13/M14/N10/
N11/N12/N13/ GND - G - - -
N14/P10/P11/
P12/P13/P14/
P15/R11/R12/
R13/T11/T12/
W9/W10/W11/
V19/W18/Y18/
AA18
H8/H9/J8/J9/J14/
VCC - P - - -
H15
W12/W13/W14 VCC-LVDS - P - - -
R14/R16 NC - - - - -
EFUSE
T9 VDDQE P - - -
Pin Description
4.2. GPIO MULTIPLEXING FUNCTIONS

Following table provides a description of the GPIO multiplexing functions of A20.
Default
Default Default IO
Port IO Type Pull-up/ Multi2 Multi3 Multi4 Multi5 Multi6 Multi7
Function State
down
UART2-
PA0 GPIO I/O I Z ERXD3 SPI1-CS0 GRXD3 - -
RTS
UART2-
PA1 GPIO I/O I Z ERXD2 SPI1-CLK GRXD2 - -
CTS
PA2 GPIO I/O I Z ERXD1 SPI1-MOSI UART2-TX
GRXD1 - -
PA3 GPIO I/O I Z ERXD0 SPI1-MISO UART2-RX
GRXD0 - -
PA4 GPIO I/O I Z ETXD3 SPI1-CS1 - GTXD3 - -
PA5 GPIO I/O I Z ETXD2 SPI3-CS0 - GTXD2 - -
PA6 GPIO I/O I Z ETXD1 SPI3-CLK - GTXD1 - -
PA7 GPIO I/O I Z ETXD0 SPI3-MOSI - GTXD0 - -
PA8 GPIO I/O I Z ERXCK SPI3-MISO - GRXCK - -
GNULL/ERX-
PA9 GPIO I/O I Z ERXERR SPI3-CS1 - I2S1-MCLK -
ERR
GRXCTL/
PA10 GPIO I/O I Z ERXDV - UART1-TX - -
RXDV
PA11 GPIO I/O I Z EMDC - UART1-RX GMDC - -
UART1-
PA12 GPIO I/O I Z EMDIO UART6-TX GMDIO - -
RTS
UART1- GTXCTL/
PA13 GPIO I/O I Z ETXEN UART6-RX - -
CTS ETXEN
UART1- GNULL/
PA14 GPIO I/O I Z ETXCK UART7-TX I2S1-BCLK -
DTR ETXCK
UART1- GTXCK/
PA15 GPIO I/O I Z ECRS UART7-RX I2S1-LRCK -
DSR ECRS
UART1- GCLKIN/
PA16 GPIO I/O I Z ECOL CAN-TX I2S1-DO -
DCD ECOL
UART1- GNULL/ETX-
PA17 GPIO I/O I Z ETXERR CAN-RX I2S1-DI -
RING ERR
PB0 GPIO I/O I Z TWI0-SCK - - - - -
PB1 GPIO I/O I Z TWI0-SDA - - - - -
PB2 GPIO I/O I Z PWM0 - - - - -
PB3 GPIO I/O I Z IR0-TX - OWA-MCLK - -
PB4 GPIO I/O I Z IR0-RX - - - - -
PB5 GPIO I/O I Z I2S-MCLK AC97-MCLK - - - -
PB6 GPIO I/O I Z I2S-BCLK AC97-BCLK - - - -
PB7 GPIO I/O I Z I2S-LRCK AC97-SYNC - - - -
PB8 GPIO I/O I Z I2S-DO0 AC97-DO - - - -
PB9 GPIO I/O I Z I2S-DO1 - - - - -
PB12 GPIO I/O I Z I2S-DI AC97-DI OWA-DI - - -
PB13 GPIO I/O I Z SPI2-CS1 - OWA-DO - - -
PB14 GPIO I/O I Z SPI2-CS0 JTAG-MS0 - - - -
PB15 GPIO I/O I Z SPI2-CLK JTAG-CK0 - - - -
PB16 GPIO I/O I Z SPI2-MOSI JTAG-DO0 - - - -
PB17 GPIO I/O I Z SPI2-MISO JTAG-DI0 - - - -
Pin Description
Default
Default Default IO
Function State
down
PB22 GPIO I/O I Z UART0-TX IR1-TX - - - -
PB23 GPIO I/O I Z UART0-RX IR1-RX - - - -
PC0 GPIO I/O I Z NWE# SPI0-MOSI - - - -
PC1 GPIO I/O I Z NALE SPI0-MISO - - - -
PC2 GPIO I/O I Z NCLE SPI0-CLK - - - -
PC3 GPIO I/O I Pull-Up NCE1 - - - - -
PC5 GPIO I/O I Z NRE# - - - - -
PC6 GPIO I/O I Pull-Up NRB0 SDC2-CMD - - - -
PC7 GPIO I/O I Pull-Up NRB1 SDC2-CLK - - - -
PC8 GPIO I/O I Z NDQ0 SDC2-D0 - - - -
PC12 GPIO I/O I Z NDQ4 - - - - -
PC16 GPIO I/O I Pull-Down NWP - - - - -
PC19 GPIO I/O I Z NCE4 SPI2-CS0 - - - -
PC20 GPIO I/O I Z NCE5 SPI2-CLK - - - -
PC21 GPIO I/O I Z NCE6 SPI2-MOSI - - - -
PC22 GPIO I/O I Z NCE7 SPI2-MISO - - - -
PC23 GPIO I/O I Pull-Up - SPI0-CS0 - - - -
PC24 GPIO I/O I Z NDQS - - - - -
PD0 GPIO I/O I Z LCD0-D0 LVDS0-VP0 - - - -
PD1 GPIO I/O I Z LCD0-D1 LVDS0-VN0 - - - -
PD6 GPIO I/O I Z LCD0-D6 LVDS0-VPC - - - -
PD7 GPIO I/O I Z LCD0-D7 LVDS0-VNC - - - -
PD16 GPIO I/O I Z LCD0-D16 LVDS1-VPC - - - -
PD17 GPIO I/O I Z LCD0-D17 LVDS1-VNC - - - -
PD20 GPIO I/O I Z LCD0-D20 CSI1-MCLK - - - -
PD21 GPIO I/O I Z LCD0-D21 SMC-VPPEN - - - -
PD22 GPIO I/O I Z LCD0-D22 SMC-VPPPP - - - -
PD23 GPIO I/O I Z LCD0-D23 SMC-DET - - - -
PD24 GPIO I/O I Z LCD0-CLK SMC-VCCEN - - - -
PD25 GPIO I/O I Z LCD0-DE SMC-RST - - - -
PD26 GPIO I/O I Z LCD0-HSYNC SMC-SLK - - - -
PD27 GPIO I/O I Z LCD0-VSYNC SMC-SDA - - - -
Pin Description
Default
Default Default IO
Function State
down
PE0 GPIO I/O I Z TS0-CLK CSI0-PCLK - - - -
PE1 GPIO I/O I Z TS0-ERR CSI0-MCLK - - - -
PE2 GPIO I/O I Z TS0-SYNC CSI0-HSYNC - - - -
PE3 GPIO I/O I Z TS0-DVLD CSI0-VSYNC - - - -
PE4 GPIO I/O I Z TS0-D0 CSI0-D0 - - - -
PF0 GPIO I/O I Z SDC0-D1 - JTAG-MS1 - - -
PF1 GPIO I/O I Z SDC0-D0 - JTAG-DI1 - - -
PF2 GPIO I/O I Z SDC0-CLK - UART0-TX - - -
PF3 GPIO I/O I Z SDC0-CMD - JTAG-DO1 - - -
PF4 GPIO I/O I Z SDC0-D3 - UART0-RX - - -
PF5 GPIO I/O I Z SDC0-D2 - JTAG-CK1 - - -
PG0 GPIO I/O I Z TS1-CLK CSI1-PCLK SDC1-CMD - - -
PG1 GPIO I/O I Z TS1-ERR CSI1-MLCK SDC1-CLK - - -
PG2 GPIO I/O I Z TS1-SYNC CSI1-HSYNC SDC1-D0 - - -
PG3 GPIO I/O I Z TS1-DVLD CSI1-VSYNC SDC1-D1 - - -
PG4 GPIO I/O I Z TS1-D0 CSI1-D0 SDC1-D2 CSI0-D8 - -
PG5 GPIO I/O I Z TS1-D1 CSI1-D1 SDC1-D3 CSI0-D9 - -
PG6 GPIO I/O I Z TS1-D2 CSI1-D2 UART3-TX CSI0-D10 - -
PG7 GPIO I/O I Z TS1-D3 CSI1-D3 UART3-RX CSI0-D11 - -
UART3-
PG8 GPIO I/O I Z TS1-D4 CSI1-D4 CSI0-D12 - -
RTS
UART3-
PG9 GPIO I/O I Z TS1-D5 CSI1-D5 CSI0-D13 - -
CTS
PG10 GPIO I/O I Z TS1-D6 CSI1-D6 UART4-TX CSI0-D14 - -
PG11 GPIO I/O I Z TS1-D7 CSI1-D7 UART4-RX CSI0-D15 - -
PH0 GPIO I/O I Z LCD1-D0 - UART3-TX - EINT0 CSI1-D0
PH1 GPIO I/O I Z LCD1-D1 - UART3-RX - EINT1 CSI1-D1
UART3-
PH2 GPIO I/O I Z LCD1-D2 - - EINT2 CSI1-D2
RTS
UART3-
PH3 GPIO I/O I Z LCD1-D3 - - EINT3 CSI1-D3
CTS
PH8 GPIO I/O I Z LCD1-D8 ERXD3 KP-IN0 - EINT8 CSI1-D8
PH12 GPIO I/O I Z LCD1-D12 - PS2-SCK1 - EINT12 CSI1-D12
PH13 GPIO I/O I Z LCD1-D13 - PS2-SDA1 SMC-RST EINT13 CSI1-D13
PH14 GPIO I/O I Z LCD1-D14 ETXD3 KP-IN4 SMC-VPPEN EINT14 CSI1-D14
PH15 GPIO I/O I Z LCD1-D15 ETXD2 KP-IN5 SMC-VPPPP EINT15 CSI1-D15
PH16 GPIO I/O I Z LCD1-D16 ETXD1 KP-IN6 SMC-DET EINT16 CSI1-D16
PH17 GPIO I/O I Z LCD1-D17 ETXD0 KP-IN7 SMC-VCCEN EINT17 CSI1-D17
PH18 GPIO I/O I Z LCD1-D18 ERXCK KP-OUT0 SMC-SLK EINT18 CSI1-D18
PH19 GPIO I/O I Z LCD1-D19 ERXERR KP-OUT1 SMC-SDA EINT19 CSI1-D19
Pin Description
Default
Default Default IO
Function State
down
PH20 GPIO I/O I Z LCD1-D20 ERXDV CAN-TX - EINT20 CSI1-D20
PH21 GPIO I/O I Z LCD1-D21 EMDC CAN-RX - EINT21 CSI1-D21
PH22 GPIO I/O I Z LCD1-D22 EMDIO KP-OUT2 SDC1-CMD - CSI1-D22
PH23 GPIO I/O I Z LCD1-D23 ETXEN KP-OUT3 SDC1-CLK - CSI1-D23
PH24 GPIO I/O I Z LCD1-CLK ETXCK KP-OUT4 SDC1-D0 - CSI1-PCLK
PH25 GPIO I/O I Z LCD1-DE ECRS KP-OUT5 SDC1-D1 - CSI1-FIELD
CSI1-
PH26 GPIO I/O I Z LCD1-HSYNC ECOL KP-OUT6 SDC1-D2 -
HSYNC
CSI1-
PH27 GPIO I/O I Z LCD1-VSYNC ETXERR KP-OUT7 SDC1-D3 -
VSYNC
PI0 GPIO I/O I Z - TWI3-SCK - - - -
PI1 GPIO I/O I Z - TWI3-SDA - - - -
PI2 GPIO I/O I Z - TWI4-SCK - - - -
PI3 GPIO I/O I Z PWM1 TWI4-SDA - - - -
PI4 GPIO I/O I Z SDC3-CMD - - - - -
PI5 GPIO I/O I Z SDC3-CLK - - - - -
PI6 GPIO I/O I Z SDC3-D0 - - - - -
PI10 GPIO I/O I Z SPI0-CS0 UART5-TX - - EINT22 -
PI11 GPIO I/O I Z SPI0-CLK UART5-RX - - EINT23 -
CLK-OUT-
PI12 GPIO I/O I Z SPI0-MOSI UART6-TX - EINT24 -
A
CLK-OUT-
PI13 GPIO I/O I Z SPI0-MISO UART6-RX - EINT25 -
B
PI14 GPIO I/O I Z SPI0-CS1 PS2-SCK1 TCLKIN0 - EINT26 -
PI15 GPIO I/O I Z SPI1-CS1 PS2-SDA1 TCLKIN1 - EINT27 -
PI16 GPIO I/O I Z SPI1-CS0 UART2-RTS - - EINT28 -
PI17 GPIO I/O I Z SPI1-CLK UART2-CTS - - EINT29 -
PI18 GPIO I/O I Z SPI1-MOSI UART2-TX - - EINT30 -
PI19 GPIO I/O I Z SPI1-MISO UART2-RX - - EINT31 -
PI20 GPIO I/O I Z PS2-SCK0 UART7-TX HSCL - - -
PI21 GPIO I/O I Z PS2-SDA0 UART7-RX HSDA - - -
4.3. DETAILED PIN/SIGNAL DESCRIPTION

Pin/Signal Description Type
DRAM
SDQ[31:0] DRAM DQ[31:0] I/O
SVREF DRAM Reference Input P
SDQS[3:0] DRAM Data Strobe DQS[3:0] I/O
SDQSB[3:0] DRAM Data Strobe DQSB[3:0] I/O
SDQM[3:0] DRAM DQ Mask[3:0] O
SCK DRAM Clock O
SCKB DRAM CKB O
SCK1 DRAM Clock O
SCK1B DRAM CKB O
SCKE DRAM Clock Enable O
SA[15:0] DRAM Data Address[15:0] O
Pin Description

SBA[2:0] DRAM Bank Address[2:0] O
SWE DRAM Write Enable O
SCAS DRAM Column Address Strobe O
SRAS DRAM Row Address Strobe O
SCS DRAM Chip Select O
SODT DRAM ODT Control O
SZQ DRAM ZQ Calibration A
SRST DRAM Reset O
SADBG DRAM Analog Debug A
SDDBG0 DRAM Digital Debug A
SADBG1 DRAM Analog Debug A
VDD-DLL DLL Power Supply P
VCC-DRAM DRAM Power Supply P
GPIO
PA[17:0] Port A Bit[17:0] I/O
VCC-PA Port A Power Supply P
PB[23:0] Port B Bit[23:0] I/O
PC[24:0] Port C Bit[23:0] I/O
VCC-PC Port C Power Supply P
PD[27:0] Port D Bit[27:0] I/O
PE[11:0] Port E Bit[11:0] I/O
VCC-PE Port E Power Supply P
PF[5:0] Port F Bit[5:0] I/O
VCC-PF Port F Power Supply P
PG[11:0] Port G Bit[11:0] I/O
VCC-PG Port G Power Supply P
PH[27:0] Port H Bit[27:0] I/O
PI[21:0] Port I Bit[21:0] I/O
SYSTEM CONTROL
BOOTSEL Boot Mode Select I
JTAGSEL JTAG Mode Select I
TEST Test Signal I
NMI# Non-Maskable Interrupt I
RESET# Reset Signal I
INTERRUPT
EINT[31:0] External Interrupt I
JTAG
JTAG-DO[1:0] JTAG Data Output O
JTAG-DI[1:0] JTAG Data Input I
JTAG-MS[1:0] JTAG Mode Select I
JTAG-CK[1:0] JTAG Clock Signal I
PWM
PWM[1:0] PWM O
CLOCK
X32KI Clock Input of 32768Hz Crystal A
X32KO Clock Output of 32768Hz Crystal A
VDD-RTC RTC Power Supply P
X24MI Clock Input of 24MHz Crystal A
X24MO Clock Output of 24MHz Crystal A
PLLVREG PLL Power P
VCC-PLL PLL Power P
PLLDV PLL Power P
PLLTEST PLL Test Signal A
Pin Description

CLK-OUT-A Clock OUT A I/O
CLK-OUT-B Clock OUT B I/O
TCLKIN[1:0] Clock I/O
NAND FLASH
NDQ[7:0] NAND Flash Data Bit[7:0] I/O
NCE[7:0] NAND Flash Chip Select[7:0] O
NWE# NAND Flash Write Enable O
NALE NAND Flash Address Latch Enable O
NCLE NAND Flash Command Latch Enable O
NRE# NAND Flash Read Enable O
NRB[1:0] NAND Flash Ready/Busy Bit I
NWP NAND Flash Write Protection O
NDQS NAND Flash Data Strobe I/O
LCD (x=[1:0])
LCDx-D[23:0] LCD Data Bit[23:0] O
LCDx-CLK LCD Clock Signal O
LCDx-DE LCD Data Enable O
LCDx-HSYNC LCD Horizontal SYNC O
LCDx-VSYNC LCD Vertical SYNC O
LVDS (x=[1:0])
LVDS0-VP[3:0] LVDS Channel0 Data Positive Signal Output[3:0] A
LVDS0-VN[3:0] LVDS Channel0 Data Negative Signal Output[3:0] A
LVDS0-VPC LVDS Channel0 Clock Positive Output A
LVDS0-VNC LVDS Channel0 Clock Negative Output A
LVDS1-VP[3:0] LVDS Channel1 Data Positive Signal Output[3:0] A
LVDS1-VN[3:0] LVDS Channel1 Data Negative Signal Output[3:0] A
LVDS1-VPC LVDS Channel1 Clock Positive Output A
LVDS1-VNC LVDS Channel1 Clock Negative Output A
VCC- LVDS LVDS Power Supply P
HDMI
HTX0P HDMI Data0 Positive A
HTX0N HDMI Data0 Negative A
HTXCP HDMI Clock Positive A
HTXCN HDMI Clock Negative A
VCC-HDMI HDMI Power Supply P
HSCL HDMI DDC Clock I/O
HSDA HDMI DDC Data I/O
HHPD HDMI Hot Plug Detection I/O
HCEC HDMI CEC I/O
TV-OUT
TVOUT[3:0] TV-out Output[3:0] A
VCC-TVOUT TV-out Power Supply P
CSI (x=[1:0])
CSI0-D[15:0] CSI0 Data Bit[15:0] I
CSI1-D[23:0] CSI1 Data Bit[23:0] I
CSIx-PCLK CSI Pixel Clock I
CSIx-MCLK CSI Master Clock O
Pin Description

CSIx-HSYNC CSI Horizontal SYNC I
CSIx-VSYNC CSI Vertical SYNC I
TV-IN
TVIN[3:0] TV-in Input[3:0] A
VCC-TVIN TV-in Power Supply P
VCC25-TVIN TV-in Power Supply P
VRP-TVIN TV-in Reference A
VRN-TVIN TV-in Reference A
USB
DM[2:0] USB DM[2:0] Signal A
DP[2:0] USB DP[2:0] Signal A
VCC-USB USB Power Supply P
VDD-USB USB Power P
TP
TPX[2:1] TP ADC Input A
TPY[2:1] TP ADC Input A
AUDIO CODEC
MICOUTN MIC Negative Output A
MICOUTP MIC Positive Ouput A
FMINR FM Right Channel Input A
FMINL FM Left Channel Input A
VMIC MIC Power Supply A
MICIN[2:1] MIC Input A
VRA1 Reference (1.5V) A
VRA2 Reference (1.5V) A
AVCC Analog Power Supply P
VRP Reference (3.0V) A
LINEINR Linein Right Channel Input A
LINEINL Linein Left Channel Input A
AGND Analog Ground G
HPR Headphone Right Channel Output A
HPL Headphone Left Channel Output A
GND-HP Headphone Ground G
HPCOM Headphone Common Referene A
HPCOMFB Headphone Common Reference Feedback A
HPBP Headphone Bypass Output A
LRADC
LRADC[1:0] LRADC Input [1:0] A
EMAC
ERXD[3:0] EMAC MII Receive Data Nibble Data Bit[3:0] I
ETXD[3:0] EMAC MII Transmit Data Nibble Data Bit[3:0] O
ERXCK EMAC MII Receive Clock I
ERXERR EMAC MII Receive Error I
ERXDV EMAC Receive Data Valid I
EMDC EMAC MII Management Data Clock O
EMDIO EMAC MII Management Data Input/Output I/O
ETXEN EMAC MII Transmit Enable O
ETXCK EMAC MII Transmit Clock I
ECRS EMAC MII Carrier Sense I
ECOL EMAC MII Collision Detect I
ETXERR EMAC MII Transmit Error O
GMAC
GRXD[3:0] GMAC Receive Data[3:0] I
Pin Description

GTXD[3:0] GMAC Transmit Data[3:0] O
GNULL/ERXERR RGMII Null / MII Receive Error I
GRXCTL/RXDV RGMII Receive Control / MII Receive Data Valid I, I
GMDC GMAC Management Data Clock O
GMDIO GMAC Management Data Input/Output I/O
GTXCTL/ETXEN RGMII Transmit Control/ MII Transmit Enable O,O
GNULL/ETXCK RGMII Null / MII Transmit Clock I
GTXCK/ECRS RGMII Transmit Clock / MII Carrier Sense O,I
GCLKIN/ECOL RGMII Clock in / MII Collision Detect I,I
GNULL/ETXERR RGMII Null / MII Transmit Error O
SPI (x=[3:0])
SPIx-CS[1:0] SPI Chip Select Signal I/O
SPIx-CLK SPI Clock Signal I/O
SPIx-MOSI SPI Master Data Out, Slave Data In I/O
SPIx-MISO SPI Master Data In, Slave Data Out I/O
UART (x=[7:0])
UARTx-TX UART Data Transmit O
UARTx-RX UART Data Receive I
UARTx-RTS UART Data Request to Send O
UARTx-CTS UART Data Clear to Send I
UARTx-DTR UART Data Terminal Ready O
UARTx-DSR UART Data Set Ready I
UARTx-DCD UART Data Carrier Detect I
UARTx-RING UART Data Ring Indicator I
TWI (x=[4:0])(Open-Drain)
TWIx-SCK TWI Clock Signal I/O
TWIx-SDA TWI Data Signal I/O
SD/MMC (x=[3:0])
SDCx-D[3:0] SD/MMC/SDIO Data Bit[3:0] I/O
SDCx-CLK SD/MMC/SDIO Clock O
SDCx-CMD SD/MMC/SDIO Command Signa I/O
KEYPAD
KP-IN[7:0] Keypad Data Input I
KP-OUT[7:0] Keypad Data Output O
IR(x=[1:0])
IRx-TX IR Data Transmit I/O
IRx-RX IR Data Receive I/O
PS2
PS2-SCK[1:0] PS2 Clock Signal I/O
PS2-SDA[1:0] PS2 Data Signal I/O
I2S
I2S-DO[3:0] I2S Data Output O
I2S-DI I2S Data Input I
I2S-MCLK I2S Mater Clock O
I2S-BCLK I2S Bit Clock I/O
I2S-LRCK I2S Left/Right Select Clock I/O
I2S1-DO I2S1 Data Output O
I2S1-DI I2S1 Data Input I
I2S1-BCLK I2S1 Bit Clock I/O
I2S1-LRCK I2S1 Left/Right Select Clock I/O
I2S1-MCLK I2S1 Mater Clock O
AC97
Pin Description

AC97-DO AC97 Data Output O
AC97-DI AC97 Data Input I
AC97-MCLK AC97 Master Clock O
AC97-BCLK AC97 Bit Clock I/O
AC97-SYNC AC97 SYNC Signal I/O
TS (x=[1:0])
TSx-D[7:0] Transport Stream Data Bit[7:0] I
TSx-CLK Transport Stream Clock I
TSx-ERR Transport Stream Error Indicate I
TSx-SYNC Transport Stream SYNC I
TSx-DVLD Transport Stream Data Valid I
CAN
CAN-TX CAN Data Transmit O
CAN-RX CAN Data Receive I
SMC
SMC-RST Smart Card Reset O
SMC-VPPEN Smart Card Program Voltage Enable O
SMC-VPPPP Smart Card Program Control O
SMC-DET Smart Card Detect I
SMC-VCCEN Smart Card Power Enable O
SMC-SLK Smart Card Clock O
SMC-SDA Smart Card Data I/O
SATA
SATA-TXP SATA Positive Transmit A
SATA-TXM SATA Negative Transmit A
SATA-RXP SATA Positive Receive A
SATA-RXM SATA Negative Receive A
REXT-SATA Reference A
VDD-SATA SATA Power Supply P
VDD25-SATA SATA Power Supply P
SATA-CLKM SATA Negative Clock A
SATA-CLKP SATA Positve Clock A
eFUSE
VDDQE eFuse Power Supply P
POWER
VDD-CPU CPU Power Supply P
VDD-SYS System Power Supply P
GND Ground G
VCC IO Power Supply P
4.4. POWER SIGNAL DESCRIPTION

SIGNAL DESCRIPTION BALL#
DRAM
VCC-DRAM DRAM Power Supply G5/H5/L5/W5/W6/W7/M5/R5/T5/Y6
VDD-DLL DLL Power Supply M8/N9/P9
GPIO
VCC-PA Port A Power Supply H10/J10
VCC-PC Port C Power Supply H19/J19
Pin Description
SIGNAL DESCRIPTION BALL#

VCC-PE Port E Power Supply F19
VCC-PF Port F Power Supply N19
VCC-PG Port G Power Supply E18
USB
VCC-USB USB Power Supply L16/L15
VDD-USB USB Power Supply K16
AUDIO CODEC
VMIC MIC Power Supply AA21
VRA1 Reference(1.5V) W20
VRA2 Reference (1.5V) V20
AVCC Analog Power Supply T19
VRP Reference (3.0V) W21
AGND Analog Ground U19
TV-OUT
VCC-TVOUT TVOUT power supply W15
TV-IN
VCC-TVIN TVIN Power Supply W16
VCC25-TVIN TVIN Power Supply W17
VRP-TVIN TVIN BIAS AA16
VRN-TVIN TVIN BIAS Y16
HDMI
VCC-HDMI HDMI Power Supply T13
LVDS
VCC- LVDS LVDS Power Supply W12/W13/W14
RTC
VDD-RTC RTC Power Supply K8
CLOCK
VCC-PLL PLL Power Supply P16
EFUSE
VDDQE eFUSE Power Supply T9
CPU
VDD-CPU CPU Power Supply J12/J13/H11/H12/H13/H14
SYSTEM
VDD-SYS System Power Supply T8/R9/R10/L8/L9/K9/K10/K15/J15/J16
CORE POWER
J5/K5/N5/P5/U5/V5/Y7/Y8/G3/G4/L10/L11/
L12/L13/L14/K11/K12/K13/K14J11/M9/M10/
GND Ground M11/M12/M13/M14/N10/N11/N12/N13/N14/
P10/P11/P12/P13/P14/P15/R11/R12/R13/
T11/T12/W9/W10/W11/W18/Y18/AA18
VCC IO power supply H8/H9/J8/J9/J14/H15
Electrical Characteristics
5 ELECTRICAL CHARACTERISTICS
5.1. ABSOLUTE MAXIMUM RATINGS

Functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may af-
fect device reliability.
SYMBOL PARAMETER MIN MAX UNIT

Tg Storage Temperature -40 125 C
II/O In/Out current for input and output -40 40 mA
HBM(human body model) -4K 4K
VESD ESD stress voltage VESD
CDM(charged device model) -250 250
VCC DC Supply Voltage for I/O -0.3 3.6 V
VDD DC Supply Voltage for Internal Digital Logic -0.3 1.4 V
AVCC DC Supply Voltage for Analog Part -0.3 3.6 V
VCC-DRAM Power Supply for DRAM -0.3 1.98 V
VCC-USB Power Supply for USB PHY -0.3 3.6 V
VCC-TVOUT Power Supply for TV-OUT DAC -0.3 3.6 V
VCC-PLL Power Supply for PLL -0.3 3.6 V
VDD-RTC Power Supply for RTC -0.3 1.4 V
VDD-CPU Power Supply for CPU -0.3 1.4 V
VDD-SYS Power Supply for System -0.3 1.4 V
5.2. RECOMMENDED OPERATING CONDITIONS

SYMBOL PARAMETER MIN TYP MAX UNIT
Ta Ambient Operating Temperature[Commercial] -20 - +70 C
VCC DC Supply Voltage for I/O 1.7 1.8~3.3 3.6 V
VDD DC Supply Voltage for Internal Digital Logic 1.0 - 1.4 V
AVCC DC Supply Voltage for Analog Part 2.7 3.0 3.3 V
VCC-DRAM Power Supply for DRAM 1.28 - 1.98 V
VCC-USB Power Supply for USB PHY 3.0 3.3 3.45 V

VCC-TVOUT Power Supply for TV-OUT DAC 3.0 3.3 3.6 V
VCC-TVIN Power Supply for TV-in 3.0 3.3 3.6 V
VCC25-TVIN Power Supply for TV-in - 2.5 - V
VCC-PLL Power Supply for PLL 2.7 3.0 3.3 V
VCC-LVDS Power Supply for LVDS - 3.3 - V
VDD-RTC Power Supply for RTC 1.2 1.3 1.4 V
VDD-CPU Power Supply for CPU 1.0 - 1.4 V
VDD-SYS Power Supply for System 1.0 - 1.4 V
5.3. DC ELECTRICAL CHARACTERISTICS

SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIH High-Level Input Voltage VCC=3.3V 0.7*VCC - VCC+0.3 V
VIL Low-Level Input Voltage VCC=3.3V -0.3 - 0.3*VCC V
VHYS Hysteresis Voltage - - - - mV
IIH High-Level Input Current VCC=3.3V, VI=3.3V - - 10 uA
IIL Low-Level Input Current VCC=3.3V, VI=0V - - 10 uA
VOH High-Level Output Voltage VCC=3.3V VCC-0.2 - - V
VOL Low-Level Output Voltage VCC=3.3V - - 0.2 V
IOZ Tri-State Output Leakage Current VCC=3.3V -10 - 10 uA
CIN Input Capacitance - - - 5 pF
COUT Output Capacitance - - - 5 pF
5.4. OSCILLATOR ELECTRICAL CHARACTERISTICS

The A20 contains two oscillators: a 24MHz oscillator and a 32768Hz oscillator. Each oscillator requires a
specific crystal.
The A20 device operation requires following two input clocks:
The 32768Hz frequency is used for low frequency operation.
The 24MHz frequency is used to generate the main source clock of the A20 device.
5.4.1. 24MHz OSCILLATOR CHARACTERISTICS

The 24.0MHz crystal is connected between the HOSCI (amplifier input) and HOSCO (amplifier output).

1/(tCPMAIN) Crystal Oscillator Frequency Range - 24 - MHz
tST Startup Time - - - ms

Frequency Tolerance at 25C -50 - +50 ppm
Oscillation Mode Fundamental -
Maximum Change Over Temperature Range -50 - +50 ppm
PON Drive Level - - 50 uW
CL Equivalent Load Capacitance - - - pF
CL1,CL2 Internal Load Capacitance(CL1=CL2) - - - pF
RS Series Resistance(ESR) - - -
Duty Cycle 30 50 70 %
CM Motional Capacitance - - - pF
CSHUT Shunt Capacitance - - - pF
RBIAS Internal Bias Resistor - - - M
5.4.2. 32768HZ OSCILLATOR CHARACTERISTICS

The 32768Hz crystal is connected between the LOSCI (amplifier input) and LOSCO (amplifier output).
1/(tCPMAIN) Crystal Oscillator Frequency Range - 32768 - Hz
tST Startup Time - - - ms
Frequency Tolerance at 25C -50 - +50 ppm
Oscillation Mode Fundamental -
Maximum Change Over Temperature Range -50 - +50 ppm
PON Drive Level - - 50 uW
CL Equivalent Load Capacitance - - - pF
CL1,CL2 Internal Load Capacitance(CL1=CL2) - - - pF
RS Series Resistance(ESR) - - -
Duty Cycle 30 50 70 %
CM Motional Capacitance - - - pF
CSHUT Shunt Capacitance - - - pF
RBIAS Internal Bias Resistor - - - M
5.5. POWER UP/DOWN SEQUENCE

The following figure shows an example of the power-up sequence for A20 device.During the entire power-up
sequence,the PWROK pin must be held low until all power domains are stable.
The following figure shows an example of the power-down sequence for A20 device.Power-down is achieved by
setting PWRON input to 0.When this occurs,except VCC-DRAM,other voltages ramp down at the same time.The
ramp down rate of each voltage is generally determined by the load on that voltage.Depending on the different
application solution,the ramp down rate of each voltage is different.
Pin Assignment
6 PIN ASSIGNMENT
6.1. PIN MAP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
A PH15 PH13 PH10 PH6 PH3 PH0 PB22 PB18 PB16 PB14 PB8 PB6 PB4 PB2 PB0 PI8 PI6 PI4 PI2 PI0 PE11 PE9 PE8 A
B PH16 PH14 PH11 PH7 PH4 PH1 PB23 PB19 PB17 PB15 PB13 PB7 PB5 PB3 PB1 PI9 PI7 PI5 PI3 PI1 PE10 PE7 PE6 B
C PH17 PH18 PH12 PH8 PH5 PH2 PB21 PB20 PB12 PB11 PB10 PB9 PA17 RESET# PI14 PI12 PI10 PG11 PG9 PG7 PG5 PE5 PE4 C
D PH19 PH20 PH21 PH9 PA0 PA2 PA4 PA6 PA8 PA10 PA12 PA14 PA16 PI19 PI15 PI13 PI11 PG10 PG8 PG4 PG3 PE3 PE2 D
VCC-
E PH22 PH23 PH24 PH25 PA1 PA3 PA5 PA7 PA9 PA11 PA13 PA15 PI21 PI20 PI18 PI17 PI16 PG6 PG2 PG1 PE1 PE0 E
PG
F X32KI X32KO PH26 PH27 NMI# VCC-PE PG0 PC24 PC18 PC17 F
VCC-
G SDQM3 SDQ29 GND GND PC23 PC15 PC14 PC11 PC10 G
DRAM
VCC- VCC- VDD- VDD- VDD-

H SDQ26 SDQ31 SVREF SVREF VCC VCC VDD-CPU VCC TEST VCC-PC PC13 PC12 PC9 PC8 H
DRAM PA CPU CPU CPU
VCC- VDD- VDD-

J SDQ24 SDQS3B SCK1B SCK1 GND VCC VCC GND VCC VDD-SYS VDD-SYS VCC-PC PC22 PC21 PC7 PC6 J
PA CPU CPU
VDD- VDD-
K SDQS3 SDQ27 SBA0 SBA2 GND VDD-RTC GND GND GND GND VDD-SYS VDD-USB PF5 PF4 PC20 PC5 PC4 K
SYS SYS
VCC- VDD-
L SDQ25 SDQ28 SA10 SBA1 VDD-SYS GND GND GND GND GND VCC-USB VCC-USB PF3 PF2 PC19 PC3 PC2 L
DRAM SYS
VCC-
M SDQ30 SDQ23 SA7 SA3 VDD-DLL GND GND GND GND GND GND VDD-SATA VDD-SATA PF1 PF0 PC16 PC1 PC0 M
DRAM
VDD- VDD25- VDD25-

N SDQ22 SDQ17 SCKE SA5 GND SADBG GND GND GND GND GND VCC-PF DM0 DP0 X24MO X24MI N
DLL SATA SATA
VDD- SATA-
P SDQ19 SDQS2B SA12 SA9 GND SDDBG0 GND GND GND GND GND GND VCC-PLL DM1 DP1 HHPD HCEC P
DLL CLKM
VCC- VDD- VDD- SATA-

R SDQS2 SDQM2 SA14 SA1 SDDBG1 GND GND GND NC PLLVREG NC DM2 DP2 HSDA HSCL R
DRAM SYS SYS CLKP
VCC- JTAG- VCC- SATA-

T SDQ20 SDQ16 SWE SRAS VDD-SYS VDDQE GND GND HVREG1 PLLTEST PLLDV AVCC SATA-TXP HTX2N HTX2P T
DRAM SEL HMDI TXM
SATA- SATA-
U SDQ21 SDQ18 SCAS SA2 GND AGND HTX1N HTX1P U
RXM RXP
REXT-
V SCK SCKB SCS SA6 GND GND-HP VRA2 HTX0N HTX0P V
SATA
VCC- VCC- VCC- VCC- VCC- VCC- VCC- VCC25-

W SDQM1 SDQ13 SA11 SA0 BOOTSEL GND GND GND VCC-TVIN GND HPR VRA1 VRP HTXCN HTXCP W
DRAM DRAM DRAM LVDS LVDS LVDS TVOUT TVIN
VCC-
Y SDQ10 SDQ15 SA13 SA4 SVREF GND GND PD24 PD20 PD18 PD16 PD14 PD12 PD10 VRN-TVIN TVIN3 GND HPL FMINL FMINR TPX1 TPY1 Y
DRAM
AA SDQ8 SDQS1B SA8 SA15 SODT SRST SZQ SVREF PD25 PD21 PD19 PD17 PD15 PD13 PD11 VRP-TVIN TVIN2 GND HPCOM HPCOMFB VMIC TPX2 TPY2 AA
AB SDQS1 SDQ11 SDQ14 SDQ6 SDQ3 SDQS0 SDQ4 SDQ5 PD26 PD22 PD8 PD6 PD4 PD2 PD0 TVOUT1 TVOUT3 TVIN1 VCC-HP LINEINL LINEINR LRADC1 LRADC0 AB
AC SDQ9 SDQ12 SDQ7 SDQ1 SDQS0B SDQM0 SDQ0 SDQ2 PD27 PD23 PD9 PD7 PD5 PD3 PD1 TVOUT0 TVOUT2 TVIN0 HPBP MICIN1 MICIN2 MICOUTP MICOUTN AC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Pin Assignment
6.2. PACKAGE DIMENSION

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A20

Copyright 2015 Allwinner Technology Co., Ltd. All Rights Reserved.

THE INFORMATION FURNISHED BY ALLWINNER IS BELIEVED TO BE ACCURATE AND RELIABLE.

THIRD PARTY LICENCES MAY BE REQUIRED TO IMPLEMENT THE SOLUTION/PRODUCT. CUSTOM-

Copyright 2015 Allwinner Technology Co., Ltd. All Rights Reserved.

Allwinner Technology Co., Ltd.

Contact Us: service@allwinnertech.com

Revision Date Description

CHAPTER 3 BLOCK DIAGRAM...................  10

CHAPTER 4 PIN DESCRIPTION.................  11

CHAPTER 5 ELECTRICAL CHARACTERISTICS....  31

CHAPTER 6 PIN ASSIGNMENT 35

Dual-Core CPU SDRAM

System Resources Alpha

GIC Video Output

Video Engine (Phoenix 3.0)

Analog Audio Output GMAC

Stereo audio DAC Comply

Stereo capless headphone drivers Programmable

RTP Open-Drain TWI

USB EHCI/OHCI UART

SATA Power Management

4.1. PIN CHARACTERISTICS

Default Default Pull Buffer

Default Default Pull Buffer

Default Default Pull Buffer

Default Default Pull Buffer

Default Default Pull Buffer

Default Default Pull Buffer

Default Default Pull Buffer

Default Default Pull Buffer

4.2. GPIO MULTIPLEXING FUNCTIONS

4.3. DETAILED PIN/SIGNAL DESCRIPTION

Pin/Signal Description Type

Pin/Signal Description Type

Pin/Signal Description Type

Pin/Signal Description Type

Pin/Signal Description Type

4.4. POWER SIGNAL DESCRIPTION

SIGNAL DESCRIPTION BALL#

5.1. ABSOLUTE MAXIMUM RATINGS

SYMBOL PARAMETER MIN MAX UNIT

5.2. RECOMMENDED OPERATING CONDITIONS

SYMBOL PARAMETER MIN TYP MAX UNIT

5.3. DC ELECTRICAL CHARACTERISTICS

5.4. OSCILLATOR ELECTRICAL CHARACTERISTICS

5.4.1. 24MHz OSCILLATOR CHARACTERISTICS

SYMBOL PARAMETER MIN TYP MAX UNIT

SYMBOL PARAMETER MIN TYP MAX UNIT

5.4.2. 32768HZ OSCILLATOR CHARACTERISTICS

5.5. POWER UP/DOWN SEQUENCE

6.1. PIN MAP

VCC- VCC- VDD- VDD- VDD-

VCC- VDD- VDD-

VDD- VDD25- VDD25-

VCC- VDD- VDD- SATA-

VCC- JTAG- VCC- SATA-

CHAPTER 3 BLOCK DIAGRAM................... 10

CHAPTER 4 PIN DESCRIPTION................. 11

CHAPTER 5 ELECTRICAL CHARACTERISTICS.... 31

CHAPTER 6 PIN ASSIGNMENT 35