Digital Electronics Lab Manual
Digital Electronics Lab Manual
Digital Electronics Lab Manual
IC 7486
IC 7408
IC 7432
14 13 12 11 10 9 8
Vcc
IC 7411 IC 7400
Gnd
1 2 3 4 5 6 7
Aim:
To design, Implement and verify the truth table of adder using logic gates.
Apparatus Required:
2. OR GATE IC 7432 1
5. PATCH CORD - -
A half adder is a combinat onal c rcu t that performs the sum of two binary digits (A, B) to give a
maximum of two binary outputs amely the sum(S) and the carry(C). Carry is the higher order bit
and the sum is the low ord r b t of the output. The Boolean expression for the sum(S) and
carry(C) of half add r is,
S =A B C= AB
Full Adder:
A full adder is a combinational circuit that performs the sum of three binary digits (A, B,
Cin) to give a maximum of two binary outputs namely the sum(S) and the carry- out (Cout).The
full adder becomes necessary when a carry input must be added to the two binary digits to
obtain the correct sum. A half adder has no input for carries from previous circuits. The
Boolean expression for the sum (S) and carry-out (Cout) of full adder is,
Truth Table:
A B CARRY(C)SUM(S)
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
A 0 1 A 0 1
0 1 0
1 1 1 1
Full Adder:
A 1 3 4 6 S=ABCin
B 2 IC 7486 5 IC 7486
Cin 1
3
2 IC 7408 1 3 Cout = AB+ACin+BCin
4 2
6 IC 7432
5 IC 7408 Truth
Table:
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
Sum (S) =
AB
Cin
CARRY
(Cout) =
AB + BCin + ACin
Aim:
To design, Implement and verify the truth table subtractor using logic gates.
Apparatus Required:
3. OR GATE IC 7432 1
rejinpaul
6. PATCH CORD - -
Theory:
Half Subtractor:
A half subtractor is comb nat onal c rcuit that performs the difference between two binary
digits (A, B) to give maximum of two binary outputs namely the Difference (Diff) and the
Borrow (Brw) The Bo ow output here specifies whether a 1 has been borrowed to perform the
.
subtraction. The Bool an xp ssion for the difference (Diff) and borrow (Brw) of half subtractor
is,
Diff = A B Brw= AB
Full Subtractor:
A full subtractor is a combinational circuit that performs the three bit subtraction (A, B, Bin)
to give a maximum of two binary outputs namely the difference (Diff) and the borrow (Bout).
Full subtractor takes into consideration whether a 1 has already been borrowed by the
previous adjacent lower minuend or not. The Boolean expression for the difference (Diff) and
borrow (Bout) of full subtractor is,
A 1 3 Diff = A B
2
B
IC 7486
1 2 1 3 Brw = AB
IC 7404 2 IC 7408
Truth Table:
A B BORROW DIFFERENCE
(Brw) (Diff)
0 0 0 0
0 1 1 1
1 0 0 1
1 1 0 0
B B
A 0 1 A 0 1
0 1 0 1
1 1 1
Truth Table:
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 1 0
1 0 0 0 1
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
Differen
ce (Diff)
=
A B
Bin Borrow (Bout) = AB + ABin + BBin
Thus the subtractor was designed and implemented with their truth table verified using logic
gates.
Code Converters:
Aim:
To design, implement and verify the following code converters using logic gates,
a) BCD to Excess-3 code converter
b) Excess-3 to BCD code converter
Apparatus Required:
3. OR GATE IC 7432 1
7. PATCH CORD - -
Theory:
Code Converters:
The availability of large variety of codes for the same discrete elements of information results
in the use of different codes by different systems. A conversion circuit must be inserted between
the t o systems if each uses different codes for same information. Thus, code converter is a
circuit that makes the two systems compatible even though each uses different binary code.
Binary Coded Decimal:
Binary Coded Decimal is a method of using binary digits to represent the decimal digits 0
through 9. It is possible to assign weights to the binary bits according to their positions. The
weights in the BCD code are 8, 4, 2 and 1. Ex: (127) 10 - BCD equivalent (0001 0010 0111)2.
X3 = B0B2 + B1B2 + B3
_ _
X2 = B0B2 + B1B2 + B0B1B2
This is an un-weighted code. Its code assignment is obtained from the corresponding value of
BCD after the addition of (0011)2.
BCD to Excess-3 (or) Excess-3 to BCD:
Since each code uses four bits to represent a decimal digit, there must be four inputs and four
output variables. Four binary variables have sixteen different input combinations, only ten of the
input combinations are listed in the truth table. The six bit combinationscomnotlistedforthe input
variables are dont care combination. For BCD to Excess-3, the input variable are designated as B3,
B2, B1, B0 and the output variables are designated as X3, X2, X1, X0 in the truth table. The
Boolean functions are obtained from K-Map for each output variable. The binational logic for the code
converters are designed according the Boolean expressi ns from K-Map simplification. The Boolean
expressions from the K-Map are shown bel w.
_______
X1 = B0 B1
_
X0 = B0
B3 = X0X1X3 + X2X3
_
B2 = X0X2 + X0X1X2 + X1X2
B 1 = X0 X1
B 0 = X0
Procedure:
1. Verify the gates.
2. Make the connections as per the circuit diagram.
3. Switch on VCC and apply various combinations of input according to truth table.
4. For all input combinations the outputs are verified with the truth table.
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0
X0 = B0
B0 = X0 B1 = X1 X0
Thus BCD to Excess-3 and Excess-3 to BCD converters are designed, constructed using logic
gates and their truth table was verified.
Code Converters:
Aim:
To design, implement and verify the following code converters using logic gates,
a) Binary to Gray code converter
b) Gray to Binary code converter
Apparatus Required:
3. PATCH CORD - -
The availability of la ge va ty of codes for the same discrete elements of information results in
the use of diffe ent cod s by diff rent systems. A conversion circuit must be inserted between the
two systems if ach us s diff rent codes for same information. Thus, code converter is a circuit
that makes the two systems compatible even though each uses different binary code.
To obtain a different gray code, one can start with any bit information and proceed to obtain
the next bit combination by changing only one bit from 0 to 1 (or) 1 to 0 in any desired random
fashion provided any two numbers do not have identical code assignments.
Binary to Gray (or) Gray to Binary:
To convert from binary code to Gray code, the input lines must supply the bit combination of
elements as specified by the code and the output lines generate the corresponding bit
combination of code. Each one of the four maps represents one of the four outputs of the circuit
as a function of the four input variables.
B B B B
3 2 1 0
BINARY 1 0 1 1
+ + +
GRAY 1 1 1 0
G3 G2 G1 G0
rejinpaul
In the conversion process the most significant bit (MSB) of the binary code is taken as the
MSB of the Gray code. The bit positions G2, G1 nd G0 is obtained by adding (B3, B2), (B2,
B1) and (B1, B0) respectively, ignoring the c rry generated. From the K-Map simplification for
binary to Gray code conversion the following Boole expressions are obtained,
G = B3
3
G = B3 B
2 2
G1 = B2 B1
G0 = B1 B0
Conversion Steps:
The example sho s the steps involved in conversion of a Gray code to binary code.
Gray code taken for the example is 1110.
G G G G
3 2 1 0
GRAY 1 1 1 0
+ + +
BINARY 1 0 1 1
B3 B2 B1 B0
B3 B2 B1 B0 X3 X2 X1 X0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0
G0 = B1 B0 G1 = B1 B2
In the conversion process the most significant bit (MSB) of the Gray code is taken as the MSB of
the binary code. The bit positions B2, B1 and B0 is obtained by adding (B3, G2), (B2, G1) and
EC2207 ~ 27 ~ DIGITAL ELECTRONICS LAB
(B1, G0) respectively, ignoring the carry generated. From the K-Map simplification for Gray
code to binary code conversion the following Boolean expressions are obtained,
B3 = G3
B 2 = G3 G2
B 1 = G3 G2 G1
B 0 = G3 G2 G1 G0
Procedure:
1. Verify the gates.
2. Make the connections as per the circuit diagram.
3. Switch on VCC and apply various combinations of input a ording to truth table.
4. For all input combinations the outputs are verified with the truth table.
K-Map for
G2: K-Map for
EC2207 ~ 28 ~ DIGITAL ELECTRONICS LAB
G3:
G2 = B2 B3 G3 = B3
B0 = G1 G2 G3 G4 B1 = G1 G2 G3
B2 = G2 G3 B3 = G3
Thus Binary to Gray and Gray to Binary converters are designed, constructed using logic
gates and their truth table was verified.
Aim:
To design and implement 4 bit binary adder and 4 bit binary subtractor using IC 7483.
Apparatus Required:
4. PATCH CORD - -
Theory:
A 4 bit binary adder can be co structed using four full adders. Here the full adders are
connected in cascade, with the output carry from each full adder connected to the input carry of
next full adder in chain. The nput carry to the adder is C 1 and it ripples through the full adder to
the output carry C4.
Binary subtraction is done using 2s complement subtraction method. For subtracting B from
A using adders, S = A + B + 1. A 4 bit binary subtractor using 4 bit binary adder consists of
inverted B inputs and the carry input C 1 set to 1.
A4 bit binary adder/subtractor is used to perform both addition and sub-traction using a
control line add/sub. If add/sub =0 binary addition takes place and if add/sub = 1 binary
subtraction takes place, i.e. 2s complement subtraction of B from A.
Pin Diagram:
EC2207 ~ 32 ~ DIGITAL ELECTRONICS LAB
4 Bit Adder/Subtractor circuit diagram:
Procedure:
EC2207 ~ 33 ~ DIGITAL ELECTRONICS LAB
1. Verify the gates.
2. Make the connections as per the circuit diagram.
3. Switch on VCC and apply and verify various combinations of input according to the
truth table for 4 bit binary adder/subtractor,
a) By keeping add/sub as low, binary addition takes place.
b) By keeping add/sub as high, binary subtraction takes place.
A4 A3 A2 A1 B4 B3 B2 B1 Cout S4 S3 S2 S1 Bout D4 D3 D2 D1
1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0
1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0
0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0
0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0
1 0 1 0 1 0 1 1 1 0 1 0 1 0 1 1 1 1
1 1 1 0 1 1 1 1 1 1 1 0 1 0 1 1 1 1
1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1
Result:
Aim:
To design and implement BCD adder using 4 bit binary adder IC 7483.
Apparatus Required:
3. OR GATE IC 7432 1
5. PATCH CORD - -
Binary Coded Decimal is a method of usi g binary digits to represent the decimal digits 0 through
9. The valid BCD numbers are (0000 to 1001) BCD. Each digit of the decimal number will be
represented by its four bit binary equivalent. Ex: (127) 10 - BCD equivalent (0001 0010 0111)2.
In BCD addition the following thr cases are observed,
1. The resulting BCD numb qual to less than (1001)BCD.
For case 2 and 3, the result is added with correction factor (0110) BCD so that the result is in
valid BCD number.
Pin Diagram:
EC2207 ~ 38 ~ DIGITAL ELECTRONICS LAB
Logic Diagram:
BCD Adder:
BCD Adder:
Where S4, S3, S2, S1 are the sum of the BCD from the first binary adder with S4 as the MSB
and S1 as the LSB. Cout1 is the carry output from the first binary adder.
Procedure:
A4 A3 A2 A1 B4 B3 B2 B1 Cout X4 X3 X2 X1
1 0 0 0 0 0 1 0 1 0 0 0 0
1 0 0 0 1 0 0 0 1 0 1 1 0
1 0 0 1 1 0 0 1 1 1 0 0 0
0 1 1 1 0 0 0 1 0 1 0 0 0
Result:
Thus BCD adder was designed and implemented using IC 7483 with their truth table verified.
EC2207 ~ 41 ~ DIGITAL ELECTRONICS LAB
EC2207 ~ 42 ~ DIGITAL ELECTRONICS LAB
EX: NO: DATE:
Design and Implementation of 2 Bit Magnitude Comparator:
EC2207 ~ 43 ~ DIGITAL ELECTRONICS LAB
Aim:
Apparatus Required:
3. OR GATE IC 7432 1
7. PATCH CORD - -
Theory:
The comparison of two numbers s an operation that determines one number is greater than,
less than (or) equal to the other umber. A magnitude comparator is a combinational circuit that
compares two numb rs A and B to determine their relative magnitude. The outcome of the
comparator is specifi d by thr binary variables that indicate whether A>B, A=B (or) A<B.
Consider two numb s A and B with two digits each. Here A = A1 A0 and B = B1 B0.
Now the Boolean equation for the two numbers to be equal to, greater than and lesser than are
as follo s,
Logic Diagram:
Aim:
Apparatus Required:
3. PATCH CORD - -
Theory: rejinpaul
The magnitude comparator is combinational circ it that compares two numbers A and B to
determine their relative magnitude. The outcome of the comparator is specified by three binary
variables that indicate whether A>B, A=B (or) A<B.
IC 7485 is a four bit mag tude com arator that compares two four bit inputs (A3, A2, A1, A0) and
(B3, B2, B1, B0). By cascading IC 7485 it is possible to construct n-bit comparators. Two IC 7485
is cascaded for the construction of one eight bit comparator. First the LSB of both A and B namely
(A3, A2, A1, A0) and (B3, B2, B1, B0) is compared for cascading outputs 1(A>B), 1(A=B) and
1(A<B). The operation of the first four bit comparator is as follows. Depending on wheth A3>B3
(or) A3<B3 the cascading outputs of the 4-bit comparator 1(A>B) (or) 1(A<B) are activat d. But if
A3=B3, then the next MSB bits B2 and A2 are compared. Similarly, if A2=B2 then comparison of
A1 and B1 is performed and so on. Note if all the inputs (A3, A2, A1, A0) and (B3, B2, B1, B0) are
equal then the IC 7485 will check for the cascading inputs. Function table for IC 7485 consolidates
this operation. The intermediate outputs of the
first four bit comparator are the intermediate inputs to the second four bit comparator. The
second magnitude comparator gives the final outputs, whether A>B (or) A<B (or) A=B.
Procedure:
1. Verify the gates.
2. Make the connections as per the circuit diagram.
3. Switch on VCC and apply various combinations of input according to truth table.
4. For all input combinations the outputs are verified with the truth table.
Logic Diagram:
O/P
TRUTH TABLE:
Inputs Outputs
Result:
Aim:
Apparatus Required:
4. Patch cord - -
When digital data is transmitted from one loc tion to another, it is necessary to know at
the receiving end, whether data received is free from errors. To help make the transmission
accurate, special error detect on methods are used. To detect errors there must be constant check
on the data being transmitted. To check accuracy of the data an extra bit can be generated and
transmitted along with the data. Th s b t s called the parity bit. A parity bit is used for detecting
errors during transmission of binary information.
Parity gene ato s e circuits that accept an n-1 bit data stream and generate an extra bit
that is transmitted ith the bit stream. This extra bit is referred to as parity bit. In an even parity
bit scheme, the parity bit is 1 if there are odd number of 1s in the data stream and the parity
bit is 0 if there are even number of 1s in the data stream. In the case of odd parity bit scheme,
the reverse happens, that is the parity bit is 0 for odd number of 1s and 1 for even number of
1s in the bit stream.
{Inputs} {Inputs}
I I I I I O / E I I I I I I
I0 I1 I2 3 4 5 6 7 I8 I9 10 11 12 13 14 15
7
4
1
2 1 13 12 11 10 9 8 PE 2 1 13 12 11 10 9 8
Vcc 14 3 0
2 4
14 Vcc
IC 74180 (1) PE 3 IC 74180 (2)
Gnd 7 Gnd
4 4 7
PO PO
5 6 5 6
E O
E O
{Outputs}
Truth Table:
1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0
1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1
1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0
Procedure:
1. Verify the gates.
EC2207 ~ 57 ~ DIGITAL ELECTRONICS LAB
2. Make the connections as per the circuit diagram.
3. Switch on VCC and apply various combinations of input according to truth table.
4. For all input combinations the outputs are verified with the truth table.
Result:
Thus a 16-bit parity generator was designed and implemented using IC74180 with its truth
table verified.
Apparatus Required:
4. Patch cord - -
Theory: rejinpaul
A parity bit is used for detecting errors d ring tr nsmission of binary information. A
parity bit is an extra bit included with a bin ry mess ge to make the number as either even or
odd. The message including the parity bit is tr nsmitted nd then checked at the receiver end for
errors. An error is detected if the checked arity bit doesnt correspond to the transmitted parity
bit. The circuit that generates the par ty b t in the transmitter is called a parity generator and
the circuit that checks the parity n the rece ver is called a parity checker.
In even parity, the add d par ty bit will make the total number of 1s as even. In odd
parity, the added pa ity bit will make the total number of 1s as odd. The parity checker circuit
checks for possible o s the transmission. If the information is passed in even parity, then the bits
required must have an even number of 1s. An error occur during transmission, if the received
bits have an odd number of 1s indicating that one bit has changed in value during transmission
Truth Table:
I7 I6 I5 I4 I3 I2 I1 I0 I7I6I5I4I3I211 I0 Active E O
0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 0
0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 1 0
0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 1 0 1
Procedure:
1. Verify the gates.
EC2207 ~ 61 ~ DIGITAL ELECTRONICS LAB
2. Make the connections as per the circuit diagram.
3. Switch on VCC and apply various combinations of input according to truth table.
4. For all input combinations the outputs are verified with the truth table.
Result:
Thus a 16-bit parity checker was designed and implemented using IC74180 with its truth
table verified.
To design and implement multiplexer and de-multiplexer using logic gates, study of IC 74150
and IC 74154.
Apparatus Required:
2. OR GATE IC 7432 1
5. - -
rejinpaul
PATCH CORD
Multiplexer is a combinational circuit that selects binary information from one of many input
lines and directs it to a single output li e. Selection of input lines controlled by a set of selection
lines 2n input lines and n select on l es. Multiplexers are used to form a selected path between
multiple sources and single dest at on.
De-Multiplexe :
De-multiplexer is ci cuit that receives information on single line and transmits the
n
information on one of 2 possible output lines. Selection of specific output lines is controlled
by n selection lines
IC74150 16 to 1 Multiplexer:
IC74150 is a data selector/multiplexer IC that selects one of the sixteen data sources E0 to
E15. The STROBE input of the IC must be at a low logic level to enable these devices. A high
level at the STROBE forces the Q output high. IC 74150 is used in parallel to serial conversion.
In digital communication, a number of input lines are connected to a single output channel
using multiplexer, so that information transmitted one by one in a time shared basis.
Logic Diagram:
4:1 Multiplexer:
EC2207 ~ 64 ~ DIGITAL ELECTRONICS
LAB
S0 S1
7404
7404
1 3
IC
IC
2 4
D0 13 1 12
2 IC 7411
1 3
D1 4 3 6
2 IC 7432
5 10 8
IC 7411 Output
D2 11 10 8 9 IC 7432
9
IC 7411 4 6
D3 13 1 12 5 IC 7432
2
IC 7411
Truth Table:
S0 S1 Output
0 0 D0
0 1 D1
1 0 D2
1 1 D3
Output = D0S0S1+D1S0S1+D2S0S1+D3S0S1
IC74154 1 to 16 De-Multiplexer:
Procedure:
1. Verify the gates.
2. Make the connections as per the circuit diagram.
3. Switch on VCC and apply various combinations of input according to truth table.
4. For all input combinations the outputs are verified with the truth table.
Logic Diagram:
1:4 De-multiplexer:
EC2207 ~ 66 ~ DIGITAL ELECTRONICS LAB
Truth Table:
Input Output
D S0 S1 D0 D1 D2 D3
1 0 0 D 0 0 0
1 0 1 0 D 0 0
1 1 0 0 0 D 0
1 1 1 0 0 0 D
D0 = DS0S1
D1 = DS0S1
D2 = DS0S1
D3 = DS0S1
Result:
EC2207 ~ 69 ~ DIGITAL ELECTRONICS LAB
Thus multiplexer and de-multiplexer was designed and implemented using logic gates with
their truth table verified. Multiplexer and De-multiplexer, IC 74150 and IC 74154 are studied.
Aim:
To design and implement encoder and decoder using logic gates, study of IC7445 and
IC74147.
Apparatus Required:
2. OR GATE IC 7432 1
5. PATCH CORD - -
n
An encoder is a combinat o al log c c rcuit that has 2 input lines and n output lines. As an
example consider an four input a d two output encoder. It is assumed that only one input has 1
at any given time. From truth table, t s obvious that the output is 1 for A when the input is 2
and 3; B is 1 when the input s 1 and 2.
n
A decoder is a combinational circuit that converts -bit binary input lines into 2 output lines
such that output line ill be activated for only one of possible combination of inputs. The outputs
are selected based on two select inputs. The inputs AB are decoded into four digits output each
representing one of minterms of two input variables.
IC 7445 is a BCD to decimal decoder that accepts 4 active high inputs and produces ten
active low outputs. Full decoding of BCD input logic ensures that all outputs remain OFF for
all invalid (10101111) binary input conditions. IC 7445 is widely used in BCD to seven
segment display. It is also used as address decoders where the decoded output is used as chip
select signal to select the chip of interest.
Logic Diagram:
EC2207 ~ 72 ~ DIGITAL ELECTRONICS LAB
4x2 Encoder:
Truth Table:
Input Output
D0 D1 D2 D3 A B
1 0 0 0 0 0
0 1 0 0 0 1
0 0 1 0 1 0
0 0 0 1 1 1
A = D2 + D3
B = D1 + D3
Procedure:
1. Verify the gates.
2. Make the connections as per the circuit diagram.
3. Switch on VCC and apply various combinations of input a rding to truth table.
4. For all input combinations the outputs are verified with the truth table.
Logic Diagram:
EC2207 ~ 74 ~ DIGITAL ELECTRONICS LAB
2x4 De-Coder:
IC 7404
IC 7404
Truth Table:
Input Output
A B D0 D1 D2 D3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1
D0 = AB
D1 = AB
D2 = AB
D3 = AB
EC2207 ~ 75 ~ DIGITAL ELECTRONICS LAB
Pin Diagram IC7445:
Result:
EC2207 ~ 77 ~ DIGITAL ELECTRONICS LAB
Thus the Encoder and De-Coder were designed and implemented using logic gates with their
truth table verified. Encoder and De-Coder, IC 7445 and IC 74147 are studied.
Aim:
Apparatus Required:
4. PATCH CORD - -
Theory: rejinpaul
Counters are a group of flip flops connected together to perform counting operation.
According to the way the flip flops are clocked, there are two ty es of flip flops,
a) Asynchronous Counter
b) Synchronous Counter
In asynchronous counter, the f rst fl flop is clocked by the external clock pulse. Then each
successive flip flops are clock d by Q (or) Q output of the previous flip flop. In 4-bit ripple
4
counter, the total numb of stat s is 16 (2 ) and this varies from 00002 to 11112
Procedure:
1. Verify the flip flop
2. Make the connections as per the circuit diagram.
3. S itch on VCC and apply various combinations of input according to truth table.
4. By applying clock pulse, all the input combinations are given and the outputs are
verified ith the truth table.
Clk Qd Qc Qb Qa
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1
Result:
Aim:
Apparatus Required:
4. PATCH CORD - -
rejinpaul
Theory:
Counters are a group of flip flops connected together to perform counting operation.
According to the way the flip flops are clocked, there are two ty es of flip flops,
c) Asynchronous Counter
d) Synchronous Counter
In asynchronous counter, the f rst fl p flop is clocked by the external clock pulse. Then each
successive flip flops are clock d by Q (or) Q output of the previous flip flop. In 4-bit ripple
4
counter, the total numb of stat s is 16 (2 ) and this varies from 0000 2 to 11112. If the counters
are designed with numb of s qu nce which is less than 2 , then those counters are said to be
Mod N counte s whe e N denotes number of sequence. Thus in Mod10 counter, total number
of states is 10 and number of flip flops are 4. Similarly Mod12 counter, total number of states
is 10 and number of flip flops are 4.
Procedure:
1. Verify the flip flop.
2. Make the connections as per the circuit diagram.
3. Switch on VCC and apply various combinations of input according to truth table.
4. By applying the clock pulse, all the input combinations are given and the outputs are
verified with the truth table.
Mod 10 Counter:
Clk Qd Qc Qb Qa
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 0 0 0 0
Clk Qd Qc Qb Qa
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 0 0 0 0
Result:
To design, implement 3 bit synchronous up/ down counter and verify its truth table.
Apparatus Required:
3. OR GATE IC 7432 1
5. 1
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6. PATCH CORD - -
A counter that advances upward through its sequence (0, 1, 2, 3...0, 1.) is called up counter.
A counter that decrement downward through its sequence (3, 2, 1, 0, 3, 2 ..) is called down
counter. A up/down counter s cou ter used to perform both up counting and down counting
operation using up/down control s g al.
1J, 2J = J Input
1k, 2k = K Input
1Q, 2Q = Q Output
1Q, 2Q = Q Output
Logic Diagram:
J K Qn+1 Qn Qn+1 J K
0 0 Qn 0 0 0 X
0 1 0 0 1 1 X
1 0 1 1 0 X 1
1 1 Qn 1 1 X 0
Input
Up/Down Present State Next State Flip Flop Input
JA = 1 JB = XQA+ XQA
JC = XQB QA + XQBQA KA = 1
K-Map for K B : K-Map for K C:
Thus 3 bit synchronous up/ down counter was designed and implemented with its truth
table verified.
parallel form
Procedure:
To implement SISO and SIPO shift registers using flip flop with its truth table verified.
Apparatus Required:
3. PATCH CORD - -
a shift register. The logic types of shift registers in terms of d ta movement are,
In Serial Out:
SISO shift register accepts data ser ally (i.e.) one bit at a time on a single line and produces
In Parallel Out:
SIPO shift register acc pts data s rially and produces the stored information on its output in
2. Make the connections as per the circuit diagram.
3. S itch on VCC and apply various combinations of input according to truth table.
4. By applying the clock pulse, all input combinations are given and the outputs are
verified ith the truth table.
Logic Diagram:
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Serial In Serial Out:
Thus SISO and SIPO shift registers are implemented using flip flop with its truth table verified.
To implement PIPO and PISO shift registers using flip flop with its truth table verified.
Apparatus Required:
3. OR GATE IC 7432 1
4.
rejinpaul
6. PATCH CORD - -
Theory:
A register capable of shift ng ts b ary i formation either to the right or to the left is called a
shift register. The logic typ s of shift registers in terms of data movement are,
PIPO shift register accepts data parallel and produces the stored data on its output also in
parallel form on application of the clock input.
PISO shift register accepts data in parallel and produces the stored data on its output in
serial form. The data are presented on the input lines Da to Dd in parallel. The data loads
into the register hen the Shift/Load control lines is held low. When the Shift/Load is held
high the data stored are clocked out serially.
Procedure:
1. Verify the flip flop.
2. Make the connections as per the circuit diagram.
3. Switch on VCC and apply various combinations of input according to truth table.
4. By applying the clock pulse, all input combinations are given and the outputs are
verified with the truth table.
Logic Diagram:
QA QB QC QD
IC 7408
IC 7408
IC 7408
IC 7408
IC 7408
IC 7408
IC 7432
IC 7432
IC 7432
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Thus PISO and PIPO shift registers are implemented using flip flop with its truth table verified.