A B C D E

1 1

Compal Confidential
2 2

QCL40 MB Schematic Document

LA-8221P
3 3

Rev: 0.2
2011.09.28

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/07/12 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Sheet
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-8221P
Date: Wednesday, October 26, 2011 Sheet 1 of 58
A B C D E
 1 2 3 4 5

Compal Confidential
ZZZ1
QCL40
PCB-MB
PCB P/N for Load BOM DDR3 1333/1600MHz 1.5V DDR3-SO-DIMM X 2
BANK 0, 1, 2, 3
A Mobile +1.5V, +0.75VS A

Dual Channel Page 10, 11

NV N13P-GL PEG 16X Ivy Bridge

(N13M-GE1) Processor
rPGA 988B Socket
Page 4 ~ 9
Page 20 ~ 28 +VCC_CORE, +VCCP,
+VCC_GFXCORE_AVG, +1.5V_CPU_VDDQ, port 4
+1.8VS, _VCCSA
USB conn x1
USB Board Page 33
FDI x8
DMI x4
(UMA) 100MHz port 8
100MHz Camera
5GB/s Page 30
2.7GT/s
LCD conn LVDS, EDID, DISPOFF#, PWM USB2.0
Page 30
port 10 Card Reader Memory Card Slot
SD/MMC
RTS5137 Page 34
RGB, HV Sync, DDC Page 34
CRT Conn
B
Page 30 Intel port 9
B

MiniCard-2
HDMI, DDC
PANTHER-POINT Page 40

HDMI PCH
Page 35
port 0,1
USB3.0 conn x2
USB3.0 port 1,2
Page 36
HM77
Audio Jack (HP)
Page 33

Azalia Realtek
FCBGA 989 Balls ALC269 Page 33 Audio Jack (MIC)
Page 33

Page 12 ~ 19 SATA
Speaker Connector
Page 33
C C

PCI-e
port 0
+1.05VS, +1.8VS, +3VS, 2.5" SATA HDD Connector
port 1 port 2 +3V_PCH, +5V_PCH, +RTCVCC,
+VCCAFDI_VRM Page 31
LAN/CRT Board Mini Card-1
10/100/1000 LAN WLAN port 2
Realtek GbE Bluetooth SATA ODD Connector
RTL8111F Page 32 Page 40 Page 31

SPI SPI ROM

4MB+2MB
Page 12

LPC BUS

Touch Pad CONN. ENE KB9012QF

D
External board Reserve KB930F D
Page 38
+3VLP/+3VALW page 39 Int. KBD
Page 38
DC/DC Interface CKT. LS-4221P
Page 29,41 USB/B Page 33

SPI ROM
Security Classification Compal Secret Data Compal Electronics, Inc.
Fan Control Issued Date 2011/07/12 Deciphered Date 2012/12/31 Title

Page 37 Page 39 Block Diagram

256KB THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number
Custom
Rev
0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-8221P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 26, 2011 Sheet 2 of 58
1 2 3 4 5
 A

X76@: VRAMX16X8 VRAMX16X4 VRAMX8X8

N13P-GS N13P-GL N13M-GE1 N13M-GE1 x8 CLKOUT DESTINATION USB3 PORT DESTINATION USB2 PORT DESTINATION
ER37 ZZZ11 X76L11@ ZZZ X76L01@ ZZZ3 X76L03@ ZZZ7 X76L07@
PCI0 PCH_LOOPBACK 1 USB2.0+3.0 0 USB2.0+3.0

PCI1 EC PCH 2 USB2.0+3.0 1 USB2.0+3.0

2G HYN 2G SAM 1G SAM 2G HYN

ZZZ12 X76L12@ ZZZ2 X76L02@ ZZZ4 X76L04@ ZZZ8 X76L08@ PCI2 None 3 None 2 None

PCI3 LPC Debug Port 4 None 3 None

2G SAM 2G HYN 1G HYN 2G ELP
PCI4 None 4 JMINI1 (WLAN) Bluetooth
ZZZ5 X76L05@ ZZZ9 X76L09@

5 None
Voltage Rails
1G SAM 4G ELP 6 None
Power Plane Description S1 S3 Deep S5
ZZZ10 X76L10@ S3
ZZZ6 X76L06@ VIN Adapter power supply (19V) N/A N/A N/A N/A PCH 7 None
BATT+ Battery power supply (12.6V) N/A N/A N/A N/A
B+ AC or battery power rail for power circuit N/A N/A N/A N/A 8 CAMERA
4G HYN
1G HYN +3VLP 3.3V power rail for 51ON power management ON ON ON ON
+3VALW 3.3V always on power rail ON ON ON AC/ON; DC/OFF 9 USB2
+LAN_IO 3.3V power rail for ethernet ON ON OFF OFF
N13P-GS N13P-GL N13M-GE1 N13M-GE1 x8 10 Card Reader
GS@ GL@ GE@ GE8@ +3VS_WLAN 3.3V power rail for WLAN/BT Combo ON OFF OFF OFF
+3V_PCH 3.3V power rail for PCH suspend well plane ON ON OFF OFF
U10 GE@ U10 GE8@
U10 GS@ U10 GL@ +3VS 3.3V power rail for DDR SPI,PCH,HDD,Audio,Card Reader ON OFF OFF OFF 11 None
+3VSG 3.3V power rail for VGA ON OFF OFF OFF
+LCDVDD 3.3V power rail for LCD ON OFF OFF OFF 12 None
N13M-GE1 N13M-GE1 x8
N13P-GS N13P-GL +5VALW 5V always on power rail ON ON ON AC/ON; DC/OFF
+5V_PCH 5V power rail for PCH suspend well plane ON ON OFF OFF 13 None
+5VS 5V power rail for HDD,AUDIO,FAN,Touch PAD ON OFF OFF OFF
+5VS_ODD 5V power rail for SATA ODD ON OFF OFF OFF
VGA componet 930@: EC(ENE 930 chip)
DIS@: XDP@: Intel debug port +1.8VS 1.8V power rail for CPU,PCH ON OFF OFF OFF
GEL@: N13P-GL or N13M-GE1 +1.05VS 1.05V power rail for PCH ON OFF OFF OFF
GSL@: N13P-GL or N13P-GS +VCCP 1.05V power rail for CPU VCCIO,PCH ON OFF OFF OFF
GS@: N13P-GS IU3@: USB3.0 by PCH
+1.05VSG 1.05V power rail for N13P ON OFF OFF OFF
1 USB30@:USB3.0 controller IC 1

+1.5V 1.5V power rail for DDR3 system memory ON ON ON OFF

9012@: EC(ENE 9012 chip) AI@: AI Charger +1.5V_CPU_VDDQ 1.5V power rail CPU VDDQ ON OFF OFF OFF
NAI@: Non AI Charger +1.5VSG 1.5V power rail for N13P,VRAM ON OFF OFF OFF
SMBUS Control Table
+1.5VS 1.5V power rail for PCH,WLAN/BT combo ON OFF OFF OFF
+0.75VS 0.75V power rail for DDR VREF ON OFF OFF OFF
SOURCE MINI1 BATT PCH EC SODIMM DGPU +VCCSA VCCSA for CPU system agent ON OFF OFF OFF
+VCC_CORE CORE Voltage for CPU ON OFF OFF OFF
EC_SMB_CK1
EC_SMB_DA1
KB930 X V X X X X +VCC_GFXCORE_AXG

+VGA_CORE
1.5V power rail for N13P,VRAM
CORE Voltage for N13P Graphics ON OFF OFF
ON
ON
OFF
OFF
OFF
OFF
OFF
OFF
EC_SMB_CK2
EC_SMB_DA2
KB930 X X V X X V
PCI EXPRESS DESTINATION
PCH_SMBCLK SATA DESTINATION
PCH_SMBDATA PCH V X X X V X Lane 1 10/100/1G LAN
SATA0 HDD
PCH_SMLCLK
PCH_SMLDATA PCH
X X X V X V SATA1 None Lane 2 MINI CARD WLAN

Lane 3 None
DIFFERENTIAL DESTINATION FLEX CLOCKS DESTINATION SATA2 ODD
Lane 4 USB3.0 controller
SATA3 None
CLKOUT_PCIE0 10/100/1G LAN CLKOUTFLEX0 CLK_SD_48M
Lane 5 None
CLKOUT_PCIE1 MINI CARD WLAN CLKOUTFLEX1 None SATA4 None

SATA5 None Lane 6 None

CLKOUT_PCIE2 None CLKOUTFLEX2 None
Lane 7 None
CLK CLKOUT_PCIE3 USB3.0 controller CLKOUTFLEX3 None
Lane 8 None
CLKOUT_PCIE4 None

CLKOUT_PCIE5 None 6\PERO1RWH

CLKOUT_PCIE6 None PHDQV'LJLWDO*URXQG

CLKOUT_PCIE7 None Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/07/12 Deciphered Date 2012/12/31 Title
PHDQV$QDORJ*URXQG Notes List
CLKOUT_PEG_B None THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C
Size Document Number Rev
0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-8221P
Date: Wednesday, October 26, 2011 Sheet 3 of 58
A
 5 4 3 2 1

+1.05VS

1
JCPU1I
R1 PEG_ICOMPI and RCOMPO signals should be shorted and routed
24.9_0402_1% with - max length = 500 mils - typical impedance = 43 mohms
PEG_ICOMPO signals should be routed with - max length = 500 mils
T35 F22

2
JCPU1A
- typical impedance = 14.5 mohms VSS161 VSS234
T34 F19
D PEG_COMP VSS162 VSS235 D
J22 T33 E30
PEG_ICOMPI VSS163 VSS236
J21 T32 E27
PEG_ICOMPO VSS164 VSS237
14 DMI_CRX_PTX_N0 B27 H22 T31 E24
DMI_RX#[0] PEG_RCOMPO VSS165 VSS238
14 DMI_CRX_PTX_N1 B25 T30 E21
DMI_RX#[1] VSS166 VSS239
14 DMI_CRX_PTX_N2 A25 PCIE_GTX_C_CRX_N[0..15] 20 T29 E18
DMI_RX#[2] PCIE_GTX_CRX_N15 DIS@ C1 0.22U_0402_10V6K PCIE_GTX_C_CRX_N15 VSS167 VSS240
14 DMI_CRX_PTX_N3 B24 K33 1 2 T28 E15
DMI_RX#[3] PEG_RX#[0] PCIE_GTX_CRX_N14 DIS@ C2 0.22U_0402_10V6K PCIE_GTX_C_CRX_N14 VSS168 VSS241
M35 1 2 T27 E13
PEG_RX#[1] PCIE_GTX_CRX_N13 DIS@ C3 0.22U_0402_10V6K PCIE_GTX_C_CRX_N13 VSS169 VSS242
14 DMI_CRX_PTX_P0 B28 L34 1 2 T26 E10
DMI_RX[0] PEG_RX#[2] PCIE_GTX_CRX_N12 DIS@ C4 0.22U_0402_10V6K PCIE_GTX_C_CRX_N12 VSS170 VSS243
14 DMI_CRX_PTX_P1 B26 J35 1 2 P9 E9
DMI_RX[1] PEG_RX#[3] PCIE_GTX_CRX_N11 DIS@ C5 0.22U_0402_10V6K PCIE_GTX_C_CRX_N11 VSS171 VSS244
14 DMI_CRX_PTX_P2 A24 J32 1 2 P8 E8

DMI
DMI_RX[2] PEG_RX#[4] PCIE_GTX_CRX_N10 DIS@ C6 0.22U_0402_10V6K PCIE_GTX_C_CRX_N10 VSS172 VSS245
14 DMI_CRX_PTX_P3 B23 H34 1 2 P6 E7
DMI_RX[3] PEG_RX#[5] PCIE_GTX_CRX_N9 DIS@ C7 0.22U_0402_10V6K PCIE_GTX_C_CRX_N9 VSS173 VSS246
PEG_RX#[6] H31 1 2 P5 VSS174 VSS247 E6
G21 G33 PCIE_GTX_CRX_N8 DIS@ C8 1 2 0.22U_0402_10V6K PCIE_GTX_C_CRX_N8 P3 E5
14 DMI_CTX_PRX_N0 DMI_TX#[0] PEG_RX#[7] PCIE_GTX_CRX_N7 PCIE_GTX_C_CRX_N7 VSS175 VSS248
E22 G30 DIS@ C9 1 2 0.22U_0402_10V6K P2 E4
14 DMI_CTX_PRX_N1 DMI_TX#[1] PEG_RX#[8] VSS176 VSS249
F21 F35 PCIE_GTX_CRX_N6 DIS@ C10 1 2 0.22U_0402_10V6K PCIE_GTX_C_CRX_N6 N35 E3
14 DMI_CTX_PRX_N2 DMI_TX#[2] PEG_RX#[9] PCIE_GTX_CRX_N5 PCIE_GTX_C_CRX_N5 VSS177 VSS250
D21 E34 DIS@ C11 1 2 0.22U_0402_10V6K N34 E2
14 DMI_CTX_PRX_N3 DMI_TX#[3] PEG_RX#[10] PCIE_GTX_CRX_N4 PCIE_GTX_C_CRX_N4 VSS178 VSS251
E32 DIS@ C12 1 2 0.22U_0402_10V6K N33 E1
PEG_RX#[11] PCIE_GTX_CRX_N3 DIS@ C13 0.22U_0402_10V6K PCIE_GTX_C_CRX_N3 VSS179 VSS252
14 DMI_CTX_PRX_P0 G22 DMI_TX[0] PEG_RX#[12] D33 1 2 N32 VSS180 VSS253 D35
D22 D31 PCIE_GTX_CRX_N2 DIS@ C14 1 2 0.22U_0402_10V6K PCIE_GTX_C_CRX_N2 N31 D32
14 DMI_CTX_PRX_P1 DMI_TX[1] PEG_RX#[13] PCIE_GTX_CRX_N1 PCIE_GTX_C_CRX_N1 VSS181 VSS254
F20 B33 DIS@ C15 1 2 0.22U_0402_10V6K N30 D29
14 DMI_CTX_PRX_P2 DMI_TX[2] PEG_RX#[14] VSS182 VSS255

PCI EXPRESS* - GRAPHICS

C21 C32 PCIE_GTX_CRX_N0 DIS@ C16 1 2 0.22U_0402_10V6K PCIE_GTX_C_CRX_N0 N29 D26
14 DMI_CTX_PRX_P3 DMI_TX[3] PEG_RX#[15] VSS183 VSS256
PCIE_GTX_C_CRX_P[0..15] 20 N28 VSS184 VSS257 D20
J33 PCIE_GTX_CRX_P15 DIS@ C17 1 2 0.22U_0402_10V6K PCIE_GTX_C_CRX_P15 N27 D17
PEG_RX[0] PCIE_GTX_CRX_P14 DIS@ C18 0.22U_0402_10V6K PCIE_GTX_C_CRX_P14 VSS185 VSS258
PEG_RX[1] L35 1 2 N26 VSS186 VSS259 C34
K34 PCIE_GTX_CRX_P13 DIS@ C19 1 2 0.22U_0402_10V6K PCIE_GTX_C_CRX_P13 M34 C31
FDI_CTX_PRX_N0 PEG_RX[2] PCIE_GTX_CRX_P12 DIS@ C20 0.22U_0402_10V6K PCIE_GTX_C_CRX_P12 VSS187 VSS260
14 FDI_CTX_PRX_N0 A21 FDI0_TX#[0] PEG_RX[3] H35 1 2 L33 VSS188 VSS261 C28
FDI_CTX_PRX_N1 H19 H32 PCIE_GTX_CRX_P11 DIS@ C21 1 2 0.22U_0402_10V6K PCIE_GTX_C_CRX_P11 L30 C27
14 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI0_TX#[1] PEG_RX[4] PCIE_GTX_CRX_P10 PCIE_GTX_C_CRX_P10 VSS189 VSS262
E19 G34 DIS@ C22 1 2 0.22U_0402_10V6K L27 C25
14 FDI_CTX_PRX_N2 FDI0_TX#[2] PEG_RX[5] VSS190 VSS263
FDI_CTX_PRX_N3 F18 G31 PCIE_GTX_CRX_P9 DIS@ C23 1 2 0.22U_0402_10V6K PCIE_GTX_C_CRX_P9 L9 C23
14 FDI_CTX_PRX_N3 FDI0_TX#[3] PEG_RX[6] VSS191 VSS264
14 FDI_CTX_PRX_N4
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
B21
C20
FDI1_TX#[0] Intel(R) FDI PEG_RX[7] F33
F30
PCIE_GTX_CRX_P8
PCIE_GTX_CRX_P7
DIS@
DIS@
C24
C25
1
1
2
2
0.22U_0402_10V6K
0.22U_0402_10V6K
PCIE_GTX_C_CRX_P8
PCIE_GTX_C_CRX_P7
L8
L6
VSS192 VSS265 C10
C1
14 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI1_TX#[1] PEG_RX[8] PCIE_GTX_CRX_P6 PCIE_GTX_C_CRX_P6 VSS193 VSS266
D18 E35 DIS@ C26 1 2 0.22U_0402_10V6K L5 B22
C 14 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7 FDI1_TX#[2] PEG_RX[9] PCIE_GTX_CRX_P5 PCIE_GTX_C_CRX_P5 VSS194 VSS267 C
E17 E33 DIS@ C27 1 2 0.22U_0402_10V6K L4 B19
14 FDI_CTX_PRX_N7 FDI1_TX#[3] PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
F32
D34
PCIE_GTX_CRX_P4
PCIE_GTX_CRX_P3
DIS@
DIS@
C28
C29
1
1
2
2
0.22U_0402_10V6K
0.22U_0402_10V6K
PCIE_GTX_C_CRX_P4
PCIE_GTX_C_CRX_P3
L3
L2
VSS195
VSS196
VSS197
VSS VSS268
VSS269
VSS270
B17
B15
FDI_CTX_PRX_P0 A22 E31 PCIE_GTX_CRX_P2 DIS@ C30 1 2 0.22U_0402_10V6K PCIE_GTX_C_CRX_P2 L1 B13
14 FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI0_TX[0] PEG_RX[13] PCIE_GTX_CRX_P1 PCIE_GTX_C_CRX_P1 VSS198 VSS271
G19 C33 DIS@ C31 1 2 0.22U_0402_10V6K K35 B11
14 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI0_TX[1] PEG_RX[14] PCIE_GTX_CRX_P0 PCIE_GTX_C_CRX_P0 VSS199 VSS272
E20 B32 DIS@ C32 1 2 0.22U_0402_10V6K K32 B9
14 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI0_TX[2] PEG_RX[15] VSS200 VSS273
14 FDI_CTX_PRX_P3 G18 FDI0_TX[3] PCIE_CTX_C_GRX_N[0..15] 20 K29 VSS201 VSS274 B8
FDI_CTX_PRX_P4 B20 M29 PCIE_CTX_GRX_N15 DIS@ C33 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_N15 K26 B7
14 FDI_CTX_PRX_P4 FDI1_TX[0] PEG_TX#[0] VSS202 VSS275
FDI_CTX_PRX_P5 C19 M32 PCIE_CTX_GRX_N14 DIS@ C34 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_N14 J34 B5
14 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI1_TX[1] PEG_TX#[1] PCIE_CTX_GRX_N13 PCIE_CTX_C_GRX_N13 VSS203 VSS276
D19 M31 DIS@ C35 1 2 0.22U_0402_10V6K J31 B3
14 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7 FDI1_TX[2] PEG_TX#[2] PCIE_CTX_GRX_N12 PCIE_CTX_C_GRX_N12 VSS204 VSS277
F17 L32 DIS@ C36 1 2 0.22U_0402_10V6K H33 B2
14 FDI_CTX_PRX_P7 FDI1_TX[3] PEG_TX#[3] VSS205 VSS278
L29 PCIE_CTX_GRX_N11 DIS@ C37 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_N11 H30 A35
+1.05VS FDI_FSYNC0 PEG_TX#[4] PCIE_CTX_GRX_N10 DIS@ C38 0.22U_0402_10V6K PCIE_CTX_C_GRX_N10 VSS206 VSS279
14 FDI_FSYNC0 J18 K31 1 2 H27 A32
FDI_FSYNC1 FDI0_FSYNC PEG_TX#[5] PCIE_CTX_GRX_N9 DIS@ C39 0.22U_0402_10V6K PCIE_CTX_C_GRX_N9 VSS207 VSS280
14 FDI_FSYNC1 J17 K28 1 2 H24 A29
FDI1_FSYNC PEG_TX#[6] PCIE_CTX_GRX_N8 DIS@ C40 0.22U_0402_10V6K PCIE_CTX_C_GRX_N8 VSS208 VSS281
J30 1 2 H21 A26
FDI_INT PEG_TX#[7] PCIE_CTX_GRX_N7 DIS@ C41 0.22U_0402_10V6K PCIE_CTX_C_GRX_N7 VSS209 VSS282
14 FDI_INT H20 J28 1 2 H18 A23
FDI_INT PEG_TX#[8] PCIE_CTX_GRX_N6 DIS@ C42 0.22U_0402_10V6K PCIE_CTX_C_GRX_N6 VSS210 VSS283
H29 1 2 H15 A20
PEG_TX#[9] VSS211 VSS284
1

FDI_LSYNC0 J19 G27 PCIE_CTX_GRX_N5 DIS@ C43 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_N5 H13 A3

14 FDI_LSYNC0 FDI0_LSYNC PEG_TX#[10] VSS212 VSS285
R2 14 FDI_LSYNC1 FDI_LSYNC1 H17 E29 PCIE_CTX_GRX_N4 DIS@ C44 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_N4 H10
FDI1_LSYNC PEG_TX#[11] PCIE_CTX_GRX_N3 DIS@ C45 0.22U_0402_10V6K PCIE_CTX_C_GRX_N3 VSS213
F27 1 2 H9
24.9_0402_1% PEG_TX#[12] PCIE_CTX_GRX_N2 DIS@ C46 0.22U_0402_10V6K PCIE_CTX_C_GRX_N2 VSS214
D28 1 2 H8
PEG_TX#[13] PCIE_CTX_GRX_N1 DIS@ C47 0.22U_0402_10V6K PCIE_CTX_C_GRX_N1 VSS215
F26 1 2 H7
2

PEG_TX#[14] PCIE_CTX_GRX_N0 DIS@ C48 0.22U_0402_10V6K PCIE_CTX_C_GRX_N0 VSS216

E25 1 2 H6
EDP_COMP PEG_TX#[15] VSS217
A18 PCIE_CTX_C_GRX_P[0..15] 20 H5
eDP_COMPIO PCIE_CTX_GRX_P15 DIS@ C49 0.22U_0402_10V6K PCIE_CTX_C_GRX_P15 VSS218
A17 M28 1 2 H4
eDP_ICOMPO PEG_TX[0] PCIE_CTX_GRX_P14 DIS@ C50 0.22U_0402_10V6K PCIE_CTX_C_GRX_P14 VSS219
B16 M33 1 2 H3
eDP_HPD# PEG_TX[1] PCIE_CTX_GRX_P13 DIS@ C51 0.22U_0402_10V6K PCIE_CTX_C_GRX_P13 VSS220
M30 1 2 H2
PEG_TX[2] PCIE_CTX_GRX_P12 PCIE_CTX_C_GRX_P12 VSS221
eDP_COMPIO L31 DIS@ C52 1 2 0.22U_0402_10V6K H1
PEG_TX[3] PCIE_CTX_GRX_P11 DIS@ C53 0.22U_0402_10V6K PCIE_CTX_C_GRX_P11 VSS222
and ICOMPO C15 L28 1 2 G35
eDP_AUX PEG_TX[4] PCIE_CTX_GRX_P10 DIS@ C54 0.22U_0402_10V6K PCIE_CTX_C_GRX_P10 VSS223
signals D15 K30 1 2 G32
eDP_AUX# PEG_TX[5] PCIE_CTX_GRX_P9 DIS@ C55 0.22U_0402_10V6K PCIE_CTX_C_GRX_P9 VSS224
K27 1 2 G29
eDP

should be PEG_TX[6] PCIE_CTX_GRX_P8 DIS@ C56 0.22U_0402_10V6K PCIE_CTX_C_GRX_P8 VSS225

J29 1 2 G26
B shorted PEG_TX[7] PCIE_CTX_GRX_P7 DIS@ C57 0.22U_0402_10V6K PCIE_CTX_C_GRX_P7 VSS226 B
C17 J27 1 2 G23
near balls eDP_TX[0] PEG_TX[8] PCIE_CTX_GRX_P6 DIS@ C58 0.22U_0402_10V6K PCIE_CTX_C_GRX_P6 VSS227
F16 H28 1 2 G20
and routed eDP_TX[1] PEG_TX[9] PCIE_CTX_GRX_P5 DIS@ C59 0.22U_0402_10V6K PCIE_CTX_C_GRX_P5 VSS228
C16 G28 1 2 G17
eDP_TX[2] PEG_TX[10] PCIE_CTX_GRX_P4 DIS@ C60 0.22U_0402_10V6K PCIE_CTX_C_GRX_P4 VSS229
with G15 E28 1 2 G11
eDP_TX[3] PEG_TX[11] PCIE_CTX_GRX_P3 DIS@ C61 0.22U_0402_10V6K PCIE_CTX_C_GRX_P3 VSS230
typical F28 1 2 F34
PEG_TX[12] PCIE_CTX_GRX_P2 DIS@ C62 0.22U_0402_10V6K PCIE_CTX_C_GRX_P2 VSS231
impedance C18 D27 1 2 F31
eDP_TX#[0] PEG_TX[13] PCIE_CTX_GRX_P1 DIS@ C63 0.22U_0402_10V6K PCIE_CTX_C_GRX_P1 VSS232
E16 E26 1 2 F29
<25 mohms eDP_TX#[1] PEG_TX[14] PCIE_CTX_GRX_P0 DIS@ C64 0.22U_0402_10V6K PCIE_CTX_C_GRX_P0 VSS233
D16 D25 1 2
eDP_TX#[2] PEG_TX[15]
F15
eDP_TX#[3]

TYCO_2013620-2_IVY BRIDGE
CONN@

TYCO_2013620-2_IVY BRIDGE

CONN@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/07/12 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(1/6) DMI,FDI,PEG
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-8221P
Date: Wednesday, October 26, 2011 Sheet 4 of 58
5 4 3 2 1
 5 4 3 2 1

JXDP1 ER14
XDP_PREQ# 1 1
XDP_PRDY# 2 2 +3V_PCH +3VALW
3 3
4 4
5 5
6 6

0_0402_5%

0_0402_5%
7 7 +3VALW

2
8 8 +1.05VS

R576

R267
1K_0402_5% R5 9 9
H_CPUPWRGD 1 XDP@ 2 H_CPUPWRGD_XDP 10 10

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D
0_0402_5% 1 XDP@ 2 R6 CFD_PWRBTN#_XDP 11 11 @
D 14,40 PBTN_OUT# D
1K_0402_5% 1 XDP@ 2 R7 XDP_HOOK2 12 12 R8 1 1 @
7 CFG0

1
0_0402_5% 1 XDP@ 2 R10 SYS_PWROK_XDP 13 13 1K_0402_5% XDP@ XDP@
14,51 VGATE

C66

C67
CLK_CPU_ITP 14 14 +3VS
13 CLK_CPU_ITP

0.1U_0402_16V4Z~D
CLK_CPU_ITP# 15 15 +1.5V_CPU_VDDQ
13 CLK_CPU_ITP#

2
0_0402_5% 1 XDP@ 2R12 +VCCP_XDP 2 2
+1.05VS 16 16

1
PLT_RST# 1 XDP@ 2R13 XDP_RST#_R 17 17 SYS_PWROK_XDP 1

1
C65
1K_0402_5% XDP_DBRESET# 18 18 R3
19 19 10K_0402_5% R4
XDP_TDO 20 20 Place near JXDP1 200_0402_1%
XDP_TRST# 21 21 2

5
XDP_TDI 22 22 U1

2
XDP_TMS 23 23 R9 1 2 S_PWG 1

P
14 SYSTEM_PWROK @ 0_0402_5% A VDDPWRGOOD
24 24 O 4
25 25 G1 27 1 2 D_PWG 2
14 PM_DRAM_PWRGD B

G
XDP_TCK 26 26 G2 28 R11 0_0402_5%
R14 74AHC1G09GW TSSOP 5P

3
ACES_87152-26051 +3V_PCH 1 2
CONN@ 200_0402_1%

@ 1 2 H_PECI
C C68 100P_0402_50V8J +3VS +1.05VS C

Processor Pullups

0.1U_0402_16V4Z

1
+1.05VS Reserve for EMI please close to JCPU1 1
R15

C69
75_0402_5%
H_PROCHOT# 62_0402_5%
1 2 R16
2

2
5

1
JCPU1B
U2 R17

P
NC
2 4 BUFO_CPU_RST# 1 2 BUF_CPU_RST#
15,32,36,40,41 PLT_RST# A Y 43_0402_1%

G
A28 CLK_CPU_DMI_R R18 1 2 0_0402_5%
BCLK CLK_CPU_DMI#_R CLK_CPU_DMI 13
C26 A27 R19 1 2 0_0402_5% SN74LVC1G07DCKR_SC70-5
MISC

CLOCKS

3
16 H_SNB_IVB# PROC_SELECT# BCLK# CLK_CPU_DMI# 13

1
@
+1.05VS R20
AN34 R21 0_0402_5%
SKTOCC# CLK_CPU_DPLL_R CLK_CPU_DPLL#_R 1K_0402_1%
A16 1 2
DPLL_REF_CLK CLK_CPU_DPLL#_R CLK_CPU_DPLL_R 1K_0402_1%
A15 1 2

2
DPLL_REF_CLK# R22

PAD T1 @ H_CATERR# AL33

CATERR#
THERMAL

H_PECI AN33 R8 H_DRAMRST#

40 H_PECI PECI SM_DRAMRST# H_DRAMRST# 6
DDR3
MISC

R23
40,43 H_PROCHOT# 1 2 H_PROCHOT#_R AL32 AK1 SM_RCOMP0
B 56_0402_5% PROCHOT# SM_RCOMP[0] SM_RCOMP1 +3VS B
SM_RCOMP[1]
A5 PU/PD for JTAG signals
A4 SM_RCOMP2 @ 1 2 H_DRAMRST#
SM_RCOMP[2] C70 100P_0402_50V8J XDP_DBRESET#_R11K_0402_5% 1 +1.05VS
2 R24
H_THERMTRIP# AN32
16 H_THERMTRIP# THERMTRIP#

Reserve for EMI please close to JCPU1 H_CPUPWRGD_R 10K_0402_5%1 2 R25 XDP_TMS 51_0402_5% 1 2 R26

AP29 XDP_PRDY# ER17 XDP_TDI_R 51_0402_5% 1 2 R27

PRDY# XDP_PREQ#
AP27
PREQ# XDP_PREQ# 51_0402_5% 1 @ 2 R28
AR26 XDP_TCK
TCK XDP_TMS XDP_TDO_R 51_0402_5% 1
AR27 2 R29
PWR MANAGEMENT

TMS
JTAG & BPM

H_PM_SYNC AM34 AP30 XDP_TRST#

14 H_PM_SYNC PM_SYNC TRST#
ER17 AR28 XDP_TDI_R 1 R30 2 0_0402_5% XDP@ XDP_TDI DDR3 Compensation Signals
R684 TDI XDP_TDO_R XDP_TDO XDP_TCK
AP26 1 R31 2 0_0402_5% XDP@ 51_0402_5% 1 2 R32
H_CPUPWRGD1 H_CPUPWRGD_R TDO
16 H_CPUPWRGD 2 AP33
0_0402_5% UNCOREPWRGOOD XDP_TRST# 51_0402_5% 1 2 R33
SM_RCOMP0 140_0402_1%1 2 R34
R36 AL35 XDP_DBRESET#_R11 R35 2 0_0402_5% XDP@ XDP_DBRESET#
VDDPWRGOOD 1 DBR#
2 VDDPWRGOOD_R V8 1 R37 2 0_0402_5% XDP_DBRESET#_R 12,14
SM_RCOMP1 25.5_0402_1%1 2 R38
130_0402_1% SM_DRAMPWROK
AT28 XDP_BPM#0 @ T2 PAD SM_RCOMP2 200_0402_1%1 2 R39
BPM#[0] XDP_BPM#1 @ T3 PAD
AR29
BPM#[1] XDP_BPM#2 @ T4 PAD
AR30
BUF_CPU_RST# BPM#[2] XDP_BPM#3 @ T5 PAD
AR33 AT30
RESET# BPM#[3] XDP_BPM#4 @ T6 PAD
AP32
BPM#[4] XDP_BPM#5 @ T7 PAD
AR31
BPM#[5] XDP_BPM#6 @ T8 PAD
AT31
BPM#[6] XDP_BPM#7 @ T9 PAD
AR32
BPM#[7] @ XDP_DBRESET#_R1
1 2
A C71 100P_0402_50V8J A
@ 1 2 VDDPWRGOOD_R
C72 100P_0402_50V8J
TYCO_2013620-2_IVY BRIDGE
Reserve for EMI please close to JCPU1
CONN@
Reserve for EMI please close to JCPU1

@ H_CPUPWRGD_R ER17
@ 1
C426
2 BUF_CPU_RST#
100P_0402_50V8J
Security Classification Compal Secret Data Compal Electronics, Inc.
1 2 Issued Date 2011/07/12 Deciphered Date 2012/12/31 Title
C421 100P_0402_50V8J
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(2/6) PM,XDP,CLK
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Reserve for EMI please close to JCPU1 Custom 0.2
Reserve for EMI please close to JCPU1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-8221P
Date: Wednesday, October 26, 2011 Sheet 5 of 58
5 4 3 2 1
 5 4 3 2 1

JCPU1C

JCPU1D

10 DDR_A_D[0..63] AB6 DDRA_CLK0 10

SA_CLK[0]
AA6 DDRA_CLK0# 10
DDR_A_D0 SA_CLK#[0]
D C5 V9 DDRA_CKE0 10 11 DDR_B_D[0..63] AE2 DDRB_CLK0 11 D
DDR_A_D1 SA_DQ[0] SA_CKE[0] SB_CLK[0]
D5 AD2 DDRB_CLK0# 11
DDR_A_D2 SA_DQ[1] DDR_B_D0 SB_CLK#[0]
D3 C9 R9 DDRB_CKE0 11
DDR_A_D3 SA_DQ[2] DDR_B_D1 SB_DQ[0] SB_CKE[0]
D2 A7
DDR_A_D4 SA_DQ[3] DDR_B_D2 SB_DQ[1]
D6 AA5 DDRA_CLK1 10 D10
DDR_A_D5 SA_DQ[4] SA_CLK[1] DDR_B_D3 SB_DQ[2]
C6 AB5 DDRA_CLK1# 10 C8
DDR_A_D6 SA_DQ[5] SA_CLK#[1] DDR_B_D4 SB_DQ[3]
C2 V10 DDRA_CKE1 10 A9 AE1 DDRB_CLK1 11
DDR_A_D7 SA_DQ[6] SA_CKE[1] DDR_B_D5 SB_DQ[4] SB_CLK[1]
C3 A8 AD1 DDRB_CLK1# 11
DDR_A_D8 SA_DQ[7] DDR_B_D6 SB_DQ[5] SB_CLK#[1]
F10 D9 R10 DDRB_CKE1 11
DDR_A_D9 SA_DQ[8] DDR_B_D7 SB_DQ[6] SB_CKE[1]
F8 D8
DDR_A_D10 SA_DQ[9] DDR_B_D8 SB_DQ[7]
G10 AB4 G4
DDR_A_D11 SA_DQ[10] RSVD_TP[1] DDR_B_D9 SB_DQ[8]
G9 AA4 F4
DDR_A_D12 SA_DQ[11] RSVD_TP[2] DDR_B_D10 SB_DQ[9]
F9 SA_DQ[12] RSVD_TP[3] W9 F1 SB_DQ[10] RSVD_TP[11] AB2
DDR_A_D13 F7 DDR_B_D11 G1 AA2
DDR_A_D14 SA_DQ[13] DDR_B_D12 SB_DQ[11] RSVD_TP[12]
G8 SA_DQ[14] G5 SB_DQ[12] RSVD_TP[13] T9
DDR_A_D15 G7 DDR_B_D13 F5
DDR_A_D16 SA_DQ[15] DDR_B_D14 SB_DQ[13]
K4 SA_DQ[16] RSVD_TP[4] AB3 F2 SB_DQ[14]
DDR_A_D17 K5 AA3 DDR_B_D15 G2
DDR_A_D18 SA_DQ[17] RSVD_TP[5] DDR_B_D16 SB_DQ[15]
K1 SA_DQ[18] RSVD_TP[6] W10 J7 SB_DQ[16] RSVD_TP[14] AA1
DDR_A_D19 J1 DDR_B_D17 J8 AB1
DDR_A_D20 SA_DQ[19] DDR_B_D18 SB_DQ[17] RSVD_TP[15]
J5 SA_DQ[20] K10 SB_DQ[18] RSVD_TP[16] T10
DDR_A_D21 J4 DDR_B_D19 K9
DDR_A_D22 SA_DQ[21] DDR_B_D20 SB_DQ[19]
J2 SA_DQ[22] SA_CS#[0] AK3 DDRA_SCS0# 10 J9 SB_DQ[20]
DDR_A_D23 K2 AL3 DDR_B_D21 J10
SA_DQ[23] SA_CS#[1] DDRA_SCS1# 10 SB_DQ[21]
DDR_A_D24 M8 AG1 DDR_B_D22 K8 AD3
SA_DQ[24] RSVD_TP[7] SB_DQ[22] SB_CS#[0] DDRB_SCS0# 11
DDR_A_D25 N10 AH1 DDR_B_D23 K7 AE3
SA_DQ[25] RSVD_TP[8] SB_DQ[23] SB_CS#[1] DDRB_SCS1# 11
DDR_A_D26 N8 DDR_B_D24 M5 AD6
DDR_A_D27 SA_DQ[26] DDR_B_D25 SB_DQ[24] RSVD_TP[17]
N7 SA_DQ[27] N4 SB_DQ[25] RSVD_TP[18] AE6
DDR_A_D28 M10 DDR_B_D26 N2
DDR_A_D29 SA_DQ[28] DDR_B_D27 SB_DQ[26]
M9 SA_DQ[29] SA_ODT[0] AH3 DDRA_ODT0 10 N1 SB_DQ[27]
DDR_A_D30 N9 AG3 DDR_B_D28 M4
SA_DQ[30] SA_ODT[1] DDRA_ODT1 10 SB_DQ[28]
DDR_A_D31 M7 AG2 DDR_B_D29 N5 AE4
DDR SYSTEM MEMORY A

SA_DQ[31] RSVD_TP[9] SB_DQ[29] SB_ODT[0] DDRB_ODT0 11

DDR_A_D32 AG6 AH2 DDR_B_D30 M2 AD4
SA_DQ[32] RSVD_TP[10] SB_DQ[30] SB_ODT[1] DDRB_ODT1 11

DDR SYSTEM MEMORY B

DDR_A_D33 AG5 DDR_B_D31 M1 AD5
DDR_A_D34 SA_DQ[33] DDR_B_D32 SB_DQ[31] RSVD_TP[19]
C
AK6 SA_DQ[34] AM5 SB_DQ[32] RSVD_TP[20] AE5 C
DDR_A_D35 AK5 DDR_B_D33 AM6
DDR_A_D36 SA_DQ[35] DDR_B_D34 SB_DQ[33]
AH5 SA_DQ[36] DDR_A_DQS#[0..7] 10 AR3 SB_DQ[34]
DDR_A_D37 AH6 C4 DDR_A_DQS#0 DDR_B_D35 AP3
DDR_A_D38 SA_DQ[37] SA_DQS#[0] DDR_A_DQS#1 DDR_B_D36 SB_DQ[35]
AJ5 SA_DQ[38] SA_DQS#[1] G6 AN3 SB_DQ[36] DDR_B_DQS#[0..7] 11
DDR_A_D39 AJ6 J3 DDR_A_DQS#2 DDR_B_D37 AN2 D7 DDR_B_DQS#0
DDR_A_D40 SA_DQ[39] SA_DQS#[2] DDR_A_DQS#3 DDR_B_D38 SB_DQ[37] SB_DQS#[0] DDR_B_DQS#1
AJ8 SA_DQ[40] SA_DQS#[3] M6 AN1 SB_DQ[38] SB_DQS#[1] F3
DDR_A_D41 AK8 AL6 DDR_A_DQS#4 DDR_B_D39 AP2 K6 DDR_B_DQS#2
DDR_A_D42 SA_DQ[41] SA_DQS#[4] DDR_A_DQS#5 DDR_B_D40 SB_DQ[39] SB_DQS#[2] DDR_B_DQS#3
AJ9 AM8 AP5 N3
DDR_A_D43 SA_DQ[42] SA_DQS#[5] DDR_A_DQS#6 DDR_B_D41 SB_DQ[40] SB_DQS#[3] DDR_B_DQS#4
AK9 AR12 AN9 AN5
DDR_A_D44 SA_DQ[43] SA_DQS#[6] DDR_A_DQS#7 DDR_B_D42 SB_DQ[41] SB_DQS#[4] DDR_B_DQS#5
AH8 AM15 AT5 AP9
DDR_A_D45 SA_DQ[44] SA_DQS#[7] DDR_B_D43 SB_DQ[42] SB_DQS#[5] DDR_B_DQS#6
AH9 AT6 AK12
DDR_A_D46 SA_DQ[45] DDR_B_D44 SB_DQ[43] SB_DQS#[6] DDR_B_DQS#7
AL9 AP6 AP15
DDR_A_D47 SA_DQ[46] DDR_B_D45 SB_DQ[44] SB_DQS#[7]
AL8 AN8
DDR_A_D48 SA_DQ[47] DDR_B_D46 SB_DQ[45]
AP11 DDR_A_DQS[0..7] 10 AR6
DDR_A_D49 SA_DQ[48] DDR_A_DQS0 DDR_B_D47 SB_DQ[46]
AN11 D4 AR5
DDR_A_D50 SA_DQ[49] SA_DQS[0] DDR_A_DQS1 DDR_B_D48 SB_DQ[47]
AL12 F6 AR9 DDR_B_DQS[0..7] 11
DDR_A_D51 SA_DQ[50] SA_DQS[1] DDR_A_DQS2 DDR_B_D49 SB_DQ[48] DDR_B_DQS0
AM12 K3 AJ11 C7
DDR_A_D52 SA_DQ[51] SA_DQS[2] DDR_A_DQS3 DDR_B_D50 SB_DQ[49] SB_DQS[0] DDR_B_DQS1
AM11 N6 AT8 G3
DDR_A_D53 SA_DQ[52] SA_DQS[3] DDR_A_DQS4 DDR_B_D51 SB_DQ[50] SB_DQS[1] DDR_B_DQS2
AL11 AL5 AT9 J6
DDR_A_D54 SA_DQ[53] SA_DQS[4] DDR_A_DQS5 DDR_B_D52 SB_DQ[51] SB_DQS[2] DDR_B_DQS3
AP12 AM9 AH11 M3
DDR_A_D55 SA_DQ[54] SA_DQS[5] DDR_A_DQS6 DDR_B_D53 SB_DQ[52] SB_DQS[3] DDR_B_DQS4
AN12 AR11 AR8 AN6
DDR_A_D56 SA_DQ[55] SA_DQS[6] DDR_A_DQS7 DDR_B_D54 SB_DQ[53] SB_DQS[4] DDR_B_DQS5
AJ14 AM14 AJ12 AP8
DDR_A_D57 SA_DQ[56] SA_DQS[7] DDR_B_D55 SB_DQ[54] SB_DQS[5] DDR_B_DQS6
AH14 AH12 AK11
DDR_A_D58 SA_DQ[57] DDR_B_D56 SB_DQ[55] SB_DQS[6] DDR_B_DQS7
AL15 AT11 AP14
DDR_A_D59 SA_DQ[58] DDR_B_D57 SB_DQ[56] SB_DQS[7]
AK15 AN14
DDR_A_D60 SA_DQ[59] DDR_B_D58 SB_DQ[57]
AL14 DDR_A_MA[0..15] 10 AR14
DDR_A_D61 SA_DQ[60] DDR_A_MA0 DDR_B_D59 SB_DQ[58]
AK14 AD10 AT14
DDR_A_D62 SA_DQ[61] SA_MA[0] DDR_A_MA1 DDR_B_D60 SB_DQ[59]
AJ15 W1 AT12 DDR_B_MA[0..15] 11
DDR_A_D63 SA_DQ[62] SA_MA[1] DDR_A_MA2 DDR_B_D61 SB_DQ[60] DDR_B_MA0
AH15 W2 AN15 AA8
SA_DQ[63] SA_MA[2] DDR_A_MA3 DDR_B_D62 SB_DQ[61] SB_MA[0] DDR_B_MA1
W7 AR15 T7
SA_MA[3] DDR_A_MA4 DDR_B_D63 SB_DQ[62] SB_MA[1] DDR_B_MA2
V3 AT15 R7
SA_MA[4] DDR_A_MA5 SB_DQ[63] SB_MA[2] DDR_B_MA3
V2 T6
SA_MA[5] DDR_A_MA6 SB_MA[3] DDR_B_MA4
W3 T2
SA_MA[6] DDR_A_MA7 SB_MA[4] DDR_B_MA5
10 DDR_A_BS0 AE10 W6 T4
SA_BS[0] SA_MA[7] DDR_A_MA8 SB_MA[5] DDR_B_MA6
B
10 DDR_A_BS1 AF10 V1 T3 B
SA_BS[1] SA_MA[8] DDR_A_MA9 SB_MA[6] DDR_B_MA7
10 DDR_A_BS2 V6 W5 11 DDR_B_BS0 AA9 R2
SA_BS[2] SA_MA[9] DDR_A_MA10 SB_BS[0] SB_MA[7] DDR_B_MA8
AD8 11 DDR_B_BS1 AA7 T5
SA_MA[10] DDR_A_MA11 SB_BS[1] SB_MA[8] DDR_B_MA9
V4 11 DDR_B_BS2 R6 R3
SA_MA[11] DDR_A_MA12 SB_BS[2] SB_MA[9] DDR_B_MA10
W4 AB7
SA_MA[12] DDR_A_MA13 SB_MA[10] DDR_B_MA11
10 DDR_A_CAS# AE8 AF8 R1
SA_CAS# SA_MA[13] DDR_A_MA14 SB_MA[11] DDR_B_MA12
10 DDR_A_RAS# AD9 V5 T1
SA_RAS# SA_MA[14] DDR_A_MA15 SB_MA[12] DDR_B_MA13
10 DDR_A_WE# AF9 V7 11 DDR_B_CAS# AA10 AB10
SA_WE# SA_MA[15] SB_CAS# SB_MA[13] DDR_B_MA14
11 DDR_B_RAS# AB8 R5
SB_RAS# SB_MA[14] DDR_B_MA15
11 DDR_B_WE# AB9 R4
SB_WE# SB_MA[15]

TYCO_2013620-2_IVY BRIDGE
CONN@
TYCO_2013620-2_IVY BRIDGE

CONN@

+1.5V
1

R40
1K_0402_5%
Q6
BSS138_SOT23
2
S

5 H_DRAMRST# H_DRAMRST# 3 1 DDR3_DRAMRST#_R 1 2

A DDR3_DRAMRST# 10,11 A
R41 1K_0402_5%
G
2
1

@
R42 1 2 DRAMRST_CNTRL_PCH 9,13,40
4.99K_0402_1% 0_0402_5% R43
1 2 EC_DRAMRST_CNTRL_PCH 40
0_0402_5% R44
2

1
C73
Instant ON Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/07/12 Deciphered Date 2012/12/31 Title
0.047U_0402_16V4Z
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(3/6) DDRIII
ER25 Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-8221P
Date: Wednesday, October 26, 2011 Sheet 6 of 58
5 4 3 2 1
 5 4 3 2 1

CFG Straps for Processor

D D
CFG2

1
JCPU1E R45
1K_0402_1%

2
AH27
CFG0 VCC_DIE_SENSE
5 CFG0 AK28 AH26
CFG[0] VSS_DIE_SENSE
AK29
CFG2 CFG[1]
AL26
CFG[2]
AL27 CFG[3]
CFG4 AK26 L7
CFG5 CFG[4] RSVD28
AL29 CFG[5] RSVD29 AG7 PEG Static Lane Reversal - CFG2 is for the 16x
CFG6 AL30 AE7
CFG[6] RSVD30
AM31 CFG[7] RSVD31 AK2
AM32 CFG[8] 1:(Default) Normal Operation; Lane #
AM30 W8 CFG2

CFG
PAD T38 @ CFG10 AM28
CFG[9] RSVD32 definition matches socket pin map definition
+VCC_GFXCORE_AXG PAD T39 @ CFG11 CFG[10]
AM26 CFG[11] 0:Lane Reversed
PAD T40 @ CFG12 AN28 AT26
+VCC_CORE PAD T41 @ CFG13 CFG[12] RSVD33
AN31 CFG[13] RSVD34 AM33
PAD T42 @ CFG14 AN26 AJ27
CFG[14] RSVD35
1

PAD T43 @ CFG15 AM27 CFG4

R46 PAD T10 @ CFG16 CFG[15]
AK31 CFG[16]

1
49.9_0402_1% PAD T11 @ CFG17 AN29 CFG[17]
1

@ @R47
@ R47
R48 1K_0402_1%
2

49.9_0402_1% T8
@ RSVD37
J16

2
VCC_AXG_VAL_SENSE RSVD38
AJ31 H16
2

VSS_AXG_VAL_SENSE VAXG_VAL_SENSE RSVD39

AH31 VSSAXG_VAL_SENSE RSVD40 G16
VCC_VAL_SENSE AJ33
VSS_VAL_SENSE VCC_VAL_SENSE
C
AH33 VSS_VAL_SENSE C
Please place as close as JCPU1
AJ26 RSVD5 RSVD_NCTF1 AR35 Display Port Presence Strap
RSVD_NCTF2 AT34

RESERVED
RSVD_NCTF3 AT33
RSVD_NCTF4 AP35 1 : Disabled; No Physical Display Port
RSVD_NCTF5 AR34 CFG4 attached to Embedded Display Port
F25
RSVD8 0 : Enabled; An external Display Port device is
F24 connected to the Embedded Display Port
RSVD9
F23
RSVD10
D24 B34
RSVD11 RSVD_NCTF6
G25 A33
RSVD12 RSVD_NCTF7
G24 A34
RSVD13 RSVD_NCTF8 CFG6
E23 B35
RSVD14 RSVD_NCTF9
D23 C35
RSVD15 RSVD_NCTF10 CFG5
C30
RSVD16
A31
RSVD17

1
B30
RSVD18 R49 @ R50
B29
RSVD19 1K_0402_1% 1K_0402_1%
D30 AJ32
RSVD20 RSVD51 @
B31 AK32
RSVD21 RSVD52
A30

2
RSVD22
C29
RSVD23
AN35 CLK_RES_ITP 13
BCLK_ITP
J20 AM35 CLK_RES_ITP# 13
RSVD24 BCLK_ITP#
B18
RSVD25

J15
RSVD27 RSVD_NCTF11
AT2 PCIE Port Bifurcation Straps
AT1
RSVD_NCTF12
B AR1 B
RSVD_NCTF13
11: (Default) x16 - Device 1 functions 1 and 2 disabled
CFG[6:5] 10: x8, x8 - Device 1 function 1 enabled ; function 2
B1 disabled
KEY
01: Reserved - (Device 1 function 1 disabled ; function
2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
TYCO_2013620-2_IVY BRIDGE

CONN@

VSS_AXG_VAL_SENSE

VSS_VAL_SENSE
1

R51 R52
49.9_0402_1%
49.9_0402_1%
@
2

A A
@

Please place as close as JCPU1

Security Classification
2011/07/12
Compal Secret Data
2012/12/31 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(4/6) RSVD,CFG
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-8221P
Date: Wednesday, October 26, 2011 Sheet 7 of 58
5 4 3 2 1
 5 4 3 2 1

JCPU1F POWER
+1.05VS
+VCC_CORE
D 8.5A D
97AAG35
VCC1
AG34 VCC2 VCCIO1 AH13
AG33 VCC3 VCCIO2 AH10
AG32 VCC4 VCCIO3 AG10
AG31 VCC5 VCCIO4 AC10
AG30 VCC6 VCCIO5 Y10
AG29 VCC7 VCCIO6 U10
AG28 VCC8 VCCIO7 P10
AG27 VCC9 VCCIO8 L10
AG26 VCC10 VCCIO9 J14
AF35 VCC11 VCCIO10 J13
AF34 J12
VCC12 VCCIO11
AF33 J11
VCC13 VCCIO12
AF32 H14
VCC14 VCCIO13
AF31 H12
VCC15 VCCIO14
AF30 H11
VCC16 VCCIO15
AF29 G14
VCC17 VCCIO16
AF28 G13
VCC18 VCCIO17
AF27 G12

PEG AND DDR

VCC19 VCCIO18
AF26 F14
VCC20 VCCIO19
AD35 F13
VCC21 VCCIO20
AD34 F12
VCC22 VCCIO21
AD33 F11
VCC23 VCCIO22
AD32 E14
VCC24 VCCIO23
AD31 E12
VCC25 VCCIO24
AD30
VCC26
AD29 E11
VCC27 VCCIO25
AD28 D14
VCC28 VCCIO26
AD27 D13
VCC29 VCCIO27
AD26 D12
VCC30 VCCIO28
AC35 D11
VCC31 VCCIO29
AC34 C14
VCC32 VCCIO30
AC33 C13
VCC33 VCCIO31
AC32 C12
VCC34 VCCIO32
C AC31 C11 C
VCC35 VCCIO33
AC30 B14
VCC36 VCCIO34
AC29 B12
VCC37 VCCIO35
AC28 A14
VCC38 VCCIO36
AC27 A13
VCC39 VCCIO37
AC26 A12
VCC40 VCCIO38
AA35 A11
VCC41 VCCIO39
AA34
VCC42
AA33 J23
VCC43 VCCIO40
AA32
VCC44
AA31
VCC45
AA30
VCC46 +1.05VS
AA29
VCC47
AA28
VCC48
AA27
VCC49
AA26
VCC50

0.1U_0402_16V4Z
Y35 H_CPU_SVIDCLK 1 2

CORE SUPPLY
VCC51 VR_SVID_CLK 51
Y34 1 R53 0_0402_5%
VCC52
Y33
VCC53 Place the PU

C74
Y32
Y31
VCC54 @ resistors close to CPU
VCC55

1
Y30 2
VCC56 R54
Y29
VCC57
Y28 75_0402_5%
VCC58
Y27
VCC59
Y26

2
VCC60
V35
VCC61 H_CPU_SVIDALRT# R55
V34 AJ29 1 2

SVID
VCC62 VIDALERT# H_CPU_SVIDCLK VR_SVID_ALRT# 51
V33 AJ30 43_0402_1%
VCC63 VIDSCLK VR_SVID_DAT
V32 AJ28
VCC64 VIDSOUT +1.05VS
V31
VCC65
V30
VCC66

0.1U_0402_16V4Z
V29
VCC67
V28
VCC68 Place the PU 1
V27
VCC69 resistors close to CPU

C75
V26
VCC70 R56 @
B U35 B
VCC71 130_0402_1% 2
U34
VCC72
U33
VCC73
U32

2
VCC74 VR_SVID_DAT
U31 VR_SVID_DAT 51
VCC75
U30
VCC76
U29
VCC77
U28
VCC78
U27
VCC79
U26
VCC80 +VCC_CORE
R35
VCC81
R34
VCC82
R33
VCC83

1
R32
VCC84 R57
R31
VCC85
R30 100_0402_1%
VCC86
R29
VCC87
R28
SENSE LINES

2
VCC88
R27 AJ35 VCCSENSE_R 1 2 0_0402_5% VCCSENSE 51
VCC89 VCC_SENSE
R26 AJ34 VSSSENSE_R R58 1 2 0_0402_5% VSSSENSE 51
VCC90 VSS_SENSE R59
P35
VCC91 +1.05VS
P34
VCC92

1
P33 R60
VCC93 R61
P32 B10 2 1
VCC94 VCCIO_SENSE 10_0402_1%
P31 A10 100_0402_1%
VCC95 VSS_SENSE_VCCIO
P30
VCC96
P29

2
VCC97
P28
VCC98
P27 VCCIO_SENSE 48
VCC99
P26
VCC100
1

R62
10_0402_1%
A A
2

TYCO_2013620-2_IVY BRIDGE

CONN@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/07/12 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(5/6) PWR,BYPASS
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-8221P
Date: Wednesday, October 26, 2011 Sheet 8 of 58
5 4 3 2 1
 5 4 3 2 1

+1.5V_CPU_VDDQ 5A
ER16
+1.5V Q7 +1.5V_CPU_VDDQ
+5VALW +5VALW AO4304L_SO8
8 1
7 2 JCPU1H

20K_0402_5%
6 3 1

10U_0805_10V4Z~D
5 AT35 AJ22
VSS1 VSS81

C76

R64
R63 AT32 AJ19
R65 36.5K_0402_1% VSS2 VSS82
D AT29 AJ16 D

4
100K_0402_5% 2 VSS3 VSS83
AT27 AJ13

2
VSS4 VSS84
AT25 AJ10
RUN_ON_CPU1.5VS3 VSS5 VSS85
AT22 AJ7

2
VSS6 VSS86

3
AT19 AJ4
VSS7 VSS87
AT16 AJ3
Q4B VSS8 VSS88
AT13 AJ2
VSS9 VSS89

2
RUN_ON_CPU1.5VS3# 5 AT10 AJ1
C77 VSS10 VSS90
AT7 AH35
2N7002KDWH_SOT363-6 VSS11 VSS91
2200P_0402_50V7K AT4 AH34

1
VSS12 VSS92
AT3 AH32
VSS13 VSS93

6
AR25 AH30
VSS14 VSS94
AR22 AH29
R66 Q4A VSS15 VSS95
AR19 AH28
VSS16 VSS96
40 CPU1.5V_S3_GATE 1 2 2 AR16 AH25
0_0402_5% 2N7002KDWH_SOT363-6 VSS17 VSS98
AR13 AH22
VSS18 VSS99
AR10 AH19

1
VSS19 VSS100
RUN_ON_CPU1.5VS3# 42 AR7 AH16
VSS20 VSS101
AR4 AH7
VSS21 VSS102
AR2 AH4
VSS22 VSS103
AP34 AG9
VSS23 VSS104
AP31 AG8
VSS24 VSS105
AP28 AG4
VSS25 VSS106
AP25 AF6
+VCC_GFXCORE_AXG VSS26 VSS107
AP22 AF5
VSS27 VSS108
AP19 AF3
VSS28 VSS109

1
AP16 AF2
R67 VSS29 VSS110
AP13 AE35
100_0402_1%
Place near CPU AP10
VSS30
VSS31
VSS111
VSS112
AE34
AP7 AE33
VSS32 VSS113
AP4 AE32

2
VSS33 VSS114
VCC_AXG_SENSE 51 AP1 AE31
+VCC_GFXCORE_AXG VSS34 VSS115
AN30 AE30

JCPU1G
POWER R68
VSS_AXG_SENSE 51
+V_SM_VREF should
AN27
AN25
AN22
VSS35
VSS36
VSS37
VSS
VSS116
VSS117
VSS118
AE29
AE28
AE27
VSS38 VSS119
2 1 have 10 mil trace width AN19 AE26
100_0402_1% VSS39 VSS120
AN16 AE9
33A AT24 AK35 AN13
VSS40 VSS121
AD7

SENSE
LINES
VAXG1 VAXG_SENSE +1.5V_CPU_VDDQ +1.5V VSS41 VSS122
AT23 AK34 AN10 AC9
VAXG2 VSSAXG_SENSE VSS42 VSS123
AT21 AN7 AC8
C VAXG3 VSS43 VSS124 C
AT20 AN4 AC6
VAXG4 VSS44 VSS125
AT18 2 1 AM29 AC5
VAXG5 VSS45 VSS126

1
AT17 0_0402_5% R69 @ AM25 AC3
VAXG6 R70 R71 VSS46 VSS127
AR24 AM22 AC2
VAXG7 1K_0402_1% 1K_0402_1% VSS47 VSS128
AR23 AM19 AB35
VAXG8 Q8 @ VSS48 VSS129
AR21 AM16 AB34
VAXG9 @ VSS49 VSS130
AR20 AM13 AB33

2
VAXG10 VSS50 VSS131

D
AR18 AL1 +V_SM_VREF_CNT 3 1 +V_SM_VREF AM10 AB32
VAXG11 SM_VREF VSS51 VSS132

0.1U_0402_16V4Z
AR17 AM7 AB31
VAXG12 VSS52 VSS133

1
AP24 ER20 AM4 AB30
VREF

VAXG13 1 VSS53 VSS134

1
R72 PMV45EN_SOT23-3

G
AP23 AM3 AB29

2
VAXG14 VSS54 VSS135

C149
AP21 1K_0402_1% R73 AM2 AB28
VAXG15 +V_DDR_REFA_R @ 1K_0402_1% VSS55 VSS136
AP20 B4 AM1 AB27
VAXG16 SA_DIMM_VREFDQ +V_DDR_REFB_R 2 VSS56 VSS137
AP18 D1 AL34 AB26

2
VAXG17 SB_DIMM_VREFDQ RUN_ON_CPU1.5VS3 VSS57 VSS138
AP17 AL31 Y9

2
VAXG18 VSS58 VSS139
AN24 AL28 Y8
VAXG19 VSS59 VSS140
AN23 AL25 Y6
VAXG20 VSS60 VSS141
AN21 AL22 Y5
VAXG21 +1.5V_CPU_VDDQ VSS61 VSS142
AN20 AL19 Y3
VAXG22 VSS62 VSS143
AN18 AL16 Y2
DDR3 -1.5V RAILS

VAXG23 VSS63 VSS144

AN17 AL13 W35
AM24
VAXG24
AF7
5A AL10
VSS64 VSS145
W34
GRAPHICS

VAXG25 VDDQ1 VSS65 VSS146

AM23 AF4 AL7 W33
VAXG26 VDDQ2 VSS66 VSS147
AM21 AF1 AL4 W32
VAXG27 VDDQ3 VSS67 VSS148

10U_0805_6.3VAM

10U_0805_6.3VAM

10U_0805_6.3VAM

10U_0805_6.3VAM

10U_0805_6.3VAM

10U_0805_6.3VAM

330U_D2_2VM_R6M
AM20 AC7 1 AL2 W31
VAXG28 VDDQ4 VSS68 VSS149
AM18 AC4 1 1 1 1 1 1 AK33 W30
VAXG29 VDDQ5 VSS69 VSS150

C84

C78
AM17 AC1 + AK30 W29
VAXG30 VDDQ6 C79 VSS70 VSS151

C80

C81

C82

C83
AL24 Y7 AK27 W28
VAXG31 VDDQ7 VSS71 VSS152
AL23 Y4 AK25 W27
VAXG32 VDDQ8 2 2 2 2 2 2 2 3 VSS72 VSS153
AL21 Y1 AK22 W26
VAXG33 VDDQ9 VSS73 VSS154
AL20 U7 AK19 U9
VAXG34 VDDQ10 VSS74 VSS155
AL18 U4 AK16 U8
VAXG35 VDDQ11 VSS75 VSS156
AL17 U1 AK13 U6
VAXG36 VDDQ12 VSS76 VSS157
AK24 P7 AK10 U5
VAXG37 VDDQ13 VSS77 VSS158
AK23 P4 AK7 U3
VAXG38 VDDQ14 VSS78 VSS159
AK21 P1 AK4 U2
VAXG39 VDDQ15 VSS79 VSS160
AK20 AJ25
VAXG40 VSS80
AK18
VAXG41
AK17
VAXG42
AJ24
VAXG43
AJ23
B VAXG44 TYCO_2013620-2_IVY BRIDGE B
AJ21
VAXG45
AJ20
VAXG46
AJ18
AJ17
VAXG47
M27
6A +VCCSA
CONN@
VAXG48 VCCSA1
SA RAIL

AH24 M26
VAXG49 VCCSA2
10U_0805_6.3VAM

10U_0805_6.3VAM

10U_0805_6.3VAM

AH23 L26 1
VAXG50 VCCSA3
10U_0603_6.3V6M

330U_D2_2VM_R6M
AH21 J26 1 1 1 1 @
VAXG51 VCCSA4 +
AH20 J25
VAXG52 VCCSA5
C86

C87

C88

C89

C85

AH18 J24 +1.5V_CPU_VDDQ +1.5V

VAXG53 VCCSA6
AH17 H26
VAXG54 VCCSA7 2 2 2 2 2 3
H25
VCCSA8 C90 2 1 0.1U_0402_10V7K

+1.8VS C91 2 1 0.1U_0402_10V7K

1.8V RAIL

H23 +VCCSA_SENSE 50
ER20 VCCSA_SENSE C92 2 1 0.1U_0402_10V7K
R242 1.5A
1

1 2 +1.8VS_VCCPLL B6
VCCPLL1 @ R74 C93
A6 C22 2 1 0.1U_0402_10V7K
MISC

VCCPLL2 VCCSA_VID[0] H_VCCSA_VID0 50

10U_0805_6.3VAM

1U_0402_6.3V6K

1U_0402_6.3V6K

0_0805_5% 1 1 1 1 A2 C24 0_0402_5%

VCCPLL3 VCCSA_VID[1] H_VCCSA_VID1 50
330U_D2_2VM_R6M
C94

C95

C96

C97

+
2

2 2 2 A19 VCCIO_SEL +3VS

2 3 VCCIO_SEL

TYCO_2013620-2_IVY BRIDGE
2

CONN@ R75
10K_0402_5% @
1

Q9
1

D BSS138_SOT23
2 DRAMRST_CNTRL_PCH 6,13,40
+V_DDR_REFA G
A A
+V_DDR_REFB S
3

R77 1 @ 2 0_0402_5% +V_DDR_REFA_R

R78 1 @ 2 0_0402_5% +V_DDR_REFB_R
1

1
1

D
DRAMRST_CNTRL_PCH 2 Q10 R79 R80
G 1K_0402_1% 1K_0402_1%
S BSS138_SOT23 @ @
3

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/07/12 Deciphered Date 2012/12/31 Title
M3 Circuit (Processor Generated SO-DIMM VREF_DQ) PROCESSOR(6/6) PWR,VSS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-8221P
Date: Wednesday, October 26, 2011 Sheet 9 of 58
5 4 3 2 1
 5 4 3 2 1

+1.5V 3.56A
+1.5V +1.5V 6 DDR_A_D[0..63]

1
6 DDR_A_DQS[0..7]
R81
1K_0402_1% DDR3 SO-DIMM A 6 DDR_A_DQS#[0..7]
ER12 JDIMM1

2
6 DDR_A_MA[0..15]
+V_DDR_REFA 1 VREF_DQ VSS1 2
3 4 DDR_A_D4
VSS2 DQ4

0.1U_0402_10V6K
DDR_A_D0 5 6 DDR_A_D5
DQ0 DQ5

C98
1 DDR_A_D1 7 8
DQ1 VSS3
1

1
2.2U_0402_6.3V6M
9 10 DDR_A_DQS#0
VSS4 DQS#0

C99
R82 11 12 DDR_A_DQS0
D DM0 DQS0 D
13 14

2
1K_0402_1% 2 DDR_A_D2 VSS5 VSS6 DDR_A_D6
15 16
DDR_A_D3 DQ2 DQ6 DDR_A_D7
17 18
2

DQ3 DQ7
19 20
DDR_A_D8 VSS7 VSS8 DDR_A_D12
21 22
DDR_A_D9 DQ8 DQ12 DDR_A_D13
23 24
DQ9 DQ13
25 26
DDR_A_DQS#1 VSS9 VSS10
27 28
DDR_A_DQS1 DQS#1 DM1 DDR3_DRAMRST#
29 30 DDR3_DRAMRST# 6,11
DQS1 RESET#
31 32
DDR_A_D10 VSS11 VSS12 DDR_A_D14
33 34
DDR_A_D11 DQ10 DQ14 DDR_A_D15
35 DQ11 DQ15 36
37 VSS13 VSS14 38
DDR_A_D16 39 40 DDR_A_D20
DDR_A_D17 DQ16 DQ20 DDR_A_D21
41 DQ17 DQ21 42
43 VSS15 VSS16 44
DDR_A_DQS#2 45 46
DDR_A_DQS2 DQS#2 DM2
47 DQS2 VSS17 48
49 50 DDR_A_D22
DDR_A_D18 VSS18 DQ22 DDR_A_D23
51 DQ18 DQ23 52
DDR_A_D19 53 54
DQ19 VSS19 DDR_A_D28
55 VSS20 DQ28 56
DDR_A_D24 57 58 DDR_A_D29
DDR_A_D25 DQ24 DQ29
59 DQ25 VSS21 60
61 62 DDR_A_DQS#3
VSS22 DQS#3 DDR_A_DQS3
63 DM3 DQS3 64
65 VSS23 VSS24 66
DDR_A_D26 67 68 DDR_A_D30
DDR_A_D27 DQ26 DQ30 DDR_A_D31
69 DQ27 DQ31 70
71 VSS25 VSS26 72
Layout Note:
C Place near JDDRL C
DDRA_CKE0 73 74 DDRA_CKE1 +1.5V
6 DDRA_CKE0 CKE0 CKE1 DDRA_CKE1 6
75 VDD1 VDD2 76
77 78 DDR_A_MA15
NC1 A15

330U_B2_2.5VM_R15M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
DDR_A_BS2 79 80 DDR_A_MA14
6 DDR_A_BS2 BA2 A14

C100
81 VDD3 VDD4 82 1

C101

C102

C103

C104

C105

C106

C107
DDR_A_MA12 83 84 DDR_A_MA11 1 1 1 1 1 1 1
DDR_A_MA9 A12/BC# A11 DDR_A_MA7 +
85 86
A9 A7
87 88
DDR_A_MA8 VDD5 VDD6 DDR_A_MA6 @
89 90
DDR_A_MA5 A8 A6 DDR_A_MA4 2 2 2 2 2 2 2 2
91 92
A5 A4
93 94
DDR_A_MA3 VDD7 VDD8 DDR_A_MA2
95 96
DDR_A_MA1 A3 A2 DDR_A_MA0
97 98
A1 A0
99 100
DDRA_CLK0 VDD9 VDD10 DDRA_CLK1
6 DDRA_CLK0 101 102 DDRA_CLK1 6
DDRA_CLK0# CK0 CK1 DDRA_CLK1#
6 DDRA_CLK0# 103 104 DDRA_CLK1# 6
CK0# CK1# +1.5V
105 106
DDR_A_MA10 VDD11 VDD12 DDR_A_BS1
107 108 DDR_A_BS1 6
DDR_A_BS0 A10/AP BA1 DDR_A_RAS#
6 DDR_A_BS0 109 110 DDR_A_RAS# 6
BA0 RAS#

1
111 112
DDR_A_WE# VDD13 VDD14 DDRA_SCS0# R83
6 DDR_A_WE# 113 114 DDRA_SCS0# 6
DDR_A_CAS# WE# S0# DDRA_ODT0 1K_0402_1%
6 DDR_A_CAS# 115
CAS# ODT0
116 DDRA_ODT0 6 Layout Note: Place these 4 Caps near
117 118 Command and Control signals of JDDRL
DDR_A_MA13 VDD15 VDD16 DDRA_ODT1
119 120

2
DDRA_SCS1# A13 ODT1 DDRA_ODT1 6
6 DDRA_SCS1# 121 122
S1# NC2 +1.5V
123 124
VDD17 VDD18 +VREF_CA
125 126
NCTEST VREF_CA
127 128
VSS27 VSS28

0.1U_0402_10V6K
DDR_A_D32 129 130 DDR_A_D36 ER12
DQ32 DQ36

1
C108

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
DDR_A_D33 131 132 DDR_A_D37 1
DQ33 DQ37

1
2.2U_0402_6.3V6M

C110

C111

C112

C113
133 134 1 1 1 1
VSS29 VSS30

C109
B DDR_A_DQS#4 R84 B
135 136
DDR_A_DQS4 DQS#4 DM4 1K_0402_1%
137 138

2
DQS4 VSS31 DDR_A_D38 2
139 140

2
DDR_A_D34 VSS32 DQ38 DDR_A_D39 2 2 2 2
141 142
DDR_A_D35 DQ34 DQ39
143 144
DQ35 VSS33 DDR_A_D44
145 146
DDR_A_D40 VSS34 DQ44 DDR_A_D45
147 148
DDR_A_D41 DQ40 DQ45
149 150
DQ41 VSS35 DDR_A_DQS#5
151 152
VSS36 DQS#5 DDR_A_DQS5
153 154
DM5 DQS5
155 156
DDR_A_D42 VSS37 VSS38 DDR_A_D46
157 158
DDR_A_D43 DQ42 DQ46 DDR_A_D47
159 160
DQ43 DQ47
161 162
DDR_A_D48 VSS39 VSS40 DDR_A_D52
163
DQ48 DQ52
164 Layout Note:
DDR_A_D49 165 166 DDR_A_D53
167
DQ49 DQ53
168
Place near JDDRL.203,204
DDR_A_DQS#6 VSS41 VSS42
169 170
DDR_A_DQS6 DQS#6 DM6
171 172
DQS6 VSS43 DDR_A_D54
173 174
DDR_A_D50 VSS44 DQ54 DDR_A_D55 +0.75VS
175 176
DDR_A_D51 DQ50 DQ55
177 178
DQ51 VSS45 DDR_A_D60
179 180
DDR_A_D56 VSS46 DQ60 DDR_A_D61
181 182
DDR_A_D57 DQ56 DQ61
183 184
DQ57 VSS47

1U_0402_6.3V6K
C114

1U_0402_6.3V6K
C115

1U_0402_6.3V6K
C116

1U_0402_6.3V6K
C117
185 186 DDR_A_DQS#7
VSS48 DQS#7 DDR_A_DQS7
187 188 1 1 1 1
DM7 DQS7
189 190
DDR_A_D58 VSS49 VSS50 DDR_A_D62
191 192
DDR_A_D59 DQ58 DQ62 DDR_A_D63
193 194
DQ59 DQ63 2 2 2 2
195 196
VSS51 VSS52
197 SA0 EVENT# 198
A PCH_SMBDATA A
+3VS 199 VDDSPD SDA 200 PCH_SMBDATA 11,13,41
0.1U_0402_10V6K

201 202 PCH_SMBCLK

SA1 SCL PCH_SMBCLK 11,13,41
C119

ER12 1 203 204

VTT1 VTT2 +0.75VS
1

1
2.2U_0402_6.3V6M

10K_0402_5%
R85

10K_0402_5%
R86
C118

205 206 1/76BA1/86W

G1 G2
2

2
TYCO 2-1932323-1
Security Classification Compal Secret Data Compal Electronics, Inc.
2

Issued Date 2011/07/12 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII-DDRL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-8221P
Date: Wednesday, October 26, 2011 Sheet 10 of 58
5 4 3 2 1
 5 4 3 2 1

+1.5V
+1.5V +1.5V

3.56A

1
R87
6 DDR_B_DQS#[0..7]
+V_DDR_REFB 1K_0402_1%
JDIMM2
6 DDR_B_D[0..63]
1 2

2
VREF_DQ VSS1 DDR_B_D4
0.1U_0402_10V6K 3 VSS2 DQ4 4 6 DDR_B_DQS[0..7]
ER12 R88 DDR_B_D0 5 6 DDR_B_D5
DDR_B_D1 DQ0 DQ5
1 7 DQ1 VSS3 8 6 DDR_B_MA[0..15]
1

1
2.2U_0402_6.3V6M

9 10 DDR_B_DQS#0
VSS4 DQS#0
C120

C121 DDR_B_DQS0
11 12
DM0 DQS0
13 14
2

2 DDR_B_D2 VSS5 VSS6 DDR_B_D6

15 16
DQ2 DQ6
1K_0402_1%

D DDR_B_D3 DDR_B_D7 D
17 18
2

DQ3 DQ7
19 20
DDR_B_D8 VSS7 VSS8 DDR_B_D12
21 22
DDR_B_D9 DQ8 DQ12 DDR_B_D13
23 24
DQ9 DQ13
25 26
DDR_B_DQS#1 VSS9 VSS10
27 28
DDR_B_DQS1 DQS#1 DM1 DDR3_DRAMRST#
29 30 DDR3_DRAMRST# 6,10
DQS1 RESET#
31 32
DDR_B_D10 VSS11 VSS12 DDR_B_D14
33 34
DDR_B_D11 DQ10 DQ14 DDR_B_D15
35 36
DQ11 DQ15
37 38
DDR_B_D16 VSS13 VSS14 DDR_B_D20
39 DQ16 DQ20 40
DDR_B_D17 41 42 DDR_B_D21
DQ17 DQ21
43 VSS15 VSS16 44 Layout Note: Place these 4 Caps near Layout Note:
DDR_B_DQS#2 45 46
DDR_B_DQS2 DQS#2 DM2 Command and Control signals of JDDRH Place near JDDRH
47 DQS2 VSS17 48
49 50 DDR_B_D22
DDR_B_D18 VSS18 DQ22 DDR_B_D23 +1.5V +1.5V
51 DQ18 DQ23 52
DDR_B_D19 53 54
DQ19 VSS19

330U_B2_2.5VM_R15M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
55 56 DDR_B_D28 @
VSS20 DQ28

C122
DDR_B_D24 57 58 DDR_B_D29 1
DQ24 DQ29

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

C123

C124

C125

C126

C127

C128

C129

C130
DDR_B_D25 59 60 1 1 1 1 1 1 1 1
DQ25 VSS21

C131

C132

C133

C134
61 62 DDR_B_DQS#3 +
VSS22 DQS#3 1 1 1 1
63 64 DDR_B_DQS3
DM3 DQS3 @ @
65 VSS23 VSS24 66
DDR_B_D26 DDR_B_D30 2 2 2 2 2 2 2 2 2
67 DQ26 DQ30 68
DDR_B_D27 69 70 DDR_B_D31 2 2 2 2
DQ27 DQ31
71 VSS25 VSS26 72

DDRB_CKE0 73 74 DDRB_CKE1
C 6 DDRB_CKE0 CKE0 CKE1 DDRB_CKE1 6 C
75 VDD1 VDD2 76
77 78 DDR_B_MA15
DDR_B_BS2 NC1 A15 DDR_B_MA14
6 DDR_B_BS2 79 BA2 A14 80
81 VDD3 VDD4 82
DDR_B_MA12 83 84 DDR_B_MA11
DDR_B_MA9 A12/BC# A11 DDR_B_MA7
85 A9 A7 86
87 VDD5 VDD6 88
DDR_B_MA8 89 90 DDR_B_MA6
DDR_B_MA5 A8 A6 DDR_B_MA4
91
A5 A4
92 Layout Note:
93 94 Place near JDDRH.203 and 204
DDR_B_MA3 VDD7 VDD8 DDR_B_MA2
95 96
DDR_B_MA1 A3 A2 DDR_B_MA0
97 98
A1 A0 +0.75VS
99 100
DDRB_CLK0 VDD9 VDD10 DDRB_CLK1
6 DDRB_CLK0 101 102 DDRB_CLK1 6
DDRB_CLK0# CK0 CK1 DDRB_CLK1#
6 DDRB_CLK0# 103 104 DDRB_CLK1# 6
CK0# CK1#
105 106
DDR_B_MA10 VDD11 VDD12 DDR_B_BS1
107 108 DDR_B_BS1 6
A10/AP BA1 +1.5V

1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z
DDR_B_BS0 109 110 DDR_B_RAS#
6 DDR_B_BS0 BA0 RAS# DDR_B_RAS# 6

C135

C136

C137

C138
111 112 1 1 1 1
DDR_B_WE# VDD13 VDD14 DDRB_SCS0#
6 DDR_B_WE# 113 114 DDRB_SCS0# 6
WE# S0#

1
DDR_B_CAS# 115 116 DDRB_ODT0
6 DDR_B_CAS# CAS# ODT0 DDRB_ODT0 6
117 118 R89
DDR_B_MA13 VDD15 VDD16 DDRB_ODT1 1K_0402_1% 2 2 2 2
119 120 DDRB_ODT1 6
DDRB_SCS1# A13 ODT1
6 DDRB_SCS1# 121 122
S1# NC2
123 124

2
VDD17 VDD18 +VREF_CB
125 126
NCTEST VREF_CA
0.1U_0402_10V6K

127 128
DDR_B_D32 VSS27 VSS28 DDR_B_D36 ER12
129 130
DQ32 DQ36
C139

DDR_B_D33 131 132 DDR_B_D37 1

DQ33 DQ37

1
2.2U_0402_6.3V6M
133 134
VSS29 VSS30

C140
DDR_B_DQS#4 135 136 R90
DDR_B_DQS4 DQS#4 DM4
137 138
2
B DQS4 VSS31 DDR_B_D38 2 1K_0402_1% B
139 140
DDR_B_D34 VSS32 DQ38 DDR_B_D39
141 142

2
DDR_B_D35 DQ34 DQ39
143 144
DQ35 VSS33 DDR_B_D44
145 146
DDR_B_D40 VSS34 DQ44 DDR_B_D45
147 148
DDR_B_D41 DQ40 DQ45
149 150
DQ41 VSS35 DDR_B_DQS#5
151 152
VSS36 DQS#5 DDR_B_DQS5
153 154
DM5 DQS5
155 156
DDR_B_D42 VSS37 VSS38 DDR_B_D46
157 158
DDR_B_D43 DQ42 DQ46 DDR_B_D47
159 160
DQ43 DQ47
161 162
DDR_B_D48 VSS39 VSS40 DDR_B_D52
163 164
DDR_B_D49 DQ48 DQ52 DDR_B_D53
165 166
DQ49 DQ53
167 168
DDR_B_DQS#6 VSS41 VSS42
169 170
DDR_B_DQS6 DQS#6 DM6
171 172
DQS6 VSS43 DDR_B_D54
173 174
DDR_B_D50 VSS44 DQ54 DDR_B_D55
175 176
DDR_B_D51 DQ50 DQ55
177 178
DQ51 VSS45 DDR_B_D60
179 180
DDR_B_D56 VSS46 DQ60 DDR_B_D61
181 182
DDR_B_D57 DQ56 DQ61
183 184
DQ57 VSS47 DDR_B_DQS#7
185 186
VSS48 DQS#7 DDR_B_DQS7
187 188
DM7 DQS7
189 190
DDR_B_D58 VSS49 VSS50 DDR_B_D62
191 192
DDR_B_D59 DQ58 DQ62 DDR_B_D63
193 194
DQ59 DQ63
1 R91 2 195
VSS51 VSS52
196
10K_0402_5% 197 198
SA0 EVENT# PCH_SMBDATA
+3VS 199 200 PCH_SMBDATA 10,13,41
VDDSPD SDA
0.1U_0402_10V6K

ER12 201 202 PCH_SMBCLK

SA1 SCL PCH_SMBCLK 10,13,41
C142

A A
1 1 2 203 VTT1 VTT2 204 +0.75VS
1
2.2U_0402_6.3V6M

R92 10K_0402_5%
C141

205 206 1/76BA1/86W

G1 G2
2

2 TYCO_2-2013287-1

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/07/12 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII-DDRH
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-8221P
Date: Wednesday, October 26, 2011 Sheet 11 of 58
5 4 3 2 1
 5 4 3 2 1

PCH_RTCX1

1 2 PCH_RTCX2
R93 10M_0402_5%
Y1
1 2
+RTCVCC
32.768KHZ_12.5PF_9H03200019
1 2 SM_INTRUDER#
R94 1M_0402_5%

1 1
C144 C145
18P_0402_50V8J 18P_0402_50V8J
2 2
D D
ER13

CLRP1 & CLRP2 place near DIMM

U3A
far away hot spot
+RTCVCC PCH_RTCX1 A20 C38 LPC_AD0
1 RTCX1 FWH0 / LAD0 LPC_AD0 40,41

1
CMOS A38 LPC_AD1
FWH1 / LAD1 LPC_AD1 40,41

LPC
C146 CLRP1 PCH_RTCX2 C20 B37 LPC_AD2
RTCX2 FWH2 / LAD2 LPC_AD2 40,41
1U_0603_10V4Z SHORT PADS C37 LPC_AD3

2
2 FWH3 / LAD3 LPC_AD3 40,41
1 2 PCH_RTCRST# D20
R99 20K_0402_5% RTCRST# LPC_FRAME#
D36 LPC_FRAME# 40,41
PCH_SRTCRST# FWH4 / LFRAME#
1 2 G22
R100 20K_0402_5% SRTCRST# LPC_LDRQ0#
1 E36 @ T12 PAD~D
LDRQ0#

1
SM_INTRUDER# LPC_LDRQ1#

RTC
K22 K36 @ T13 PAD~D
C147 CLRP2 INTRUDER# LDRQ1# / GPIO23
1U_0603_10V4Z SHORT PADS PCH_INTVRMEN C17 V5 SERIRQ SERIRQ 40

2
2 ME CMOS INTVRMEN SERIRQ
40 HDA_SDO 1 2 HDA_SDOUT
R101 0_0402_5%~D AM3 SATA_PRX_DTX_N0 31
HDA_BIT_CLK SATA0RXN
N34 AM1 SATA_PRX_DTX_P0 31
HDA_BCLK SATA0RXP HDD1 +3VS
HDA for AUDIO

SATA 6G
AP7 SATA_PTX_DRX_N0 31
HDA_SYNC SATA0TXN
L34 AP5 SATA_PTX_DRX_P0 31
HDA_BIT_CLK HDA_SYNC SATA0TXP
33 HDA_BITCLK_AUDIO 1 2
R102 33_0402_5% HDA_SPKR T10 AM10 SERIRQ R103 2 1 10K_0402_5%
SPKR SATA1RXN
AM8
HDA_RST# SATA1RXP +RTCVCC PCH_GPIO21 R104
1 K34 AP11 2 1 10K_0402_5%
@ C148 HDA_RST# SATA1TXN
AP10
10P_0402_50V8J SATA1TXP PCH_SATALED#R105 2 1 10K_0402_5%
HDA_SDIN0 E34 AD7 SATA_PRX_DTX_N2 31 PCH_INTVRMEN R106 2 1 330K_0402_5%
2 33 HDA_SDIN0 HDA_SDIN0 SATA2RXN
AD5 SATA_PRX_DTX_P2 31 BBS_BIT0_R R107 2 1 10K_0402_5%
SATA2RXP
Reserve for EMI G34
HDA_SDIN1 SATA2TXN
AH5 SATA_PTX_DRX_N2 31 ODD
please close to R102 AH4 SATA_PTX_DRX_P2 31
SATA2TXP
C34
HDA_SDIN2
INTVRMEN

IHDA
C AB8 C
SATA3RXN
33 HDA_RST_AUDIO# 1 2 HDA_RST# A34
HDA_SDIN3 SATA3RXP
AB10
AF3
* HIntegrated
LIntegrated
VRM enable
VRM disable +3VS
R108 33_0402_5% SATA3TXN
HDA_SDOUT AF1
33 HDA_SDOUT_AUDIO 1 2 HDA_SDOUT SATA3TXP
R109 33_0402_5% A36
HDA_SDO HDA_SPKR R110 @ 1 1K_0402_5%

SATA
Y7 2
SATA4RXN
Y5
PCH_SPI_WP SATA4RXP
+3V_PCH +3V_PCH +3V_PCH ER32
C36
HDA_DOCK_EN# / GPIO33 SATA4TXN
SATA4TXP
AD3
AD1 *LOW=Default
HIGH=No Reboot
N32
HDA_DOCK_RST# / GPIO13
Y3
SATA5RXN
1

R111 R112 R113 Y1

SATA5RXP
AB3
PCH_JTAG_TCK SATA5TXN
200_0402_5% 200_0402_5% 200_0402_5% PAD T45 @ J3 AB1
JTAG_TCK SATA5TXP
T46 PCH_JTAG_TMS H7 Y11 +1.05VS_VCC_SATA
PAD @
2

JTAG_TMS SATAICOMPO

JTAG
PCH_JTAG_TDO PCH_JTAG_TMS PCH_JTAG_TDI
PAD T47 @ PCH_JTAG_TDI K5 Y10 SATA_COMP 1 2
JTAG_TDI SATAICOMPI
1

R116 R117 R118 R114 37.4_0402_1%

PAD T48 @ PCH_JTAG_TDO H1
JTAG_TDO +1.05VS_SATA3
100_0402_1% 100_0402_1% 100_0402_1% AB12
SATA3RCOMPO
AB13 SATA3_COMP 1 2
2

SATA3COMPI R115 49.9_0402_1%

PCH_SPI_CLK_RR T3 AH1 RBIAS_SATA3 1 2

SPI_CLK SATA3RBIAS R120 750_0402_1%
R124 2 1 PCH_JTAG_TCK PCH_SPI_CS#_RR Y14
51_0402_5% SPI_CS0# R123
T1 2 1 FLASH_EN HDA_SYNC
SPI_CS1#
SPI

P3 PCH_SATALED#
SATALED# PCH_SATALED# 39
XDP_DBRESET#_R @ T49 PAD 10K_0402_5% This signal has a weak internal pull-down
5,14 XDP_DBRESET#_R
PCH_SPI_SI_RR V4 V14 PCH_GPIO21 On Die PLL VR is supplied by
SPI_MOSI SATA0GP / GPIO21
1.5V when smapled high
PCH_SPI_SO_RR U3 P1 BBS_BIT0_R
+5VS SPI_MISO SATA1GP / GPIO19 1.8V when sampled low
Needs to be pulled High for Chief River platfrom
PANTHER-POINT_FCBGA989 +3V_PCH
B B
+3V_PCH
2
G

U4
1
HDA_SYNC VDD FLASH_EN HDA_SYNC R128
33 HDA_SYNC_AUDIO 1 2 3 1 4 12 FLASH_EN 40 2 1 1K_0402_5%
VDD SEL
63,5200%\WH
R127 33_0402_5%
S

9
VDD
19 2 +3V_SPI
BSS138_SOT23 VDD YA PCH_SPI_CS#_R
5
YB
1

Q11 +3VS 24 6 PCH_SPI_CLK 1 2 PCH_SPI_CLK_R

R129 +3V_SPI R131 PCH_SPI_CS#_RR A0 YC 0_0402_5%
22
1M_0402_5% PCH_SPI_CLK_RR PCH_SPI_CLK_RRR B0 PCH_SPI_SI_R R133
1 2 18 8
+3V_SPI 0_0402_5% PCH_SPI_SI_RR C0 YD PCH_SPI_SO_R
17
D0 YE
11 EMI
EMI PCH_SPI_SO_RR 14
2

E0
0.1U_0402_16V4Z

1 +3VALW 23 3
A1 GND
R132 1 2 PCH_SPI_WP# C150 39,40 KSI4 KSI4 21
B1 GND
7
3.3K_0402_5% 39,40 KSI5 KSI5 16 10
KSI6 C1 GND
39,40 KSI6 15 20
2 D1 GND
R134 1 2 PCH_SPI_HOLD# 39,40 KSI7 KSI7 13
3.3K_0402_5% E1
U5 PI3V512QE_QSOP24 +RTCBATT
8 4
C152 R139 VCC VSS
RTC Battery

1
2 1 1 2PCH_SPI_CLK_RRR PCH_SPI_WP# 3
@ 33_0402_5% @ W R136
22P_0402_50V8J PCH_SPI_HOLD# 7
Reserve for EMI please close to U4 HOLD MAX. 8000mil 1K_0402_5%

PCH_SPI_CS#_R 1

2
S D1
+RTCVCC
PCH_SPI_CLK_R 6 2 W=20mils
C
W=20mils 1
PCH_SPI_SI_R 5 2 PCH_SPI_SO_R 3
C155
R142 D Q W=20mils +CHGRTC

0.1U_0402_16V4Z
2 1 1 2PCH_SPI_CLK_R W25Q32BVSSIG_SO8 1 DAN202UT106_SC70-3
@ 0_0402_5% @ C154
10P_0402_50V8J
Reserve for EMI please close to U5
2
A A

PCH_SPI_WP#

@
PCH_SPI_WP 1 2 PCH_WP
1

R137 0_0402_5% Q63 D

40 EC_SPI_WP 1 2 2
R135 0_0402_5% G
S
3

ER38
SSM3K7002FU_SC70-3 ER32 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/07/12 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (1/8) SATA,HDA,SPI, LPC
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-8221P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 26, 2011 Sheet 12 of 58
5 4 3 2 1
 5 4 3 2 1

SMBALERT# 2 1 +3V_PCH
R149 10K_0402_5%
SMBCLK 1 2
R150 2.2K_0402_5%
U3B SMBDATA 1 2
R151 2.2K_0402_5%
SML0CLK 1 2
D PCIE_PRX_GLANTX_N1 BG34 R152 2.2K_0402_5% D
32 PCIE_PRX_GLANTX_N1 PERN1
32 PCIE_PRX_GLANTX_P1 PCIE_PRX_GLANTX_P1 BJ34 E12 SMBALERT# SML0DATA 1 2
C158 1 PERP1 SMBALERT# / GPIO11
10/100/1G LAN ---> 32 PCIE_PTX_GLANRX_N1 2 0.1U_0402_10V7K PCIE_PTX_GLANRX_N1_C AV32 PETN1
R153 2.2K_0402_5%
C159 1 2 0.1U_0402_10V7K PCIE_PTX_GLANRX_P1_C AU32 H14 SMBCLK PCH_SMLCLK 1 2
32 PCIE_PTX_GLANRX_P1 PETP1 SMBCLK
MEMORY ER03 R154 2.2K_0402_5%
41 PCIE_PRX_WLANTX_N2 PCIE_PRX_WLANTX_N2 BE34 C9 SMBDATA PCH_SMLDATA 1 2
PCIE_PRX_WLANTX_P2 PERN2 SMBDATA R155 2.2K_0402_5%
41 PCIE_PRX_WLANTX_P2 BF34 PERP2
MiniWLAN (Mini Card 1)---> C160 1 2 0.1U_0402_10V7K PCIE_PTX_WLANRX_N2_C BB32
41 PCIE_PTX_WLANRX_N2 PETN2
C161 1 2 0.1U_0402_10V7K PCIE_PTX_WLANRX_P2_C AY32 PCH_HOT# 1 2
41 PCIE_PTX_WLANRX_P2 PETP2

SMBUS
A12 DRAMRST_CNTRL_PCH R156 10K_0402_5%
SML0ALERT# / GPIO60 DRAMRST_CNTRL_PCH 6,9,40
BG36 PERN3
BJ36 C8 SML0CLK DRAMRST_CNTRL_PCH 1 2
PERP3 SML0CLK R157 1K_0402_1%
AV34 PETN3
AU34 G12 SML0DATA
PETP3 SML0DATA
1 2
36 PCIE_PRX_USB3TX_N4 PCIE_PRX_USB3TX_N4 BF36 R750 100K_0402_5%
USB30@ PCIE_PRX_USB3TX_P4 PERN4 ER14 @
36 PCIE_PRX_USB3TX_P4 BE36 PERP4
USB3.0 controller ---> C1043 1 2 0.1U_0402_10V7K PCIE_PTX_USB3RX_N4_C AY34 C13 PCH_HOT#
36 PCIE_PTX_USB3RX_N4 PETN4 SML1ALERT# / PCHHOT# / GPIO74
C1044 1 2 0.1U_0402_10V7K PCIE_PTX_USB3RX_P4_C BB34
36 PCIE_PTX_USB3RX_P4 PETP4
USB30@ E14 PCH_SMLCLK
SML1CLK / GPIO58

PCI-E*
BG37 PERN5 PCH_SMLDATA
EC
BH37 PERP5 SML1DATA / GPIO75 M16
AY36 PETN5
BB36 ER03 CLKIN_DMI2# R158 1 2 10K_0402_5%
PETP5 CLKIN_DMI2 R159 10K_0402_5%
1 2
BJ38 CLKIN_DMI# R160 1 2 10K_0402_5%
PERN6 CLKIN_DMI R161 10K_0402_5%
BG38 PERP6 1 2
@ T14 PAD CLKIN_DOT96# R162 10K_0402_5%

Controller
AU36 PETN6 CL_CLK1 M7 1 2
AV36 CLKIN_DOT96 R163 1 2 10K_0402_5%
PETP6 CLKIN_SATA# R164 10K_0402_5%
1 2

Link
BG40 T11 @ T15 PAD CLKIN_SATA R165 1 2 10K_0402_5%
PERN7 CL_DATA1 CLK_PCH_14M R166 10K_0402_5%
BJ40 PERP7 1 2
C AY40 C
PETN7 @ T16 PAD
BB40 PETP7 CL_RST1# P10
If use extenal CLK gen, please place close to CLK gen
BE38 else, please place close to PCH
PERN8
BC38 PERP8
AW38 PETN8
AY38 PETP8
M10 PEG_CLKREQ#_R
PEG_A_CLKRQ# / GPIO47 PEG_CLKREQ#_R 20
R167 1 2 0_0402_5% PCIE_LAN# Y40
32 CLK_PCIE_LAN# CLKOUT_PCIE0N
10/100/1G LAN ---> R168 1 2 0_0402_5% PCIE_LAN Y39
32 CLK_PCIE_LAN CLKOUT_PCIE0P
AB37 CLK_PCIE_VGA#
CLKOUT_PEG_A_N CLK_PCIE_VGA# 20
R169 1 2 10K_0402_5% LANCLK_REQ# CLK_PCIE_VGA VGA

CLOCKS
+3V_PCH J2 PCIECLKRQ0# / GPIO73 CLKOUT_PEG_A_P AB38 CLK_PCIE_VGA 20
32 LANCLK_REQ#
R170 2 1 0_0402_5% PCIE_WLAN# AB49 AV22 CLK_CPU_DMI#
41 CLK_PCIE_WLAN# CLKOUT_PCIE1N CLKOUT_DMI_N CLK_CPU_DMI# 5 +3VS +3VS
R171 2 1 0_0402_5% PCIE_WLAN AB47 AU22 CLK_CPU_DMI
41 CLK_PCIE_WLAN CLKOUT_PCIE1P CLKOUT_DMI_P CLK_CPU_DMI 5
MiniWLAN (Mini Card 1)---> +3VS R172 2 1 10K_0402_5%
41 WLANCLK_REQ# WLANCLK_REQ# M1 PCIECLKRQ1# / GPIO18
CLKOUT_DP_N AM12
CLKOUT_DP_P AM13

2
AA48 CLKOUT_PCIE2N
AA47 R173 R174
CLKOUT_PCIE2P CLKIN_DMI#
CLKIN_DMI_N BF18 2.2K_0402_5% 2.2K_0402_5%
+3VS R175 1 2 10K_0402_5% V10 BE18 CLKIN_DMI
PCIECLKRQ2# / GPIO20 CLKIN_DMI_P

1
2
R1054 2 USB30@ 1 0_0402_5% PCIE_USB30# Y37 BJ30 CLKIN_DMI2#
36 CLK_PCIE_USB30# CLKOUT_PCIE3N CLKIN_GND1_N
R1055 2 USB30@ 1 0_0402_5% PCIE_USB30 Y36 BG30 CLKIN_DMI2 SMBCLK 6 1
36 CLK_PCIE_USB30 CLKOUT_PCIE3P CLKIN_GND1_P PCH_SMBCLK 10,11,41
USB3.0 controller ---> +3V_PCH R176 2 1 10K_0402_5%
A8 2N7002DW-T/R7_SOT363-6
36 CLKREQ_USB30# PCIECLKRQ3# / GPIO25
G24 CLKIN_DOT96# Q2A
B CLKIN_DOT_96N CLKIN_DOT96 B
CLKIN_DOT_96P E24
Y43 CLKOUT_PCIE4N

5
Y45 CLKOUT_PCIE4P
AK7 CLKIN_SATA#
R177 CLKIN_SATA_N
+3V_PCH 2 1 10K_0402_5% L12 PCIECLKRQ4# / GPIO26 CLKIN_SATA_P AK5 CLKIN_SATA SMBDATA 3 4 PCH_SMBDATA 10,11,41
2N7002DW-T/R7_SOT363-6
V45 K45 CLK_PCH_14M Q2B
CLKOUT_PCIE5N REFCLK14IN
V46 CLKOUT_PCIE5P

+3V_PCH R178 2 1 10K_0402_5% L14 H45 CLK_PCI_LPBACK

PCIECLKRQ5# / GPIO44 CLKIN_PCILOOPBACK CLK_PCI_LPBACK 15

AB42 V47 XTAL25_IN

CLKOUT_PEG_B_N XTAL25_IN XTAL25_OUT
AB40 CLKOUT_PEG_B_P XTAL25_OUT V49
@ @
R180 C162 +3V_PCH R179 1 2 10K_0402_5% PEG_B_CLKREQ# E6
CLK_PCI_LPBACK 2 PEG_B_CLKRQ# / GPIO56
1 1 2
33_0402_5% 22P_0402_50V8J Y47 XCLK_RCOMP 1 2 +1.05VS_VCCDIFFCLKN ER03
XCLK_RCOMP R181 90.9_0402_1%
Reserve for EMI please close to V40 CLKOUT_PCIE6N
U3 V42 CLKOUT_PCIE6P PCH_SMLCLK PCH_SMLCLK 20,40
+3V_PCH R182 1 2 10K_0402_5% PCIE_CLKREQ6# T13 PCIECLKRQ6# / GPIO45
XTAL25_IN V38 K43 CLK_SD_48M_R 2 1 CLK_SD_48M PCH_SMLDATA PCH_SMLDATA 20,40
CLKOUT_PCIE7N CLKOUTFLEX0 / GPIO64 CLK_SD_48M 34
R277 0_0402_5%
FLEX CLOCKS

V37 CLKOUT_PCIE7P
2 1 XTAL25_OUT F47 @ T17 PAD
1M_0402_5% R183 R184 1 GPIO46 CLKOUTFLEX1 / GPIO65
+3V_PCH 2 10K_0402_5% K12 PCIECLKRQ7# / GPIO46
ER13 H47 @ T18 PAD
CLK_CPU_ITP# R185 CLKOUTFLEX2 / GPIO66
Y2 5 CLK_CPU_ITP# 2 XDP@ 1 0_0402_5% CLK_BCLK_ITP# AK14 CLKOUT_ITPXDP_N
CLK_CPU_ITP R186 2 1 0_0402_5% CLK_BCLK_ITP AK13 K49 @ T19 PAD
5 CLK_CPU_ITP CLKOUT_ITPXDP_P CLKOUTFLEX3 / GPIO67
XDP@
A 1 3 A
1 3 R187 @
7 CLK_RES_ITP# 2 1 0_0402_5% PANTHER-POINT_FCBGA989
GND GND R188 @
7 CLK_RES_ITP 2 1 0_0402_5%
2 25MHZ_10PF_7V25000014
2
C163 2 4 C164
12P_0402_50V8J 12P_0402_50V8J
1 1 @ @

CLK_PCH_14M
R189 C165 Security Classification Compal Secret Data Compal Electronics, Inc.
2 1 1 2 Issued Date 2011/07/12 Deciphered Date 2012/12/31 Title
33_0402_5% 22P_0402_50V8J
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (2/8) PCIE, SMBUS, CLK
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-8221P
Date: Wednesday, October 26, 2011 Sheet 13 of 58
5 4 3 2 1
 5 4 3 2 1

U3C PCH_ENBKL
40 PCH_ENBKL
U3D

4 DMI_CTX_PRX_N0 DMI_CTX_PRX_N0 BC24 BJ14 FDI_CTX_PRX_N0 FDI_CTX_PRX_N0 4 1 R190 2 J47 AP43

DMI_CTX_PRX_N1 DMI0RXN FDI_RXN0 FDI_CTX_PRX_N1 100K_0402_5% M45 L_BKLTEN SDVO_TVCLKINN
4 DMI_CTX_PRX_N1 BE20 DMI1RXN FDI_RXN1 AY14 FDI_CTX_PRX_N1 4 30 PCH_ENVDD L_VDD_EN SDVO_TVCLKINP AP45
4 DMI_CTX_PRX_N2 DMI_CTX_PRX_N2 BG18 BE14 FDI_CTX_PRX_N2 FDI_CTX_PRX_N2 4
DMI_CTX_PRX_N3 DMI2RXN FDI_RXN2 FDI_CTX_PRX_N3
4 DMI_CTX_PRX_N3 BG20 DMI3RXN FDI_RXN3 BH13 FDI_CTX_PRX_N3 4 30 PCH_INV_PWM P45 L_BKLTCTL SDVO_STALLN AM42
BC12 FDI_CTX_PRX_N4 FDI_CTX_PRX_N4 4 AM40
DMI_CTX_PRX_P0 FDI_RXN4 FDI_CTX_PRX_N5 SDVO_STALLP
4 DMI_CTX_PRX_P0 BE24 DMI0RXP FDI_RXN5 BJ12 FDI_CTX_PRX_N5 4 30 PCH_LCD_CLK T40 L_DDC_CLK
4 DMI_CTX_PRX_P1 DMI_CTX_PRX_P1 BC20 BG10 FDI_CTX_PRX_N6 FDI_CTX_PRX_N6 4 K47 AP39
DMI1RXP FDI_RXN6 30 PCH_LCD_DATA L_DDC_DATA SDVO_INTN
4 DMI_CTX_PRX_P2 DMI_CTX_PRX_P2 BJ18 BG9 FDI_CTX_PRX_N7 FDI_CTX_PRX_N7 4 AP40
DMI_CTX_PRX_P3 DMI2RXP FDI_RXN7 CTRL_CLK SDVO_INTP
D 4 DMI_CTX_PRX_P3 BJ20 DMI3RXP T45 L_CTRL_CLK
D
BG14 FDI_CTX_PRX_P0 FDI_CTX_PRX_P0 4 CTRL_DATA P39
DMI_CRX_PTX_N0 FDI_RXP0 FDI_CTX_PRX_P1 L_CTRL_DATA
4 DMI_CRX_PTX_N0 AW24 DMI0TXN FDI_RXP1 BB14 FDI_CTX_PRX_P1 4
DMI_CRX_PTX_N1 AW20 BF14 FDI_CTX_PRX_P2 FDI_CTX_PRX_P2 4 2 1 LVDS_IBG AF37 P38 HDMICLK_NB
4 DMI_CRX_PTX_N1 DMI1TXN FDI_RXP2 LVD_IBG SDVO_CTRLCLK HDMICLK_NB 35
DMI_CRX_PTX_N2 BB18 BG13 FDI_CTX_PRX_P3 FDI_CTX_PRX_P3 4 R191 2.37K_0402_1% AF36 M39 HDMIDAT_NB
4 DMI_CRX_PTX_N2 DMI2TXN FDI_RXP3 LVD_VBG SDVO_CTRLDATA HDMIDAT_NB 35
DMI_CRX_PTX_N3 AV18 BE12 FDI_CTX_PRX_P4 FDI_CTX_PRX_P4 4 T20
4 DMI_CRX_PTX_N3 DMI3TXN FDI_RXP4

DMI
FDI
BG12 FDI_CTX_PRX_P5 FDI_CTX_PRX_P5 4 PAD AE48
DMI_CRX_PTX_P0 FDI_RXP5 FDI_CTX_PRX_P6 LVD_VREFH
4 DMI_CRX_PTX_P0 AY24 DMI0TXP FDI_RXP6 BJ10 FDI_CTX_PRX_P6 4 AE47 LVD_VREFL DDPB_AUXN AT49
DMI_CRX_PTX_P1 AY20 BH9 FDI_CTX_PRX_P7 FDI_CTX_PRX_P7 4 AT47
4 DMI_CRX_PTX_P1 DMI1TXP FDI_RXP7 DDPB_AUXP
DMI_CRX_PTX_P2 AY18 AT40 TMDS_B_HPD
4 DMI_CRX_PTX_P2 DMI2TXP DDPB_HPD TMDS_B_HPD 35
DMI_CRX_PTX_P3 AU18 PCH_TXCLK- AK39
4 DMI_CRX_PTX_P3 DMI3TXP 30 PCH_TXCLK- LVDSA_CLK#

LVDS
AW16 FDI_INT PCH_TXCLK+ AK40 AV42 TMDS_B_DATA2#
FDI_INT FDI_INT 4 30 PCH_TXCLK+ LVDSA_CLK DDPB_0N TMDS_B_DATA2# 35
AV40 TMDS_B_DATA2
+1.05VS_VCC_EXP DDPB_0P TMDS_B_DATA2 35
BJ24 AV12 FDI_FSYNC0 PCH_TXOUT0- AN48 AV45 TMDS_B_DATA1#
DMI_ZCOMP FDI_FSYNC0 FDI_FSYNC0 4 30 PCH_TXOUT0- LVDSA_DATA#0 DDPB_1N TMDS_B_DATA1# 35
PCH_TXOUT1- AM47 AV46 TMDS_B_DATA1
30 PCH_TXOUT1- LVDSA_DATA#1 DDPB_1P TMDS_B_DATA1 35

Digital Display Interface

1 2 DMI_IRCOMP BG25 BC10 FDI_FSYNC1 PCH_TXOUT2- AK47 AU48 TMDS_B_DATA0#
DMI_IRCOMP FDI_FSYNC1 FDI_FSYNC1 4 30 PCH_TXOUT2- LVDSA_DATA#2 DDPB_2N TMDS_B_DATA0# 35
R192 49.9_0402_1% AJ48 AU47 TMDS_B_DATA0
LVDSA_DATA#3 DDPB_2P TMDS_B_DATA0 35
1 2 RBIAS_CPY BH21 AV14 FDI_LSYNC0 AV47 TMDS_B_CLK#
DMI2RBIAS FDI_LSYNC0 FDI_LSYNC0 4 DDPB_3N TMDS_B_CLK# 35
R193 750_0402_1% PCH_TXOUT0+ AN47 AV49 TMDS_B_CLK
30 PCH_TXOUT0+ LVDSA_DATA0 DDPB_3P TMDS_B_CLK 35
4mil width and place BB10 FDI_LSYNC1 PCH_TXOUT1+ AM49
FDI_LSYNC1 FDI_LSYNC1 4 30 PCH_TXOUT1+ LVDSA_DATA1
PCH_TXOUT2+ AK49
within 500mil of the PCH 30 PCH_TXOUT2+
AJ47
LVDSA_DATA2
P46
LVDSA_DATA3 DDPC_CTRLCLK
DDPC_CTRLDATA P42
ER23 A18 DSWODVREN ER23
DSWVRMEN
AF40 LVDSB_CLK#
R800 1 @ 2 0_0402_5% PCH_DPWROK AF39 AP47

System Power Management

PCH_DPWROK 40 LVDSB_CLK DDPC_AUXN
40 SUSACK# R802 1 @ 2 SUSACK#_R C12 E22 PCH_DPWROK_R AP49
0_0402_5% SUSACK# DPWROK DDPC_AUXP
1 R194 2 0_0402_5% PCH_RSMRST#_R AH45 LVDSB_DATA#0 DDPC_HPD AT38
AH47 LVDSB_DATA#1
5,12 XDP_DBRESET#_R XDP_DBRESET#_R K3 B9 WAKE# 1 R195 2 PCIE_WAKE# 32,36,41 AF49 AY47
SYS_RESET# WAKE# 0_0402_5% LVDSB_DATA#2 DDPC_0N
AF45 LVDSB_DATA#3 DDPC_0P AY49
DDPC_1N AY43
SYSTEM_PWROK 1 2 SYSTEM_PWROK_I P12 N3 PM_CLKRUN# 1 R529 2 PM_CLKRUNEC# 40 AH43 AY45
R196 0_0402_5% SYS_PWROK CLKRUN# / GPIO32 0_0402_5% @ LVDSB_DATA0 DDPC_1P
AH49 LVDSB_DATA1 DDPC_2N BA47
C
AF47 LVDSB_DATA2 DDPC_2P BA48 C
40 PCH_PWROK 1 2PM_PWROK_R L22 PWROK SUS_STAT# / GPIO61 G8 SUS_STAT# T22 PAD AF43 LVDSB_DATA3 DDPC_3N BB47
R197 0_0402_5% BB49
DDPC_3P
1 2 L10 N14 SUSCLK 2 R199 1
APWROK SUSCLK / GPIO62 SUSCLK_R 40
R198 0_0402_5% 0_0402_5% PCH_CRT_BLU N48 M43
30 PCH_CRT_BLU CRT_BLUE DDPD_CTRLCLK
PCH_CRT_GRN P49 M36
30 PCH_CRT_GRN CRT_GREEN DDPD_CTRLDATA
PM_DRAM_PWRGD B13 D10 PM_SLP_S5# PCH_CRT_RED T49
5 PM_DRAM_PWRGD DRAMPWROK SLP_S5# / GPIO63 PM_SLP_S5# 40 30 PCH_CRT_RED CRT_RED

DDPD_AUXN AT45

CRT
40 PCH_RSMRST# R200 1 2 PCH_RSMRST#_R C21 H4 PM_SLP_S4# PCH_CRT_DDC_CLK T39 AT43
RSMRST# SLP_S4# PM_SLP_S4# 40 30 PCH_CRT_DDC_CLK CRT_DDC_CLK DDPD_AUXP
0_0402_5% PCH_CRT_DDC_DAT M40 BH41
30 PCH_CRT_DDC_DAT CRT_DDC_DATA DDPD_HPD
ER23
R801 1 @ 2 SUSWARN#_R K16 F4 PM_SLP_S3# R201 33_0402_5% BB43
40 SUSWARN# SUSWARN#/SUSPWRDNACK/GPIO30 SLP_S3# PM_SLP_S3# 40 DDPD_0N
0_0402_5% 30 PCH_CRT_HSYNC 1 2 HSYNC_PCH M47 BB45
CRT_HSYNC DDPD_0P
30 PCH_CRT_VSYNC 1 2 VSYNC_PCH M49 CRT_VSYNC DDPD_1N BF44
5,40 PBTN_OUT# 1 2 PBTN_OUT#_R E20 G10 T23 PAD R202 33_0402_5% BE44
R203 0_0402_5% PWRBTN# SLP_A# DDPD_1P
DDPD_2N BF42
D2 @ CRT_IREF T43 BE42
AC_PRESENT_R T24 PAD DAC_IREF DDPD_2P
40,44 ACIN 1 2 H20 ACPRESENT / GPIO31 SLP_SUS# G16 T42 CRT_IRTN DDPD_3N BJ42
DDPD_3P BG42

1
RB751V-40_SOD323-2
PCH_GPIO72 E10 AP14 H_PM_SYNC PANTHER-POINT_FCBGA989
BATLOW# / GPIO72 PMSYNCH H_PM_SYNC 5
Reserve 40 AC_PRESENT 1 2 R204
R751 0_0402_5% 1K_0402_0.5%
RI# A10 K14 PCH_GPIO29 T25 PAD

2
RI# SLP_LAN# / GPIO29
ER18
PANTHER-POINT_FCBGA989
@ 1 2 XDP_DBRESET#_R <BOM Structure>
C166 100P_0402_50V8J

Reserve for EMI please close to U3

B +3VS ER01 B

1 2 PCH_CRT_DDC_CLK Del R205

R206 2.2K_0402_5%
1 2 PCH_CRT_DDC_DAT
R207 2.2K_0402_5%
+3VS 1 2 CTRL_CLK
R208 2.2K_0402_5%
5

U7 1 2 CTRL_DATA +3VS
1 2 2 +RTCVCC R209 2.2K_0402_5%
P

5,51 VGATE
R210 0_0402_5% B 4 SYSTEM_PWROK R211 1 2 2.2K_0402_5% PCH_LCD_CLK
Y SYSTEM_PWROK 5
PCH_PWROK 1 A R212 1 2 2.2K_0402_5% PCH_LCD_DATA
G

DSWODVREN R213 2 1 330K_0402_5%

NC7SZ08P5X_NL_SC70-5
3

DSWODVREN R214 2 @ 1 330K_0402_5%

+3V_PCH DSWODVREN - On Die DSW VR Enable

ER20
* HEnable
LDisable 1 2 PCH_CRT_BLU
PCH_GPIO29 R230 1 2 10K_0402_5% R215 150_0402_1%~D
1 2 PCH_CRT_GRN
R216 150_0402_1%~D
PCH_GPIO72 R217 1 2 10K_0402_5% 1 2 PCH_CRT_RED
R218 150_0402_1%~D
RI# R219 1 2 10K_0402_5% 1 2 PCH_ENVDD
R220 @ 100K_0402_5%~D
WAKE# R221 1 2 10K_0402_5% +3VS

AC_PRESENT_R R222 1 2 200K_0402_5%

1

SUSWARN#_R R223 1 2 10K_0402_5%

@ R224
ER23 8.2K_0402_5%
A A
PCH_DPWROK R803 2 @ 1 100K_0402_5%
2

PCH_RSMRST# R225 1 2 10K_0402_5% PM_CLKRUN#

2

R130
PM_PWROK_R 2 1 10K_0402_5%

SYSTEM_PWROK_I
@ R226 100K_0402_5% Security Classification Compal Secret Data Compal Electronics, Inc.
2 1 Issued Date 2011/07/12 Deciphered Date 2012/12/31 Title
1

@ R227 100K_0402_5% Intel CRB EMRLDLKE2 Rev1.0

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (3/8) DMI,FDI,PM,GFX,DP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-8221P
Date: Wednesday, October 26, 2011 Sheet 14 of 58
5 4 3 2 1
 5 4 3 2 1

U3E
RSVD1 AY7
RSVD2 AV7
BG26 TP1 RSVD3 AU3
BJ26 TP2 RSVD4 BG4
BH25
BJ16
TP3
AT10
GPIO19 => BBS_BIT0
TP4 RSVD5
BG16
AH38
TP5 RSVD6 BC8 GPIO51 => BBS_BIT1
TP6
AH37 TP7 RSVD7 AU2 Boot BIOS Strap
AK43 TP8 RSVD8 AT4
AK45 TP9 RSVD9 AT3 BBS_BIT0 BBS_BIT1 Boot BIOS
C18 TP10 RSVD10 AT1 Location
N30 TP11 RSVD11 AY3
D
H3 TP12 RSVD12 AT5 0 0 LPC D
AH12 TP13 RSVD13 AV3
AM4 TP14 RSVD14 AV1 0 1 Reserved(NAND)
AM5 TP15 RSVD15 BB1
Y13 TP16 RSVD16 BA3 Panther Point USB Port Mapping 1 0 Reserved
K24 TP17 RSVD17 BB5
L24 TP18 RSVD18 BB3 1 1 SPI *
AB46 TP19 RSVD19 BB7
AB45 TP20 RSVD20 BE8

RSVD
RSVD21 BD4
RSVD22 BF6

B21 AV5 NV_ALE
TP21 RSVD23
M20 TP22 RSVD24 AV10
AY16 TP23 Intel Anti-Theft Techonlogy
BG46 TP24 RSVD25 AT8
High=Endabled
RSVD26 AY5 NV_ALE
BA2 Low=Disable(floating)
37 USB3_RX1_N BE28 USB3Rn1
RSVD27 *
37 USB3_RX2_N BC30 USB3Rn2 RSVD28 AT12 +1.8VS
BE32 USB3Rn3 RSVD29 BF3
BJ32 USB3Rn4
37 USB3_RX1_P BC28 NV_ALE @ R228 1 2 1K_0402_5%
USB3Rp1
37 USB3_RX2_P BE30 USB3Rp2
BF32 USB3Rp3
BG32 C24 USB20_N0 USB2/3 port 1
USB3Rp4 USBP0N USB20_N0 37
AV26 A24 USB20_P0
37 USB3_TX1_N USB3Tn1 USBP0P USB20_P0 37
BB26 C25 USB20_N1 USB2/3 port 2
37 USB3_TX2_N USB3Tn2 USBP1N USB20_N1 37
AU28 B25 USB20_P1
USB3Tn3 USBP1P USB20_P1 37
AY30 USB3Tn4 USBP2N C26
37 USB3_TX1_P AU26 USB3Tp1 USBP2P A26
37 USB3_TX2_P AY26 USB3Tp2 USBP3N K28
C AV28 H28 C
USB3Tp3 USBP3P USB20_N4
AW30 USB3Tp4 USBP4N E28 USB20_N4 41
D28 USB20_P4 Mini Card(WLAN) Bluetooth
USBP4P USB20_P4 41
(5
USBP5N C28
USBP5P A28
USBP6N C29
USBP6P B29
PCI_PIRQA# K40 N28 HM76 not Support USB Port6,7 +3V_PCH
PCI_PIRQB# PIRQA# USBP7N
K38 PIRQB# USBP7P M28

PCI
PCI_PIRQC# H38 L30 USB20_N8
PIRQC# USBP8N USB20_N8 30
PCI_PIRQD# G38 K30 USB20_P8 Camera USB_OC0# 10K_0402_5% 1 2 R776 Over Current Pin Default Usage
PIRQD# USBP8P USB20_P8 30
G30 USB20_N9 USB_OC2# 10K_0402_5% 1 2 R777
USBP9N USB20_N9 33
DGPU_HOLD_RST# C46 E30 USB20_P9 USB2 Conn. R USB_OC7# 10K_0402_5% 1 2 R778
REQ1# / GPIO50 USBP9P USB20_P9 33

USB
PCH_GPIO52 C44 C30 USB20_N10 USB_OC5# 10K_0402_5% 1 2 R779
REQ2# / GPIO52 USBP10N USB20_N10 34
20,29,54 DGPU_PWR_EN
DGPU_PWR_EN E40 REQ3# / GPIO54 USBP10P A30 USB20_P10
USB20_P10 34 Card Reader
USBP11N L32
D47 GNT1# / GPIO51 USBP11P K32
E42 GNT2# / GPIO53 USBP12N G32 USB_OC6# 10K_0402_5% 1 2 R780
41 PCH_WAN_RADIO_OFF# PCH_WAN_RADIO_OFF# F46 E32 USB_OC4# 10K_0402_5% 1 2 R781
GNT3# / GPIO55 USBP12P USB_OC3# 10K_0402_5% R782
USBP13N C32 1 2
A32 USB_OC1# 10K_0402_5% 1 2 R783
PCH_GPIO2 USBP13P
G42 PIRQE# / GPIO2
C167 31 ODD_DA# ODD_DA# G40 Within 500 mils
PIRQF# / GPIO3
@ 1 2 ODD_DA# PCH_GPIO4 C42 PIRQG# / GPIO4 USBRBIAS# C33 USBRBIAS 1 2
0.1U_0402_16V4Z~D PCH_GPIO5 D44 R231 22.6_0402_1%
PIRQH# / GPIO5
Reserve for EMI please close to U3 B33
PAD T26 @ USBRBIAS
K10 PME#
PCH_PLTRST# C6 PLTRST# OC0# / GPIO59 A14 USB_OC0#
USB_OC0# 37 (For USB Port0, 1)
K20 USB_OC1#
OC1# / GPIO40 USB_OC2#
OC2# / GPIO41 B17
B
13 CLK_PCI_LPBACK
CLK_PCI_LPBACK R232 2 1 22_0402_5% CLK_PCI0 H49 CLKOUT_PCI0 OC3# / GPIO42 C16 USB_OC3# B
CLK_PCI_LPC R233 1 2 22_0402_5% CLK_PCI1 H43 L16 USB_OC4# (For USB Port9)
40 CLK_PCI_LPC CLKOUT_PCI1 OC4# / GPIO43 USB_OC4# 37
CLK_LPC_DEBUG1 R234 1 2 22_0402_5% CLK_PCI3 J48 A16 USB_OC5#
41 CLK_LPC_DEBUG1 CLKOUT_PCI2 OC5# / GPIO9
K42 D14 USB_OC6#
CLKOUT_PCI3 OC6# / GPIO10 USB_OC7#
H40 CLKOUT_PCI4 OC7# / GPIO14 C14

PANTHER-POINT_FCBGA989

(5 +3VS
1 @ 2
R235 0_0402_5% 1 @ 2
PCH_GPIO4 8.2K_0402_5% 1 2 R784 +3VS +3VS R236 0_0402_5%
PCI_PIRQB# 8.2K_0402_5% 1 2 R785
2

PCI_PIRQD# 8.2K_0402_5% 1 2 R786 @ C168 +3VS

PCI_PIRQC# 8.2K_0402_5% 1 2 R787 R238 1 2
10K_0402_5% 0.1U_0402_16V4Z~D C169 DIS@
5

U8 1 2
0.1U_0402_16V4Z~D
VCC
1

5
1 PCH_PLTRST# U9
PCH_WAN_RADIO_OFF# 8.2K_0402_5% R788 IN1 DIS@ PCH_PLTRST#
1 2 4 B 2

P
5,32,36,40,41 PLT_RST# OUT
PCI_PIRQA# 8.2K_0402_5% 1 2 R789 2 2 1 R240 4
GND

IN2 20 DGPU_RST# Y
ODD_DA# 8.2K_0402_5% 1 2 R790 100_0402_5% 1 DGPU_HOLD_RST#
A

G
PCH_GPIO5 8.2K_0402_5% 1 2 R791

1
DIS@ NC7SZ08P5X_NL_SC70-5
3

3
MC74VHC1G08DFT2G_SC70-5 R241
100K_0402_5%
DIS@
1

PCH_GPIO52 8.2K_0402_5% 1 2 R792

2
PCH_GPIO2 8.2K_0402_5% 1 2 R793
R243
A 100K_0402_5% A
2

ER20
DGPU_HOLD_RST# 1 R244 2 10K_0402_5%

DGPU_PWR_EN
Security Classification Compal Secret Data Compal Electronics, Inc.
1 R288 2 10K_0402_5% Issued Date 2011/07/12 Deciphered Date 2012/12/31 Title
@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (4/8) PCI, USB, NVRAM
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-8221P
Date: Wednesday, October 26, 2011 Sheet 15 of 58
5 4 3 2 1
 5 4 3 2 1

+3VS

CRT_DET 1 @ 2 10K_0402_5%
R245 U3F
ODD_DETECT# 1 2 200K_0402_5%
R246 CRT_DET T7 C40 ODD_EN#
BMBUSY# / GPIO0 TACH4 / GPIO68 ODD_EN# 31
PCH_GPIO16 1 2 10K_0402_5% DMI Termination Voltage
R247 PCH_GPIO1 A42 B41 PCH_GPIO69 ER22
PCH_BT_ON TACH1 / GPIO1 TACH5 / GPIO69
1 2 10K_0402_5% Set to Vcc when HIGH
R248 USB30_SMI# H36 C41 GPIO70 @ T28 PAD +3VS DF_TVS
KB_RST# 36 USB30_SMI# TACH2 / GPIO6 TACH6 / GPIO70
1 2 10K_0402_5% Set to Vss when LOW
R249 40 EC_SCI# EC_SCI# E38 A40 GPIO71 @ T29 PAD
TACH3 / GPIO7 TACH7 / GPIO71

2
D PCH_GPIO48 1 2 10K_0402_5% D
R250 EC_SMI# C10 R251 +1.8VS
40 EC_SMI# GPIO8
PCH_GPIO22 1 2 10K_0402_5% 10K_0402_5%
R252 C4 LAN_PHY_PWR_CTRL / GPIO12

1
ODD_EN# 1 2 10K_0402_5%

1
R253 EC_LID_OUT# 1 2 PCH_LID_SW_IN# G2 P4 GATEA20
40 EC_LID_OUT# GPIO15 A20GATE GATEA20 40
DGPU_PWROK 1 2 10K_0402_5% 0_0402_5% R498 R254
R255 AU16 2.2K_0402_5%
PCH_GPIO16 PECI
U2

2
SATA4GP / GPIO16 DF_TVS
RCIN# P5 KB_RST# 40 2 1 H_SNB_IVB# 5
+3VS 1K_0402_5% R256

GPIO
ER22 DGPU_PWROK D40 AY11
40 DGPU_PWROK TACH0 / GPIO17 PROCPWRGD H_CPUPWRGD 5
PCH_GPIO69

CPU/MISC
1 2 CLOSE TO THE BRANCHING POINT
10K_0402_5% R807 PCH_GPIO22 T5 AY10 H_THERMTRIP#_C 1 2 H_THERMTRIP# H_THERMTRIP# 5
SCLOCK / GPIO22 THRMTRIP# 390_0402_5% R258
2 1 PCH_GPIO1 E8 T14
10K_0402_5% R257 GPIO24 INIT3_3V#
1 @ 2 PCH_GPIO37
40 DS_WAKE#
DS_WAKE# 1 @ 2 PCH_GPIO27 E16 GPIO27 DF_TVS AY1 DF_TVS
10K_0402_5% R259 R804 0_0402_5%
2 1 PCH_GPIO38 PCH_GPIO28 P8
10K_0402_5% R260 GPIO28
ER23 TS_VSS1 AH8
2 1 PCH_GPIO39 PCH_BT_ON K1
41 PCH_BT_ON STP_PCI# / GPIO34
10K_0402_5% R261 AK11
PCH_GPIO49 TS_VSS2
1 2 K4 GPIO35
10K_0402_5% R262 AH10
USB30_SMI# ODD_DETECT# TS_VSS3
2 1 31 ODD_DETECT# V8 SATA2GP / GPIO36
10K_0402_5% R263 AK10
PCH_GPIO37 TS_VSS4
M5 SATA3GP / GPIO37 @ 1 2 H_CPUPWRGD
PCH_GPIO38 N2 P37 @ T30 PAD C170 100P_0402_50V8J
SLOAD / GPIO38 NC_1
R264 2 1 PCH_GPIO37 PCH_GPIO39 M3
C 100K_0402_5% SDATAOUT0 / GPIO39 C
PCH_GPIO48 V13 BG2 Reserve for EMI please close to U3
SDATAOUT1 / GPIO48 VSS_NCTF_15
2 R265 1 0_0402_5% PCH_GPIO49 V3 BG48
30 CABC_SAVING SATA5GP / GPIO49 / TEMP_ALERT# VSS_NCTF_16
@
HDD2_DETECT# D6 BH3
GPIO57 VSS_NCTF_17
+3VALW
ER23
VSS_NCTF_18 BH47

A4 VSS_NCTF_1 VSS_NCTF_19 BJ4

1 @ 2 DS_WAKE#
10K_0402_5% R805 A44 BJ44
VSS_NCTF_2 VSS_NCTF_20
1 2 PCH_GPIO27 A45 BJ45
@ R266 10K_0402_5% VSS_NCTF_3 VSS_NCTF_21

NCTF
A46 VSS_NCTF_4 VSS_NCTF_22 BJ46

A5 VSS_NCTF_5 VSS_NCTF_23 BJ5

A6 VSS_NCTF_6 VSS_NCTF_24 BJ6

B3 VSS_NCTF_7 VSS_NCTF_25 C2

B47 VSS_NCTF_8 VSS_NCTF_26 C48

BD1 VSS_NCTF_9 VSS_NCTF_27 D1

+3V_PCH
BD49 VSS_NCTF_10 VSS_NCTF_28 D49

BE1 VSS_NCTF_11 VSS_NCTF_29 E1

PCH_GPIO28 1 2 10K_0402_5%
R268 BE49 E49
B VSS_NCTF_12 VSS_NCTF_30 B
BF1 VSS_NCTF_13 VSS_NCTF_31 F1
HDD2_DETECT# 1 2 10K_0402_5%
R269 BF49 F49
VSS_NCTF_14 VSS_NCTF_32

PCH_LID_SW_IN# 1 2 1K_0402_5% PANTHER-POINT_FCBGA989

R270
EC_SMI# 1 2 10K_0402_5%
R271
GPIO28
On-Die PLL Voltage Regulator
This signal has a weak internal pull up
HOn-Die voltage regulator enable
* LOn-Die PLL Voltage Regulator disable
1 2 PCH_GPIO28

@ R272 1K_0402_5%

+3VS
2

High: CRT Plugged R273

10K_0402_5%
A A
1

CRT_DET
1

D
2 Q12
30 CRT_DET#
G 2N7002_SOT23-3
S
3

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/07/12 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (5/8) GPIO, CPU, MISC
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-8221P
Date: Wednesday, October 26, 2011 Sheet 16 of 58
5 4 3 2 1
 5 4 3 2 1

PCH Power Rail Table

+1.05VS Refer to CPU EDS R1.5
U3G POWER +3VS S0 Iccmax
Voltage Rail Voltage Current (A)
1300mA L1

0.01U_0402_16V7K

0.1U_0402_10V7K
AA23 U48 +VCCADAC 2 1
VCCCORE[1] 1mA VCCADAC BLM18PG181SN1_0603
AC23 VCCCORE[2] 1 1 1 V_PROC_IO 1.05 0.001

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1 1 1 1 AD21

CRT
VCCCORE[3]

C171

C172
AD23 U47 C173
VCCCORE[4] VSSADAC

C175

C176

C177
C174 AF21 10U_0805_6.3V6M V5REF 5 0.001

VCC CORE
10U_0805_6.3V6M VCCCORE[5] 2 2 2
AF23
D 2 2 2 2 VCCCORE[6] +3VS D
AG21
VCCCORE[7]
AG23
VCCCORE[8]
V5REF_Sus 5 0.001
AG24 1mAVCCALVDS AK36
VCCCORE[9]
AG26
VCCCORE[10] +1.8VS
AG27
VCCCORE[11] VSSALVDS
AK37 Vcc3_3 3.3 0.228
AG29
VCCCORE[12] L2
AJ23
VCCCORE[13] Near AP43

LVDS
AJ26 AM37 +VCCTX_LVDS C180 2 1 VccADAC 3.3 0.001
VCCCORE[14] VCCTX_LVDS[1] C178 1 0.1UH_MLF1608DR10KT_10%_1608
AJ27 1 1
+1.05VS VCCCORE[15] 0.01U_0402_16V7K 22U_0805_6.3V6M 0.1uH inductor, 200mA
AJ29 AM38
VCCCORE[16] VCCTX_LVDS[2] C179
AJ31
VCCCORE[17]
VccADPLLA 1.05 0.075
40mAVCCTX_LVDS[3] AP36 0.01U_0402_16V7K
2 2 2

VCCTX_LVDS[4] AP37 VccADPLLB 1.05 0.075

AN19 VCCIO[28]
VccCore 1.05 1.3
BJ22 VCCAPLLEXP

VCC3_3[6] V33 +3VS VccDMI 1.05 0.042

HVCMOS
AN16 VCCIO[15]
1
AN17 VCCIO[16]
VccIO 1.05 3.709
+1.05VS V34 C182
VCC3_3[7]
0.1U_0402_10V7K
2 VccASW 1.05 0.903
AN21 VCCIO[17]
AN26 +1.5VS
VCCIO[18]
1

VccSPI 3.3 0.01

R274 R275 AN27 3709mA AT16
0_0805_5% +1.05VS_VCC_EXP VCCIO[19] VCCVRM[3]
0_0805_5%
AP21 +VCCP_VCCDMI +1.05VS VccDSW 3.3 0.001
C VCCIO[20] R276 C
2

+1.05VS_VCC_EXP AP23 AT20 +VCCP_VCCDMI 1 2

VCCIO[21] VCCDMI[1]
1 VccDFTERM 1.8 0.002

DMI
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1 1 1 1 1 AP24 0_0805_5%
VCCIO[22]

VCCIO
R387 C183
C185

C186

C187

C188

C184 AP26 75mA VCCCLKDMI AB36 +1.05VS_VCC_DMI_CCI 1 2 VccRTC 3.3 6 uA

VCCIO[23] +1.05VS 2
10U_0805_6.3V6M 1 0_0805_5% 1U_0402_6.3V6K
2 2 2 2 2 AT24
VCCIO[24] C189 VccSus3_3 3.3 0.065
1U_0402_6.3V6K ER20
+3VS AN33 2
VCCIO[25]
VccSusHDA 3.3 / 1.5 0.01
AN34 AG16
VCCIO[26] VCCDFTERM[1]
VccVRM 1.8 / 1.5 0.167
BH29 2mA VCCDFTERM[2] AG17 +1.8VS
VCC3_3[3]

DFT / SPI
1

0.1U_0402_10V7K
C190 +1.5VS VccCLKDMI 1.05 0.075
AJ16 1
0.1U_0402_10V7K VCCDFTERM[3]
2

C191
AP16
VCCVRM[2]
VccSSC 1.05 0.095
AJ17
VCCDFTERM[4] 2
BG6
VccAFDIPLL
VccDIFFCLKN 1.05 0.055

+1.05VS AP17 @ VccALVDS 3.3 0.001

VCCIO[27] +3V_VCCPSPI
10mA VCCSPI V1 2 1
FDI

+3V_PCH
R278 0_0603_5%
+VCCP_VCCDMI AU20
VCCDMI[2] 1 VccTX_LVDS 1.8 0.04
2 1 +3VS
C193 R279 0_0603_5%
B PANTHER-POINT_FCBGA989 1U_0402_6.3V6K B
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/07/12 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (6/8) PWR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-8221P
Date: Wednesday, October 26, 2011 Sheet 17 of 58
5 4 3 2 1
 5 4 3 2 1

+1.05VS

2 @ 1 +VCCACLK
+3V_PCH R280 0_0603_5%
U3J POWER
1 2
R281 0_0603_5% 1 AD49 N26 +1.05VS
VCCACLK VCCIO[29]

+3VALW
ER08 C194
VCCIO[30]
P26 1
0.1U_0402_10V7K +VCCPDSW T16
D 2 VCCDSW3_33mA C195 D
P28
@ VCCIO[31] 1U_0402_6.3V6K
1 2
R290 0_0603_5% +PCH_VCCDSW V12 T27 2
DCPSUSBYP VCCIO[32]
1
T29
@ C196 +3VS_VCC_CLKF33 VCCIO[33]
T38
0.1U_0402_10V7K VCC3_3[5]
2 T23
+1.05VS 119mA VCCSUS3_3[7] +3V_PCH

0.1U_0402_10V7K
BH23
VCCAPLLDMI2
T24 1 +3V_PCH
VCCSUS3_3[8] +5V_PCH +3V_PCH

0.1U_0402_10V7K
AL29
VCCIO[14]

C198
VCCSUS3_3[9] V23 1

USB

2
2

C199
+VCCSUS1 AL24 V24 +VCCA_USBSUS
DCPSUS[3] VCCSUS3_3[10]

1U_0402_6.3V6K
1 R282 D3
@ 2
VCCSUS3_3[6] P24 1 10_0402_5% RB751V40_SC76-2

@ C201
C200
1U_0402_6.3V6K AA19

1
2 VCCASW[1] +PCH_V5REF_SUS
VCCIO[34] T26 +1.05VS
AA21 903mA 2
VCCASW[2] 1

AA24 M26 +PCH_V5REF_SUS C202

VCCASW[3] 1mA V5REF_SUS 0.1U_0603_25V7K
1 1 +3V_PCH 2

0.1U_0402_10V7K
AA26

Clock and Miscellaneous

C203 C204 VCCASW[4] +VCCA_USBSUS
DCPSUS[4] AN23 1
22U_0805_6.3V6M 22U_0805_6.3V6M AA27
2 2 VCCASW[5]

C205
VCCSUS3_3[1] AN24
AA29 VCCASW[6] 2
+1.05VS AA31 +5VS +3VS
VCCASW[7]
AC26 P34 +PCH_V5REF_RUN
VCCASW[8] 1mA V5REF

2
C C

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D
1 1 1
AC27 R283 D4
VCCASW[9]
C206

C207

C208
VCCSUS3_3[2] N20 +3V_PCH 10_0402_5% RB751V40_SC76-2

PCI/GPIO/LPC
AC29 VCCASW[10] 1
2 2 2 N22

1
VCCSUS3_3[3] C209 +PCH_V5REF_RUN
AC31 VCCASW[11]
P20 1U_0402_6.3V +3VS
VCCSUS3_3[4] 2 1
AD29
VCCASW[12] C210
P22
VCCSUS3_3[5] 1U_0603_10V6K
AD31 1
VCCASW[13] 2
+3VS W21 AA16 C211
ER20 VCCASW[14] VCC3_3[1] 0.1U_0402_10V7K
R289 2 +3VS
W23 W16
+3VS_VCC_CLKF33 VCCASW[15] VCC3_3[8]
1 2
10U_0805_10V4Z

1U_0402_6.3V6K

1 1 W24 T34
0_0805_5% VCCASW[16] VCC3_3[4]
1
C212

C213

W26
VCCASW[17] C214
@ 2 2 W29 +3VS 0.1U_0402_10V7K
VCCASW[18] 2
W31 AJ2
VCCASW[19] VCC3_3[2] +1.05VS_SATA3
1
W33 R284
VCCASW[20] C215
AF13 2 1 +1.05VS
VCCIO[5] 0.1U_0402_10V7K
2 1
+1.05VS +VCCRTCEXT N16 0_0805_5%
+1.5VS DCPRTC C216
1 AH13
@ +1.05VM_VCCSUS VCCIO[12] 1U_0402_6.3V6K
2 1
R285 0_0603_5% C217 Y49 AH14 +1.05VS_SATA3 2
0.1U_0402_10V7K VCCVRM[4] VCCIO[13]
2
B +1.05VS AF14 B
+1.05VS_VCCA_A_DPL VCCIO[6]
BD47
VCCADPLLA75mA

SATA
AK1
+1.05VS_VCCA_B_DPL VCCAPLLSATA +1.5VS
BF47
VCCADPLLB75mA
1
C218 AF11
VCCVRM[1] +1.05VS_VCC_SATA
AF17
+1.05VS 1U_0402_6.3V6K +1.05VS_VCCDIFFCLKN VCCIO[7] R286
AF33
2 VCCDIFFCLKN[1] +1.05VS_VCC_SATA
18mil AF34
VCCDIFFCLKN[2]
55mA VCCIO[2]
AC16 2 1 +1.05VS
2 1 +1.05VS_VCCDIFFCLKN AG34
VCCDIFFCLKN[3]

1U_0402_6.3V6K
R287 0_0603_5% 1 AC17 1 0_0805_5%
VCCIO[3]
18mil

C221
C220 AG33 AD17
1U_0402_6.3V6K VCCSSC95mA VCCIO[4]
+1.05VS 2 2 +1.05VS
+VCCSST V16
DCPSST
1 1 +1.05VM_VCCSUS
C223 1 T17 T21
C222 0.1U_0402_10V7K @ DCPSUS[1] VCCASW[22]
V19
1U_0402_6.3V6K C224 DCPSUS[2]
MISC

+1.05VS 2 2 1U_0402_6.3V6K V21

2 VCCASW[23]
0.1U_0402_10V7K

0.1U_0402_10V7K

CPU

BJ8
V_PROC_IO
1mA
1 1 1 T19
VCCASW[21]
+RTCVCC
C226

C227

C225
4.7U_0603_6.3V6K
2 2 2 A22 P32 +VCCSUSHDA 1 2
RTC

VCCRTC 10mA VCCSUSHDA +3V_PCH

0.1U_0402_10V7K

0.1U_0402_10V7K

1U_0402_6.3V6K

0.1U_0402_10V7K
HDA

R291 0_0402_5%
1 1 1 1

150_0402_1%
L8 PANTHER-POINT_FCBGA989 If it support 3.3V audio signals

1
C228

C229

C230

C231

A 10UH_LBR2012T100M_20%~D POP:RH12 (0ohm) A

1 2 +1.05VS_VCCA_A_DPL
+1.05VS 2 2 2 2
R292
@
If it support 1.5V audio signals
220U_B2_2.5VM_R35M

1 2 +1.05VS_VCCA_B_DPL POP:RH12 (180 ohm)/RH13 (150 ohm)

2
220U_B2_2.5VM_R35M

L9
1U_0402_6.3V6K

1U_0402_6.3V6K

10UH_LBR2012T100M_20%~D 1 1
1 1 Security Classification Compal Secret Data Compal Electronics, Inc.
C232

C233

+ +
C234

C235

Issued Date 2011/07/12 Deciphered Date 2012/12/31 Title

2 2 2 2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (7/8) PWR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-8221P
Date: Wednesday, October 26, 2011 Sheet 18 of 58
5 4 3 2 1
 5 4 3 2 1

U3I

AY4 VSS[159] VSS[259] H46

AY42 K18
VSS[160] VSS[260]
AY46 K26
U3H VSS[161] VSS[261]
AY8 K39
D VSS[162] VSS[262] D
H5 B11 K46
VSS[0] VSS[163] VSS[263]
B15 K7
VSS[164] VSS[264]
AA17 AK38 B19 L18
VSS[1] VSS[80] VSS[165] VSS[265]
AA2 AK4 B23 L2
VSS[2] VSS[81] VSS[166] VSS[266]
AA3 AK42 B27 L20
VSS[3] VSS[82] VSS[167] VSS[267]
AA33 AK46 B31 L26
VSS[4] VSS[83] VSS[168] VSS[268]
AA34 AK8 B35 L28
VSS[5] VSS[84] VSS[169] VSS[269]
AB11 AL16 B39 L36
VSS[6] VSS[85] VSS[170] VSS[270]
AB14 AL17 B7 L48
VSS[7] VSS[86] VSS[171] VSS[271]
AB39 AL19 F45 M12
VSS[8] VSS[87] VSS[172] VSS[272]
AB4 AL2 BB12 P16
VSS[9] VSS[88] VSS[173] VSS[273]
AB43 VSS[10] VSS[89] AL21 BB16 VSS[174] VSS[274] M18
AB5 VSS[11] VSS[90] AL23 BB20 VSS[175] VSS[275] M22
AB7 VSS[12] VSS[91] AL26 BB22 VSS[176] VSS[276] M24
AC19 VSS[13] VSS[92] AL27 BB24 VSS[177] VSS[277] M30
AC2 VSS[14] VSS[93] AL31 BB28 VSS[178] VSS[278] M32
AC21 VSS[15] VSS[94] AL33 BB30 VSS[179] VSS[279] M34
AC24 VSS[16] VSS[95] AL34 BB38 VSS[180] VSS[280] M38
AC33 VSS[17] VSS[96] AL48 BB4 VSS[181] VSS[281] M4
AC34 VSS[18] VSS[97] AM11 BB46 VSS[182] VSS[282] M42
AC48 VSS[19] VSS[98] AM14 BC14 VSS[183] VSS[283] M46
AD10 VSS[20] VSS[99] AM36 BC18 VSS[184] VSS[284] M8
AD11 VSS[21] VSS[100] AM39 BC2 VSS[185] VSS[285] N18
AD12 VSS[22] VSS[101] AM43 BC22 VSS[186] VSS[286] P30
AD13 VSS[23] VSS[102] AM45 BC26 VSS[187] VSS[287] N47
AD19 VSS[24] VSS[103] AM46 BC32 VSS[188] VSS[288] P11
AD24 VSS[25] VSS[104] AM7 BC34 VSS[189] VSS[289] P18
AD26 VSS[26] VSS[105] AN2 BC36 VSS[190] VSS[290] T33
AD27 VSS[27] VSS[106] AN29 BC40 VSS[191] VSS[291] P40
AD33 VSS[28] VSS[107] AN3 BC42 VSS[192] VSS[292] P43
AD34 VSS[29] VSS[108] AN31 BC48 VSS[193] VSS[293] P47
AD36 VSS[30] VSS[109] AP12 BD46 VSS[194] VSS[294] P7
C C
AD37 VSS[31] VSS[110] AP19 BD5 VSS[195] VSS[295] R2
AD38 VSS[32] VSS[111] AP28 BE22 VSS[196] VSS[296] R48
AD39 VSS[33] VSS[112] AP30 BE26 VSS[197] VSS[297] T12
AD4 VSS[34] VSS[113] AP32 BE40 VSS[198] VSS[298] T31
AD40 VSS[35] VSS[114] AP38 BF10 VSS[199] VSS[299] T37
AD42 VSS[36] VSS[115] AP4 BF12 VSS[200] VSS[300] T4
AD43 VSS[37] VSS[116] AP42 BF16 VSS[201] VSS[301] W34
AD45 AP46 BF20 T46
VSS[38] VSS[117] VSS[202] VSS[302]
AD46 AP8 BF22 T47
VSS[39] VSS[118] VSS[203] VSS[303]
AD8 AR2 BF24 T8
VSS[40] VSS[119] VSS[204] VSS[304]
AE2 AR48 BF26 V11
VSS[41] VSS[120] VSS[205] VSS[305]
AE3 AT11 BF28 V17
VSS[42] VSS[121] VSS[206] VSS[306]
AF10 AT13 BD3 V26
VSS[43] VSS[122] VSS[207] VSS[307]
AF12 AT18 BF30 V27
VSS[44] VSS[123] VSS[208] VSS[308]
AD14 AT22 BF38 V29
VSS[45] VSS[124] VSS[209] VSS[309]
AD16 AT26 BF40 V31
VSS[46] VSS[125] VSS[210] VSS[310]
AF16 AT28 BF8 V36
VSS[47] VSS[126] VSS[211] VSS[311]
AF19 AT30 BG17 V39
VSS[48] VSS[127] VSS[212] VSS[312]
AF24 AT32 BG21 V43
VSS[49] VSS[128] VSS[213] VSS[313]
AF26 AT34 BG33 V7
VSS[50] VSS[129] VSS[214] VSS[314]
AF27 AT39 BG44 W17
VSS[51] VSS[130] VSS[215] VSS[315]
AF29 AT42 BG8 W19
VSS[52] VSS[131] VSS[216] VSS[316]
AF31 AT46 BH11 W2
VSS[53] VSS[132] VSS[217] VSS[317]
AF38 AT7 BH15 W27
VSS[54] VSS[133] VSS[218] VSS[318]
AF4 AU24 BH17 W48
VSS[55] VSS[134] VSS[219] VSS[319]
AF42 AU30 BH19 Y12
VSS[56] VSS[135] VSS[220] VSS[320]
AF46 AV16 H10 Y38
VSS[57] VSS[136] VSS[221] VSS[321]
AF5 AV20 BH27 Y4
VSS[58] VSS[137] VSS[222] VSS[322]
AF7 AV24 BH31 Y42
VSS[59] VSS[138] VSS[223] VSS[323]
AF8 AV30 BH33 Y46
VSS[60] VSS[139] VSS[224] VSS[324]
AG19 AV38 BH35 Y8
VSS[61] VSS[140] VSS[225] VSS[325]
AG2 AV4 BH39 BG29
B VSS[62] VSS[141] VSS[226] VSS[328] B
AG31 AV43 BH43 N24
VSS[63] VSS[142] VSS[227] VSS[329]
AG48 AV8 BH7 AJ3
VSS[64] VSS[143] VSS[228] VSS[330]
AH11 AW14 D3 AD47
VSS[65] VSS[144] VSS[229] VSS[331]
AH3 AW18 D12 B43
VSS[66] VSS[145] VSS[230] VSS[333]
AH36 AW2 D16 BE10
VSS[67] VSS[146] VSS[231] VSS[334]
AH39 AW22 D18 BG41
VSS[68] VSS[147] VSS[232] VSS[335]
AH40 AW26 D22 G14
VSS[69] VSS[148] VSS[233] VSS[337]
AH42 AW28 D24 H16
VSS[70] VSS[149] VSS[234] VSS[338]
AH46 AW32 D26 T36
VSS[71] VSS[150] VSS[235] VSS[340]
AH7 AW34 D30 BG22
VSS[72] VSS[151] VSS[236] VSS[342]
AJ19 AW36 D32 BG24
VSS[73] VSS[152] VSS[237] VSS[343]
AJ21 AW40 D34 C22
VSS[74] VSS[153] VSS[238] VSS[344]
AJ24 AW48 D38 AP13
VSS[75] VSS[154] VSS[239] VSS[345]
AJ33 AV11 D42 M14
VSS[76] VSS[155] VSS[240] VSS[346]
AJ34 AY12 D8 AP3
VSS[77] VSS[156] VSS[241] VSS[347]
AK12 AY22 E18 AP1
VSS[78] VSS[157] VSS[242] VSS[348]
AK3 AY28 E26 BE16
VSS[79] VSS[158] VSS[243] VSS[349]
G18 BC16
PANTHER-POINT_FCBGA989 VSS[244] VSS[350]
G20 BG28
VSS[245] VSS[351]
G26 BJ28
VSS[246] VSS[352]
G28
VSS[247]
G36
VSS[248]
G48
VSS[249]
H12
VSS[250]
H18
VSS[251]
H22
VSS[252]
H24
VSS[253]
H26
VSS[254]
H30
VSS[255]
H32
VSS[256]
H34
VSS[257]
F3 VSS[258]
A A

PANTHER-POINT_FCBGA989

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/07/12 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (8/8) VSS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-8221P
Date: Wednesday, October 26, 2011 Sheet 19 of 58
5 4 3 2 1
 A B C D E

the boot voltage is 1.0V +3VSG

U10A GPIO I/O USAGE
PCIE_CTX_C_GRX_P0 AN12 Part 1 of 7
PCIE_CTX_C_GRX_N0 PEX_RX0 VID_4
AM12 PEX_RX0_N GPIO0 P6 GPIO0 O GPU_VID4

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%
PCIE_CTX_C_GRX_P1 AN14 M3 VID_3
PCIE_CTX_C_GRX_N1 PEX_RX1 GPIO1
AM14 PEX_RX1_N GPIO2 L6
PCIE_CTX_C_GRX_P2 AP14 P5 GPIO1 O GPU_VID3
PCIE_CTX_C_GRX_N2 PEX_RX2 GPIO3
AP15 PEX_RX2_N GPIO4 P7

@ 1

@ 1

@ 1

2 DIS@ 1

@ 1

2 DIS@ 1
PCIE_CTX_C_GRX_P3 AN15 L7 VID_1
PCIE_CTX_C_GRX_N3 PEX_RX3 GPIO5 VID_2
PCIE_CTX_C_GRX_P4
AM15 PEX_RX3_N GPIO6 M7
+3VSG
GPIO2 O LCD_BL_PWM
AN17 N8
PCIE_GTX_C_CRX_P[0..15] PCIE_CTX_C_GRX_N4 PEX_RX4 GPIO7 R299 2 DIS@
4 PCIE_GTX_C_CRX_P[0..15] AM17
PEX_RX4_N GPIO8
M1 1 10K_0402_5%

R293

R294

R295

R296

R297

R298
PCIE_CTX_C_GRX_P5 AP17 M2 R300 2 DIS@ 1 10K_0402_5% GPU_GPIO16 R301 1 @ 2 0_0402_5% GPIO3 O LCD_VCC

2
1 PCIE_CTX_C_GRX_N5 PEX_RX5 GPIO9 1
AP18 L1
PCIE_GTX_C_CRX_N[0..15] PCIE_CTX_C_GRX_P6 PEX_RX5_N GPIO10 VID_0
AN18 M5

GPIO
4 PCIE_GTX_C_CRX_N[0..15] PCIE_CTX_C_GRX_N6 PEX_RX6 GPIO11 ACIN_BUF_VGA ER31 VID_0
AM18 N3 R302 1 DIS@ 2 0_0402_5% GPIO4 O LCD_BLEN
PEX_RX6_N GPIO12 GPU_VID0 54
PCIE_CTX_C_GRX_P7 AN20 M4 VID_5 VID_1 R303 1 DIS@ 2 0_0402_5%
PCIE_CTX_C_GRX_P[0..15] PCIE_CTX_C_GRX_N7 PEX_RX7 GPIO13 VID_2 GPU_VID1 54
AM20 N4 R304 1 DIS@ 2 0_0402_5%
4 PCIE_CTX_C_GRX_P[0..15] PCIE_CTX_C_GRX_P8 PEX_RX7_N GPIO14 VID_3 GPU_VID2 54
AP20 P2 R305 1 DIS@ 2 0_0402_5% GPIO5 O GPU_VID1
PCIE_CTX_C_GRX_N8 PEX_RX8 GPIO15 GPU_GPIO16 VID_4 GPU_VID3 54
AP21 R8 R306 1 DIS@ 2 0_0402_5%
PCIE_CTX_C_GRX_N[0..15] PCIE_CTX_C_GRX_P9 PEX_RX8_N GPIO16 VID_5 GPU_VID4 54
AN21 M6 R307 1 DIS@ 2 0_0402_5%
4 PCIE_CTX_C_GRX_N[0..15] PEX_RX9 GPIO17 GPU_VID5 54
PCIE_CTX_C_GRX_N9 AM21 R1 GPIO6 O GPU_VID2
PEX_RX9_N GPIO18

R308

R309

R310

R311

R312

R313
PCIE_CTX_C_GRX_P10 AN23 P3
PEX_RX10 GPIO19

DIS@ 1

DIS@ 1

DIS@ 1

@ 1

DIS@ 1

@ 1
PCIE_CTX_C_GRX_N10 AM23 P4
PCIE_CTX_C_GRX_P11 PEX_RX10_N GPIO20
PCIE_CTX_C_GRX_N11
AP23 PEX_RX11 GPIO21 P1 GPIO7 O 3D Vision
AP24 PEX_RX11_N
PCIE_CTX_C_GRX_P12 AN24 PEX_RX12

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%
PCIE_CTX_C_GRX_N12 AM24 GPIO8 I/O OVERT

2
PCIE_CTX_C_GRX_P13 PEX_RX12_N
AN26 PEX_RX13
PCIE_CTX_C_GRX_N13 AM26
PCIE_CTX_C_GRX_P14 PEX_RX13_N
PCIE_CTX_C_GRX_N14
AP26 PEX_RX14 GPIO9 I/O ALERT
AP27 PEX_RX14_N
PCIE_CTX_C_GRX_P15 AN27 AK9
PCIE_CTX_C_GRX_N15 PEX_RX15 DACA_RED
AM27 PEX_RX15_N DACA_GREEN AL10 GPIO10 O MEM_VREF_CTL
DACA_BLUE AL9

DACs
PCIE_GTX_C_CRX_P0 AK14 MEM_VDD_CTL(PES)
PCIE_GTX_C_CRX_N0 PEX_TX0
PCIE_GTX_C_CRX_P1
AJ14 PEX_TX0_N DACA_HSYNC AM9 GPIO11 O
PCIE_GTX_C_CRX_N1
AH14 PEX_TX1 DACA_VSYNC AN9 GPU_VID0(Real N13P)
AG14 DIS@
PCIE_GTX_C_CRX_P2 PEX_TX1_N R314 +3VSG
AK15 PEX_TX2
PCIE_GTX_C_CRX_N2 AJ15 AG10 2 1 10K_0402_5% GPIO12 I PWR_LEVEL
PEX_TX2_N DACA_VDD

PCI EXPRESS
PCIE_GTX_C_CRX_P3 AL16 AP9
PEX_TX3 DACA_VREF

1
PCIE_GTX_C_CRX_N3 AK16 AP8
PCIE_GTX_C_CRX_P4 PEX_TX3_N DACA_RSET R315 ER31
AK17 PEX_TX4 GPIO13 O THERM_LOAD_STEP_DOWN
2 PCIE_GTX_C_CRX_N4 DIS@ 2
AJ17 PEX_TX4_N

5
PCIE_GTX_C_CRX_P5 AH17 10K_0402_5% U11
PCIE_GTX_C_CRX_N5 PEX_TX5
AG17 2 GPIO14 I HPD_AB

P
2
PCIE_GTX_C_CRX_P6 PEX_TX5_N ACIN_BUF_VGA B VGA_BUF# 40
AK18 PEX_TX6 4 Y
PCIE_GTX_C_CRX_N6 AJ18 1
PEX_TX6_N A ACIN_BUF 54

G
PCIE_GTX_C_CRX_P7 AL19 GPIO15 I HPD_C
PEX_TX7

2
PCIE_GTX_C_CRX_N7 AK19 R4 VGA_DDC_CLK @ NC7SZ08P5X_NL_SC70-5

3
PCIE_GTX_C_CRX_P8 PEX_TX7_N I2CA_SCL VGA_DDC_DATA R428
AK20 R5
PCIE_GTX_C_CRX_N8 PEX_TX8 I2CA_SDA
AJ20
PEX_TX8_N 0_0402_5% GPIO16 O THERM_LOAD_STEP_UP
PCIE_GTX_C_CRX_P9 AH20 R7 I2CB_SCL
PEX_TX9 I2CB_SCL DIS@
PCIE_GTX_C_CRX_N9 AG20 R6 I2CB_SDA 2 1

1
PCIE_GTX_C_CRX_P10 PEX_TX9_N I2CB_SDA DIS@ D5
AK21 GPIO17 I HPD_D

I2C
PCIE_GTX_C_CRX_N10 PEX_TX10 VGA_LCD_CLK CH751H-40PT_SOD323-2
AJ21 R2
PCIE_GTX_C_CRX_P11 PEX_TX10_N I2CC_SCL VGA_LCD_DATA
AL22 R3
PCIE_GTX_C_CRX_N11 PEX_TX11 I2CC_SDA
PCIE_GTX_C_CRX_P12
AK22
PEX_TX11_N I2CS_SCL
GPIO18 I HPD_E
AK23 T4
PCIE_GTX_C_CRX_N12 PEX_TX12 I2CS_SCL I2CS_SDA +3VSG
AJ23 T3
PCIE_GTX_C_CRX_P13 PEX_TX12_N I2CS_SDA
AH23
PEX_TX13 under GPU GPIO19 I HPD_F
PCIE_GTX_C_CRX_N13 AG23 VGA_DDC_CLK R316 1 DIS@ 2 2.2K_0402_5%
PCIE_GTX_C_CRX_P14 AK24
PEX_TX13_N close to ball : AD8 VGA_DDC_DATA R317 1 DIS@ 2 2.2K_0402_5%
PCIE_GTX_C_CRX_N14 PEX_TX14
PCIE_GTX_C_CRX_P15
AJ24
PEX_TX14_N I2CB_SCL
GPIO20 Reserved
AL25 C236 1 2 R318 1 DIS@ 2 2.2K_0402_5%
PCIE_GTX_C_CRX_N15 PEX_TX15 DIS@ 0.1U_0402_16V4Z I2CB_SDA R319 1 DIS@
AK25 2 2.2K_0402_5%
PEX_TX15_N
GPIO21 Reserved
AD8 +PLLVDD VGA_LCD_CLK R320 1 DIS@ 2 2.2K_0402_5%
PLLVDD VGA_LCD_DATA R321 1 DIS@
AJ11
PEX_WAKE_N 2 2.2K_0402_5%
AE8 +GPU_PLLVDD 1 @ 2 GPIO22 I/O SLI_RASTER_SYNC
SP_PLLVDD I2CS_SCL
+3VSG 1 DIS@ 2 13 CLK_PCIE_VGA AL13 R322 0_0402_5% R324 1 DIS@ 2 2.2K_0402_5%
R323 10K_0402_5% PEX_REFCLK I2CS_SDA R325 1 DIS@
13 CLK_PCIE_VGA# AK13
PEX_REFCLK_N VID_PLLVDD
AD7 2 2.2K_0402_5%

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
PEG_CLKREQ# AK12 GPIO23 O SLI_SWAPRDY
CLK

PEX_CLKREQ_N

DIS@ C237

DIS@ C238

DIS@ C239
1 1 1
PEX_TSTCLK_OUT+ AJ26 H3 XTALIN
3 PEX_TSTCLK_OUT- PEX_TSTCLK_OUT XTAL_IN XTALOUT 3
2 1 AK26
PEX_TSTCLK_OUT_N XTAL_OUT
H2 GPIO24
R326 @ 200_0402_1%
AJ12 J4 XTAL_OUTBUFF 2 2 2
15 DGPU_RST# PEX_TREMP PEX_RST_N XTAL_OUTBUFF XTAL_SSIN
2 1 AP29
PEX_TERMP XTAL_SSIN
H1
R327 DIS@ 2.49K_0402_1%
1

1
10K_0402_5% under GPU +3VSG
R328 R329
N13P-PES-A1_FCBGA908 10K_0402_5% DIS@
close to ball : AE8,AD7

2
XTALOUT @ XTALIN @ DIS@
2

R330 1M_0402_5% L10 +1.05VSG

BLM18PG300SN1D_2P I2CS_SCL 1 6
+PLLVDD PCH_SMLCLK 13,40
27MHZ_10PF_7V27000050 1 2

22U_0805_6.3V6M
3 1 DIS@ DMN66D0LDW-7_SOT363-6
3 1

DIS@ C240
1 Q5A DIS@
DIS@ GND GND ER13
1 1
C241 Y3 +3VSG
12P_0402_50V8J DIS@ 4 2 C242 DIS@

5
12P_0402_50V8J 2
2 2
I2CS_SDA 4 3 PCH_SMLDATA 13,40
DMN66D0LDW-7_SOT363-6
L11 Q5B DIS@
150mA BLM18PG181SN1D_2P
+GPU_PLLVDD 1 2
+3V_PCH DGPU_PWR_EN 15,29,54

22U_0805_6.3V6M

22U_0805_6.3V6M
0.1U_0402_16V4Z

4.7U_0603_6.3V6K
DIS@ C243

DIS@ C244

DIS@ C245

DIS@ C246
1 1 1 DIS@ 1
1
1

DIS@
R332 R331
10K_0402_5% 10K_0402_5% 2 2 2 2
4 4
2

DIS@
2

Q13
2

2N7002H_SOT23-3
G

PEG_CLKREQ#_R 1 3 1 DIS@ 2 PEG_CLKREQ#

13 PEG_CLKREQ#_R
R333
D

S
1

0_0402_5%
@ @ Security Classification Compal Secret Data Compal Electronics, Inc.
for safe R334 R335 Issued Date 2011/07/12 2012/12/31 Title
2.2K_0402_5% 2.2K_0402_5%
Deciphered Date
N13P PEG 1/9
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-8221P
Date: Wednesday, October 26, 2011 Sheet 20 of 58
A B C D E
 A

VRAM Interface 25

25
MDA[15..0]

MDA[31..16]
MDA[15..0]

MDA[31..16] 27 MDC[15..0]
MDC[15..0]

MDC[31..16]
MDA[47..32] 27 MDC[31..16]
26 MDA[47..32] MDC[47..32]
MDA[63..48] 28 MDC[47..32]
26 MDA[63..48] MDC[63..48]
28 MDC[63..48]

U10B U10C
CMDA[30..0] 25,26 CMDC[30..0] 27,28
Part 2 of 7 Part 3 of 7
MDA0 L28 U30 CMDA0 MDC0 G9 D13 CMDC0
MDA1 FBA_D0 FBA_CMD0 MDC1 FBB_D0 FBB_CMD0
M29 T31 E9 E14
MDA2 FBA_D1 FBA_CMD1 CMDA2 MDC2 FBB_D1 FBB_CMD1 CMDC2
L29 U29 G8 F14
MDA3 FBA_D2 FBA_CMD2 CMDA3 MDC3 FBB_D2 FBB_CMD2 CMDC3
M28 R34 F9 A12
MDA4 FBA_D3 FBA_CMD3 CMDA4 MDC4 FBB_D3 FBB_CMD3 CMDC4
N31 R33 F11 B12
MDA5 FBA_D4 FBA_CMD4 CMDA5 MDC5 FBB_D4 FBB_CMD4 CMDC5
P29 U32 G11 C14
MDA6 FBA_D5 FBA_CMD5 CMDA6 MDC6 FBB_D5 FBB_CMD5 CMDC6
R29 U33 F12 B14
MDA7 FBA_D6 FBA_CMD6 CMDA7 MDC7 FBB_D6 FBB_CMD6 CMDC7
P28 FBA_D7 FBA_CMD7 U28 G12 FBB_D7 FBB_CMD7 G15
MDA8 J28 V28 CMDA8 MDC8 G6 F15 CMDC8
MDA9 FBA_D8 FBA_CMD8 CMDA9 MDC9 FBB_D8 FBB_CMD8 CMDC9
H29 FBA_D9 FBA_CMD9 V29 F5 FBB_D9 FBB_CMD9 E15
MDA10 J29 V30 CMDA10 MDC10 E6 D15 CMDC10
MDA11 FBA_D10 FBA_CMD10 CMDA11 MDC11 FBB_D10 FBB_CMD10 CMDC11
H28 FBA_D11 FBA_CMD11 U34 F6 FBB_D11 FBB_CMD11 A14
MDA12 G29 U31 CMDA12 MDC12 F4 D14 CMDC12
MDA13 FBA_D12 FBA_CMD12 CMDA13 MDC13 FBB_D12 FBB_CMD12 CMDC13
E31 FBA_D13 FBA_CMD13 V34 G4 FBB_D13 FBB_CMD13 A15
MDA14 E32 V33 CMDA14 MDC14 E2 B15 CMDC14
MDA15 FBA_D14 FBA_CMD14 CMDA15 MDC15 FBB_D14 FBB_CMD14 CMDC15
F30 FBA_D15 FBA_CMD15 Y32 F3 FBB_D15 FBB_CMD15 C17
MDA16 C34 AA31 CMDA16 MDC16 C2 D18 CMDC16
MDA17 FBA_D16 FBA_CMD16 MDC17 FBB_D16 FBB_CMD16
D32 FBA_D17 FBA_CMD17 AA29 D4 FBB_D17 FBB_CMD17 E18
MDA18 B33 AA28 CMDA18 MDC18 D3 F18 CMDC18
MDA19 FBA_D18 FBA_CMD18 CMDA19 MDC19 FBB_D18 FBB_CMD18 CMDC19
C33 FBA_D19 FBA_CMD19 AC34 C1 FBB_D19 FBB_CMD19 A20
MDA20 F33 AC33 CMDA20 MDC20 B3 B20 CMDC20
MDA21 FBA_D20 FBA_CMD20 CMDA21 MDC21 FBB_D20 FBB_CMD20 CMDC21
F32 FBA_D21 FBA_CMD21 AA32 C4 FBB_D21 FBB_CMD21 C18
MDA22 H33 AA33 CMDA22 MDC22 B5 B18 CMDC22
MDA23 FBA_D22 FBA_CMD22 CMDA23 MDC23 FBB_D22 FBB_CMD22 CMDC23
H32 FBA_D23 FBA_CMD23 Y28 C5 FBB_D23 FBB_CMD23 G18
MDA24 P34 Y29 CMDA24 MDC24 A11 G17 CMDC24
MEMORY INTERFACE
MDA25 FBA_D24 FBA_CMD24 CMDA25 MDC25 FBB_D24 FBB_CMD24 CMDC25
P32 FBA_D25 FBA_CMD25 W31 C11 FBB_D25 FBB_CMD25 F17

MEMORY INTERFACE B
MDA26 P31 Y30 CMDA26 MDC26 D11 D16 CMDC26
MDA27 FBA_D26 FBA_CMD26 CMDA27 MDC27 FBB_D26 FBB_CMD26 CMDC27
P33 FBA_D27 FBA_CMD27 AA34 B11 FBB_D27 FBB_CMD27 A18
MDA28 L31 Y31 CMDA28 MDC28 D8 D17 CMDC28
MDA29 FBA_D28 FBA_CMD28 CMDA29 MDC29 FBB_D28 FBB_CMD28 CMDC29
L34 FBA_D29 FBA_CMD29 Y34 A8 FBB_D29 FBB_CMD29 A17
MDA30 L32 Y33 CMDA30 MDC30 C8 B17 CMDC30
MDA31 FBA_D30 FBA_CMD30 MDC31 FBB_D30 FBB_CMD30
L33 FBA_D31 FBA_CMD31 V31 B8 FBB_D31 FBB_CMD31 E17
MDA32 AG28 MDC32 F24
MDA33 FBA_D32 MDC33 FBB_D32
AF29 FBA_D33 G23 FBB_D33
MDA34 AG29 MDC34 E24
MDA35 FBA_D34 MDC35 FBB_D34
AF28 FBA_D35 FBA_CMD_RFU0 R32 G24 FBB_D35 FBB_CMD_RFU0 C12
MDA36 AD30 AC32 MDC36 D21 C20
MDA37 FBA_D36 FBA_CMD_RFU1 MDC37 FBB_D36 FBB_CMD_RFU1
AD29 E21
MDA38 FBA_D37 +1.5VSG MDC38 FBB_D37 +1.5VSG
AC29 G21
MDA39 FBA_D38 R336 60.4_0402_1% MDC39 FBB_D38 R337 60.4_0402_1%
AD28 F21
FBA_D39 FBB_D39
A

MDA40 AJ29 R28 FBA_DEBUG0 2 @ 1 MDC40 G27 G14 FBB_DEBUG0 2 @ 1

MDA41 FBA_D40 FBA_DEBUG0 FBB_D40 FBB_DEBUG0
AK29 AC28 FBA_DEBUG1 2 @ 1 MDC41 D27 G20 FBB_DEBUG1 2 @ 1
MDA42 FBA_D41 FBA_DEBUG1 R338 60.4_0402_1% MDC42 FBB_D41 FBB_DEBUG1 R339 60.4_0402_1%
AJ30 G26
MDA43 FBA_D42 MDC43 FBB_D42
AK28 E27
MDA44 FBA_D43 MDC44 FBB_D43
1
AM29 E29 1

MDA45 FBA_D44 MDC45 FBB_D44

AM31 R30 CLKA0 25 F29 D12 CLKC0 27
MDA46 FBA_D45 FBA_CLK0 MDC46 FBB_D45 FBB_CLK0
AN29 R31 CLKA0# 25 E30 E12 CLKC0# 27
MDA47 FBA_D46 FBA_CLK0_N MDC47 FBB_D46 FBB_CLK0_N
AM30 AB31 CLKA1 26 D30 E20 CLKC1 28
MDA48 FBA_D47 FBA_CLK1 MDC48 FBB_D47 FBB_CLK1
AN31 AC31 CLKA1# 26 A32 F20 CLKC1# 28
MDA49 FBA_D48 FBA_CLK1_N MDC49 FBB_D48 FBB_CLK1_N
AN32 C31
MDA50 FBA_D49 MDC50 FBB_D49
AP30 C32
MDA51 FBA_D50 MDC51 FBB_D50
AP32 B32
MDA52 FBA_D51 MDC52 FBB_D51
AM33 K31 D29 F8
MDA53 FBA_D52 FBA_WCK01 MDC53 FBB_D52 FBB_WCK01
AL31 L30 A29 E8
MDA54 FBA_D53 FBA_WCK01_N MDC54 FBB_D53 FBB_WCK01_N
AK33 H34 C29 A5
MDA55 FBA_D54 FBA_WCK23 MDC55 FBB_D54 FBB_WCK23
AK32 J34 B29 A6
MDA56 FBA_D55 FBA_WCK23_N MDC56 FBB_D55 FBB_WCK23_N
AD34 AG30 B21 D24
MDA57 FBA_D56 FBA_WCK45 MDC57 FBB_D56 FBB_WCK45
AD32 AG31 C23 D25
MDA58 FBA_D57 FBA_WCK45_N MDC58 FBB_D57 FBB_WCK45_N
AC30 AJ34 A21 B27
MDA59 FBA_D58 FBA_WCK67 MDC59 FBB_D58 FBB_WCK67
AD33 AK34 C21 C27
MDA60 FBA_D59 FBA_WCK67_N MDC60 FBB_D59 FBB_WCK67_N
AF31 B24
MDA61 FBA_D60 MDC61 FBB_D60
AG34 C24
MDA62 FBA_D61 MDC62 FBB_D61
AG32 B26
MDA63 FBA_D62 MDC63 FBB_D62
AG33 J30 C26 D6
FBA_D63 FBA_WCKB01 FBB_D63 FBB_WCKB01
25 DQMA[3..0] J31 27 DQMC[3..0] D7
DQMA0 FBA_WCKB01_N DQMC0 FBB_WCKB01_N
P30 J32 E11 C6
DQMA1 FBA_DQM0 FBA_WCKB23 DQMC1 FBB_DQM0 FBB_WCKB23
F31 J33 E3 B6
DQMA2 FBA_DQM1 FBA_WCKB23_N DQMC2 FBB_DQM1 FBB_WCKB23_N
F34 AH31 A3 F26
DQMA3 FBA_DQM2 FBA_WCKB45 DQMC3 FBB_DQM2 FBB_WCKB45
26 DQMA[7..4] M32 AJ31 28 DQMC[7..4] C9 E26
DQMA4 FBA_DQM3 FBA_WCKB45_N DQMC4 FBB_DQM3 FBB_WCKB45_N
AD31 AJ32 F23 A26
DQMA5 FBA_DQM4 FBA_WCKB67 DQMC5 FBB_DQM4 FBB_WCKB67
AL29 AJ33 F27 A27
DQMA6 FBA_DQM5 FBA_WCKB67_N DQMC6 FBB_DQM5 FBB_WCKB67_N
AM32 C30
DQMA7 FBA_DQM6 DQMC7 FBB_DQM6
AF34 A24
FBA_DQM7 FBB_DQM7
25 DQSA[3..0] 27 DQSC[3..0]
DQSA0 M31 E1 FB_CLAMP DQSC0 D10
DQSA1 FBA_DQS_WP0 FB_CLAMP DQSC1 FBB_DQS_WP0
G31 D5
DQSA2 FBA_DQS_WP1 DQSC2 FBB_DQS_WP1
E33
FBA_DQS_WP2 Under GPU C3
FBB_DQS_WP2
DQSA3 M33 DQSC3 B9
26 DQSA[7..4] DQSA4 AE31
FBA_DQS_WP3
K27
close to ball : K27 28 DQSC[7..4] DQSC4 E23
FBB_DQS_WP3
H17 +FB_PLLAVDD
DQSA5 FBA_DQS_WP4 FB_DLL_AVDD C247 DIS@ DQSC5 FBB_DQS_WP4 FBB_PLL_AVDD
AK30
FBA_DQS_WP5 100mA E28
FBB_DQS_WP5 100mA
DQSA6 AN33 1 2 DQSC6 B30
FBA_DQS_WP6 FBB_DQS_WP6

0.1U_0402_16V4Z
DQSA7 AF33 0.1U_0402_16V4Z DQSC7 A23
FBA_DQS_WP7 FBB_DQS_WP7

DIS@ C249
U27 +FB_PLLAVDD 1
25 DQSA#[3..0] FBA_PLL_AVDD 27 DQSC#[3..0] +FB_PLLAVDD
DQSA#0 M30
FBA_DQS_RN0
DQSC#0 D9
FBB_DQS_RN0 300mA L12 DIS@ +1.05VSG
DQSA#1 H30 1 2 DQSC#1 E4 FBMA-L11-160808300LMA25T_2P
DQSA#2 FBA_DQS_RN1 C248 0.1U_0402_16V4Z DQSC#2 FBB_DQS_RN1 +FB_PLLAVDD
E34 B2 1 2
FBA_DQS_RN2 FBB_DQS_RN2 2

22U_0805_6.3V6M
1U_0402_6.3V6K

1U_0402_6.3V6K
DQSA#3 M34 H26 DIS@ DQSC#3 A9
26 DQSA#[7..4] FBA_DQS_RN3 FB_VREF 28 DQSC#[7..4] FBB_DQS_RN3

DIS@ C250

DIS@ C251

DIS@ C252
DQSA#4 AF30 DQSC#4 D22 1 1 1
DQSA#5 FBA_DQS_RN4 DQSC#5 FBB_DQS_RN4
AK31
FBA_DQS_RN5 Under GPU D28
FBB_DQS_RN5
DQSA#6 AM34 DQSC#6 A30 Under GPU
DQSA#7 AF32
FBA_DQS_RN6 close to ball : U27 DQSC#7 B23
FBB_DQS_RN6
FBA_DQS_RN7 FBB_DQS_RN7 close to ball : H17 2 2 2

N13P-PES-A1_FCBGA908 N13P-PES-A1_FCBGA908
@ FB_CLAMP 1 GS@ @
2
R683 10K_0402_5%

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/07/12 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N13P VRAM 2/9
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-8221P
Date: Wednesday, October 26, 2011 Sheet 21 of 58
A
 5 4 3 2 1

D U10D D

Part 4 of 7
AM6
IFPA_TXC @
AN6 P8 PAD T31
IFPA_TXC_N NC
AP3 AC6
IFPA_TXD0 NC
AN3
IFPA_TXD0_N NC
AJ28 MULTI LEVEL STRAPS
AN5 AJ4
IFPA_TXD1 NC +3VSG +3VSG
AM5
IFPA_TXD1_N NC
AJ5 Straps
AL6 AL11
IFPA_TXD2 NC
AK6 C15
IFPA_TXD2_N NC

NC
AJ6 IFPA_TXD3 NC D19

2 DIS@ 1

@ 1

@ 1

@ 1

@ 1

@ 1
10K_0402_1%

15K_0402_5%
45.3K_0402_1%

4.99K_0402_1%

34.8K_0402_1%

34.8K_0402_1%

4.99K_0402_1%

4.99K_0402_1%
AH6 IFPA_TXD3_N NC D20

@
NC D23
NC D26
AJ9 IFPB_TXC NC H31

R340

R341

R342

R343

R344

R345

R346

R347
AH9 T8

2
IFPB_TXC_N NC
AP6 IFPB_TXD4 NC V32
AP5 STRAP0 ROM_SI
IFPB_TXD4_N STRAP1 STRAP3 ROM_SO
AM7 IFPB_TXD5
AL7 STRAP2 STRAP4 ROM_SCLK
IFPB_TXD5_N
AN8 IFPB_TXD6
AM8 IFPB_TXD6_N

@ 1

2 DIS@ 1

@ 1

@ 1

@ 1

@ 1
10K_0402_1%

10K_0402_1%
4.99K_0402_1%

45.3K_0402_1%

4.99K_0402_1%

4.99K_0402_1%

34.8K_0402_1%

34.8K_0402_1%
AK8 IFPB_TXD7

R352 DIS@
AL8 IFPB_TXD7_N
L4 VCCSENSE_VGA_R 1 DIS@ 2
VDD_SENSE R356 0_0402_5% VCCSENSE_VGA 54

R348

R349

R350

R351

R353

R354

R355
AK1

2
IFPC_L0
AJ1 IFPC_L0_N
AJ3 L5 VSSSENSE_VGA_R 1 DIS@ 2
IFPC_L1 GND_SENSE VSSSENSE_VGA 54
AJ2 R357 0_0402_5%
IFPC_L1_N ER36
AH3 IFPC_L2
C ER19 C
AH4 IFPC_L2_N
AG5 IFPC_L3
AG4 IFPC_L3_N
TEST DIS@
AM1 AK11 R358 1 2 10K_0402_5% 10/12 nVidia Keven
IFPD_L0 TESTMODE Strap1
AM2
AM3
IFPD_L0_N
AM10 JTAG_TCK R359 1 @ 2 10K_0402_5%
Need check with NVIDIA 10/17 nVidia Keven N13P-GS
IFPD_L1 JTAG_TCK JTAG_TDI @ ER36 Strap2 / Strap3
AM4
AL3
IFPD_L1_N JTAG_TDI
AM11
AP12 JTAG_TDO
PAD T32
@
For N13P-GS strap table
IFPD_L2 JTAG_TDO PAD T33
AL4 AP11 JTAG_TMS @
IFPD_L2_N JTAG_TMS PAD T34
AK4 AN11 JTAG_TRST PAD T35 @ GPU Frenq. Memory Size Memory Config strap0 strap1 strap2 strap3 strap4 ROM_SI ROM_SO ROM_SCLK
IFPD_L3 JTAG_TRST_N
AK5
IFPD_L3_N
LVDS/TMDS

1 DIS@ 2 N13P-GS 900 MHz 128M* 16* 8 Samsung R R R R R R R R

R360 10K_0402_5% 2GB SA000047QA0 PU 45K PD 45K PU 20K PD 25K PD 10K PD 45K PU 10K PU 5K
AD2 N13P-GS 900 MHz 128M* 16* 8 Hynix R R R R R R R R
IFPE_L0
AD3 2GB SA00003YO30 PU 45K PD 45K PU 20K PD 25K PD 10K PD 35K PU 10K PU 5K
IFPE_L0_N N13P-GS 900 MHz 64M* 16* 8 Samsung R R R R R R R R
AD1
AC1
IFPE_L1 SERIAL R361 10K_0402_5% 1GB SA00004GS30 PU 45K PD 45K PU 20K PD 25K PD 10K PD 20K PU 10K PU 5K
IFPE_L1_N ROM_CS# N13P-GS
AC2
IFPE_L2 ROM_CS_N
H6 1 DIS@ 2 +3VSG 900 MHz 64M* 16* 8 Hynix R R R R R R R R
AC3 H4 ROM_SCLK 1GB SA000041S60 PU 45K PD 45K PU 20K PD 25K PD 10K PD 15K PU 10K PU 5K
IFPE_L2_N ROM_SCLK ROM_SI
AC4 H5
IFPE_L3 ROM_SI ROM_SO
AC5
IFPE_L3_N ROM_SO
H7 For N13P-GL strap table
AE3 GPU Frenq. Memory Size Memory Config strap0 strap1 strap2 strap3 strap4 ROM_SI ROM_SO ROM_SCLK
IFPF_L0
AE4
IFPF_L0_N 900 MHz 128M* 16* 8 Samsung R R R R R R R R
AF4
IFPF_L1 N13P-GL 2GB SA000047QA0 PU 45K PD 45K PU 10K PD 5K PD 10K PD 45K PD 30K PD 15K
AF5
AD4
IFPF_L1_N GENERAL R362 10K_0402_5% 900 MHz 128M* 16* 8 Hynix R R R R R R R R
IFPF_L2 N13P-GL
AD5
IFPF_L2_N BUFRST_N
L2 1 @ 2 2GB SA00003YO30 PU 45K PD 45K PU 10K PD 5K PD 10K PD 35K PD 30K PD 15K
AG1 900 MHz 64M* 16* 8 Samsung R R R R R R R R
B IFPF_L3 R363 1 DIS@ N13P-GL B
AF1 L3 2 10K_0402_5% +3VSG 1GB SA00004GS30 PU 45K PD 45K PU 10K PD 5K PD 10K PD 20K PD 30K PD 15K
IFPF_L3_N CEC 900 MHz 64M* 16* 8 Hynix R R R R R R R R
J1 MULTI_STRAP_REF0_GND 1 DIS@ 2 N13P-GL 1GB SA000041S60 PU 45K PD 45K PU 10K PD 5K PD 10K PD 15K PD 30K PD 15K
MULTI_STRAP_REF0_GND R364 40.2K_0402_1%
AG3
AG2
IFPC_AUX_I2CW_SCL For N13M-GE1 strap table
IFPC_AUX_I2CW_SDA_N STRAP0
J2
STRAP0 STRAP1 GPU Frenq. Memory Size Memory Config strap0 strap1 strap2 strap3 strap4 ROM_SI ROM_SO ROM_SCLK
J7
STRAP1 STRAP2
AK3 J6
IFPD_AUX_I2CX_SCL STRAP2 STRAP3 900 MHz 128M* 16* 4 Samsung R R R R R R R R
AK2 J5
IFPD_AUX_I2CX_SDA_N STRAP3 STRAP4 N13M-GE1
J3 1GB SA000047QA0 PU 45K PD 45K PU 5K PD 5K PD 10K PD 45K PD 30K PU 5K
STRAP4 900 MHz 128M* 16* 4 Hynix R R R R R R R R
AB3 N13M-GE1 1GB SA00003YO30 PU 45K PD 45K PU 5K PD 5K PD 10K PD 35K PD 30K PU 5K
IFPE_AUX_I2CY_SCL
AB4
IFPE_AUX_I2CY_SDA_N
K3
THERMDP
AF3
THERMDN
K4 For N13M-GE1 GB1b-64 strap table
IFPF_AUX_I2CZ_SCL
AF2
IFPF_AUX_I2CZ_SDA_N GPU Frenq. Memory Size Memory Config strap0 strap1 strap2 strap3 strap4 ROM_SI ROM_SO ROM_SCLK

900 MHz 256M* 8* 8 ELPIDA R R R R R R R R

N13M-GE1 2GB SA000056P00 PU 45K PD 45K PU 5K PD 5K PD 10K PD 5K PD 30K PU 5K
900 MHz 256M* 8* 8 Hynix R R R R R R R R
N13P-PES-A1_FCBGA908 N13M-GE1 2GB SA000056O00 PU 45K PD 45K PU 5K PD 5K PD 10K PD 10K PD 30K PU 5K
@ 900 MHz 512M* 8* 8 HYNIX R R R R R R R R
N13M-GE1 4GB SA00005BL00 PU 45K PD 45K PU 5K PD 5K PD 10K PD 15K PD 30K PU 5K
900 MHz 512M* 8* 8 ELPIDA R R R R R R R R
N13M-GE1 4GB SA00005AA00 PU 45K PD 45K PU 5K PD 5K PD 10K PD 20K PD 30K PU 5K

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/07/12 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N13P LVDS 3/9
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-8221P
Date: Wednesday, October 26, 2011 Sheet 22 of 58
5 4 3 2 1
 5 4 3 2 1

Near GPU Under GPU +1.05VSG

10U_0603_6.3V6M

10U_0603_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
1U_0402_6.3V6K

1U_0402_6.3V6K

4.7U_0603_6.3V6K
DIS@ C253

DIS@ C254

DIS@ C255

DIS@ C256

DIS@ C257

DIS@C258
C258

DIS@C259
C259
1 1 1 1 1 1 1

DIS@

DIS@
2 2 2 2 2 2 2
U10E

+1.5VSG Under GPU Part 5 of 7

D D
7200mA
AA27 AG19 Near GPU Under GPU +1.05VSG
FBVDDQ_0 PEX_IOVDD_0

1U_0402_6.3V6K

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
4.7U_0603_6.3V6K
AA30 AG21
FBVDDQ_1 PEX_IOVDD_1
DIS@ C260

DIS@ C261

DIS@ C262

DIS@ C263

DIS@ C264

DIS@ C265
1 1 1 1 1 1 AB27 AG22
FBVDDQ_2 PEX_IOVDD_2

10U_0603_6.3V6M

10U_0603_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
1U_0402_6.3V6K

1U_0402_6.3V6K

4.7U_0603_6.3V6K
AB33 AG24
FBVDDQ_3 PEX_IOVDD_3

DIS@ C266

DIS@ C267

DIS@ C268

DIS@ C269

DIS@ C270

DIS@ C271

DIS@ C272
AC27
FBVDDQ_4 PEX_IOVDD_4
AH21 2700 mA 1 1 1 1 1 1 1
AD27 AH25
2 2 2 2 2 2 FBVDDQ_5 PEX_IOVDD_5
AE27
FBVDDQ_6
AF27
FBVDDQ_7 2 2 2 2 2 2 2
AG27 AG13
FBVDDQ_8 PEX_IOVDDQ_0
B13 AG15
Under GPU FBVDDQ_9 PEX_IOVDDQ_1
B16 FBVDDQ_10 PEX_IOVDDQ_2 AG16
B19 FBVDDQ_11 PEX_IOVDDQ_3 AG18
E13 FBVDDQ_12 PEX_IOVDDQ_4 AG25
1U_0402_6.3V6K

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
4.7U_0603_6.3V6K

E16 FBVDDQ_13 PEX_IOVDDQ_5 AH15

+3VSG
DIS@ C273

DIS@ C274

DIS@ C275

DIS@ C276

DIS@ C277

DIS@ C278
1 1 1 1 1 1 E19 FBVDDQ_14 PEX_IOVDDQ_6 AH18
H10 FBVDDQ_15 PEX_IOVDDQ_7 AH26 Near GPU
H11 FBVDDQ_16 PEX_IOVDDQ_8 AH27

1U_0402_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
H12 FBVDDQ_17 PEX_IOVDDQ_9 AJ27
2 2 2 2 2 2

DIS@ C279

DIS@ C280

DIS@ C281
H13 FBVDDQ_18 PEX_IOVDDQ_10 AK27 1 1 1
H14 AL27

POWER
FBVDDQ_19 PEX_IOVDDQ_11 L13
H15 FBVDDQ_20 PEX_IOVDDQ_12 AM28
H16 FBVDDQ_21 PEX_IOVDDQ_13 AN28
Near GPU H18 2 2 2
FBVDDQ_22 GS@
H19 FBVDDQ_23
H20 FBVDDQ_24 150mA 370mA
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

H21 FBVDDQ_25 PEX_PLL_HVDD AH12

DIS@ C283

DIS@ C284

DIS@ C285

DIS@ C286

1 1 1 1 H22 FBVDDQ_26 0_0603_5%

H23 @ 1 2
FBVDDQ_27 C282 0.1U_0402_16V4Z +1.05VSG
H24 FBVDDQ_28
H8 AG12 Under GPU Near GPU GEL@
2 2 2 2 FBVDDQ_29 PEX_SVDD_3V3
H9 FBVDDQ_30 2 1
C C

1U_0402_6.3V6K
0.1U_0402_16V4Z

4.7U_0603_6.3V6K
L27 @ 1 2 L13
FBVDDQ_31

DIS@ C288

DIS@ C289

DIS@ C290
M27 C287 0.1U_0402_16V4Z 150mA 1 1 1 BLM18PG121SN1D_0603
FBVDDQ_32 +PEX_PLLVDD
N27 FBVDDQ_33 PEX_PLLVDD AG26
P27 FBVDDQ_34
R27 FBVDDQ_35 2 2 2
T27 FBVDDQ_36 +3V3MISC
120mA
T30 FBVDDQ_37 VDD33_0 J8
T33 K8
FBVDDQ_38 VDD33_1 +VDD33
V27 L8
FBVDDQ_39 VDD33_2
W27 M8
FBVDDQ_40 VDD33_3
W30 Under GPU (one per pin)
FBVDDQ_41
W33
FBVDDQ_42
Y27
FBVDDQ_43 +IFPAB_PLLVDD R366 1 DIS@
AH8 2 10K_0402_5%
IFPAB_PLLVDD IFPAB_RESET R367 1 @
AJ8 2 1K_0402_5%
IFPAB_RSET
+1.5VSG AG8 +IFPAB_IOVDD R368 1 DIS@ 2 10K_0402_5%
IFPA_IOVDD
AG9 29 DGPU_PWR_EN#
FB_VDDQ_SENSE IFPB_IOVDD
2 1 F1
R369 DIS@ 10_0402_5% FB_VDDQ_SENSE
AF7 +IFPC_PLLVDD R370 1 DIS@ 2 10K_0402_5%
FB_GND_SENSE IFPC_PLLVDD R372 1 @ 2 1K_0402_5% +3VSG
2 1 F2 AF8
FB_GND_SENSE IFPC_RSET

2
G
+1.5VSG R371 DIS@ 10_0402_5% Under GPU (one per pin) AO3419L 1P SOT23-3 Q62
AF6 +IFPC_IOVDD R373 1 DIS@ 2 10K_0402_5%
DIS@ 1 FB_CAL_PD_VDDQ J27 IFPC_IOVDD +3V3MISC
2 3 1
FB_CAL_PD_VDDQ

0.1U_0402_16V4Z

0.1U_0402_16V4Z
R374 40.2_0402_1%

D
DIS@ C291

DIS@ C292
AG7 +IFPD_PLLVDD R375 1 DIS@ 2 10K_0402_5% 1 1 GS@
DIS@ 2 FB_CAL_PU_GND H27 IFPD_PLLVDD IFPD_RESET R377 1 @ 2 1K_0402_5%
1 AN2
R376 42.2_0402_1% FB_CAL_PU_GND IFPD_RSET
AG6 +IFPD_IOVDD R378 1 DIS@ 2 10K_0402_5% 1 2
DIS@ 1 FB_CAL_TERM_GND H25 IFPD_IOVDD 2 2 R741 GEL@ 0_0402_5%
2 FB_CAL_TERM_GND
R379 51.1_0402_1%
B
AB8 +IFPEF_PLLVDD R380 1 DIS@ 2 10K_0402_5% +3VS B
IFPEF_PLVDD IFPEF_RESET R381 1 @ 2 1K_0402_5% @
AD6
IFPEF_RSET
1 2
AC7 +IFPEF_IOVDD R382 1 DIS@ 2 10K_0402_5% R740 0_0402_5%
Place near balls IFPE_IOVDD
IFPF_IOVDD
AC8

Under GPU (one per pin)

N13P-PES-A1_FCBGA908
@ +VDD33 2 DIS@ 1

1U_0402_6.3V6K

1U_0402_6.3V6K
0.1U_0402_16V4Z

0.1U_0402_16V4Z

4.7U_0603_6.3V6K
R365

DIS@ C293

DIS@ C294

DIS@ C295

DIS@ C296

DIS@ C297
1 1 1 1 1 0_0603_5%

2 2 2 2 2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/07/12 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N13P POWER & GND 4/9
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-8221P
Date: Wednesday, October 26, 2011 Sheet 23 of 58
5 4 3 2 1
 5 4 3 2 1

U10F +VGA_CORE U10G +VGA_CORE

Part 6 of 7
A2 D2 50A Part 7 of 7 V17
D GND_0 GND_100 VDD_56 D
AA17 D31 AA12 V18
GND_1 GND_101 VDD_0 VDD_57
AA18 D33 AA14 V20
GND_2 GND_102 VDD_1 VDD_58
AA20 E10 AA16 V22
GND_3 GND_103 VDD_2 VDD_59
AA22 E22 AA19 W12
GND_4 GND_104 VDD_3 VDD_60
AB12 E25 AA21 W14
GND_5 GND_105 VDD_4 VDD_61
AB14 E5 AA23 W16
GND_6 GND_106 VDD_5 VDD_62
AB16 E7 AB13 W19
GND_7 GND_107 VDD_6 VDD_63
AB19 F28 AB15 W21
GND_8 GND_108 VDD_7 VDD_64
AB2 F7 AB17 W23
GND_9 GND_109 VDD_8 VDD_65
AB21 G10 AB18 Y13
GND_10 GND_110 VDD_9 VDD_66
A33 G13 AB20 Y15
GND_11 GND_111 VDD_10 VDD_67
AB23 GND_12 GND_112 G16 AB22 VDD_11 VDD_68 Y17
AB28 GND_13 GND_113 G19 AC12 VDD_12 VDD_69 Y18
AB30 GND_14 GND_114 G2 AC14 VDD_13 VDD_70 Y20
AB32 GND_15 GND_115 G22 AC16 VDD_14 VDD_71 Y22
AB5 GND_16 GND_116 G25 AC19 VDD_15
AB7 GND_17 GND_117 G28 AC21 VDD_16
AC13 GND_18 GND_118 G3 AC23 VDD_17 XVDD_1 U1
AC15 GND_19 GND_119 G30 M12 VDD_18 XVDD_2 U2
AC17 GND_20 GND_120 G32 M14 VDD_19 XVDD_3 U3

POWER
AC18 GND_21 GND_121 G33 M16 VDD_20 XVDD_4 U4
AA13 GND_22 GND_122 G5 M19 VDD_21 XVDD_5 U5
AC20 GND_23 GND_123 G7 M21 VDD_22 XVDD_6 U6
AC22 GND_24 GND_124 K2 M23 VDD_23 XVDD_7 U7
AE2 GND_25 GND_125 K28 N13 VDD_24 XVDD_8 U8
AE28 GND_26 GND_126 K30 N15 VDD_25
AE30 GND_27 GND_127 K32 N17 VDD_26
AE32 GND_28 GND_128 K33 N18 VDD_27 XVDD_9 V1
AE33 GND_29 GND_129 K5 N20 VDD_28 XVDD_10 V2
AE5 GND_30 GND_130 K7 N22 VDD_29 XVDD_11 V3
AE7 GND_31 GND_131 M13 P12 VDD_30 XVDD_12 V4
AH10 GND_32 GND_132 M15 P14 VDD_31 XVDD_13 V5
C C
AA15 GND_33 GND_133 M17 P16 VDD_32 XVDD_14 V6
AH13 GND_34 GND_134 M18 P19 VDD_33 XVDD_15 V7
AH16 GND_35 GND_135 M20 P21 VDD_34 XVDD_16 V8
AH19 GND_36 GND_136 M22 P23 VDD_35
AH2 GND_37 GND_137 N12 R13 VDD_36
AH22 GND_38 GND_138 N14 R15 VDD_37 XVDD_17 W2
AH24 GND_39 GND_139 N16 R17 VDD_38 XVDD_18 W3
AH28 N19 R18 W4
GND_40 GND_140 VDD_39 XVDD_19
AH29 N2 R20 W5
GND_41 GND_141 VDD_40 XVDD_20
AH30 N21 R22 W7
GND_42 GND_142 VDD_41 XVDD_21
GND

AH32 N23 T12 W8

GND_43 GND_143 VDD_42 XVDD_22
AH33 N28 T14
GND_44 GND_144 VDD_43
AH5 N30 T16
GND_45 GND_145 VDD_44
AH7 N32 T19 Y1
GND_46 GND_146 VDD_45 XVDD_23
AJ7 N33 T21 Y2
GND_47 GND_147 VDD_46 XVDD_24
AK10 N5 T23 Y3
GND_48 GND_148 VDD_47 XVDD_25
AK7 N7 U13 Y4
GND_49 GND_149 VDD_48 XVDD_26
AL12 P13 U15 Y5
GND_50 GND_150 VDD_49 XVDD_27
AL14 P15 U17 Y6
GND_51 GND_151 VDD_50 XVDD_28
AL15 P17 U18 Y7
GND_52 GND_152 VDD_51 XVDD_29
AL17 P18 U20 Y8
GND_53 GND_153 VDD_52 XVDD_30
AL18 P20 U22
GND_54 GND_154 VDD_53
AL2 P22 V13
GND_55 GND_155 VDD_54
AL20 R12 V15 AA1
GND_56 GND_156 VDD_55 XVDD_31
AL21 R14 AA2
GND_57 GND_157 XVDD_32
AL23 R16 AA3
GND_58 GND_158 XVDD_33
AL24 R19 AA4
GND_59 GND_159 XVDD_34
AL26 R21 AA5
GND_60 GND_160 XVDD_35
AL28 R23 AA6
GND_61 GND_161 XVDD_36
AL30 T13 AA7
GND_62 GND_162 XVDD_37
AL32 T15 AA8
GND_63 GND_163 XVDD_38
AL33 T17
B GND_64 GND_164 B
AL5 T18
GND_65 GND_165
AM13 T2
GND_66 GND_166
AM16 T20
GND_67 GND_167 N13P-PES-A1_FCBGA908
AM19 T22
GND_68 GND_168
AM22 AG11
GND_69 GND_169
AM25 T28
GND_70 GND_170
AN1 T32
GND_71 GND_171
AN10 T5
GND_72 GND_172
AN13 T7
GND_73 GND_173
AN16 U12
GND_74 GND_174
AN19 U14
GND_75 GND_175
AN22 U16
GND_76 GND_176
AN25 U19
GND_77 GND_177
AN30 U21
GND_78 GND_178
AN34 U23
GND_79 GND_179
AN4 V12
GND_80 GND_180
AN7 V14
GND_81 GND_181
AP2 V16
GND_82 GND_182
AP33 V19
GND_83 GND_183
B1 V21
GND_84 GND_184
B10 V23
GND_85 GND_185
B22 W13
GND_86 GND_186
B25 W15
GND_87 GND_187
B28 W17
GND_88 GND_188
B31 W18
GND_89 GND_189
B34 W20
GND_90 GND_190
B4 W22
GND_91 GND_191
B7 W28
GND_92 GND_192
C10 Y12
GND_93 GND_193
C13 Y14
GND_94 GND_194
C19 Y16
GND_95 GND_195
C22 GND_96 GND_196 Y19
A A
C25 GND_97 GND_197 Y21
C28 GND_98 GND_198 Y23
C7 GND_99 GND_199 AH11
GND_OPT C16
GND_OPT W32

Security Classification Compal Secret Data Compal Electronics, Inc.

N13P-PES-A1_FCBGA908 Issued Date 2011/07/12 2012/12/31 Title
Deciphered Date
@ THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N13P POWER & GND 5/9
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-8221P
Date: Wednesday, October 26, 2011 Sheet 24 of 58
5 4 3 2 1
 5 4 3 2 1

VRAM DDR3 chips (1GB) Mode D

Address 0..31 32..63
CMD0 CS0_L#
D
64Mx16 DDR3 *8==>1GB CMD1 D

128Mx16 DDR3 *8==>2GB CMD2 ODT_L

CMD3 CKE
CMD4 A14 A14
DQSA[7..0] CMD5 RST RST
21,26 DQSA[7..0]
U12 @ U13 @
DQSA#[7..0] CMD6 A9 A9
21,26 DQSA#[7..0] +MEM_VREF0 MDA9 +MEM_VREF1 M8 MDA1
M8 VREFCA DQL0 E3 VREFCA DQL0 E3
DQMA[7..0] H1 F7 MDA13 H1 F7 MDA4 CMD7 A7 A7
21,26 DQMA[7..0] VREFDQ DQL1 MDA11 VREFDQ DQL1 MDA3
DQL2 F2 DQL2 F2
MDA[63..0] CMDA9 N3 F8 MDA15 CMDA9 N3 F8 MDA5 CMD8 A2 A2
21,26 MDA[63..0] CMDA11 A0 DQL3 MDA8 Group1 CMDA11 A0 DQL3 MDA0 Group0
P7 A1 DQL4 H3 P7 A1 DQL4 H3
CMDA[30..0] CMDA8 P3 H8 MDA14 CMDA8 P3 H8 MDA7 CMD9 A0 A0
21,26 CMDA[30..0] CMDA25 A2 DQL5 MDA10 CMDA25 A2 DQL5 MDA2
N2 A3 DQL6 G2 N2 A3 DQL6 G2
CMDA10 P8 H7 MDA12 CMDA10 P8 H7 MDA6 CMD10 A4 A4
CMDA24 A4 DQL7 CMDA24 A4 DQL7
P2 A5 P2 A5
CMDA22 R8 CMDA22 R8 CMD11 A1 A1
+1.5VSG CMDA7 A6 MDA18 CMDA7 A6 MDA24
R2 A7 DQU0 D7 R2 A7 DQU0 D7
CMDA21 T8 C3 MDA22 CMDA21 T8 C3 MDA28 CMD12 BA0 BA0
CMDA6 A8 DQU1 MDA19 CMDA6 A8 DQU1 MDA27
R3 A9 DQU2 C8 R3 A9 DQU2 C8
CMDA29 L7 C2 MDA23 CMDA29 L7 C2 MDA30 CMD13 WE* WE*
DIS@ CMDA23 A10/AP DQU3 MDA17 Group2 CMDA23 A10/AP DQU3 MDA25 Group3
R7 A11 DQU4 A7 R7 A11 DQU4 A7
R383 CMDA28 N7 A2 MDA21 CMDA28 N7 A2 MDA31 CMD14 A15 A15
240_0402_1% CMDA20 A12 DQU5 MDA16 CMDA20 A12 DQU5 MDA26
T3 A13 DQU6 B8 T3 A13 DQU6 B8
CMDA4 T7 A3 MDA20 CMDA4 T7 A3 MDA29 CMD15 CAS* CAS*
CMDA14 A14 DQU7 CMDA14 A14 DQU7
M7 A15/BA3 M7 A15/BA3
+MEM_VREF0 +1.5VSG +1.5VSG CMD16 CS0_H#
C C
DIS@
0.1U_0402_16V4Z

1 CMDA12 M2 B2 CMDA12 M2 B2 CMD17

DIS@ CMDA27 BA0 VDD CMDA27 BA0 VDD
N8 BA1 VDD D9 N8 BA1 VDD D9
R384 CMDA26 M3 G7 CMDA26 M3 G7 CMD18 ODT_H
240_0402_1% BA2 VDD BA2 VDD
VDD K2 VDD K2
2
C298

VDD K8 VDD K8 CMD19 CKE_H

VDD N1 VDD N1
CLKA0 J7 N9 CLKA0 J7 N9 CMD20 A13 A13
CLKA0# CK VDD CLKA0# CK VDD
K7 R1 K7 R1
CMDA3 CK VDD CMDA3 CK VDD
K9
CKE/CKE0 VDD
R9
+1.5VSG
K9
CKE/CKE0 VDD
R9
+1.5VSG
CMD21 A8 A8
CMD22 A6 A6
+1.5VSG CMDA2 K1 A1 CMDA2 K1 A1
CMDA0 ODT/ODT0 VDDQ CMDA0 ODT/ODT0 VDDQ
L2
CS/CS0 VDDQ
A8 L2
CS/CS0 VDDQ
A8 CMD23 A11 A11
CMDA30 J3 C1 CMDA30 J3 C1
CMDA15 RAS VDDQ CMDA15 RAS VDDQ
K3
CAS VDDQ
C9 K3
CAS VDDQ
C9 CMD24 A5 A5
DIS@ CMDA13 L3 D2 CMDA13 L3 D2
WE VDDQ WE VDDQ
R385 310mAVDDQ E9
VDDQ
E9 CMD25 A3 A3
240_0402_1% F1 310mAVDDQ F1
DQSA1 VDDQ DQSA0
F3
DQSL VDDQ
H2 F3
DQSL VDDQ
H2 CMD26 BA2 BA2
DQSA2 C7 H9 DQSA3 C7 H9
+MEM_VREF1 DQSU VDDQ DQSU VDDQ
CMD27 BA1 BA1
DIS@
0.1U_0402_16V4Z

1 DQMA1 E7 A9 DQMA0 E7 A9 CMD28 A12 A12

DIS@ DQMA2 DML VSS DQMA3 DML VSS
D3 B3 D3 B3
DMU VSS DMU VSS
R386
VSS
E1
VSS
E1 CMD29 A10 A10
240_0402_1% G8 G8
2 VSS VSS
C299

DQSA#1 G3 J2 DQSA#0 G3 J2 CMD30 RAS* RAS*

DQSA#2 DQSL VSS DQSA#3 DQSL VSS
B7 J8 B7 J8
DQSU VSS DQSU VSS
M1 M1 Not Available
VSS VSS
M9 M9
VSS VSS
CMDA5 VSS
P1
CMDA5 VSS
P1 LOW HIGH
T2 P9 T2 P9
B RESET VSS RESET VSS B
T1 T1
ZQ0 VSS ZQ1 VSS
L8 T9 L8 T9
ZQ/ZQ0 VSS ZQ/ZQ0 VSS
1

1
CLKA0
21 CLKA0
DIS@ J1 B1 DIS@ J1 B1 CMDA2 R390 1 DIS@ 2 10K_0402_5%
NC/ODT1 VSSQ NC/ODT1 VSSQ Command Bit Default Pull-down
1

R388 L1 B9 R389 L1 B9 CMDA3 R391 1 DIS@ 2 10K_0402_5%

DIS@ 243_0402_1% NC/CS1 VSSQ 243_0402_1% NC/CS1 VSSQ CMDA5 R393 DIS@ 10K_0402_5%
J9 D1 J9 D1 1 2 ODTx 10k
R392 NC/CE1 VSSQ NC/CE1 VSSQ CMDA18 R394 DIS@ 10K_0402_5%
L9 D8 L9 D8 1 2
2

2
160_0402_1% NCZQ1 VSSQ NCZQ1 VSSQ CMDA19 R395 DIS@ 10K_0402_5% DDR3 CKEx 10k
E2 E2 1 2
VSSQ VSSQ
E8 E8 RST 10k
2

CLKA0# VSSQ VSSQ

21 CLKA0# F9 F9
VSSQ VSSQ CS* No Termination
G1 G1
VSSQ VSSQ
G9 G9
VSSQ VSSQ
96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3
K4B1G1646E-HC12_FBGA96 K4B1G1646E-HC12_FBGA96
NV recommand 0720

+1.5VSG +1.5VSG
Samsung : SA000035700 (S IC D3 64MX16 K4W1G1646E-HC12 FBGA 96P)
Hynix : SA000032400 (S IC D3 64MX16 H5TQ1G63BFR-12C FBGA 1.5V )
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
DIS@ C305

DIS@ C306

DIS@ C307

DIS@ C308

DIS@ C309

DIS@ C310

DIS@ C315

DIS@ C316

DIS@ C317

DIS@ C318

DIS@ C319
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 AMD :SA00003PF10
DIS@ C301

DIS@ C302

DIS@ C303

DIS@ C304

DIS@ C311

DIS@ C312

DIS@ C313

DIS@ C314

(S IC D3 64M16/800 23EY2387MB-12 PG-TFBGA 96P 1.5V)

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/07/12 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N13P DDR3 6/9
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-8221P
Date: Wednesday, October 26, 2011 Sheet 25 of 58
5 4 3 2 1
 5 4 3 2 1

VRAM DDR3 chips (1GB) Mode D

Address 0..31 32..63
64Mx16 DDR3 *8==>1GB CMD0 CS0_L#
CMD1
D
128Mx16 DDR3 *8==>2GB D
CMD2 ODT_L
U14 @ U15 @
CMD3 CKE
+MEM_VREF2 M8 E3 MDA39 +MEM_VREF3 M8 E3 MDA42
VREFCA DQL0 MDA35 VREFCA DQL0 MDA45
H1
VREFDQ DQL1
F7 H1
VREFDQ DQL1
F7 CMD4 A14 A14
DQMA[7..0] F2 MDA34 F2 MDA43
21,25 DQMA[7..0] CMDA9 DQL2 MDA33 CMDA9 DQL2 MDA47
N3
A0 DQL3
F8 N3
A0 DQL3
F8 CMD5 RST RST
CMDA[30..0] CMDA11 P7 H3 MDA38 Group4 CMDA11 P7 H3 MDA40 Group5
21,25 CMDA[30..0] A1 DQL4 A1 DQL4
CMDA8 P3 H8 MDA37 CMDA8 P3 H8 MDA46 CMD6 A9 A9
DQSA#[7..0] CMDA25 A2 DQL5 MDA32 CMDA25 A2 DQL5 MDA41
21,25 DQSA#[7..0] N2 G2 N2 G2
CMDA10 A3 DQL6 MDA36 CMDA10 A3 DQL6 MDA44
P8
A4 DQL7
H7 P8
A4 DQL7
H7 CMD7 A7 A7
DQSA[7..0] CMDA24 P2 CMDA24 P2
21,25 DQSA[7..0] CMDA22 A5 CMDA22 A5
R8 A6 R8 A6 CMD8 A2 A2
MDA[63..0] CMDA7 R2 D7 MDA58 CMDA7 R2 D7 MDA49
21,25 MDA[63..0] A7 DQU0 A7 DQU0
CMDA21 T8 C3 MDA60 CMDA21 T8 C3 MDA54 CMD9 A0 A0
CMDA6 A8 DQU1 MDA56 CMDA6 A8 DQU1 MDA50
R3 A9 DQU2 C8 R3 A9 DQU2 C8
CMDA29 L7 C2 MDA61 CMDA29 L7 C2 MDA55 CMD10 A4 A4
CMDA23 A10/AP DQU3 MDA57 Group7 CMDA23 A10/AP DQU3 MDA51 Group6
R7 A11 DQU4 A7 R7 A11 DQU4 A7
CMDA28 N7 A2 MDA62 CMDA28 N7 A2 MDA52 CMD11 A1 A1
+1.5VSG CMDA20 A12 DQU5 MDA59 CMDA20 A12 DQU5 MDA48
T3 A13 DQU6 B8 T3 A13 DQU6 B8
CMDA4 T7 A3 MDA63 CMDA4 T7 A3 MDA53 CMD12 BA0 BA0
CMDA14 A14 DQU7 CMDA14 A14 DQU7
M7 A15/BA3 M7 A15/BA3
DIS@ +1.5VSG +1.5VSG CMD13 WE* WE*
R397
240_0402_1% CMDA12 M2 B2 CMDA12 M2 B2 CMD14 A15 A15
CMDA27 BA0 VDD CMDA27 BA0 VDD
N8 BA1 VDD D9 N8 BA1 VDD D9
CMDA26 M3 G7 CMDA26 M3 G7 CMD15 CAS* CAS*
BA2 VDD BA2 VDD
VDD K2 VDD K2
+MEM_VREF2 K8 K8 CMD16 CS0_H#
VDD VDD
VDD N1 VDD N1
DIS@
0.1U_0402_16V4Z

DIS@ 1 CLKA1 J7 N9 CLKA1 J7 N9 CMD17

R398 CLKA1# CK VDD CLKA1# CK VDD
K7 CK VDD R1 K7 CK VDD R1
C CMDA19 CMDA19 C
240_0402_1% K9 CKE/CKE0 VDD R9 K9 CKE/CKE0 VDD R9 CMD18 ODT_H
+1.5VSG +1.5VSG
2
C320

CMD19 CKE_H
CMDA18 K1 A1 CMDA18 K1 A1
CMDA16 ODT/ODT0 VDDQ CMDA16 ODT/ODT0 VDDQ
L2 CS/CS0 VDDQ A8 L2 CS/CS0 VDDQ A8 CMD20 A13 A13
CMDA30 J3 C1 CMDA30 J3 C1
CMDA15 RAS VDDQ CMDA15 RAS VDDQ
K3 CAS VDDQ C9 K3 CAS VDDQ C9 CMD21 A8 A8
CMDA13 L3 D2 CMDA13 L3 D2
WE VDDQ WE VDDQ
310mAVDDQ E9 310mAVDDQ E9 CMD22 A6 A6
+1.5VSG F1 F1
DQSA4 VDDQ DQSA5 VDDQ
F3
DQSL VDDQ
H2 F3
DQSL VDDQ
H2 CMD23 A11 A11
DQSA7 C7 H9 DQSA6 C7 H9
DQSU VDDQ DQSU VDDQ
DIS@ CMD24 A5 A5
R399
240_0402_1% DQMA4 E7 A9 DQMA5 E7 A9 CMD25 A3 A3
DQMA7 DML VSS DQMA6 DML VSS
D3 B3 D3 B3
DMU VSS DMU VSS
VSS
E1
VSS
E1 CMD26 BA2 BA2
G8 G8
+MEM_VREF3 DQSA#4 VSS DQSA#5 VSS
G3
DQSL VSS
J2 G3
DQSL VSS
J2 CMD27 BA1 BA1
DQSA#7 B7 J8 DQSA#6 B7 J8
DQSU VSS DQSU VSS
DIS@
0.1U_0402_16V4Z

DIS@ 1 VSS
M1
VSS
M1 CMD28 A12 A12
R400 M9 M9
VSS VSS
240_0402_1%
VSS
P1
VSS
P1 CMD29 A10 A10
CMDA5 T2 P9 CMDA5 T2 P9
2 RESET VSS RESET VSS
C321

VSS
T1
VSS
T1 CMD30 RAS* RAS*
ZQ2 L8 T9 ZQ3 L8 T9
ZQ/ZQ0 VSS ZQ/ZQ0 VSS
Not Available
1

1
DIS@
DIS@ J1 B1 R402 J1 B1 LOW HIGH
R401 NC/ODT1 VSSQ 243_0402_1% NC/ODT1 VSSQ
L1 B9 L1 B9
243_0402_1% NC/CS1 VSSQ NC/CS1 VSSQ
J9 D1 J9 D1
CLKA1 NC/CE1 VSSQ NC/CE1 VSSQ
L9 D8 L9 D8
2

2
B 21 CLKA1 NCZQ1 VSSQ NCZQ1 VSSQ B
E2 E2
VSSQ VSSQ
1

E8 E8
DIS@ VSSQ VSSQ
F9 F9
R404 VSSQ VSSQ
G1 G1
160_0402_1% VSSQ VSSQ
G9 G9
VSSQ VSSQ
2

CLKA1# 96-BALL 96-BALL

21 CLKA1#
SDRAM DDR3 SDRAM DDR3
K4B1G1646E-HC12_FBGA96 K4B1G1646E-HC12_FBGA96

+1.5VSG +1.5VSG

0.1U_0402_16V4Z
C327

C328

C329

C330

C331

C332
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
DIS@ C337

DIS@ C338

DIS@ C339

DIS@ C340

DIS@ C341
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2
DIS@ C323

DIS@ C324

DIS@ C325

DIS@ C326

DIS@ C333

DIS@ C334

DIS@ C335

DIS@ C336
DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/07/12 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N13P DDR3 7/9
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-8221P
Date: Wednesday, October 26, 2011 Sheet 26 of 58
5 4 3 2 1
 5 4 3 2 1

Mode D
Address 0..31 32..63
VRAM DDR3 chips (1GB) CMD0 CS0_L#
CMD1
64Mx16 DDR3 *8==>1GB CMD2 ODT_L
D D
CMD3 CKE
128Mx16 DDR3 *8==>2GB CMD4 A14 A14
CMD5 RST RST
DQSC[7..0]
21,28 DQSC[7..0]
CMD6 A9 A9
DQSC#[7..0] U16 @ U17 @
21,28 DQSC#[7..0]
CMD7 A7 A7
DQMC[7..0] +MEM_VREF4 M8 E3 MDC15 +MEM_VREF5 M8 E3 MDC3
21,28 DQMC[7..0] VREFCA DQL0 VREFCA DQL0
H1 F7 MDC14 H1 F7 MDC7 CMD8 A2 A2
MDC[63..0] VREFDQ DQL1 MDC12 VREFDQ DQL1 MDC2
21,28 MDC[63..0] DQL2 F2 DQL2 F2
CMDC9 N3 F8 MDC13 CMDC9 N3 F8 MDC4 CMD9 A0 A0
CMDC[30..0] CMDC11 A0 DQL3 MDC9 Group1 CMDC11 A0 DQL3 MDC1 Group0
21,28 CMDC[30..0] P7 A1 DQL4 H3 P7 A1 DQL4 H3
CMDC8 P3 H8 MDC10 CMDC8 P3 H8 MDC6 CMD10 A4 A4
CMDC25 A2 DQL5 MDC11 CMDC25 A2 DQL5 MDC0
N2 A3 DQL6 G2 N2 A3 DQL6 G2
CMDC10 P8 H7 MDC8 CMDC10 P8 H7 MDC5 CMD11 A1 A1
CMDC24 A4 DQL7 CMDC24 A4 DQL7
P2 A5 P2 A5
CMDC22 R8 CMDC22 R8 CMD12 BA0 BA0
+1.5VSG CMDC7 A6 MDC18 CMDC7 A6 MDC26
R2 A7 DQU0 D7 R2 A7 DQU0 D7
CMDC21 T8 C3 MDC23 CMDC21 T8 C3 MDC28 CMD13 WE* WE*
CMDC6 A8 DQU1 MDC16 CMDC6 A8 DQU1 MDC25
R3 A9 DQU2 C8 R3 A9 DQU2 C8
CMDC29 L7 C2 MDC22 CMDC29 L7 C2 MDC30 CMD14 A15 A15
GSL@ CMDC23 A10/AP DQU3 MDC17 Group2 CMDC23 A10/AP DQU3 MDC27 Group3
R7 A11 DQU4 A7 R7 A11 DQU4 A7
R406 CMDC28 N7 A2 MDC21 CMDC28 N7 A2 MDC31 CMD15 CAS* CAS*
240_0402_1% CMDC20 A12 DQU5 MDC19 CMDC20 A12 DQU5 MDC24
T3 A13 DQU6 B8 T3 A13 DQU6 B8
CMDC4 T7 A3 MDC20 CMDC4 T7 A3 MDC29 CMD16 CS0_H#
CMDC14 A14 DQU7 CMDC14 A14 DQU7
M7 A15/BA3 M7 A15/BA3
+MEM_VREF4 +1.5VSG +1.5VSG CMD17
C342 GSL@
0.1U_0402_16V4Z

1 CMDC12 M2 B2 CMDC12 M2 B2 CMD18 ODT_H

GSL@ CMDC27 BA0 VDD CMDC27 BA0 VDD
N8 BA1 VDD D9 N8 BA1 VDD D9
C CMDC26 CMDC26 C
R407 M3 BA2 VDD G7 M3 BA2 VDD G7 CMD19 CKE_H
240_0402_1% K2 K2
2 VDD VDD
VDD K8 VDD K8 CMD20 A13 A13
VDD N1 VDD N1
CLKC0 J7 N9 CLKC0 J7 N9 CMD21 A8 A8
CLKC0# CK VDD CLKC0# CK VDD
K7 CK VDD R1 K7 CK VDD R1
CMDC3 K9 R9 CMDC3 K9 R9 CMD22 A6 A6
CKE/CKE0 VDD +1.5VSG CKE/CKE0 VDD +1.5VSG
CMD23 A11 A11
CMDC2 K1 A1 CMDC2 K1 A1
CMDC0 ODT/ODT0 VDDQ CMDC0 ODT/ODT0 VDDQ
L2
CS/CS0 VDDQ
A8 L2
CS/CS0 VDDQ
A8 CMD24 A5 A5
CMDC30 J3 C1 CMDC30 J3 C1
CMDC15 RAS VDDQ CMDC15 RAS VDDQ
K3
CAS VDDQ
C9 K3
CAS VDDQ
C9 CMD25 A3 A3
+1.5VSG CMDC13 L3 D2 CMDC13 L3 D2
WE VDDQ WE VDDQ
310mAVDDQ E9
VDDQ
E9 CMD26 BA2 BA2
DQSC1 VDDQ
F1
DQSC0
310mAVDDQ F1
F3
DQSL VDDQ
H2 F3
DQSL VDDQ
H2 CMD27 BA1 BA1
GSL@ DQSC2 C7 H9 DQSC3 C7 H9
DQSU VDDQ DQSU VDDQ
R408 CMD28 A12 A12
240_0402_1%
DQMC1 E7 A9 DQMC0 E7 A9 CMD29 A10 A10
DQMC2 DML VSS DQMC3 DML VSS
D3 B3 D3 B3
+MEM_VREF5 DMU VSS DMU VSS
VSS
E1
VSS
E1 CMD30 RAS* RAS*
G8 G8
VSS VSS
C343 GSL@
0.1U_0402_16V4Z

1 DQSC#1 G3 J2 DQSC#0 G3 J2 Not Available

GSL@: DQSC#2 DQSL VSS DQSC#3 DQSL VSS
B7 DQSU VSS
J8 B7 DQSU VSS
J8
R409 M1 M1 LOW HIGH
240_0402_1% VSS VSS
M9 M9
2 VSS VSS
P1 P1
CMDC5 VSS CMDC5 VSS
T2 P9 T2 P9
RESET VSS RESET VSS
T1 T1
ZQ4 VSS ZQ5 VSS
L8 T9 L8 T9
B ZQ/ZQ0 VSS ZQ/ZQ0 VSS B
1

1
GSL@: J1 B1 GSL@ J1 B1 Command Bit Default Pull-down
R410 NC/ODT1 VSSQ R411 NC/ODT1 VSSQ CMDC2 R412 GSL@ 10K_0402_5%
L1 NC/CS1 VSSQ
B9 L1 NC/CS1 VSSQ
B9 1 2
243_0402_1% J9 D1 243_0402_1% J9 D1 CMDC3 R413 1 GSL@ 2 10K_0402_5% ODTx 10k
NC/CE1 VSSQ NC/CE1 VSSQ CMDC5 R414 GSL@ 10K_0402_5%
L9 D8 L9 D8 1 2
2

2
NCZQ1 VSSQ NCZQ1 VSSQ CMDC18 R415 GSL@ 10K_0402_5% DDR3 CKEx 10k
E2 E2 1 2
VSSQ VSSQ CMDC19 R416 GSL@ 10K_0402_5%
E8 E8 1 2 RST 10k
VSSQ VSSQ
F9 F9
VSSQ VSSQ CS* No Termination
G1 G1
CLKC0 VSSQ VSSQ
21 CLKC0 G9 G9
VSSQ VSSQ
1

96-BALL 96-BALL
GSL@: SDRAM DDR3 SDRAM DDR3
R418 K4B1G1646E-HC12_FBGA96 K4B1G1646E-HC12_FBGA96
160_0402_1%
2

CLKC0#
21 CLKC0# +1.5VSG
+1.5VSG
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
GSL@: C349

GSL@: C350

GSL@: C351

GSL@: C352

GSL@: C353

GSL@: C354

GSL@ C359

GSL@ C360

GSL@ C361

GSL@ C362

GSL@ C363
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1U_0402_6.3V6K 1 1 1 1 1
GSL@: C345

GSL@: C346

GSL@: C347

GSL@: C348

GSL@ C355

GSL@ C356

GSL@ C357

GSL@ C358

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/07/12 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N13P DDR3 8/9
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-8221P
Date: Wednesday, October 26, 2011 Sheet 27 of 58
5 4 3 2 1
 5 4 3 2 1

VRAM DDR3 chips (1GB)

64Mx16 DDR3 *8==>1GB
D
128Mx16 DDR3 *8==>2GB D

DQMC[7..0]
21,27 DQMC[7..0]
CMDC[30..0] Mode D
21,27 CMDC[30..0]
Address 0..31 32..63
DQSC#[7..0] U18 @ U19 @
21,27 DQSC#[7..0]
CMD0 CS0_L#
DQSC[7..0] +MEM_VREF6 M8 E3 MDC33 +MEM_VREF7 M8 E3 MDC63
21,27 DQSC[7..0] VREFCA DQL0 VREFCA DQL0
H1 F7 MDC34 H1 F7 MDC58 CMD1
MDC[63..0] VREFDQ DQL1 MDC38 VREFDQ DQL1 MDC62
21,27 MDC[63..0] DQL2 F2 DQL2 F2
CMDC9 N3 F8 MDC35 CMDC9 N3 F8 MDC57 CMD2 ODT_L
CMDC11 A0 DQL3 MDC39 Group4 CMDC11 A0 DQL3 MDC60 Group7
P7 A1 DQL4 H3 P7 A1 DQL4 H3
CMDC8 P3 H8 MDC32 CMDC8 P3 H8 MDC59 CMD3 CKE
CMDC25 A2 DQL5 MDC37 CMDC25 A2 DQL5 MDC61
N2 A3 DQL6 G2 N2 A3 DQL6 G2
CMDC10 P8 H7 MDC36 CMDC10 P8 H7 MDC56 CMD4 A14 A14
CMDC24 A4 DQL7 CMDC24 A4 DQL7
P2 A5 P2 A5
CMDC22 R8 CMDC22 R8 CMD5 RST RST
+1.5VSG CMDC7 A6 MDC44 CMDC7 A6 MDC54
R2 A7 DQU0 D7 R2 A7 DQU0 D7
CMDC21 T8 C3 MDC42 CMDC21 T8 C3 MDC49 CMD6 A9 A9
CMDC6 A8 DQU1 MDC46 CMDC6 A8 DQU1 MDC55
R3 A9 DQU2 C8 R3 A9 DQU2 C8
GSL@ CMDC29 L7 C2 MDC40 CMDC29 L7 C2 MDC51 CMD7 A7 A7
R420 CMDC23 A10/AP DQU3 MDC45 Group5 CMDC23 A10/AP DQU3 MDC52 Group6
R7 A11 DQU4 A7 R7 A11 DQU4 A7
240_0402_1% CMDC28 N7 A2 MDC43 CMDC28 N7 A2 MDC50 CMD8 A2 A2
CMDC20 A12 DQU5 MDC47 CMDC20 A12 DQU5 MDC53
T3 A13 DQU6 B8 T3 A13 DQU6 B8
CMDC4 T7 A3 MDC41 CMDC4 T7 A3 MDC48 CMD9 A0 A0
CMDC14 A14 DQU7 CMDC14 A14 DQU7
M7 A15/BA3 M7 A15/BA3
+MEM_VREF6 +1.5VSG +1.5VSG CMD10 A4 A4
C364 GSL@
0.1U_0402_16V4Z

GSL@ 1 CMDC12 M2 B2 CMDC12 M2 B2 CMD11 A1 A1

R421 CMDC27 BA0 VDD CMDC27 BA0 VDD
N8 BA1 VDD D9 N8 BA1 VDD D9
C CMDC26 CMDC26 C
240_0402_1% M3 BA2 VDD G7 M3 BA2 VDD G7 CMD12 BA0 BA0
VDD K2 VDD K2
2
VDD K8 VDD K8 CMD13 WE* WE*
VDD N1 VDD N1
CLKC1 J7 N9 CLKC1 J7 N9 CMD14 A15 A15
CLKC1# CK VDD CLKC1# CK VDD
K7 CK VDD R1 K7 CK VDD R1
CMDC19 K9 R9 CMDC19 K9 R9 CMD15 CAS* CAS*
CKE/CKE0 VDD +1.5VSG CKE/CKE0 VDD +1.5VSG
CMD16 CS0_H#
CMDC18 K1 A1 CMDC18 K1 A1
CMDC16 ODT/ODT0 VDDQ CMDC16 ODT/ODT0 VDDQ
+1.5VSG L2
CS/CS0 VDDQ
A8 L2
CS/CS0 VDDQ
A8 CMD17
CMDC30 J3 C1 CMDC30 J3 C1
CMDC15 RAS VDDQ CMDC15 RAS VDDQ
K3
CAS VDDQ
C9 K3
CAS VDDQ
C9 CMD18 ODT_H
GSL@ CMDC13 L3 D2 CMDC13 L3 D2
WE VDDQ WE VDDQ
R422 310mAVDDQ E9 310mAVDDQ E9 CMD19 CKE_H
240_0402_1% F1 F1
DQSC4 VDDQ DQSC7 VDDQ
F3
DQSL VDDQ
H2 F3
DQSL VDDQ
H2 CMD20 A13 A13
DQSC5 C7 H9 DQSC6 C7 H9
DQSU VDDQ DQSU VDDQ
CMD21 A8 A8
+MEM_VREF7
DQMC4 E7 A9 DQMC7 E7 A9 CMD22 A6 A6
DML VSS DML VSS
GSL@
0.1U_0402_16V4Z

GSL@ 1 DQMC5 D3 B3 DQMC6 D3 B3

DMU VSS DMU VSS
R423
VSS
E1
VSS
E1 CMD23 A11 A11
240_0402_1% G8 G8
DQSC#4 VSS DQSC#7 VSS
2
G3
DQSL VSS
J2 G3
DQSL VSS
J2 CMD24 A5 A5
C365

DQSC#5 B7 J8 DQSC#6 B7 J8
DQSU VSS DQSU VSS
VSS
M1
VSS
M1 CMD25 A3 A3
M9 M9
VSS VSS
VSS
P1
VSS
P1 CMD26 BA2 BA2
CMDC5 T2 P9 CMDC5 T2 P9
RESET VSS RESET VSS
VSS
T1
VSS
T1 CMD27 BA1 BA1
ZQ6 L8 T9 ZQ7 L8 T9
B ZQ/ZQ0 VSS ZQ/ZQ0 VSS B
CMD28 A12 A12

1
1

J1
NC/ODT1 VSSQ
B1 GSL@ J1
NC/ODT1 VSSQ
B1 CMD29 A10 A10
GSL@ L1 B9 R424 L1 B9
NC/CS1 VSSQ NC/CS1 VSSQ
R425 J9
NC/CE1 VSSQ
D1 243_0402_1% J9
NC/CE1 VSSQ
D1 CMD30 RAS* RAS*
CLKC1 243_0402_1% L9 D8 L9 D8

2
21 CLKC1 NCZQ1 VSSQ NCZQ1 VSSQ
E2 E2 Not Available
2

VSSQ VSSQ
1

E8 E8
GSL@ VSSQ VSSQ
VSSQ
F9
VSSQ
F9 LOW HIGH
R427 G1 G1
160_0402_1% VSSQ VSSQ
G9 G9
VSSQ VSSQ
2

CLKC1# 96-BALL 96-BALL

21 CLKC1#
SDRAM DDR3 SDRAM DDR3
K4B1G1646E-HC12_FBGA96 K4B1G1646E-HC12_FBGA96

+1.5VSG
+1.5VSG
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
C371

C372

C373

C374

C375

C376

GSL@ C381

GSL@ C382

GSL@ C383

GSL@ C384

GSL@ C385
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
GSL@ C367

GSL@ C368

GSL@ C369

GSL@ C370

GSL@ C377

GSL@ C378

GSL@ C379

GSL@ C380
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
GSL@

GSL@

GSL@

GSL@

GSL@

GSL@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/07/12 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N13P DDR3 9/9
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-8221P
Date: Wednesday, October 26, 2011 Sheet 28 of 58
5 4 3 2 1
 5 4 3 2 1

+1.5V to +1.5VSG +VCCP to +1.05VSG

+1.05VS ER16 +1.05VSG
+1.5V ER16 +1.5VSG U20
U21 AO4304L_SO8 ER12
AO4304L_SO8 ER12 +1.5VSG 8 1
8 1 7 2

2
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
7 2 6 3 1 1 C387

2
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
6 3 1 1 C389 1 1 5

330U_B2_2.5VM_R15M
D 1 1 5 R429 D

C300

C390

C391

C386

1U_0402_6.3V6K
R430 1 10_0603_5%

4
2 2

C392

C393

C388

1U_0402_6.3V6K
10_0603_5%

1
2 2 + 2 2

1
2 2 ER16

1
ER16 @ D Q14

1
D Q15 2 VGA_PWROK#
2
ER07 2 VGA_PWROK# G
G +VSBP 1 2 1.05VSG_GATE S

3
+VSBP 1 2 1.5VSG_GATE S R431 100K_0402_5% SSM3K7002BFU_SC70-3

3
R432 10K_0402_5% SSM3K7002BFU_SC70-3
ER07 ER16 1

1
ER16 Q16 D C394
1

1
Q17 D C395 VGA_PWROK# 2 R433 1 2
VGA_PWROK# 2 R434 1 2 0_0402_5% G 0.1U_0603_25V7K
0_0402_5% G 0.1U_0603_25V7K S 2

3
S 2 SSM3K7002BFU_SC70-3
1

3
SSM3K7002BFU_SC70-3
1
C396
C397 0.1U_0402_16V7K
0.1U_0402_16V7K @ @ 2
2

ER05
+3VS to +3VSG
+3VS Q3 +3VSG +3VALW +3VALW
AO3404AL_SOT23
ER12 ER07
C C

S
1 3

1
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
1 1 C399
1 1 R435

G
2 200_0603_5% R665 R667
C400

C401

C398

1U_0402_6.3V6K
100K_0402_5% 100K_0402_5%
2 2

2
2 2 VGA_PWROK# DGPU_PWR_EN#
ER16 23 DGPU_PWR_EN#

1
D Q18 D D
2 DGPU_PWR_EN# VGA_PWROK 2 Q58 DGPU_PWR_EN 2 Q59
40,54 VGA_PWROK 15,20,54 DGPU_PWR_EN
G G 2N7002_SOT23-3 G 2N7002_SOT23-3
+VSBP 1 2 3VSG_GATE S S S

3
1

1
R436 100K_0402_5% SSM3K7002BFU_SC70-3
R666 R668
ER16 1 10K_0402_5% 10K_0402_5%
1

Q19 D C402
DGPU_PWR_EN# 2 R437 1 2

2
0_0402_5% G 0.1U_0603_25V7K
S 2
3

SSM3K7002BFU_SC70-3
1
C403
0.1U_0402_16V7K @
2

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/07/12 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (2/8) PCIE, SMBUS, CLK
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA-8221P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 26, 2011 Sheet 29 of 58
5 4 3 2 1
 5 4 3 2 1

D6
BLUE 2
1
GREEN 3

L30ESDL5V0C3-2 C/A SOT-23

CRT RED 2
D7

+5VS W=40mils
+CRT_VCC
1
+CRT_VCC 3 L14 @ W=40mils
2 1+5VS_CRTVCC 1 2

L15 L30ESDL5V0C3-2 C/A SOT-23 D8 SMD1812P075TF .75A 13.2V

0.1U_0402_16V4Z
PCH_CRT_RED 1 2 RED RB491D_SOT23-3 1 1
14 PCH_CRT_RED

0.1U_0402_16V4Z
D D
CHILISIN NBQ160808T-800Y-N 0603 C404 C405
D9
@
L16 HSYNC_L 2 @
PCH_CRT_GRN 1 2 GREEN 1 2 2
14 PCH_CRT_GRN
CHILISIN NBQ160808T-800Y-N 0603 VSYNC_L 3

L17
PCH_CRT_BLU BLUE L30ESDL5V0C3-2 C/A SOT-23
14 PCH_CRT_BLU 1 2
CHILISIN NBQ160808T-800Y-N 0603
D10

150_0402_1%

150_0402_1%

150_0402_1%

10P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J
1

1
1 1 1 1 1 1 VGA_DDC_DATA_C 2
R438 R439 R440 C406 C407 C408 C409 C410 C411 1
VGA_DDC_CLK_C 3
2 2 2 2 2 2

2
L30ESDL5V0C3-2 C/A SOT-23
+CRT_VCC

+5VS
ESD ER35
T36 CRTTEST
6
11
JCRT1

RED 1
2

7
R678 VGA_DDC_DATA_C 12
0_0402_5% +3VS GREEN 2
8 G 16
+5VS_CRTVCC +5VS_CRTVCC HSYNC_L 13 17
1

G
1 2 R441 10K_0402_5% BLUE 3
C412 2 1 9

2
0.1U_0402_16V4Z VSYNC_L 14
5
1

2
R679 4
10
OE#
P

4.7K_0402_5%
PCH_CRT_HSYNC 2 4 D_CRT_HSYNC 1 2 HSYNC_L R680 VGA_DDC_CLK_C 15
14 PCH_CRT_HSYNC A Y

4.7K_0402_5%
R442 10_0402_5% 5
16 CRT_DET#

1
G

U23

1
SN74AHCT1G125GW_SOT353-5 SUYIN_070546FR015S251ZR
3

2
CONN@

100P_0402_50V8J
2
G
C R682 1 C

C414
100K_0402_5%
1 2 14 PCH_CRT_DDC_DAT PCH_CRT_DDC_DAT 3 1 VGA_DDC_DATA_C

D
C413

1
5
1

2
2

G
0.1U_0402_16V4Z BSS138_SOT23
OE#
P

PCH_CRT_VSYNC D_CRT_VSYNC 1 VSYNC_L PCH_CRT_DDC_CLK Q21 VGA_DDC_CLK_C

14 PCH_CRT_VSYNC 2 4 2 14 PCH_CRT_DDC_CLK 3 1
A Y R446 10_0402_5%

D
1 1 +5VS
G

U24 1 1 BSS138_SOT23
SN74AHCT1G125GW_SOT353-5 @ C417 @ C418

10P_0402_50V8J

10P_0402_50V8J
3

@ C419 @ C420 Q22 470P_0402_50V8J 470P_0402_50V8J

1 1 2 2
33P_0402_50V8K 33P_0402_50V8K
@ C415 @ C416 2 2

2 2

LCD POWER CIRCUIT +3VS

+LCDVDD +LCDVDD ER16 +3VS
+5VALW Q23 Panel PWM Control
PJ2301 1P SOT23-3 For EMI, close to JLVDS1.

1
For EMI, close to JLVDS1. 680P_0402_50V7K @ C523
1

+LCDVDD R454
S

1 3 1 2
D

R448 1 4.7K_0402_5%
4.7U_0805_10V4Z

R447 47K_0402_5% W=80mils @ W=60mils JLVDS1

100_0805_5% C422 1 L36 1 2 B+_L 1
G

B+
2

2
4.7U_0805_10V4Z FBMA-L11-201209-221LMA30T_0805 1
2
6 2

2 C423 0_0402_5% R457 2

1 1 3
C424 C425 INVTPWM 3
40 EC_INV_PWM 1 2 @ @ 4
2 @ 4
2 2 14 PCH_TXOUT0- 5
0.1U_0402_16V4Z 0.1U_0402_16V4Z R449 22P_0402_50V8J 22P_0402_50V8J 5
14 PCH_TXOUT0+ 6
2 2 0.047U_0402_16V7K C428 C429 6
2 2 1 14 PCH_INV_PWM 2 1 7
B
220K_0402_1% 0_0402_5% R458 7 B
14 PCH_TXOUT1- 8
2N7002DW-7-F_SOT363-6 C427 1 1 8
14 PCH_TXOUT1+ 9
1

9
3

Q1A 10
10
14 PCH_TXOUT2- 11
11

1
Q1B @ @ 12
14 PCH_TXOUT2+ 12
1 2 5 2N7002DW-7-F_SOT363-6 13
14 PCH_ENVDD
R450 0_0402_5% Panel Backlight Control 33_0402_5%
R452
33_0402_5%
R453 14 PCH_TXCLK- 14
13
14
15
4

14 PCH_TXCLK+
1

15
16

2
R451 16
33 DMIC_CLK 17
R455 33_0402_5% 17
33 DMIC_DATA 18
100K_0402_5% BKOFF# DISPOFF# 18
40 BKOFF# 1 2
USB20_N8
Camera 19
19
15 USB20_N8 20
2

USB20_P8 20
15 USB20_P8 21
R456 +3VS 21
10K_0402_5%
W=80mils 22
22
+LCDVDD 23
23
24
24
25
2

25
+3VS 26
INVTPWM 26
27

0.1U_0402_16V4Z
1

1
@ DISPOFF# 27
1 28

2.2K_0402_5%

2.2K_0402_5%
R738 R739 C640 28
29
60mil Q54
@ @
16 CABC_SAVING
CABC_SAVING 30
29
30
31
B+ SI3457BDV-T1-E3_TSOP6~D 60mil 2 32
31

2
+B+_Q R676 1 @ 32
2 0_0805_5% B+_L 33
D

33
6 34
S

14 PCH_LCD_CLK 34
4 5 14 PCH_LCD_DATA 35
35
2 36 41
36 G1
1000P_0402_50V7K
C613

100K_0402_5%~D
R675

1 +3VS 37 42
1

37 G2
G

1 1 38 43
38 G3
39 44
3

C637 39 G4
40 45
0.1U_0603_50V_X7R 40 G5
2 2 ACES_50398-04071-001
2

CONN@
PWR_SRC_ON
A A
1

R76
100K_0402_5%
2

R674
1

0_0402_5% D
+LCDVDD 2 1 2 Q31
@ G SSM3K7002FU_SC70-3~D
S
Security Classification Compal Secret Data Compal Electronics, Inc.
3

Issued Date 2011/07/12 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LVDS/CRT CONN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-8221P
Date: Wednesday, October 26, 2011 Sheet 30 of 58
5 4 3 2 1
 A B C D E F G H

SATA HDD Conn.

BELLW_80039-1022
1 GND
SATA_PTX_DRX_P0 C430 1 2 0.01U_0402_16V7K SATA_PTX_C_DRX_P0 2
12 SATA_PTX_DRX_P0 RX+
12 SATA_PTX_DRX_N0 SATA_PTX_DRX_N0 C431 1 2 0.01U_0402_16V7K SATA_PTX_C_DRX_N0 3
RX-
4
1 SATA_PRX_DTX_N0 C432 1 SATA_PRX_C_DTX_N0 GND 1
2 0.01U_0402_16V7K 5
12 SATA_PRX_DTX_N0 SATA_PRX_DTX_P0 C433 1 SATA_PRX_C_DTX_P0 TX-
2 0.01U_0402_16V7K 6
TX+
12 SATA_PRX_DTX_P0
7
GND

+3VS 8
3.3V
1 9
C434 3.3V
10
3.3V
11
0.1U_0402_16V4Z GND
12
2 GND
13
GND
14 5V
15 5V
R459 1 2 0_0805_5% +5VS_HDD 16
+5VS 5V
17 GND
18 Rsv
10U_0603_6.3V6M 0.1U_0402_16V4Z 19 GND
20 12V GND 24
1 1 C436 1 1 21 12V
C435 C437 C438 22 23
12V GND

1U_0402_6.3V6K
2 2 2 2
JHDD1
1000P_0402_50V7K CONN@

ER12

2 2

+5VS Q24
SI3456DDV-T1-GE3_TSOP6
R460
D

6
SATA ODD Conn.
S

1 5 4 +5VS_ODD_R 1 2 +5VS_ODD
C439 2
1U_0402_6.3V6K 1 0_1206_5%
G

2
3

+VSBP
JODD1
2

1
C440 1 SATA_PTX_DRX_P2_C GND
12 SATA_PTX_DRX_P2 2 0.01U_0402_16V7K 2
A+
330K_0402_5% C441 1 SATA_PTX_DRX_N2_C
12 SATA_PTX_DRX_N2 2 0.01U_0402_16V7K 3
R461 A-
4
C442 1 SATA_PRX_DTX_N2_C GND
2 0.01U_0402_16V7K 5
1

ODD_EN 12 SATA_PRX_DTX_N2 SATA_PRX_DTX_P2_C B-

C443 1 2 0.01U_0402_16V7K 6
ER16 12 SATA_PRX_DTX_P2 B+
7
GND
1

D
1.5M_0402_5%

0.1U_0402_25V6

Q25 1
16 ODD_EN# 2
G R462 C444 1 2 ODD_DETECT#_R 8
16 ODD_DETECT# DP
S R463 0_0402_5% 9
3

SSM3K7002BFU_SC70-3 2 +5VS_ODD +5V

80mils 10
1

ODD_DA#_R +5V
15 ODD_DA# 1 2 11
MD
R464 0_0402_5% 12 15
GND GND
13 14
GND GND
3 3
SANTA_204901-1

Placea caps. near ODD CONN.

+5VS_ODD 0.1U_0402_16V4Z 10U_0805_10V4Z

1 1 1 C447 1
C445 C446 C448
1U_0402_6.3V6K

2 2 2 2

1000P_0402_50V7K
ER12

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/07/12 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDD & ODD CONN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-8221P
Date: Wednesday, October 26, 2011 Sheet 31 of 58
A B C D E F G H
 5 4 3 2 1

+LAN_IO +LAN_VDD
W=60mils W=60mils

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K
+3VALW
+LAN_IO 1.5A R465 1 1 1 1 1 1 1
Q26 470_0603_5%

D
3 1 W=20mils C449 C450 C451 C452 C453 C454 C455

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K
1

1
C456 +LAN_IO_DISC 2 2 2 2 2 2 2
1 1 1 1 1 1
1U_0402_6.3V6K AO3419L 1P SOT23-3 ER16

G
2

1
C457 C458 C459 C460 C461 C462 D Q27
2
+5VALW 2 EN_WOL#
D 2 2 2 2 2 2 G D
S These caps close to Pin 3,6,9,13,29,41,45

3
2
SSM3K7002BFU_SC70-3
R466
100K_0402_5%

R467 These caps close to Pin 12,27,39,42,47,48

1

1 2 EN_WOL#
ER16 220K_0402_5%~N +LAN_IO W=40mils W=20mils
1

Q28 D R468 +LAN_VDD

1
2 C463 +LAN_IO 1 2 +LAN_VDDREG R469
40 EN_WOL

0.1U_0402_16V7K
4.7U_0603_6.3V6K
G 0.1U_0603_25V7K 0_0603_5% 1 2 +LAN_EVDD10

0.1U_0402_16V7K

1U_0402_6.3V6K
S 1 1 0_0603_5%
3
2

SSM3K7002BFU_SC70-3 2

2
R470 C464 C465 1 1
10K_0402_5% R471
10K_0402_5% 2 2 C466 C467
1

2
2 2

1
14,36,41 PCIE_WAKE# 1 3 LAN_WAKE#

S
U25
ER16 Q29
C468 1 20.1U_0402_16V7K PCIE_PRX_C_GLANTX_P1 22 31 SSM3K7002BFU_SC70-3 R472
13 PCIE_PRX_GLANTX_P1 HSOP LED3/EEDO XTLI
LED1/EESK 37 1 2 2 1
C470 1 20.1U_0402_16V7K PCIE_PRX_C_GLANTX_N1 23 40 C469 3
13 PCIE_PRX_GLANTX_N1 HSON LED0 0_0402_5%
13 PCIE_PTX_GLANRX_P1 17 HSIP EECS/SCL 30 R473 1 2 10K_0402_5% 12P_0402_50V8J
3
<BOM Structure>
13 PCIE_PTX_GLANRX_N1 18 HSIN EEDI/SDA 32 R474 1 2 10K_0402_5% L19
+LAN_VDD
GND 4
C +LAN_SROUT1.05 C
W=60mils 1 2 W=60mils

0.1U_0402_16V7K

4.7U_0603_6.3V6K
16 1 LAN_MDIP0 Y4
13 LANCLK_REQ# CLKREQB MDIP0 LAN_MDIN0
2 2.2UH +-5% NLC252018T-2R2J-N 1 1
MDIN0 LAN_MDIP1
5,15,36,40,41 PLT_RST# 25 PERSTB MDIP1 4 GND 2
5 LAN_MDIN1 C471 C472
MDIN1 LAN_MDIP2 25MHZ_10PF_7V25000014
13 CLK_PCIE_LAN 19 REFCLK_P NC/MDIP2 7
LAN_MDIN2 2 2 1
13 CLK_PCIE_LAN# 20 REFCLK_N NC/MDIN2 8
10 LAN_MDIP3
NC/MDIP3 LAN_MDIN3 1
11
XTLO NC/MDIN3 XTLO
43 1 2
CKXTAL1 C473
XTLI 44 13 +LAN_VDD These components close to Pin 36
CKXTAL2 DVDD10 12P_0402_50V8J
DVDD10
29 ( Should be place within 200 mils )
41
LAN_WAKE# DVDD10
R475 28
LANWAKEB ER13
+3VS 1 2 ISOLATEB 26 27
ISOLATEB DVDD33
39
1K_0402_5% DVDD33
14 12 +LAN_IO
NC/SMBCLK AVDD33
2

R476 1 2 10K_0402_5% 15 42
R477 R478 1 NC/SMBDATA AVDD33
+LAN_IO 2 1K_0402_5% 38 47
15K_0402_5% GPO/SMBALERT AVDD33
48
AVDD33

+LAN_IO 1 2 33
1

R479 0_0402_5% ENSWREG +LAN_EVDD10

21
3.3V : Enable switching regulator EVDD10 JLAN1
34
0V : Disable switching regulator +LAN_VDDREG VDDREG
35 3 +LAN_VDD
VDDREG AVDD10
6 9
AVDD10 RJ45_TX3- SHLD1
9 8
R480 1 AVDD10 PR4-
2 2.49K_0402_1% 46
RSET AVDD10
45
RJ45_TX3+ 7
B +LAN_SROUT1.05 PR4+ B
24 36
GND REGOUT RJ45_RX1-
49 6
PGND PR2-
RJ45_TX2- 5
RTL8111F-CGT QFN 48P PR3-
RJ45_TX2+ 4
TS1 PR3+
RJ45_RX1+ 3
+V_DAC R481 75_0603_1% PR2+
1 24 1 2
LAN_MDIP0 TCT1 MCT1 RJ45_TX0+ R482 75_0603_1% RJ45_TX0-
2 23 1 2 2
LAN_MDIN0 TD1+ MX1+ RJ45_TX0- R483 75_0603_1% PR1-
3 22 1 2
TD1- MX1- R484 75_0603_1% RJ45_TX0+
1 2 1 10
+V_DAC PR1+ SHLD2
4 21
LAN_MDIP1 TCT2 MCT2 RJ45_RX1+
5 20
C474 1 LAN_MDIN1 TD2+ MX2+ RJ45_RX1-
2 6 19 2
TD2- MX2-

2
C475 SANTA_130452-07
0.01U_0402_16V7K +V_DAC 7 18 100P_1206_2KV7K CONN@ D15

2
LAN_MDIP2 TCT3 MCT3 RJ45_TX2+ @
8 17
LAN_MDIN2 TD3+ MX3+ RJ45_TX2- 1
9 16
TD3- MX3-

1
04/19 AZC199-02SPR7G_SOT23-3
+V_DAC 10 15
ESD

1
LAN_MDIP3 TCT4 MCT4 RJ45_TX3+ D16 D17
11 14
LAN_MDIN3 TD4+ MX4+ RJ45_TX3- LAN_MDIP1 LAN_MDIP0 LAN_MDIP3 LAN_MDIP2
12 13 6 3 6 3
TD4- MX4- I/O4 I/O2 I/O4 I/O2

TAIMAG_IH-160 D18 @ LSE-200NX3216TRLF_1206-2 +LAN_IO 5 2 +LAN_IO 5 2

VDD GND VDD GND
1 2
ER34 D19 @ LSE-200NX3216TRLF_1206-2
1 2 LAN_MDIN1 4 1 LAN_MDIN0 LAN_MDIN3 4 1 LAN_MDIN2
R485 I/O3 I/O1 I/O3 I/O1
A LANGAN D20 @ LSE-200NX3216TRLF_1206-2 AZC099-04S.R7G_SOT23-6 AZC099-04S.R7G_SOT23-6 A
2 1
1 2
0.1U_0603_25V7K D21 @ LSE-200NX3216TRLF_1206-2
R486 1 2

2 1 LANGAN
Security Classification Compal Secret Data Compal Electronics, Inc.
0.1U_0603_25V7K
ESD Issued Date 2011/07/12 Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
2012/12/31 Title
LAN RTL8111F
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA-8221P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 26, 2011 Sheet 32 of 58
5 4 3 2 1
 A B C D E F G H

+5VS_PVDD
EMI close to JSPK1

SPKOUT_L1 R487 1 2 0_0603_5% SPK_L1 1 2

R488 1 C476 0.22U_0603_16V7K
+5VS 2 1 @

10U_0805_10V6K

0.1U_0402_16V7K

0.1U_0402_16V7K
0_0805_5% @ C477 1U_0603_10V6K
1 1 1 2
SPKOUT_L2 R489 1 2 0_0603_5% SPK_L2 1 2
C479 C480 C481 C478 0.22U_0603_16V7K
@
2 2 2 JSPK1
SPK_R1 1
1 R491 SPKOUT_R1 R490 1 SPK_R1 SPK_R2 1 1
2 0_0603_5% 1 2 2
+3VS_DVDD_R SPK_L1 2
+3VS_DVDD 2 1 1 C482 0.22U_0603_16V7K 3
3

10U_0603_6.3V6M
0_0603_5% @ SPK_L2 4
4

0.1U_0402_16V7K
1 1 @ C483 1U_0603_10V6K
E&T_3801-Q04N-01R
C484 C485 SPKOUT_R2 R492 1 SPK_R2 2
2 0_0603_5% 1 2 CONN@
C486 0.22U_0603_16V7K
DMIC_DATA 2 2
@
+5VS_PVDD +VDDA
1 L20
2 1 +5VS

2
+3VS_DVDD

10U_0805_10V6K
0.1U_0402_16V7K

0.1U_0402_16V7K
C487 R493 1 1 1 MBK1608800YZF 0603
22P_0402_50V8J +3VS 2 1 D22 D23
2 10U_0603_6.3V6M

0.1U_0402_16V7K
@ 0_0603_5% C488 C489 C490
1 1 2 2 2
EMI C491 C492

1
YSDA0502C 3P C/A SOT-23 YSDA0502C 3P C/A SOT-23
2 2

10P_0402_50V8J
DMIC_CLK

39

46

25

38
1

9
U26 HDA_SDOUT_AUDIO HDA_BITCLK_AUDIO
1 2
ESD @ @

DVDD_IO

PVDD1

PVDD2

AVDD1

AVDD2
DVDD

0_0402_5%
C493 C494

1
22P_0402_50V8J
2 @ 1 R494
@
23 40 SPKOUT_L1 @
LINE1_L SPK_OUT_L+ SPKOUT_L2
24 LINE1_R SPK_OUT_L- 41 EMI

22P_0402_50V8J
14 45 SPKOUT_R1
LINE2_L SPK_OUT_R+

10P_0402_50V8J
15 44 SPKOUT_R2 1
LINE2_R SPK_OUT_R- HDA_SYNC_AUDIO
MIC1 1 R495 2 MIC1_R 1 2 C495 4.7U_0603_6.3V6K MIC1_C 21 32 HP_OUTL 2 C496
2 1K_0402_5% MIC2_C 22 MIC1_L HP_OUT_L HP_OUTR 2
MIC1_R HP_OUT_R 33
MIC2 MIC2_R 1 2
1 R496 2 2 C497 4.7U_0603_6.3V6K C498 @
1K_0402_5% 16 MIC2_L @ 1
17 MIC2_R
10 HDA_SYNC_AUDIO
SYNC HDA_SYNC_AUDIO 12
DMIC_DATA R499 1 2 0_0402_5% DMIC_DATA_CODEC 2 6 HDA_BITCLK_AUDIO
30 DMIC_DATA GPIO0/DMIC_DATA BCLK HDA_BITCLK_AUDIO 12
DMIC_CLK 1 2 DMIC_CLK_CODEC 3
30 DMIC_CLK GPIO1/DMIC_CLK
L21 FBMA-L10-160808-301LMT_2P 5 HDA_SDOUT_AUDIO
SDATA_OUT HDA_SDOUT_AUDIO 12
EC_MUTE# R500 1 2 0_0402_5% PD# 4 8 HDA_SDIN_AUDIO1 R501 2 HDA_SDIN0 12
40 EC_MUTE# PD# SDATA_IN CONN@
33_0402_5%
+USB_VCCC ACES_51524-0160N-001
HDA_RST_AUDIO# 11 47 1 R502 2 18
12 HDA_RST_AUDIO# RESET# EAPD EAPD 40 GND
17
0_0402_5% R736 GND
SPDIFO
48 +MIC1_VREFO_R 2 1 2.2K_0402_1%
12 +MIC1_VREFO_L R737 2 1 2.2K_0402_1% 16
MIC_JD PCBEEP 16
1 R503 2 20 15
20K_0402_1% MONO_OUT 15
14
HP_JD SENSE_A 14
2 R504 1 13 15 USB20_N9 13
39.2K_0402_1% SENSE A 13
29 15 USB20_P9 12
MIC2_VREFO 12
18 11
SENSE B 11
30 +MIC1_VREFO_R 10
MIC1_VREFO_R 10
36 28 9
CBP LDO_CAP 9
8
8

10U_0805_10V6K
1 2 35 27 AC97_VREF 7
CBN VREF 7

10U_0805_10V6K

0.1U_0402_16V7K
C499 2.2U_0603_16V6K 1 L34 MIC_JD 6
AC_JDREF MIC2 MIC-2 6
+MIC1_VREFO_L
31
MIC1_VREFO_L JDREF
19 1 R505 2 1 1 1 2 5
5
20K_0402_1% C500 L35 BLM18PG121SN1D_0603 4
C502 C503 MIC1 MIC-1 HP_JD 4
43 34 1 2 1 2 3
PVSS2 CPVEE C501 2 BLM18PG121SN1D_0603 HP_OUTR 3
42 2
3 PVSS1 2.2U_0603_16V6K @ 2 2 HP_OUTL 2 3
49 26 1 1 1
+3VS DVSS2 AVSS1 1
7 37
DVSS1 AVSS2 C638 C639 JAU1
ALC269Q-VB5-GR_QFN48_7X7 220P_0402_50V7K 220P_0402_50V7K
2 2
1

4.7K_0402_5%
R506 @
2

HDA_RST_AUDIO# R507 1 2 0_0402_5%

@
1 R508 1 2 0_0402_5%
0.1U_0402_16V7K
C508 R509 1 2 0_0402_5%
2 R510 1 2 0_0402_5%

1 2 @

C504 0.1U_0402_16V7K

1 2 @

C505 0.1U_0402_16V7K
4 4
1 2 @

C506 0.1U_0402_16V7K
1 2 @

C507 0.1U_0402_16V7K
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/07/12 Deciphered Date 2012/12/31 Title
For EMI (on MIC and Headphone AGND to connected with
DGND)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HD CODEC ALC269
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA-8221P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 26, 2011 Sheet 33 of 58
A B C D E F G H
 5 4 3 2 1

+CARDPWR
&DUG5HDGHU&RQQHFWRU

JCR1

5 VDD
SDCMD 3
SDCLK CMD
6
CLK
4
VSS
7
D VSS D
SDD0 8
SDD1 DAT0
9
SDD2 DAT1
1
SDD3 DAT2
2
CD/DAT3
+3VS +3VS_CR 12
SDWP# GND SW
10 13
R633 SDCD WP SW GND SW
30mil 11
CD SW
2 1
0_0603_5%
@ T-SOL_156-2000302604
2 1 10mil CONN@
C615 100P_0402_50V8J U40
R497 1 2 +RREF 1
6.2K_0603_1% REFE @
GPIO0 17 1 2 1 2
USB20_N10 2 R636 10_0402_5% @ C614 10P_0402_50V8J
15 USB20_N10 USB20_P10 DM CLK_SD_48M
15 USB20_P10 3 DP CLK_IN 24 CLK_SD_48M 13
+3VS_CR 4 23 +3VS_CR +3VS_CR
+CARDPWR 3V3_IN NC
+VREG
30mil 5 CARD_3V3
1 2 6 V18 SP14 22
C623 1 10mil 21 SDD2
C619 C616 SP13 SDD3
7 NC SP12 20

1
4.7U_0805_10V4Z 1U_0402_6.3V6K 19 @ @
2 1 SDWP SP11 SDCMD
8 SP1 SP10 18
0.1U_0402_16V4Z 2 9 16 R774 100K_0402_5%
SP2 SP9

1
SDD1 10 15 1 2 SDCLK 100K_0402_5% R768
SP3 SP8

EPAD
SDD0 11 14 0_0402_5% R634 EMI

2
SP4 SP7 SDCD# R775 SDWP R773 SDCD#
12 SP5 SP6 13
100K_0402_5% 100K_0402_5%

6
RTS5137-GR_QFN24_4X4

25

2
C C

SDWP# 5 SDCD 2
2N7002DW-7-F_SOT363-6 2N7002DW-7-F_SOT363-6

1
Q20B Q20A

ER04

+CARDPWR

30mil
2

@ 1 1 1 ER30

R635 C617 C618 C622

100K_0402_5% 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 SDCLK
1

Close to connector

C612 R632
2 1 1 2 SDCLK
B EMI @
22P_0402_50V8J
33_0402_5% @
B

close JCR1

22P_0402_50V8J
C621
1 EMI
@ 2
close U40

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/07/12 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RTS5137 Media Card Controller
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA-8221P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 26, 2011 Sheet 34 of 58
5 4 3 2 1
 5 4 3 2 1

+3VS

ER35 ER35

1
D24 D25 R663
HDMI_R_D1- 1 9 HDMI_R_D1- HDMI_R_D0+ 1 9 HDMI_R_D0+ 1M_0402_5%

2
G
HDMI_R_D1+ 2 8 HDMI_R_D1+ HDMI_R_D0- 2 8 HDMI_R_D0-

2
HDMI_R_D2- 4 7 HDMI_R_D2- HDMI_R_CK+ 4 7 HDMI_R_CK+ 14 TMDS_B_HPD TMDS_B_HPD 3 1 HDMI_DETECT

D
HDMI_R_D2+ 5 6 HDMI_R_D2+ HDMI_R_CK- 5 6 HDMI_R_CK-

1
D Q57 ER16 R638
D
SSM3K7002BFU_SC70-3 20K_0402_5%
3 3

2
L05ESDL5V0NA-4 L05ESDL5V0NA-4

AP2330W-7_SC59-3
For ESD request.
W=40mils
3
OUT
W=40mils
1
IN
1

0.1U_0402_16V7K
1 2 C635

0.1U_0402_16V7K
D26 C636 GND
HDMI_DETECT 6 3 HDMI_SDATA
I/O4 I/O2 U41 2
2

+5VS 5 2
VDD GND +5VS Q53
@

D
+HDMI_5V_OUT

S
6
+HDMI_5V_OUT 4 1 HDMI_SCLK 4 5 F1 @
I/O3 I/O1 +HDMI_5V
1 2 1 2
AZC099-04S.R7G_SOT23-6 C626 1 W=40mils0.5A 15VDC_FUSE

1U_0603_10V6K

1U_0603_10V4Z
@
For ESD request.

G
1
C628

3
2 SI3456BDV-T1-E3 1N TSOP6
+VSBP @
2

470K_0402_5%
1
TMDS_B_CLK 2 1 HDMI_CK+ R664
14 TMDS_B_CLK
TMDS_B_CLK# 0.1U_0402_16V7K 2 1 C625 HDMI_CK-
14 TMDS_B_CLK#
0.1U_0402_16V7K C624 @
TMDS_B_DATA0 2 1 HDMI_D0+
14 TMDS_B_DATA0

2
C TMDS_B_DATA0# 0.1U_0402_16V7K 2 1 C630 HDMI_D0- EN_HDMI C
14 TMDS_B_DATA0#
0.1U_0402_16V7K C631

1
TMDS_B_DATA1 HDMI_D1+ D R643
2 1

1.5M_0402_5%
1

0.1U_0402_16V7K
14 TMDS_B_DATA1
TMDS_B_DATA1# 0.1U_0402_16V7K 2 1 C633 HDMI_D1- 2 Q56 C634
14 TMDS_B_DATA1# 36,41,42 SUSP ER16
0.1U_0402_16V7K C627 G
TMDS_B_DATA2 2 1 HDMI_D2+ S @ @

3
14 TMDS_B_DATA2 2
TMDS_B_DATA2# 0.1U_0402_16V7K 2 1 C629 HDMI_D2- SSM3K7002BFU_SC70-3 @
14 TMDS_B_DATA2#

2
0.1U_0402_16V7K C632

R645 680_0402_5%
TMDS_GND 1 2 HDMI_R_D2-
R649 680_0402_5%
1 2 HDMI_R_D2+
R646 680_0402_5%
1 2 HDMI_R_D1-
R653 680_0402_5%
1 2 HDMI_R_D1+
R659 680_0402_5%
1 2 HDMI_R_D0-
R647 680_0402_5%
1 2 HDMI_R_D0+
R651 680_0402_5%
1 2 HDMI_R_CK-
R652 680_0402_5% HDMI_CK- 1 2 HDMI_R_CK-
1 2 HDMI_R_CK+ R644 0_0402_5%
L32 @ WCM-2012-900T_0805
1 2
1 2 +HDMI_5V_OUT
1

ER16 D Q55 R656

2 1 2 +5VS 4 3
G 10K_0402_5% 4 3
S JHDMI1
3

SSM3K7002BFU_SC70-3 HDMI_DETECT 19
HDMI_CK+ HDMI_R_CK+ HP_DET
1 2 18
R648 0_0402_5% +5V
17
HDMI_SDATA DDC/CEC_GND
16
HDMI_SCLK SDA
15
B
HDMI_D0+ HDMI_R_D0+ SCL B
1 2 14
R658 0_0402_5% Reserved
13
HDMI_R_CK- CEC
12 20
L31 @ WCM-2012-900T_0805 CK- GND
11 21
HDMI_R_CK+ CK_shield GND
4 3 10 22
4 3 HDMI_R_D0- CK+ GND
9 23
D0- GND
8
HDMI_R_D0+ D0_shield
1 2 7
1 2 HDMI_R_D1- D0+
6
D1-
HDMI HDMI_R_D1+
5
4
D1_shield
HDMI_D0- HDMI_R_D0- HDMI_R_D2- D1+
1 2 3
R657 0_0402_5% D2-
2
+3VS +3VS +HDMI_5V_OUT HDMI_R_D2+ D2_shield
1
2.2K_0402_5% D2+
R650
HDMI_D1+ 1 2 HDMI_R_D1+ SUYIN_100042GR019M26DZL
1 2 R660 R641 R639 0_0402_5% CONN@
2
1
2.2K_0402_5%

2.2K_0402_5%

1 2
1 2
ER34 EMI
1
2

4 3
5

4 3 @ 47P_0402_50V8J HDMI_R_CK-
2 1 C641
Q52B L33 @ WCM-2012-900T_0805
14 HDMICLK_NB HDMICLK_NB 1 2 HDMI_L_SCLK 4 3 HDMI_SCLK RV91, RV92 place near JHDMI connect @ 47P_0402_50V8J 2 1 C642 HDMI_R_CK+
R654 0_0402_5% HDMI_D1- 1 2 HDMI_R_D1-
2N7002DW-T/R7_SOT363-6 R662 0_0402_5% @ 47P_0402_50V8J 2 1 C643 HDMI_R_D0+
1 2
@ 47P_0402_50V8J 2 1 C644 HDMI_R_D0-
R640 HDMI_D2+ 1 2 HDMI_R_D2+
2.2K_0402_5% R661 0_0402_5% @ 47P_0402_50V8J HDMI_R_D1+
2 1 C645

@ 47P_0402_50V8J 2 1 C646 HDMI_R_D1-

2

1 2
Q52A 1 2 @ 47P_0402_50V8J HDMI_R_D2+
2 1 C647
14 HDMIDAT_NB HDMIDAT_NB 1 2 HDMI_L_SDATA 1 6 HDMI_SDATA
A R642 0_0402_5% 4 3 @ 47P_0402_50V8J 2 1 C648 HDMI_R_D2- A
2N7002DW-T/R7_SOT363-6 4 3
L30 @ WCM-2012-900T_0805
5V PULL UP IN CONNECTER SIDE
HDMI_D2- 1 2 HDMI_R_D2- close to JHDMI
R655 0_0402_5%

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/07/12 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDMI Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-8221P
Date: Wednesday, October 26, 2011 Sheet 35 of 58
5 4 3 2 1
 5 4 3 2 1

+3V_PCH
+3VS +3VS reference delay circuit
For WAKE Function USB_PE_REXT R1030 1 USB30@2 12.1K_0402_1%
ER02 Add USB3.0 (ASM1042) R1021 1 @ 2 4.7K_0402_5% USB30_SMI#
R1022 1 USB30@2 4.7K_0402_5% USB_PEPWRDET USB_UREXT R1032 1 USB30@2 12.1K_0402_1%
USB_PEPWRDET

1
@ @

R1034 R1022 R1025 R1026

R1033 1 @ 2 4.7K_0402_5% USB_PESEL @ C1004 100K_0402_5% 100K_0402_5%
R1034 1 @ 2 4.7K_0402_5% USB_PEPWRDET S1 Mount @ USB30_XT1 2 1 22P_0402_50V8J USB_PORST#

2
R1036 1 USB30@2 4.7K_0402_5% USB_TEST_EN
R1037 1 USB30@2 4.7K_0402_5% USB_GPIO0 * S3 @ Mount @

1
R1028 @ D
1 2 4.7K_0402_5% USB_GPIO1 Q902
S3 S4/S5 R1031 1 @ 2 4.7K_0402_5% USB_GPIO2 2

3
4
USB30@ C1005 G ER16
D +3V_PCH V X
USB_PESEL 12P_0402_50V8J Y9 USB30@ S D

3
20MHZ_12PF_X3G020000FC1H-X @

1
D Q903 SSM3K7002BFU_SC70-3
+3VS X X R1033

1
2
2
+1.2VUSB V X @ ER16
* Other applaction @ USB30_XT2
G
2 1 S

3
+1.2VS X X Express Card/Mini Card Mount C1006
ER13 22P_0402_50V8J 1 @ SSM3K7002BFU_SC70-3

C1007
1U_0402_6.3V6K
2
Power Sequence
+3VS
ASM1042
+1.2VS
+5VALW/+3VALW +1.2VS
U90 USB30@
+3V_PCH/+1.2VUSB
+3VS/+1.2VS USB_GPIO1 1 64 USB_GPIO0
USB30_SMI# GPIO1 GPIO0
16 USB30_SMI# 2 SMI# GND3 63
T1 PORST# USB_GPIO2
1U_0402_6.3V6K @ C1008 USB_PESEL
3 GPIO2 VCC12_3 62
USB_PE_REXT +VDD33U
Close to ASM1042
4 PE_SEL PE_REXT 61
T2 PE_RST# 1 2 USB_PEPWRDET 5 60 +VDD33U
CLKREQ_USB30#_R PE_PWRDET VCC33P USB30@ C1009 2
13 CLKREQ_USB30# 1 2 6 PE_CLKREQ# PE_TXN 59 1 0.1U_0402_16V7K PCIE_PRX_USB3TX_N4 13
@ 7 58 USB30@ C1010 2 1 0.1U_0402_16V7K
VCC33_1 PE_TXP PCIE_PRX_USB3TX_P4 13
R1029 2 @ 1 0_0402_5% R1039 0_0402_5% USB_SPISCK 8 57
USB_SPISI SPI_CLK GNDA3
T1: 2~80ms 9 SPI_DO PE_RXN 56 PCIE_PTX_USB3RX_N4 13
USB30@ R1040 47K_0402_5% USB_SPICS# 10 55
T2: >200ms USB_SPISO SPI_CS# PE_RXP PCIE_PTX_USB3RX_P4 13
+3VS 2 1 11 SPI_DI VDD12P 54 +VDD12U
12 53 USB30_XT1
USB_PORST# GND1 XI USB30_XT2
C
13 PORST# XO 52 C
T90 PAD @ 14 51
UART_RX PE_CLKN CLK_PCIE_USB30# 13
USB30@ C1011 1U_0402_6.3V6K 2 1 T91 PAD @ 15 50

37 U2DN_B
U2DN_B
16
17
UART_TX
VCC12_1 ASM1042 PE_CLKP
VCC12_4 49
48 +VDD12U
CLK_PCIE_USB30 13

U2DP_B U2DN_B VDD12U_2 U3RXDN_A

37 U2DP_B 18 U2DP_B (TQFN 64) U3RXN_A 47
U3RXDP_A
U3RXDN_A 37
+3V_PCH 19 VSUS33_1 U3RXP_A 46 U3RXDP_A 37
+1.2VUSB 20 VSUS12_1 GNDA2 45
U2DN_A 21 44 U3TXDN_A_C
37 U2DN_A U2DN_A U3TXN_A U3TXDN_A_C 37
U2DP_A 22 43 U3TXDP_A_C
37 U2DP_A U2DP_A U3TXP_A U3TXDP_A_C 37

14,32,41 PCIE_WAKE#
USB30@
R1043 0_0402_5%
23
24
VSUS33_2
PE_WAKE#
UREXT
VCC33U
42
41
USB_UREXT
+VDD33U

R1044 4.7K_0402_5%
25
26
PPON_A
PPON_B
U3TXN_B
U3TXP_B
40
39
U3TXDN_B_C
U3TXDP_B_C
U3TXDN_B_C 37
U3TXDP_B_C 37
Q904
+3VS 2 @ 1 37 USB_OCI#A
37 USB_OCI#B
USB_OCI#A
USB_OCI#B
PLT_RST#_USB30
27
28
OCI_A#
OCI_B#
GNDA1
U3RXN_B
38
37 U3RXDN_B
U3RXDP_B
U3RXDN_B 37

+1.2VUSB AO3404AL_SOT23 +1.2VS
5,15,32,40,41 PLT_RST# 1 2
USB30@ R1045 0_0402_5% USB_TEST_EN
29
30
PE_RST# U3RXP_B
36
35 +VDD12U
U3RXDP_B 37
1

S
TEST_EN VDD12U_1 +VDD12U 3
1 31
VCC33_2 VSUS12_2
34 +1.2VUSB
1

10U_0603_6.3V6M

C1037
C1012 32 33 USB30@
@ VCC12_2 GND2

G
2
0.1U_0402_16V4Z
2 2 USB30@
+3VS
GND4
65
1

USB30@
USB30@ R1047 R1048 @ +VSBP 1
R1049
2
330K_0402_5%

1.2VS_GATE

4.7K_0402_5% 4.7K_0402_5% ASM1042_TQFN64_9X9

1.5M_0402_5%
USB30@
R1046
2

1
U92 Q905 D
USB_SPICS# 1 ER26 SUSP C1036
CS# VCC 8 35,41,42 SUSP 2
3
SCLK 6
USB_SPISCK G

USB30@ 0.1U_0603_25V7K

2
WP# USB_SPISI USB30@ USB30@
7
SI 5
S

1
HOLD#
4
GND SO 2
USB_SPISO
2 C1016 C1045 R1082
SSM3K7002BFU_SC70-3

B MX25L5121EMC-20G SOP 8P USB30@ 2
@
1 1 2
33_0402_5% @
USB_SPISCK ER16
B

1
0.1U_0402_16V4Z 22P_0402_50V8J
Reserve for EMI please close to U90


FBMA-L11-201209-221LMA30T_0805 +3VALW to +1.2V Transfer
+VDD12U +5VALW +3VALW
+5VALW +3VALW
+1.2VUSB

1U_0603_10V6K~N

10U_0603_6.3V6M
USB30@ L904
+1.2VUSB +1.2VS

C1018

C1019
+1.2VS 1 2 1 1 U91 1A 1A
5 3
USB30@ 1 USB30@ 1 USB30@ 1 VIN VOUT
9 4
VIN VOUT
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C1021 C1022 C1023 6

USB30@ 1 USB30@ 1 USB30@ 1 USB30@ 1 USB30@ 1 USB30@ 1 USB30@ 1 2 2 VCNTL
1 2 1 7 2 2 1
POK FB
10U_0603_6.3V6M

0.1U_0402_16V4Z

0.1U_0402_16V4Z

10U_0603_6.3V6M

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C1025 C1026 C1027 USB30@ C1020 C1028 C1029 C1030 C1031 R1050 R1051
2 2 2

10U_0603_6.3V6M
5.1K_0402_1% 8 10K_0402_1%
EN GND 1

C1032
USB30@ USB30@ USB30@ USB30@ 1

2
2 2 2 2 2 2 2 2 APL5930KAI-TRG_SO8
USB30@ R1052
20K_0402_1% USB30@
Pin 35 Pin 48 Pin 54 R1053 1 2 2
40,42 PCH_PWR_EN USB30@
USB30@ 0_0402_5%

1
Pin 20 Pin 34 Pin 16 Pin 32 Pin 49 Pin 62

+3VS
+3V_PCH
A +3VS A
USB30@ +VDD33U
L905
1 USB30@ 1 USB30@ 1 1 2
10U_0603_6.3V6M

0.1U_0402_16V4Z

0.1U_0402_16V4Z

USB30@ 1 USB30@ 1 USB30@ 1 USB30@ C1014 C1041 C1042 FBMA-L11-201209-221LMA30T_0805

10U_0603_6.3V6M

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C1038 C1039 C1040 USB30@ 1 USB30@ 1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C1034 C1035
2 2 2
2 2 2
2 2
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/10/1 Deciphered Date 2012/06/30 Title
Pin 19 Pin 23 Pin 7 Pin 31
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB3.0 controller
Pin 60 Pin 41 Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-8221P
Date: Wednesday, October 26, 2011 Sheet 36 of 58
5 4 3 2 1
 1 2 3 4 5

@ 1 2
R511 0_0402_5%

+5VALW L22 DLP11TB800UL2L_4P

USB3_RX1_P_L 2 1 USB3_RX1_P_R

ER12
+USB_VCCA USB3_RX1_N_L USB3_RX1_N_R
AI CHARGER +5VALW

U27 3 4

2
C509 @ 1 2 2.2U_0402_6.3V6M AI@ AI@ U28
1 8 R512 1 2 0_0402_5% 8 1 CEN# @ T44 PAD
GND OUT 40 USBAI_EN CB CEN
2 7 USB20_N0_R 7 2 USB20_N0_CON R672 AI@
IN OUT TDM DM

4.7K_0402_5%
C510 2 1 0.22U_0603_16V7K 3 6 0_0402_5% @ 1 2 USB20_P0_R 6 3 USB20_P0_CON
USBAI_PEN# IN OUT TDP DP SELCDP
40 USBAI_PEN# 4 5 1 IU3@ 2 R514 0_0402_5% +5VALW 5 4

1
EN# OC# USB_OC0# 15 VDD SELCDP
R515 @ 1 2 R516 2 9
ER33 0_0402_5% R517 0_0402_5% 100K_0402_5% Thermal Pad SELCDP
AP2301MPG-13 MSOP 8P 1 USB30@2 AI@ C511 SLG55584AVTR_TDFN8_2X2

2
USB_OCI#A 36
1 R1056 L23 DLP11TB800UL2L_4P 0.1U_0402_16V7K~N
A 1 A
Low Active C512 USB3_TX1_P_L 2 1 USB3_TX1_P_C 2 1 USB3_TX1_P_R AI@

2
@ 1000P_0402_50V7K C524 0.1U_0402_10V7K
2 USB3_TX1_N_L 2 USB3_TX1_N_C USB3_TX1_N_R R673 @
1 3 4 CB SELCDP Function

4.7K_0402_5%
C525 0.1U_0402_10V7K USB20_N0_R R745 1 NAI@ 2 0_0402_5% USB20_N0_CON
0 X DCP autodetect charger mode

1
USB20_P0_R R746 1 NAI@ 2 0_0402_5% USB20_P0_CON
@ 1 2 1 0 S0 charging with SDP only
R518 0_0402_5% U28
1 1 S0 charging with SDP or CDP

@ 1 2
R519 0_0402_5%

L24 DLP11TB800UL2L_4P
USB3_RX2_P_L 2 1 USB3_RX2_P_R
+5VALW

USB3_RX2_N_L 3 4 USB3_RX2_N_R
ER12
U29 +USB_VCCB
C515 @ 1 2 2.2U_0402_6.3V6M
1 8 @ 1 2
GND OUT R520 0_0402_5%
2 7
C516 IN OUT
2 1 0.22U_0603_16V7K 3 6 0_0402_5% @ 1 2
USBSW_EN# IN OUT
40 USBSW_EN# 4 5 1 IU3@ 2 USB_OC0# 15
R522 0_0402_5% 2 R521 1 0_0402_5%
EN# OC# R523 @
0_0402_5% L25 DLP11TB800UL2L_4P
ER33 AP2301MPG-13 MSOP 8P 1 USB30@2 USB3_TX2_P_L 2 1 USB3_TX2_P_C 2 1 USB3_TX2_P_R
USB_OCI#B 36
1 R1057 C580 0.1U_0402_10V7K L26
Low Active C517
@ 1000P_0402_50V7K USB3_TX2_N_L 2 1 USB3_TX2_N_C 3 4 USB3_TX2_N_R
USB20_N0_CON 1
1 2
2 USB20_N0_C charger port: left side & near user
C581 0.1U_0402_10V7K +USB_VCCA
2 USB20_P0_CON USB20_P0_C JUSB1
B 4
4 3
3 W=80mils B
1
@ 1 WCM-2012HS-900T USB20_N0_C VBUS
2 2
R524 0_0402_5% USB20_P0_C D-
1 1 3
D+
2 R525 1 0_0402_5% 4
@ C513 C514 USB3_RX1_N_R GND
5
470P_0402_50V7K 47U_0805_6.3V USB3_RX1_P_R StdA-SSRX-
6 10
2 2 StdA-SSRX+ GND
7 11
USB3_TX1_N_R GND-DRAIN GND
8 12
USB3_TX1_P_R StdA-SSTX- GND
9 13
StdA-SSTX+ GND
2 R526 1 0_0402_5% SANTA_373280-1
+5VALW ER35 @ CONN@
D27
USB3_RX1_P_R 1 9 USB3_RX1_P_R
L27
ER12 U30 +USB_VCCC USB3_RX1_N_R 2 8 USB3_RX1_N_R USB20_N1_R 1 2 USB20_N1_C
C518 @ 1 1 2
2 2.2U_0402_6.3V6M
1 8 USB3_TX1_P_R 4 7 USB3_TX1_P_R
GND OUT USB20_P1_R USB20_P1_C
2 7 4 3
C519 IN OUT USB3_TX1_N_R USB3_TX1_N_R 4 3
2 1 0.22U_0603_16V7K 3 6 0_0402_5% 5 6
USBSW_EN# IN OUT WCM-2012HS-900T
40 USBSW_EN# 4 5 1 2 USB_OC4# 15
EN# OC# R527
2 R528 1 0_0402_5%
ER33 AP2301MPG-13 MSOP 8P 3 @
1
Low Active C522 L05ESDL5V0NA-4
@ 1000P_0402_50V7K
2

Co-lay USB3.0 ( PCH & ASM1042) +USB_VCCB

W=80mils JUSB2
1
ER35 USB20_N1_C VBUS
2
D28 USB20_P1_C D-
1 1 3
C D29 USB20_N0_C USB20_N1_C D+ C
6 3 4
R1058 1 IU3@ USB3_RX1_P_L USB3_RX2_P_R USB3_RX2_P_R I/O4 I/O2 USB3_RX2_N_R GND
15 USB3_RX1_P 2 0_0402_5% 1 9 C520 C521 5
R1059 1 IU3@ USB3_RX1_N_L USB3_RX2_P_R StdA-SSRX-
15 USB3_RX1_N 2 0_0402_5% 470P_0402_50V7K 47U_0805_6.3V 6 10
USB3_RX2_N_R USB3_RX2_N_R 2 2 StdA-SSRX+ GND
2 8 7 11
R1060 1 USB30@2 0_0402_5% USB3_TX2_N_R GND-DRAIN GND
36 U3RXDP_A +5VALW 5 2 8 12
R1061 1 USB30@2 0_0402_5% USB3_TX2_P_R USB3_TX2_P_R VDD GND USB3_TX2_P_R StdA-SSTX- GND
36 U3RXDN_A 4 7 9 13
StdA-SSTX+ GND
USB3_TX2_N_R 5 6 USB3_TX2_N_R SANTA_373280-1
R1062 1 IU3@ 2 0_0402_5% USB3_TX1_P_L USB20_P0_C 4 1 USB20_P1_C CONN@
15 USB3_TX1_P I/O3 I/O1
R1063 1 IU3@ 2 0_0402_5% USB3_TX1_N_L
15 USB3_TX1_N
AZC099-04S.R7G_SOT23-6
R1064 1 USB30@2 0_0402_5% 3
36 U3TXDP_A_C
R1065 1 USB30@2 0_0402_5%
36 U3TXDN_A_C
L05ESDL5V0NA-4

Co-lay USB3.0 ( PCH & ASM1042)

R1066 1 IU3@ 2 0_0402_5% USB3_RX2_P_L

15 USB3_RX2_P USB3_RX2_N_L
R1067 1 IU3@ 2 0_0402_5%
15 USB3_RX2_N
R1068 1 USB30@2 0_0402_5% R1069 1 IU3@ 2 0_0402_5% USB20_N0_R
36 U3RXDP_B 15 USB20_N0
R1070 1 USB30@2 0_0402_5% R1071 1 IU3@ 2 0_0402_5% USB20_P0_R
36 U3RXDN_B 15 USB20_P0

36 U2DN_A R1072 1 USB30@2 0_0402_5%

R1073 1 IU3@ 2 0_0402_5% USB3_TX2_P_L R1074 1 USB30@2 0_0402_5%
15 USB3_TX2_P 36 U2DP_A
R1075 1 IU3@ 2 0_0402_5% USB3_TX2_N_L
15 USB3_TX2_N
ER02 Add USB3.0 (ASM1042)
R1076 1 USB30@2 0_0402_5% R1077 1 IU3@ 2 0_0402_5% USB20_N1_R
36 U3TXDP_B_C 15 USB20_N1
R1078 1 USB30@2 0_0402_5% R1079 1 IU3@ 2 0_0402_5% USB20_P1_R
36 U3TXDN_B_C 15 USB20_P1

36 U2DN_B R1080 1 USB30@2 0_0402_5%

36 U2DP_B R1081 1 USB30@2 0_0402_5%

D D

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/07/12 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB2.0/USB3.0 CONN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-8221P
Date: Wednesday, October 26, 2011 Sheet 37 of 58
1 2 3 4 5
 A B C D E

Power Button Screw Hole

H11
2.7 H_2P7
ON/OFF switch

1
ER15
@
1 1
+3VALW +3VL H3 H5 H6 H7 H12 H9 H20

3.0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0

1
2

2
R513 1 2 0_0402_5%
9012@ R530 R531
930@ 9012@ @ @ @ @ @ @ @

%RWWRP6LGH 100K_0402_5% 100K_0402_5%

1
SW 1 D30
SMT1-05-A_4P 2 H17 H18 H10
ON/OFF 40
1 3 ON/OFFBTN# 1

2 4
3 51_ON#
51_ON# 43 3.1 H_3P1 H_3P1 H_3P1

1
DAN202UT106_SC70-3
930@
6
5

PW R_ON_LED# @ @ @

H16
SW 5 ON/OFFBTN#

ON/OFFBTN# 2
NTC010-BB1G-C100C
1
3.3 H_3P3

1
4 3 @

3
5
ER28
ER21
PJSOT24CH_SOT23-3

1
2 D 930@ H2 2
EC_ON 2 Q30 D31
40,45 EC_ON
G 2N7002_SOT23-3
3.8

1
2

S H_3P8

1
R532
930@ @
10K_0402_5% @
1

H1 H4

3.8 H_3P8 H_3P8

1
LED6

PW R_ON_LED# @ @
+5VALW 1 2 2 1 PW R_ON_LED# 39,40
R669 300_0402_5%

19-213A-T1D-CP2Q2HY-3T_W HITE H13 H14 H15 H19

4.3 H_4P3 H_4P3 H_4P3 H_4P3

1
@ @ @ @

3
Fan Control Circuit 3

FD1 FD2 FD3 FD4

+5VS @ @ @ @

1
ER12 FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80
+3VS
1

1
C526
2

2.2U_0402_6.3V6M C527
2

R533 U32 1000P_0402_50V7K

10K_0402_5% 2
8 GND EN 1
7 2 JFAN1
GND VIN +5VS_FAN
6 3 1
1

GND VOUT FAN_SPEED 1

5 GND VSET 4 1 2 2 GND 4
FAN_SPEED 3 5
40 FAN_SPEED 3 GND
APL5607KI-TRG_SO8 C528
1 10U_0603_6.3V6M
C529 2 ACES_88231-03041
1000P_0402_50V7K CONN@
2 40 FAN_SET

place as close as EC

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/07/12 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWRBTN/ FAN / Screws
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-8221P
Date: W ednesday, October 26, 2011 Sheet 38 of 58
A B C D E
 KSO10 @ 1
C553
2
100P_0402_50V8J
INT_KBD Conn.
KSO11 @ 1 2
C554 100P_0402_50V8J
KSO12 @ 1 2
C555 100P_0402_50V8J
KSO15 @ 1 2
C556 100P_0402_50V8J KSI[0..7]
KSI[0..7] 12,40
KSI7 @ 1 2
C557 100P_0402_50V8J KSO[0..15]
KSI2 KSO[0..15] 40
@ 1 2
C558 100P_0402_50V8J
KSI3 @ 1 2
KSI4 @
C559
1
100P_0402_50V8J
2
Touch/B Connector
C560 100P_0402_50V8J ER09 CONN@
KSI0 @ 1 2
C561 100P_0402_50V8J ACES_88514-02401-071
KSI5 @ 1 2 26 +5VS
GND2 C564
C562 100P_0402_50V8J 25
KSI6 @ GND1
1 2 1 2
C563 100P_0402_50V8J KSO14 24 TP_CLK LEFT_BTN#
KSI1 @ KSO9 24
1 2 23 23
C565 100P_0402_50V8J KSO3 0.1U_0402_16V4Z TP_DATA RIGHT_BTN#
22 22
KSO2 @ 1 2 KSO1 21 21

2
C566 100P_0402_50V8J KSO13 20 JTP1
20

2
KSO1 @ 1 2 KSI5 19 8 6 D34
C567 100P_0402_50V8J KSI1 19 G2 6 D33 ER35
18 18 7 G1 5 5 TP_CLK 40
KSO0 @ 1 2 KSI7 17 4
KSI6 17 4 LEFT_BTN# TP_DATA 40
C568 100P_0402_50V8J 16 3 1 1
KSO4 @ KSI4 16 3 RIGHT_BTN# @ @
1 2 15 2

1
15 2

100P_0402_50V8J
C570

100P_0402_50V8J
C571
C569 100P_0402_50V8J KSI2 14 1

1
KSO3 @ KSI0 14 1 L30ESDL5V0C3-2 C/A SOT-23
1 2 13 13
C572 100P_0402_50V8J KSI3 12 ACES_51524-0060N-001 2 2 L30ESDL5V0C3-2 C/A SOT-23
KSO5 @ KSO12 12 CONN@
1 2 11
C573 100P_0402_50V8J KSO10 11
10
KSO14 @ KSO11 10
1 2 9
9
C574 100P_0402_50V8J KSO6 8
KSO6 @ KSO8 8 SW3 SW4
1 2 7
C575 100P_0402_50V8J KSO4 7 NTC010-BB1G-C100C NTC010-BB1G-C100C
6
KSO7 @ KSO2 6 LEFT_BTN# RIGHT_BTN#
1 2 5 2 1 2 1
C576 100P_0402_50V8J KSO5 5
4
KSO13 @ KSO7 4
1 2 3
3 4 3 4 3
C577 100P_0402_50V8J KSO0 2
KSO8 @ KSO15 2
1 2 1

5
C578 100P_0402_50V8J 1 ER28
KSO9 @ 1 2 JKB1
C579 100P_0402_50V8J

+5VALW

LED
2

D35
R681 @
10K_0402_5% PCH_SATALED# 2
1
LED2 Green PWR_ON_LED# 3
1

+3VALW 1 2 1 2 PWR_ON_LED# 38,40

R579 200_0402_5%3 YSDA0502C 3P C/A SOT-23
G YG
HT-121UYG_YELLOW-GREEN
BATT_CHG_LOW_LED#
D36
@ Lid Switch
Green 2
1
LED1 BATT_CHG_LED# 3 (Hall Effect Switch)
+3VS 1 2 1 2 +3VALW
PCH_SATALED# 12 YSDA0502C 3P C/A SOT-23
R577 200_0402_5% 3 YG
G D37
@
HT-121UYG_YELLOW-GREEN WL_BT_LED# 2
1
HT-210UD-UYG_AMB-GREEN CAPS_LED# 3

1
Green 2
2 2 1 BATT_CHG_LED# 40 C582 R578
YSDA0502C 3P C/A SOT-23

2
UYG

100_0402_5% R581 0.1U_0402_16V4Z U36 47K_0402_5%

1

VDD
+3VALW 1

2
UD
3 2 1 BATT_CHG_LOW_LED# 40
300_0402_5% R580 3 LID_SW_IN# 40
VOUT
LED3
Amber
1

GND
C583
ER27 LED5 10P_0402_50V8J
Green

1
1 2 1 2 APX9131AAI-TRG_SOT23-3 ER29 2 @
+3VS WL_BT_LED# 40
R582 200_0402_5% 3 YG
G
HT-121UYG_YELLOW-GREEN

BT/WLAN LED ESD

LED8 Green
+3VS 1 2 1 2 CAPS_LED# 40
R671 200_0402_5% 3 YG
G
HT-121UYG_YELLOW-GREEN
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/07/12 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
KB/EC ROM/TP/FUN/LED
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-8221P
Date: Wednesday, October 26, 2011 Sheet 39 of 58
 5 4 3 2 1

QCL40 x8 14" - N13M-GE1_Gb1B-64

+3VALW L28
FBMA-L11-160808-800LMT_0603 KSI[0..7]
1 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z +3VALW_EC 1 2 +EC_VCCA
KSI[0..7] 12,39 ID BRD ID Ra Rb Vab Board ID
R534 KSO[0..15] +3VALW
1 1 1 1 2 2 KSO[0..15] 39

2
0_0805_5% C530 C531 C532 C533 C534 C535 1
R535 0.1U_0402_16V4Z 100K 0 0V

2
1000P_0402_50V7K 0_0402_5% C536
2 2 2 2 1 1 930@ ECAGND R536
0.1U_0402_16V4Z 0.1U_0402_16V4Z 1000P_0402_50V7K +3VLP_EC 2 R537 +3VL ER15 100K_0402_1%
2 1 Ra

1
0_0402_5% 9012@

1
D AD_BID0 D

111
125

1
R538

22
33
96

67
U33 1

9
C537
0_0402_5%
Rb

EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC

EC_VDD/VCC

EC_VDD/AVCC
EC_VDD0
2

2
+3VALW 0.1U_0402_16V4Z
GATEA20 1 21 USBSW_EN# USBSW_EN# 37
16 GATEA20 KB_RST# GATEA20/GPIO00 GPIO0F VGA_PWROK
16 KB_RST# 2 KBRST#/GPIO01 BEEP#/GPIO10 23 VGA_PWROK 29,54
SERIRQ 3 26 DGPU_PWROK USBSW_EN# 1 2
12 SERIRQ SERIRQ GPIO12 DGPU_PWROK 16
LPC_FRAME# 4 27 DS_WAKE# ER23 10K_0402_5% R744
12,41 LPC_FRAME# LPC_FRAME# ACOFF/GPIO13 DS_WAKE# 16
C539 LPC_AD3 5 USBAI_PEN# 1 2
12,41 LPC_AD3 LPC_AD3
@ 22P_0402_50V8J LPC_AD2 7 PWM Output 10K_0402_5% R743 Co-lay KB930/KB9012 PECI
12,41 LPC_AD2 LPC_AD2
2 1 R539 2 1 @ 33_0402_5% 12,41 LPC_AD1 8 63 BATT_TEMP
LPC_AD1 LPC_AD1 BATT_TEMP/GPIO38 BATT_TEMPA 43
LPC_AD0 10 LPC & MISC 64 Stuff
12,41 LPC_AD0 LPC_AD0 GPIO39
65 ADP_I 2 1 ECAGND
ADP_I/GPIO3A ADP_I 43,44
12 AD Input 66 AD_BID0 C538 100P_0402_50V8J KB930 R559
15 CLK_PCI_LPC CLK_PCI_EC GPIO3B
5,15,32,36,41 PLT_RST# 13 PCIRST#/GPIO05 GPIO42 75
+3VALW R540 2 1 47K_0402_5% EC_RST# 37 76 DRAMRST_CNTRL_PCH 6,9,13 KB9012 R571
EC_SCI# EC_RST# IMON/GPIO43
16 EC_SCI# 20 EC_SCII#/GPIO0E
C540 2 1 0.1U_0402_16V4Z PM_CLKRUN# 38 +5VS
14 PM_CLKRUNEC# GPIO1D
68 USBAI_PEN#
DAC_BRIG/GPIO3C USBAI_PEN# 37 C541
70 FAN_SET ER23
EN_DFAN1/GPIO3D FAN_SET 38
DA Output 71 PCH_DPWROK TP_CLK 2 1 SA_PGOOD 1 2 0.1U_0402_16V4Z
IREF/GPIO3E PCH_DPWROK 14
KSI0 55 72 4.7K_0402_5% R541
+3VALW KSI0/GPIO30 CHGVADJ/GPIO3F EC_DRAMRST_CNTRL_PCH 6
KSI1 56 TP_DATA 2 1
KSI2 KSI1/GPIO31 4.7K_0402_5% R542
57 KSI2/GPIO32
1 2 EC_SMB_CK1_R KSI3 58 KSI3/GPIO33 EC_MUTE#/GPIO4A 83 EC_MUTE_R R544 2 1 0_0402_5% EC_MUTE#
EC_MUTE# 33
C R543 2.2K_0402_5% KSI4 59 84 USBAI_EN EC_MUTE# 1 2 C
KSI4/GPIO34 USB_EN#/GPIO4B USBAI_EN 37 ER15
1 2 EC_SMB_DA1_R KSI5 60 KSI5/GPIO35 CAP_INT#/GPIO4C 85 BT_ON 41
R546 2.2K_0402_5% KSI6 61 PS2 Interface 86 EAPD 1 @ 2 +3VL R545 10K_0402_5%
KSI6/GPIO36 EAPD/GPIO4D EAPD 33 +3VALW_EC
1 2 FLASH_EN KSI7 62 KSI7/GPIO37 TP_CLK/GPIO4E 87 TP_CLK
TP_CLK 39
R547 100K_0402_5%
R548 @ 10K_0402_5% KSO0 39 88 TP_DATA
KSO0/GPIO20 TP_DATA/GPIO4F TP_DATA 39
KSO1 40 930@ C542 100P_0402_50V8J
KSO2 KSO1/GPIO21
41 KSO2/GPIO22 1 2 200K_0402_5% ER18 ACIN 2 1
KSO3 42 97 CPU1.5V_S3_GATE R549
+3VS KSO3/GPIO23 CPU1.5V_S3_GATE/GPXIOA00 CPU1.5V_S3_GATE 9
KSO4 43 98 EN_WOL D32 @
KSO4/GPIO24 WOL_EN/GPXIOA01 EN_WOL 32
KSO5 HDA_SDO ACIN_D
KSO6
44 KSO5/GPIO25 Int. K/B ME_EN/GPXIOA02 99
R550 2
HDA_SDO 12 2 1 ACIN 14,44
45 KSO6/GPIO26 Matrix VCIN0_PH/GPXIOD00 109 1 NTC_V 43
KSO7 46 SPI Device Interface 0_0402_5% 9012@ RB751V-40_SOD323-2
EC_SCI# KSO8 KSO7/GPIO27
1 2 47 KSO8/GPIO28
R551 10K_0402_5% KSO9 48 119 FRD# 1 2
KSO10 KSO9/GPIO29 SPIDI/GPIO5B R553 FWR#
49 KSO10/GPIO2A SPIDO/GPIO5C 120 1 930@ 2 33_0402_5% R752 0_0402_5%
ER03 KSO11 50 SPI Flash ROM 126 R555 1 930@ 2 33_0402_5% SPI_CLK
KSO12 KSO11/GPIO2B SPICLK/GPIO58 R557
51 KSO12/GPIO2C SPICS#/GPIO5A 128 1 930@ 2 33_0402_5% FSEL# @ 1 2 EC_SPI_WP
KSO13 52 ER24 ER32 C543 100P_0402_50V8J
VGA_BUF# KSO14 KSO13/GPIO2D
1 2 53 KSO14/GPIO2E
R677 10K_0402_5% KSO15 54 73 R558 1 2 0_0402_5% PCH_ENBKL
KSO15/GPIO2F ENBKL/GPIO40 PCH_ENBKL 14
@ 81 74 EC_SPI_WP
ER31 KSO16/GPIO48 PECI_KB930/GPIO41 EC_SPI_WP 12
82 89 @ T37 PAD Reserve for EMI please close to U4
KSO17/GPIO49 FSTCHG/GPIO50 BATT_CHG_LED#
BATT_CHG_LED#/GPIO52 90 BATT_CHG_LED# 39
91 CAPS_LED# ER23 C544
CAPS_LED#/GPIO53 CAPS_LED# 39
EC_SMB_CK1 1 R560 2 0_0402_5% EC_SMB_CK1_R 77 GPIO 92 SUSACK# R559 1 2 43_0402_1% 2 1 SPI_CLK
43,44 EC_SMB_CK1 EC_SMB_CK1/GPIO44 PWR_LED#/GPIO54 SUSACK# 14 H_PECI 5
EC_SMB_DA1 1 R561 2 0_0402_5% EC_SMB_DA1_R 78 93 BATT_CHG_LOW_LED# 930@ @
43,44 EC_SMB_DA1 EC_SMB_DA1/GPIO45 BATT_LOW_LED#/GPIO55 BATT_CHG_LOW_LED# 39
13,20 PCH_SMLCLK 1 R562 2 0_0402_5% EC_SMB_CK2 79 SM
EC_SMB_CK2/GPIO46 Bus SYSON/GPIO56 95 SYSON
SYSON 42,49
22P_0402_50V8J
13,20 PCH_SMLDATA 1 R563 2 0_0402_5% EC_SMB_DA2 80 EC_SMB_DA2/GPIO47 VR_ON/GPIO57 121 VR_ON
VR_ON 51
127 PM_SLP_S4# EMI
B PM_SLP_S4#/GPIO59 PM_SLP_S4# 14 B

ER10 Del Y5 , C545, C546

14 PM_SLP_S3# 1 R564 2 0_0402_5% PM_SLP_S3#_R 6 PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 100 PCH_RSMRST#
PCH_RSMRST# 14 C547
14 PM_SLP_S5# 1 R565 2 0_0402_5% PM_SLP_S5#_R 14 PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXIOA04 101 EC_LID_OUT#
EC_LID_OUT# 16
R567
EC_SMI# 15 102 0_0402_5% 2 R566 1 2 1 1 2SPI_CLK
16 EC_SMI# EC_SMI#/GPIO08 PROCHOT_IN/GPXIOA05 Turbo_V 43
PCH_PWR_EN 16 103 9012@ @ 33_0402_5% @
36,42 PCH_PWR_EN GPIO0A H_PROCHOT#_EC/GPXIOA06 PROCHOT 43
FLASH_EN 17 104 9012@ 2 R568 10_0402_5% 22P_0402_50V8J
12 FLASH_EN GPIO0B VCOUT0_PH/GPXIOA07 MAINPWON 43,45
ER18 AC_PRESENT 18 GPO 105 BKOFF# Reserve for EMI please close to U6
14 AC_PRESENT GPIO0C BKOFF#/GPXIOA08 BKOFF# 30
VGA_BUF# 19 GPIO 106 PBTN_OUT#
20 VGA_BUF# GPIO0D PBTN_OUT#/GPXIOA09 PBTN_OUT# 5,14
EC_INV_PWM 25 107 R569 1 930@ 2 PCH_PWROK
30 EC_INV_PWM EC_INVT_PWM/GPIO11 PCH_APWROK/GPXIOA10 WL_BT_LED# 39
FAN_SPEED 28 108 SA_PGOOD 0_0402_5%
38 FAN_SPEED FAN_SPEED1/GPIO14 SA_PGOOD/GPXIOA11 SA_PGOOD 50
ER23 SUSWARN# 29
14 SUSWARN# E51TXD_P80DATA EC_PME#/GPIO15
41 E51TXD_P80DATA 30 EC_TX/GPIO16
VR_HOT# 9012@ E51RXD_P80CLK 31 110 ACIN_D PCH_PWROK 1 2
51 VR_HOT# 41 E51RXD_P80CLK EC_RX/GPIO17 AC_IN/GPXIOD01
14 PCH_PWROK 1 R570 2 32 PCH_PWROK/GPIO18 EC_ON/GPXIOD02 112 EC_ON
EC_ON 38,45
R554 10K_0402_5%
0_0402_5% PWR_ON_LED# 34 114 ON/OFF
38,39 PWR_ON_LED# SUSP_LED#/GPIO19 ON/OFF/GPXIOD03 ON/OFF 38
63,520 .%
+3VS +3VALW
0.1U_0402_16V4Z~D

36 GPI 115 LID_SW_IN#

NUM_LED#/GPIO1A LID_SW#/GPXIOD04 LID_SW_IN# 39
R572

116 SUSP#
SUSP#/GPXIOD05 SUSP# 42,46,48,49 20mils
1 @ GPXIOD06 117 WL_OFF# 41
1

C548

118 R571 1 2 H_PECI 1

PECI_KB9012/GPXIOD07
AGND/AGND
0_0402_5%

122 9012@ 43_0402_1% C549

XCLKI/GPIO5D +V18R 0.1U_0402_16V4Z
GND/GND
GND/GND
GND/GND
GND/GND

14 SUSCLK_R 123 XCLKO/GPIO5E V18R 124

2 930@
1 2
GND0

2 R573 1 100K_0402_5% C550

2

U34 1 2 4.7U_0805_10V4Z U35

P

H_PROCHOT# PROCHOT C551 20P_0402_50V8 KB9012QF-A3_LQFP128_14X14 2 FSEL#

5,43 H_PROCHOT# 4 2 1 8
11
24
35
94
113

69

Y A FRD# CS# VCC

2 930@ SPI_SO
NC

20mil 1 2 SO HOLD# 7
G

L29 0_0402_5% R574 3 6 SPI_CLK

A WP# SCLK A
SN74LVC1G06DCKR_SC70-5
1 R575 ECAGND 2 1 4 5 FWR#
1

100K_0402_5% FBMA-L11-160808-800LMT_0603 GND SI

C552 MX25L1005AMC-12G_SO8
47P_0402_50V8J SA00002C100
1

2 930@

Close to IMVP7 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/07/12 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EC ENE-KB930/Co-lay 9012
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-8221P
Date: Wednesday, October 26, 2011 Sheet 40 of 58
5 4 3 2 1
 A B C D E

+3VS
+1.5VS
WLAN/BT combo R583 2 @ 1 0_1206_5%

1
R584 +3VALW +3VS_WLAN
0_1206_5% U37
+3VS_WLAN +3VS_WLAN AO4478L 1N SO8 80mil

10U_0603_6.3V6M

22U_0805_6.3V6M
8 1

2
+1.5VS_WLAN 7 2
1 1 1 1 1 1 1 6 3 1

1
C591
C584 C585 C586 C587 C588 C589 C590 5
1 0.1U_0402_16V4Z 1
4.7U_0805_10V4Z 0.1U_0402_16V4Z 4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z R585

4
2 2 2 2 2 2 2 2 100_0603_5%

2 3VS_WLAN_CHG
PCIE_WAKE#
14,32,36 PCIE_WAKE#
JMINI1 3VSWLAN_GATE
+VSBP 1 2
R586 1 @ 2 0_0402_5% 1 2 +3VS_WLAN R670 47K_0402_5%
1 2
3 4
PCH_BT_ON R587 1 @ 2 3 4 ER16
5 6 +1.5VS_WLAN
5 6

1
0_0402_5% LPC_FRAME#_R Q60 D ER16 D Q32
13 WLANCLK_REQ# 7 8
7 8 LPC_AD3_R SUSP SUSP
9 10 35,36,42 SUSP 2 1 2 SUSP 35,36,42
9 10 LPC_AD2_R G G
13 CLK_PCIE_WLAN# 11 11 12 12
13 14 LPC_AD1_R S C592 S
13 CLK_PCIE_WLAN

3
13 14 LPC_AD0_R SSM3K7002BFU_SC70-3 0.1U_0603_25V7K SSM3K7002BFU_SC70-3
15 15 16 16
PCI_RST#_R 0_0402_5%1 2
17 17 18 18 2 R588 PCH_WAN_RADIO_OFF# 15
CLK_LPC_DEBUG1_R 19 20 0_0402_5%1 2@ R589 WL_OFF#
19 20 WL_OFF# 40
21 22 PLT_RST#
21 22 PLT_RST# 5,15,32,36,40
13 PCIE_PRX_WLANTX_N2 23 24 R590 1 2 0_0603_5% +3VS_WLAN
23 24 R591 1@
13 PCIE_PRX_WLANTX_P2 25 25 26 26 2 0_0603_5% +3VALW
27 28 0_0402_5%
27 28 MINI1_SMBCLK R592 1 @
29 29 30 30 2 PCH_SMBCLK 10,11,13
31 32 MINI1_SMBDATA 1 @ 2 PCH_SMBDATA 10,11,13
13 PCIE_PTX_WLANRX_N2 31 32
33 34 R593 0_0402_5%
13 PCIE_PTX_WLANRX_P2 33 34
35 35 36 36 USB20_N4 15
37 37 38 38 USB20_P4 15
+3VS_WLAN 39 39 40 40
2 41 42 2
41 42
43 43 44 44
45 45 46 46
47 47 48 48
E51TXD_P80DATA R594 1 2 0_0402_5% 49 50
40 E51TXD_P80DATA 49 50
E51RXD_P80CLK R595 1 2 0_0402_5% 51 52
40 E51RXD_P80CLK 51 52
@
2 R596 1 53 54
GND1 GND2
100K_0402_5% ACES_88913-5204
CONN@
PCH_BT_ON R597 1 2 1K_0402_0.5%
16 PCH_BT_ON
BT_ON R598 1 2@ 1K_0402_0.5%
40 BT_ON 5.2 mm High

Reserve for SW mini-pcie debug card.

Series resistors closed to KBC side.
LPC_FRAME#_R R599 1 2 0_0402_5% LPC_FRAME#
LPC_FRAME# 12,40
LPC_AD3_R R600 1 2 0_0402_5% LPC_AD3
LPC_AD3 12,40
LPC_AD2_R R601 1 2 0_0402_5% LPC_AD2
3 LPC_AD2 12,40 3
LPC_AD1_R R602 1 2 0_0402_5% LPC_AD1
LPC_AD1 12,40
LPC_AD0_R R603 1 2 0_0402_5% LPC_AD0
LPC_AD0 12,40
PCI_RST#_R R604 1 2 0_0402_5% PLT_RST#
CLK_LPC_DEBUG1_R 1 2 CLK_LPC_DEBUG1 CLK_LPC_DEBUG1 15
R605 0_0402_5%

C593
R606
2 1 1 2CLK_LPC_DEBUG1_R
@ 33_0402_5% @
22P_0402_50V8J
Reserve for EMI please close to JMINI1

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/07/12 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
WLAN/ WWAN/ m-SATA
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-8221P
Date: Wednesday, October 26, 2011 Sheet 41 of 58
A B C D E
 A B C D E

+5VALW U38
ER06

SI4178DY-T1-GE3_SO8
+5VS

+1.5V
Q33
+1.5VS

ER13 AO3413L_SOT23-3
8 1

7 2 3 1

D
2
10U_0805_10V4Z

10U_0805_10V4Z

10U_0805_10V4Z

1U_0603_10V6K
6 3 1

2
C594

C595

10U_0603_6.3V6M
5
1 1 1

G
C596

C598

2
R607

C597
R608 R609

2
2 10_0603_5% 100K_0402_5% 470_0603_5%

1
2 2 2

1
D Q34
1 ER16 2 SUSP

1

1
G ER16 ER16 D Q35
+VSBP

1
5VS_GATE R611 Q36 D SUSP
1 2 S 2

3
R610 47K_0402_5% SSM3K7002BFU_SC70-3 SUSP# 2 1 2 G
1 47K_0402_5% 1 G S

3
S SSM3K7002BFU_SC70-3

3
Q37 1
D
ER16 C599
0.1U_0603_25V7K

C600
0.22U_0603_16V4Z SSM3K7002BFU_SC70-3
2 2
SUSP 2
G

S
3

SSM3K7002BFU_SC70-3


+3VALW
R612
+3V_PCH

U39
2 @
0_0805_5%
1

+3VALW
SI4178DY-T1-GE3_SO8
+3VS
+5VALW +5V_PCH Q38

8 1
R613
@
SI4178DY-T1-GE3_SO8
40mil
7 2 1 2 8 1

2
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
6 3 1 1 C602 0_0603_5% 7 2 1

2
10U_0805_10V4Z
C603
5 6 3
1 1

1
C601

1U_0603_10V4Z
C606
R614 5

1
C604

C605

1U_0402_6.3V6K
220_0603_5% C607 R615

4

2 2 2 470_0603_5%
20mil

2
2 2 Q39 10U_0805_10V4Z

1
S

D
ER16 3 1

1
D

0.1U_0402_16V7K~N
C608

20K_0402_5%
R617
Q40
+VSBP

1
2 SUSP AO3419L 1P SOT23-3 1

1
3VS_GATE ER12 D Q41
G 20mil 10mil

G
2 1

2
R616 200K_0402_5% S ER16 2 PCH_PWR_EN#

3
SSM3K7002BFU_SC70-3 +VSBP R618 2 1 200K_0402_5% 3V_GATE G
ER16 1 PCH_PWR_EN# 2 S

3
1

Q42 D ER16 SSM3K7002BFU_SC70-3

1
SUSP 2 C609

1
G 0.1U_0603_25V7K Q43 D C610
2 2
2
S PCH_PWR_EN# 2 0.1U_0603_25V7K
3

2
SSM3K7002BFU_SC70-3 G

3
SSM3K7002BFU_SC70-3

+5VALW +5VALW
+5VALW

1
1
R718
1

100K_0402_5%
R619
R620 100K_0402_5%

2
100K_0402_5% PCH_PWR_EN#

2
SYSON#
2

1
SUSP Q61 D
35,36,41 SUSP

1
D ER16
36,40 PCH_PWR_EN 2
1

D Q44 G
40,49 SYSON 2

1
2 Q45 G 2N7002_SOT23-3 S

3
40,46,48,49 SUSP#
3 G 2N7002_SOT23-3 S SSM3K7002BFU_SC70-3 3

3
1
S R735
3
1

R621 100K_0402_5%
R622 10K_0402_5%

2
10K_0402_5%

2
2

+1.5V_CPU_VDDQ +0.75VS

+1.05VS +1.05VS

1
+1.5V

1
1

@ 1 R624 R623
1

48,50 +V1.05S_VCCP_PWRGOOD 2 10.75VR_EN 0.75VR_EN 49

R626 R627 220_0402_5%~D 22_0603_5%~D
R628

2
R625 470_0402_5% 470_0402_5%

2
100K_0402_5% 470_0402_5%

+1.5V_CPU_VDDQ_CHG
2

+DDR_CHG
+V1.05S_VCCP_D
2

+V1.05S_D
1

Q46 D
SUSP @
+1.5V_D

SSM3K7002BFU_SC70-3

SSM3K7002BFU_SC70-3
G
S ER16
3

SSM3K7002BFU_SC70-3
1

Q47 D ER16 Q50 ER16 Q51

1

1
Q48 D Q49 D SUSP ER16 D D
2
SYSON# 2 ER16 SUSP 2 G 2 2
ER16 9 RUN_ON_CPU1.5VS3#
G G S G G
3

S S SSM3K7002BFU_SC70-3 S S
3

3
SSM3K7002BFU_SC70-3 SSM3K7002BFU_SC70-3

4 @ 4
R629

0_0402_5%
R630
SUSP
0_0402_5%

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/07/12 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC/DC Interface
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-8221P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 26, 2011 Sheet 42 of 58
A B C D E
 A B C D

PL1 For KB930 --> Keep PU1 circuit

DCIN jack P/N:DC301008L00, HCB2012KF-121T50_0805 PH1 under CPU botten side :
(Vth = 0.825V)
need doble confirm P/N with ME 1 2 VIN CPU thermal protection at 93 +-3 degree C
PL2 For KB9012 (Red square) --> Remove PU1 circuit, but keep PR56
HCB2012KF-121T50_0805 Recovery at 56 +-3 degree C
ADPIN 1 2
PH1, PR2, PQ1, PR7,PQ15,PR73,PR56
PJPDC1
4 VL
GND_1
+3VL

1000P_0402_50V7K

1000P_0402_50V7K
V- 1

100P_0402_50V8J

100P_0402_50V8J
5 GND_2

1
40,44 ADP_I

@21.5K_0402_1%
V+ 2

1
PC1

PC2

PC3

PC5

1K_0402_1%

12.1K_0402_1%
6 GND_3

1
1 1

PR3
3

2
V-

PR2

PR56
7 GND_4

1
@SINGA_SDC2003-004111F PC4 +3VS

2
@0.1U_0603_16V7K PU1

2
1 8 NTC_V
VCC TMSNS1

2
OTP_N_002

@100K_0402_1%
2 GND RHYST1 7 2 1

PR5
PR4
3 6 Turbo_V @10K_0402_1%
5,40 H_PROCHOT# OT1 TMSNS2 PR6
4 5 ADP_OCP_2 1 2

100K_0402_1%_NCP15WF104F03RC
OT2 RHYST2

PH1
PQ1

2
D

20K_0402_1%
@G718TM1U_SOT23-8 @29.4K_0402_1%

PR7
2ADP_OCP_1

Turbo_V
OTP_N_003

40

40
NTC_V
G
S @SSM3K7002FU_SC70-3

2
1
PR73
PL3 @0_0402_5%
HCB2012KF-121T50_0805 40 PROCHOT 1 2 2 1 MAINPWON 40,45
1 2
PR9 @0_0402_5%
VMB
PJP2
PL4
1 HCB2012KF-121T50_0805
1
2 2
3
1 2 BATT+
B+
3 1
+VSBP
3

100K_0402_1%
10U_0805_25V6K

0.1U_0603_25V7K
0.22U_0603_25V7K
4 4

1
5 EC_SMCA
5

1
PC8

PC9
PR13
6 EC_SMDA
6
2

1
PC128
2
7 TS_A PC6 PC7 2

7 PR27 1000P_0402_50V7K 0.01U_0402_25V7K

8

2
8 1K_0402_1%
9
@PJSOT24CW_SOT323-3

2
9
GND 10 VL PQ3
1

11 PD1 PR14 TP0610K-T1-E3_SOT23-3

1

GND 22K_0402_1%
@SUYIN_200045GR009G28DZR 1 2 VSB_N_001
+3VL

1VSB_N_003
PR16
100K_0402_1%
2

PJ3
PR18 2 1

1
2 1
0_0402_5% D
+CHGRTC
45 POK 1 2VSB_N_002 2 PQ4 JUMP_43X39
G SSM3K7002FU_SC70-3
PD2

.1U_0402_16V7K
S
RTC Battery

3
1

PC10
2
1
3 PBJ1

2
PR28
100_0402_1% @PJSOT24CW _SOT323-3
1 2 EC_SMB_CK1 40,44 - +
1 2 EC_SMB_DA1 40,44 2 - + 1
PR31
100_0402_1%
PR29 +RTCBATT
1 2 +3VALW
100K_0402_5% @LOTES_AAA-BAT-054-K01
PR30
3 1 2 BATT_TEMPA 40 3

1K_0402_1%

VIN
2

PD3
RLS4148_LL34-2
VS_N_001
1

BATT+ 2 1
1

PD4
LL4148_LL34-2 PQ5 PR19 PR20
TP0610K-T1-E3_SOT23-3 68_1206_5% 68_1206_5%
2

N1 3 1
VS
1

PC12
PR23 PC11 0.1U_0603_25V7K
100K_0402_1% 0.22U_0603_25V7K
2

2
2

4 4

1 2 VS_N_002
38 51_ON#
PR24
22K_0402_1%

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/23 2010/01/23 Title
For KB9012 --> Remove all 51_ON# circuit Deciphered Date
PWR-DCIN / BATT CONN / OTP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS PBL22 LA-7391P M/B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: W ednesday, October 26, 2011 Sheet 43 of 58
A B C D
 A B C D

for reverse input protection

1
PQ106 D
2
G SI1304BDL-T1-E3_SC70-3
S

3
PR103 PR104
1 2 1 2

1
1M_0402_5% 3M_0402_5% 1

VIN P1 P2 B+
S TR MDS2659URH S TR MDS2659URH 0.01_2512_1% S TR MDS2659URH
PQ101 PQ102 PL102 PR101 PQ103
8 1 1 8 1 2 1 4 8 1

0.1U_0402_25V6
10U_0805_25V6K
7 2 2 7 7 2

10U_0805_25V6K

@0.1U_0402_25V6
10U_0805_25V6K

10U_0805_25V6K
@ 1UH_10.3A_20%
2200P_0402_50V7K

6 3 3 6 2 3 6 3

0.1U_0402_25V6

1
10U_0805_25V6K

10U_0805_25V6K
0_0402_5%
5 5 5 @

0.01U_0402_50V7K
PC111

PC104

PC101
1

0_0402_5%
PC130

PC105

PC103
PR105

PC102
1

1
VIN

PC129
PC110

PR106
4

PC114
2

1
PC112

2
1

2
0.1U_0402_25V6

2
PD101
2

BQ24725_ACDRV_1 BAS40CW_SOT323-3

1
BQ24725_BATDRV 1 2 BQ24725_BATDRV_1

PC115
0.047U_0402_25V7K PR107
4.12K_0603_1%

4.12K_0603_1%

1 1

10_1206_1%
1 2 4.12K_0603_1%
PC116

PR110
1

PC113 1 2
PR108

PR109

2.2_0603_5%
0.1U_0402_25V6

5
PR111
PQ104

0.1U_0603_25V7K

2
BQ24725_VCC

1
SIS412DN
2

PD102

1
RB751V-40_SOD323-2

PC117

BQ24725_ACP

BQ24725_BST 2

BQ24725_REGN
1 2DH_CHG1
4
2
PC118 PR125 2

BQ24725_LX
2

2
1 2 DH_CHG BATT+
0_0402_5%

DH_CHG
PL101
1U_0603_25V6K PC119 4.7UH_ETQP3W4R7WFN_5.5A_20% PR102

3
2
1
0.02_1206_1%

BQ24725_ACN
1 2
BQ24725_LX 1 2 CHG 1 4
1U_0603_25V6K

5
6
7
8

4.7_1206_5%
20

19

18

17

16
2 3

CSOP1
PU101

2200P_0402_50V7K

0.01U_0402_50V7K
CSON1
1
PQ105

VCC

PHASE

HIDRV

BTST

REGN

PR114

@10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K
21 AO4468L_SO8

0.1U_0402_25V6

0.1U_0402_25V6
PAD

PC108

PC109
PC120

PC106

PC107
1

1
1 15 DL_CHG 4
ACN LODRV

PC121

PC122
2

2
2 14

680P_0402_50V7K
ACP GND PR115

3
2
1

2
1
BQ24725RGRR_VQFN20_3P5X3P5 10_0603_1%

PC123
BQ24725_CMSRC 3 13 SRP12 CSOP1
CMSRC SRP

1
PR116

2
6.8_0603_5%
BQ24725_ACDRV 4 12 SRN 1 2 CSON1

2
ACDRV SRN

0.1U_0603_16V7K
PR117

PC124
2BQ24725_ACOK5 BQ24725_BATDRV
For KB930 --> Keep PR117 +3VALW 1 ACOK BATDRV 11

ACDET
PR126 @10K_0402_1% Remember to change PC124 from SE000006S80

IOUT
For KB9012 (Red square) --> Remove PR117

SDA

ILIM
SCL
+3VLP 1 2 to SE025104K80 (2011-02-22)
Keep PR126 10K_0402_1% PR118 Pre_chg +3VALW
6

10
1 2
14,40 ACIN PR119
1

3 3

10K_0402_1% BQ24725_ILIM 1 2

0.01U_0402_25V7K
PD8

100K_0402_1%
PR120 @RB751V-40_SOD323-2 210K_0402_1%

1
VIN

PC125
PR121

1
BQ24725_ACDET
2

1 2
154K_0402_1%

2
2
255K_0402_1%
1

PR122

Vin Dectector
Min. Typ Max.
2

100_0402_5%

H-->L 17.23V
0.1U_0402_25V6

2
66.5K_0402_1%

L--> H 17.63V EC_SMB_CK1 40,43

1

PR124
PC126

PR123

ILIM and external DPM

2

EC_SMB_DA1 40,43
3.97A PC127
2

2 1 ADP_I 40,43 Please locate the RC

Near EC chip
100P_0402_50V8J 2011-02-22

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/23 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-CHARGER
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS PBL22 LA-7391P M/B 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: W ednesday, October 26, 2011 Sheet 44 of 58
A B C D
 A B C D E

2VREF_51125

1
PC308
1U_0603_16V6K

2
1 1

PR301 PR305
13.7K_0402_1% 30.9K_0402_1%
1 2 1 2

PR302 PR306
B+ B++
20K_0402_1% 20K_0402_1%
FB_3V FB_5V 1 B++
PL301 1 2 2
HCB2012KF-121T50_0805

1 2 +3VLP

ENTRIP2

ENTRIP1
PR303 PR307
2200P_0402_50V7K

2200P_0402_50V7K

10U_0805_25V6K
0.1U_0402_25V6

0.1U_0402_25V6
133K_0402_1% 174K_0402_1%
1

1
@680P_0603_50V7K

4.7U_0805_25V6-K

1 2 1 2
1

1
PC309

PC310

PC311

PC312
PC322

PC304

PC306
2

2
6

1
PU301
2

5
ENTRIP2

FB2

TONSEL

FB1

ENTRIP1
REF
1
PC313 PQ305
PQ303 4 10U_0805_6.3V6M 25 P PAD SIS412DN-T1-GE3_POWERPAK8-5

2
SIS412DN-T1-GE3_POWERPAK8-5

2
0_0402_5%
7 VO2 VO1 24 4

1
2
3

0_0402_5%
PR318
PC314 8 23 PR309 PC315
VREG3 PGOOD

PR323
0.1U_0402_10V7K PR308 2.2_0402_5% 0.1U_0402_10V7K
1 2 BST1_3V 1 2 BST_3V 9 22 BST_5V 1 2 BST1_5V 1 2

3
2
1
2 2.2_0402_5% BOOT2 BOOT1 2
PL303 UG_3V 10 21 UG_5V PL305

1
4.7UH_FMJ-0630T-4R7 HF_5.5A_20% UGATE2 UGATE1 2.2UH_ETQP3W2R2WFN_8.5A_20%
2 1 LX_3V 11 20 LX_5V 1 2 +5VALWP
+3VALWP PHASE2 PHASE1
1

8
7
6
5

1
@4.7_1206_5%

@4.7_1206_5%
LG_3V 12 19 LG_5V
LGATE2 LGATE1
PR312

PQ304

SKIPSEL

PR313

150U_D2_6.3VY_R18M
VREG5
PR314 1

GND

VIN

NC
150U_D2_6.3VY_R18M

499K_0402_1%

EN
2

PC305
4 1 2 4 +
1 B++ POK 43
1 SNUB_3V

SNUB_5V
13

14

15

16

17

18
PC303

+ RT8205LZQW(2)_WQFN24_4X4
EN0 2
AO4468L_SO8 PQ306
1
2
3

3
2
1
2
@680P_0402_50V7K

@680P_0402_50V7K
VL

1
FDMC7692S_MLP8-5

1
PC316

PC317
PR315
95.3K_0402_1% PC320
2

1U_0603_10V6K

2
1
PC318
4.7U_0805_10V6K

2
1
B++
PC319

2
0.1U_0603_25V7K
ENTRIP1

ENTRIP2

2VREF_51125

3 3
6

D D
PQ307A 2N_3_5V_001 5 PQ307B
SSM6N7002FU_US6 G G SSM6N7002FU_US6

S S +3VLP +3VL
1

PJP302
2 1

PAD-OPEN 2x2m
PR322
2.2K_0402_5%
1 2 PR317
38,40 EC_ON PR321
1 2
VL VL
100K_0402_5%
1

1 2 PJP305 PJP301
40,43 MAINPWON 0_0402_5% PQ308 1 2 (5A,200mils ,Via NO.= 10) 2 1
+5VALWP +5VALW
DRC5115E0L_SOD323-3
PAD-OPEN 2x2m
N_3_5V_002 2 PAD-OPEN 4x4m
1 2
VS PJP303
@42.2K_0402_1%

4.7U_0805_25V6-K

PR319
+3VALWP
1 2 +3VALW (4A,120mils ,Via NO.= 8)
1

@100K_0402_1%
1
PR320

PC321

PAD-OPEN 4x4m
2
2

4 4

For KB930 --> Keep PR319, Remove PR322

For KB9012 (Red square) --> Remove PR319
Keep PR322 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-3.3VALWP/5VALWP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA-8221P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 26, 2011 Sheet 45 of 58
A B C D E
 A B C D

1 1

PL402
PU401 PL401

4
+5VALW HCB1608KF-121T30_0603 1UH_VMPI0703AR-1R0M-Z01_11A_20%
1 2 VIN_1.8VSP 10 2 LX_1.8VSP 1 2

PG
PVIN LX +1.8VSP

68P_0402_50V8J
9 PVIN LX 3

1
4.7_1206_5%
1

1
PC404
PC403 8 SVIN

PR403
22U_0805_6.3VAM PR401
6 20K_0402_1%

2
FB

22U_0805_6.3VAM

22U_0805_6.3VAM
5

2
EN

1
NC

NC
TP

PC401

PC402
FB_1.8VSP
40,42,48,49 SUSP#

11

2
SNUB_1.8VSP
2
1 2 EN_1.8VSP 2

1
1
PR404 0_0402_5%

@0.1U_0402_10V7K
PC405
SY8033BDBC_DFN10_3X3 PR402

1
PR405 10K_0402_1%
@47K_0402_5%

2
2

680P_0603_50V7K
PC406
2
PJP401

+1.8VSP 1 2 +1.8VS (3A,120mils ,Via NO.= 6)

PAD-OPEN 4x4m

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/23 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-1.8VSP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS PBL22 LA-7391P M/B 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: W ednesday, October 26, 2011 Sheet 46 of 58
A B C D
 5 4 3 2 1

D D

C C

(8.5A,360mils ,Via NO.= 17)

PJP606,PJP607,PU605

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/12/31 Title
2010/07/20 Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-V1.05S_VCCP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom PBL22 LA-7391P M/B 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 26, 2011 Sheet 47 of 58
5 4 3 2 1
 5 4 3 2 1

PL702
HCB1608KF-121T30_0603
+1.05VSP_B+ 2 1
B+
+3VS

@680P_0603_50V7K
2200P_0402_50V7K

10U_0805_25V6K

10U_0805_25V6K

1
PC711
0.1U_0402_25V6
D D

1
PC705
PC704

PC702

PC703

2
2

2
5
PR712
100K_0402_1% PQ701

1
PC706
0.22U_0402_10V6K 4
PR703
1 2 BST1_+1.05VSP 1 2
4.7_0402_5%
PU701
42,50 +V1.05S_VCCP_PWRGOOD 1 10 BST_+1.05VSP S TR AON7518 1N DFN

3
2
1
PGOOD VBST
PR704 PR711
1 2 TRIP_+1.05VSP 2 9 UG_+1.05VSP 1 2 UG_+1.05VSP1 PL701
TRIP DRVH S COIL .47U 20% FDVE0630-H-R47M=P3 17.7A
80.6K_0402_1% 0_0402_5%
EN_+1.05VSP 3 EN SW 8 SW _+1.05VSP 1 2 +1.05VS

5
PR705 FB_+1.05VSP 4 7
0_0402_5% VFB V5IN
+5VALW PQ702

330U_D2_2.5VY_R15M
1
1 2 RF_+1.05VSP 5 6 LG_+1.05VSP 1
40,42,46,49 SUSP# TST DRVL

1
PR706 +

PC701
TP 11
1

PC707 4 4.7_1206_5%
1

TPS51212DSCR_SON10_3X3 1U_0603_10V6K

SNUB_+1.05VSP2
PC708 PR707 2
@0.1U_0402_16V7K 470K_0402_1%
2

3
2
1
C MDU1512 C

1
PR710

1
PC710 PC709 0.1U 25V 0402
@1000P_0402_50V7K
PR709

2
680P_0402_50V7K
1 2 +1.05VSP1 1 2 +1.05VS

2
@1.2K_0402_1%
PR708
PR701 4.99K_0402_1% 100_0402_5%
2 1 VCCIO_SENSE1 2 1 VCCIO_SENSE 8

PU601,PR708
2

PR702
10K_0402_1%
1

B
(12A,480mils ,Via NO.= 24) B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/12/31 Title
2010/07/20 Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-V1.05SP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom PBL22 LA-7391P M/B 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 26, 2011 Sheet 48 of 58
5 4 3 2 1
 5 4 3 2 1

0.75Volt +/- 5%
TDC 0.525A
Peak Current 0.75A
PL502
HCB1608KF-121T30_0603 OCP Current 0.9A
D B+ 1 2 1.5V_B+ D
PR504
BST_1.5V 1 2 BOOT_1.5V +1.5V
2.2_0402_5%
@680P_0603_50V7K

2200P_0402_50V7K

10U_0805_25V6K

@4.7U_0805_25V6-K
PR511
DH_1.5V_1 1 2 DH_1.5V +0.75VSP

0.1U_0402_25V6

0.22U_0402_10V6K
1

1
PC516

PC505
0_0402_5%

2
PC504

PC502

PC503

10U_0805_6.3V6K

10U_0805_6.3V6K

@10U_0805_6.3V6K
SW _1.5V

PC506
2

1
5

1
DL_1.5V

PC507

PC508

PC517
16

17

18

19

20
PQ501 PU501

UGATE

VLDOIN
PHASE

BOOT

VTT

2
PAD 21

4 15 LGATE VTTGND 1

PL501 PR505 14 2
1UH_VMPI0703AR-1R0M-Z01_11A_20% SIS412DN-T1-GE3_POW ERPAK8-5 20K_0402_1% PGND VTTSNS

1
2
3
1 2 CS_1.5V
2 1 13 3
+1.5VP PC509 CS RT8207MZQW _W QFN20_3X3 GND

5
1U_0603_10V6K
PQ502 PR507 1 2 12 4 VTTREF_1.5V
330U_D2_2.5VY_R15M

VDDP VTTREF
1

1 5.1_0603_5%

+ PR506 VDD_1.5V +1.5VP

PC501

C 1 2 11 5 C
VDD VDDQ

PGOOD
@4.7_1206_5% 4
+5VALW

1
TON
2

2 PC510 PC511

FB
S5

S3
1U_0603_10V6K 0.033U_0402_16V7K
SNUB_+1.5VP

2
1
2
3

10

6
FDMC7692S_MLP8-5 +5VALW
PR501
10.2K_0402_1%
+1.5VP
1

PC512 FB_1.5V 2 1

TON_1.5V
@680P_0402_50V7K
2

1
Mode Level +0.75VSP VTTREF_1.5V PR502
PR503 10K_0402_1% PC513
S5 L off off 887K_0402_1% .1U_0402_16V7K

2
S3 L off on PR508 1.5V_B+ 1 2

1
0_0402_5%
S0 H on on EN_1.5V
40,42 SYSON 1 2

EN_0.75VSP
Note: S3 - sleep ; S5 - power off

1
PR509
2 1
PC514 42 0.75VR_EN
2
B @0.1U_0402_10V7K B
@0_0402_5%

PR510
2 1
40,42,46,48 SUSP#
PJP501
0_0402_5%
1 2

1
PAD-OPEN 4x4m
PC515

2
PJP502 @0.1U_0402_10V7K
+1.5VP 1 2 +1.5V (9A,360mils ,Via NO.= 18)
PAD-OPEN 4x4m

PJP503

+0.75VSP 1 2 +0.75VS (2A,80mils ,Via NO.= 4)

PAD-OPEN 3x3m

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/12/31 Title
2010/07/20 Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-1.5VP / +0.75VSP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom PBL22 LA-7391P M/B 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 26, 2011 Sheet 49 of 58
5 4 3 2 1
 5 4 3 2 1

The 1k PD on the VCCSA VIDs are empty.

These should be stuffed to ensure that
VCCSA VID is 00 prior to VCCIO stability. VID [0] VID[1] VCCSA Vout
0 0 0.9V
D D
0 1 0.8V
1 0 0.725V
1 1 0.675V
output voltage adjustable network

2
PC805
@680P_0402_50V7K

1
+VCC_SAP
TDC 4.2A
Peak Current 6A
OCP current 7.2A

2
PR801
@4.7_1206_5%
PL803
PU801 PL801

1
HCB1608KF-121T30_0603 SY8037DCC_DFN12_3X3 0.47UH_FDVE0630-H-R47M=P3_17.7A_20%
+5VALW 1 2 +VCCSA_PWR_SRC 12
PVIN LX
1 +VCCSA_PHASE 1 2 +VCCSAP
11 2

22U_0805_6.3V6M
PVIN LX SA_PGOOD 40

22U_0805_6.3VAM

@22U_0805_6.3VAM
2

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
1

1
2200P_0402_50V7K

0.1U_0603_25V7K
PC815 PR804

PC818
10 3

PC819

PC820

2
68P_0402_50V8J SVIN LX 100K_0402_5%

PC817

PC801

PC802

PC803

PC804
C +VCCSAP_FB 2 1 9 4 2 1 C
+3VS

2
1 FB PG

1
8 5 +VCCSA_EN 1 2
VOUT EN

GND

@0.1U_0402_10V7K
7 6 0_0402_5%
VID1 VID0

1
PR806
42,48 +V1.05S_VCCP_PWRGOOD

2
PR812

PC809
1K_0402_5%

1K_0402_5%
13
100_0402_5%

PR802

PR805

2
2 1

1
PR811
0_0402_5%
2 1 +VCCSA_SENSE 9
H_VCCSA_VID0 9

H_VCCSA_VID1 9

PJP801
B +VCCSAP 1 2 +VCCSA B

PAD-OPEN 4x4m

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/12/31 Title
2010/07/20 Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-VCC_SAP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C PBL22 LA-7391P M/B 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 26, 2011 Sheet 50 of 58
5 4 3 2 1
 5 4 3 2 1

PR201 PC214 PC253

1 2 FBA3 1 2 1 2

1200P_0402_50V7K

560P_0402_50V7K
D PUT CLOSE D

75K_0402_1%
10_0402_1% 680P_0402_50V7K .1U_0402_16V7K
TO GT

1
PR203 PR204 1 PR202 2

PC261

PC250

PR205
TRBSTA# 1 2 FBA1 1 2 Inductor
2P: 24K 24K_0402_1% PH203 PR206 PC235

1
1
1.21K_0402_1% 10.7K_0402_1% 220K_0402_5%_ERTJ0EV224J CSCOMPA 1 2 DROOPA 1 2 CSREFA
PC236 1P: 24.9K

2
PR208 PC240 PC244 2 PR207 1 NTC_PH203 1.65K_0402_1% 1000P_0402_50V7K

2
4700P_0402_25V7K 1 2 FBA2 1 2 1 2
10_0402_1% 165K_0402_1% 2P: 1.65K
560P_0402_50V7K PR210 10P_0402_50V8J PC252 2P: install
1 PR209 2 1 2 COMPA1 1 2 1 PR211 2 SWN2A 1P: 1K
1P: @
1K_0402_1% 5.11K_0402_1% 3300P_0402_25V7K 68K_0603_1% CSREFA
PC255 TSENSEA

2
1 PR212 2 SWN1A 0.047U_0402_16V7K

2P: 21.5K 68K_0603_1% PR213 6.98K_0402_1%

1
CSP1A 1 2
1P: 15.8K SWN1A 52

2
21.5K_0402_1%
CSCOMPA
PC257
9 VCC_AXG_SENSE

2
8.25K_0402_1%
1PR215
1000P_0402_50V7K CSREFA

1
PC237 2P: install PH204

PR216
1000P_0402_50V7K
CSREFA 52

1
PC249 1P: @ 100K_0402_1%_TSM0B104F4251RZ
9 VSS_AXG_SENSE 0.047U_0402_16V7K
PC264

1
CSP2A
CSP1A
1 2 CSP2A 1 2 SWN2A 52

TRBSTA#

DROOPA

CSSUMA
PR218

TSENSEA
COMPA
IMONA
FBA
.1U_0402_16V7K 6.98K_0402_1%

DIFFA

ILIMA
PR220 2P: 36K
1 2
1P: 26.1K PUT CLOSE
36K_0402_1%

61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
+5VS 1 PR221 2 PU201 TO V_GT
C C
2_0603_5% HOT SPOT

VSNA
VSPA
DIFFA

FBA
COMPA
IOUTA
ILIMA
DROOPA
CSCOMPA
CSSUMA
CSREFA
CSP2A
CSP1A
TSNSA
PAD

TRBSTA#
+1.05vs 6132_PWMA 52
PC259
1 2 6132_VCC
1 45 PR222 PC241
2.2U_0603_10V7K VCC PWMA BST3
2 VDDBP BSTA 44 1 2 BST3_1 1 2
+5VS
54.9_0402_1%

PR228 3 43 2.2_0603_5% 0.22U_0402_10V6K

VRDYA HGA HG3 52
1

1
130_0402_1%

1 2VR_ON_CPU 4 42
40 VR_ON EN SWA SW3 52
PR223

PR224

PC269 PC270 0_0402_5% VR_SVID_DAT1 5 41 PC267

SDIO LGA LG3 52
.1U_0402_16V7K .1U_0402_16V7K VR_SVID_ALRT# 6 40 BST2 1 PR226 2 BST2_1 1 2 2Phase: @
2

PR232 PR227 VR_SVID_CLK ALERT# BST2 2.2_0603_5% 0.22U_0402_10V6K

7 39 HG2 52
SCLK HG2 1Phase: install

1
95.3K_0402_1% 1 2 VBOOT 8 38 Option for
SW2 52
1

10K_0402_1% VBOOT NCP6132BMNR2G_QFN60_7X7 SW2 PC245 PR231

8 VR_SVID_DAT 1 2VR_SVID_DAT1 1 2 ROSC_CPU 9
ROSC LG2
37 LG2 52 1 phase GFX
PR266 0_0402_5% CPU_B+ 1 2 VRMP 10 36 6132P_VCCP 1 PR274 2 1 2 @0_0402_5%
8 VR_SVID_ALRT# VRMP PVCC
VR_HOT# 11 35 0_0402_5% 2.2U_0603_10V7K
8 VR_SVID_CLK VRHOT# PGND
0.01U_0402_25V7K

PR230 1K_0402_1% VGATE 12 34 1 PR265 2

LG1 52 +5VS

2
VRDY LG1
1

13 33 0_0402_5% CSP2A
+1.05vs VSN SW1 SW1 52
PC239 14 32 PC238
+3VS VSP HG1 HG1 52
DIFF_CPU 15 31 BST1 1 PR233 2 BST1_1 1 2

CSCOMP
2

DIFF BST1

TRBST#
2.2_0603_5% 0.22U_0402_10V6K

DROOP

CSSUM

DRVEN
CSREF
1

COMP

TSNS
CSP3
CSP2
CSP1

PWM
IOUT
ILIM
2

PC271 PR234

FB
47P_0402_50V8J 75_0402_1% PR235 +5VS
10K_0402_5%
1

16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
3P: 73.2K
2

1 PR236 2
40 VR_HOT#
2

COMP_CPU
2P: 41.2K

1
FB_CPU 73.2K_0402_1% Option for 3Phase: @
TRBST#
5,14 VGATE
PR237 2 phase CPU PR264

DROOP

TSENSE
ILIM_CPU
1 2 VSN 3P: 22p @0_0402_5% 2Phase: install
8 VSSSENSE 6132_PWM 52
1

0_0402_5%
IMON

PC246 2P: 10p

DRVEN 52

2
PR254 1000P_0402_50V7K CSP3 1 PR2392 CSP3
SWN3 52
2

1
1 2 VSP PC254 6.98K_0402_1%
8 VCCSENSE
2
21K_0402_1%

0_0402_5% 1 2 PC265 3P: install

0.047U_0402_16V7K

2
B .1U_0402_16V7K CSREF 2P: @ B
PR259 PC263 CSP1 TSENSE
3P: 330p 1 2 2 1 CSP2
1

CSP3 CSP2 1 PR2462

2P: 1000p SWN2 52

1
1K_0402_1% 22P_0402_50V8J 6.98K_0402_1%
PR250

PC260
PR247 PC262 PR249 PC256 3P: 21K 0.047U_0402_16V7K

2
1 2FB_CPU1 1 2 2 1COMP_CPU1 2 1 CSREF
PR248 PC242 49.9_0402_1% 6.04K_0402_1% 2P: 12.4K

8.25K_0402_1%
1 2FB_CPU3 1 2 680P_0402_50V7K 2200P_0402_50V7K

PR251 1

2
10_0402_1% 3P: 6.04K CSP1 1 PR2582
CSREF 52 SWN1 52
CSCOMP

1
0.033U_0402_25V7K 6.98K_0402_1% PH202
PR263 PR260 2P: 4.32K PC243 PC248
TRBST# 1 2 FB_CPU2 1 2 1000P_0402_50V7K 3P: 1500p 0.047U_0402_16V7K 100K_0402_1%_TSM0B104F4251RZ
1

2
0.033U_0402_16V7

CSREF

1
2P: 1200p
1

8.06K_0402_1% 806_0402_1% 3P: 2200p

PC266
2P: 3300p CSSUM
2

3P: 348 3P: 3.65K PC258

1 2
2P: 1.21K 2P: 9.53K 1 PR261 2 SWN1
23.7K_0402_1%

1500P_0402_50V7K 143K_0603_1% PUT CLOSE

2

.1U_0402_16V7K

TO VCORE
PC247

3P: 23.7K 1 2 PC268 1 PR253 2 SWN2

PR252

220P_0402_50V7K 143K_0603_1% HOT SPOT

1

2P: 24.9K
1 PR262 2NTC_PH201 1 PR255 2 1 PR256 2 SWN3
1

75K_0402_1% 143K_0603_1%
PR257 PC251 165K_0402_1%
CSCOMP 1 2 DROOP 1 2 CSREF 3P: install
PUT CLOSE 2P: @
806_0402_1% 1000P_0402_50V7K 2 1
3P: 806 TO VCORE
Phase 1 PH201 220K_0402_5%_ERTJ0EV224J
2P: 1K
A Inductor A

Security Classification
2009/12/01
Compal Secret Data
2010/12/31 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-CPU_CORE
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom PBL22 LA-7391P M/B 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 26, 2011 Sheet 51 of 58
5 4 3 2 1
 5 4 3 2 1

CPU_B+ PL206 CPU_B+

HCB2012KF-121T50_0805
2 1

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K
B+ CPU_B+

0.1U_0402_25V6

0.1U_0402_25V6
2200P_0402_25V7K

2200P_0402_25V7K
5

5
PL207
HCB2012KF-121T50_0805

1
PC201

PC202

PC280

PC281

PC203

PC204

PC282

PC283
2 1 AXG_B+

S TR AON7518 1N DFN

S TR AON7518 1N DFN
@S TR AON7518 1N DFN

@S TR AON7518 1N DFN
PR214 1 PR219
0_0603_5% 0_0603_5%

@680P_0603_50V7K
2

2
+

PQ201

@ PQ211

PQ203

@ PQ212
2 1 4 4 2 1 4 4
51 HG1 +VCC_CORE PC212
51 HG2
+VCC_CORE

1
100U_25V_M
2

PC213
PL201

3
2
1

3
2
1

3
2
1

3
2
1
D D
0.36UH_VMPI1004AR-R36M-Z03_30A_20% PL202
1 0.36UH_VMPI1004AR-R36M-Z03_30A_20%
51 SW1 1 4 51 SW2 1 4
+

1
2 3 PC211 2 3

5
@100U_25V_M
PR280 2 PR281
4.7_1206_5% 4.7_1206_5%

2
PQ202 PR282 PQ204 PR283
4 V1N_CPU 2 1 4 V2N_CPU 2 1
51 LG1 CSREF 51 51 LG2 CSREF 51

1SNUB_CPU1

SNUB_CPU2
S TR FDMS0308AS 1N POWER56-8 S TR FDMS0308AS 1N POWER56-8
10_0402_1% 10_0402_1%

SWN1 51 SWN2 51

3
2
1

3
2
1
PC284

1
680P_0402_50V7K PC285

2
680P_0402_50V7K

2
CPU_B+

10U_0805_25V6K

10U_0805_25V6K

0.1U_0402_25V6

2200P_0402_25V7K
1

1
PC207

PC208

PC291

PC292
2

2
5

5
QC 45W CPU
solution: 3+2
S TR AON7518 1N DFN

@S TR AON7518 1N DFN
PR217
0_0603_5% 1(CSD17308)
MOS: cpu_core --> 1(TPCA8059)
PQ207

2 1 4 4 @ PQ213
51 HG3
C
PL204
1(CSD17308)
Gfx_core --> 1(TPCA8059) C
QC 45W CPU DC 35W CPU
+VCC_CORE VID1=0.9V VID1=1.05V
3
2
1

3
2
1

0.36UH_VMPI1004AR-R36M-Z03_30A_20%
IccMax=94A IccMax=53A
51 SW3 1 4 Icc_Dyn=66A Icc_Dyn=43A
Icc_TDC=56A Icc_TDC=33A
1

2 3 DC 35W CPU
5

R_LL=1.9m ohm R_LL=1.9m ohm

PR268
4.7_1206_5% OCP~110A OCP~65A solution: 2+1
1(CSD17308)
MOS: cpu_core --> 1(TPCA8059)
2

PQ206
51 LG3 4
S TR FDMS0308AS 1N POWER56-8
1(CSD17308)
Gfx_core --> 1(TPCA8057)
SNUB_CPU3

V3N_CPU 2 PR271 1
CSREF 51
3
2
1

10_0402_1%
1

PC296
680P_0402_50V7K SWN3 51
2

AXG_B+
AXG_B+ 2Phase: install

10U_0805_25V6K

10U_0805_25V6K

0.1U_0402_25V6

2200P_0402_25V7K
B
PR284 1Phase:: @ B
BSTA1 1 2 BSTA1_1
10U_0805_25V6K

10U_0805_25V6K

1
2.2_0603_5%

PC209

PC210

PC293

PC294
0.1U_0402_25V6

2200P_0402_25V7K
5

5
0.22U_0402_10V6K
1

2
1

5
S TR AON7518 1N DFN

PC286 BSTA2 1 PR288 BSTA2_1

PC205

PC206

PC287

PC288

2
@S TR AON7518 1N DFN
2

1
2.2_0603_5%
2

S TR AON7518 1N DFN

@S TR AON7518 1N DFN
PC295
PQ205

@ PQ214

4 4
0.22U_0402_10V6K

PQ209

@ PQ215
PU202 4 4
1 9 PR225 +VCC_GFXCORE_AXG
BST FLAG 0_0603_5% PU203 +VCC_GFXCORE_AXG
3
2
1

3
2
1

2 8 HG1A 2 1 PL203 1 9 PR229

51 6132_PWMA PWM DRVH BST FLAG
PR285 0_0603_5%

3
2
1

3
2
1
51 DRVEN 2 1EN_GFX1 3 7 SW1A 1 4 51 6132_PWM 2 8 HG2A 2 1 PL205
2K_0402_1% EN SW PWM DRVH 0.36UH_VMPI1004AR-R36M-Z03_30A_20%
1

+5VS 2 1VCC_GFX1 2 1 4 6 2 3 51 DRVEN 2 PR267 1EN_GFX2 3 7 SW2A 1 4

5

PR272 PR275 VCC GND 0.36UH_VMPI1004AR-R36M-Z03_30A_20% 2K_0402_1% EN SW

0_0402_5% 0_0402_5% 5 LG1A PR286 +5VS 2 1VCC_GFX2 2 1 4 6 2 3
1

5
DRVL VCC GND
V1N_GFX

PQ208 4.7_1206_5% PR273 PR276

V2N_GFX
NCP5911MNTBG_DFN8_2X2 0_0402_5% 0_0402_5% 5 PQ210
2

PC289 DRVL
2

2.2U_0603_10V7K 4 2 PR287 1 NCP5911MNTBG_DFN8_2X2 PR269

CSREFA 51 51 CSREFA
PC298 4.7_1206_5% PR270
SNUB_GFX1

10_0402_1% 2.2U_0603_10V7K LG2A 4 2 1

2

2
10_0402_1%
3
2
1

SWN1A 51

SNUB_GFX2
S TR FDMS0308AS 1N POWER56-8

3
2
1
SWN2A 51
1

PC290 S TR FDMS0308AS 1N POWER56-8

680P_0402_50V7K
2

1
PC297
680P_0402_50V7K

2
A A

QC 45W GT2 DC 35W GT2

VID1=1.23V VID1=1.23V
IccMax=46A IccMax=33A
Icc_Dyn=37A Icc_Dyn=20.2A Security Classification Compal Secret Data Compal Electronics, Inc.
Icc_TDC=38A Icc_TDC=21.5A Issued Date 2009/12/01 Deciphered Date 2010/12/31 Title

R_LL=3.9m ohm R_LL=3.9m ohm THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-CPU_CORE
Size Document Number Rev
OCP~55A OCP~40A AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS PBL22 LA-7391P M/B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 26, 2011 Sheet 52 of 58
5 4 3 2 1
 5 4 3 2 1

+VCC_CORE Below is 458544_CRV_PDDG_0.5 Table 5-8.

+VCC_CORE +VCC_GFXCORE_AXG
5 x 22 F (0805)
1

1
PC1101 PC1102 PC1103 PC1104 PC1105
Socket Bottom 5 x (0805) no-stuff
10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M sites
2

2
D +VCC_GFXCORE_AXG D

7 x 22 F (0805)
Socket Top 2 x (0805) no-stuff
sites
1

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
1 1 1 1 1 1 1 1

PC1151

PC1152

PC1153

PC1154

PC1155

PC1156

PC1157

PC1158
PC1106 PC1107 PC1108 PC1109 PC1110
10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
2

2
2 2 2 2 2 2 2 2 +1.05vs
+VCC_CORE +1.05vs

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1

PC751

PC752

PC753

PC754

PC755

PC756

PC757

PC758

PC759

PC760

PC761
PC1111 PC1112 PC1113 PC1114 PC1115
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 2 2 2 2 2 2 2 2 2 2 2
2 2 2 2 2

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
1 1 1 1

PC1159

PC1160

PC1161

PC1162
2 2 2 2

22U_0805_6.3V6M
1 1 1

330U_D2_2V_Y

330U_D2_2V_Y

@330U_D2_2V_Y
1 1 1 1 1

PC762

PC763

PC764

PC765
+ + +
1
PC1116 PC1117 PC1118 PC1119 PC1120
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
C 2 2 2 2 2 2 2 2 C
2
1 1 1 1

330U_D2_2V_Y

330U_D2_2V_Y

330U_D2_2V_Y

@330U_D2_2V_Y
PC1163

PC1164

PC1165

PC1166
+ + + +

2 2 2 2
1 1 1 1 1 1
PC1121 PC1122 PC1123 PC1124 PC1125 PC1126
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
2 2 2 2 2 2

+VCC_CORE
Chief River 330uF*9m 470uF*4.5m 22uF 10uF
1 1 1 1 1
+ PC1127 + PC1128 + PC1129 + PC1130 + PC1131
330U_D2_2V_Y 330U_D2_2V_Y 330U_D2_2V_Y 330U_D2_2V_Y 330U_D2_2V_Y

2 2 2 2 2 8layer for DC CPU 16 10

4
B B

8layer for QC CPU 5 16 10

6layer for DC CPU 5 16 10

6layer for QC CPU 4 1 16 10

GFX_CORE DC 2 12

GFX_CORE QC 3 12

1.05V_VCCP 2 12
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/09/15 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR - PROCESSOR DECOUPLING
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-8221P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: W ednesday, October 26, 2011 Sheet 53 of 58
5 4 3 2 1
 A B C D

+VGA_B+
PL903
HCB2012KF-121T50_0805
1 2 B+
PL904
HCB2012KF-121T50_0805
1 2

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6

@680P_0603_50V7K
2200P_0402_50V7K
1P : @

1
2P: install

PC936

PC907

PC908
PC937

PC971
1 1
PQ903

2
5

5
1 2 S TR AON7518 1N DFN PQ905

2
PR945 PR902
68K_0402_1% 0_0402_5%
4 4

20
20
20
20
20
20
GPU_VID5
GPU_VID4
GPU_VID3
GPU_VID2
GPU_VID1
GPU_VID0
1
PR903
150K_0402_1% PR904 PC938
1 2VRON_VGA 2.2_0603_5% 0.22U_0603_10V7K @S TR AON7518 1N DFN
1P : @

3
2
1

3
2
1
15,20,29 DGPU_PWR_EN BOOT2_VGA 2 1 BOOT2_2_VGA 1 2 PR911
0_0603_5% PL902
PR905
1 2
UGATE2_VGA 2 1 UGATE2_VGA1 0.36UH_VMPI1004AR-R36M-Z03_30A_20%
2P: install
10K_0402_1% PC939 .1U_0402_16V7K
1 2 DPRSLPVR_VGA PHASE2_VGA 1 4 +VGA_CORE

5
1P: @ LF2_VGA 2 3 V2N_VGA

GPU_VID5
GPU_VID4
GPU_VID3
GPU_VID2
GPU_VID1
GPU_VID0
PQ904

10K_0402_1%
3.65K_0805_1%
1

1
2P: 1.91K
+3VS PR910 PR909

PR907
1 1

GPU_VID6

330U_D2_2V_Y
1.91K_0402_1% 1_0402_1%

PR908

470U 2V M D2 LESR4.5M SX H1.9

CLK_ENABLE#_VGA LGATE2_VGA PR906 + +

PC903

PC904
1 2 4

2
1

4.7_1206_5%
HWPU PR915 2 2

SNUB2_VGA
1.91K_0402_1% S TR FDMS0309S 1N POWER56-8

3
2
1
PD901 VSUM-_VGA
@RB751V-40TE17_SOD323-2
2

2 1 VSUM+_VGA ISEN2_VGA
29,40 VGA_PWROK
1P: @ PR918
100K_0402_5% PC940
2P: 100K

1
+3VS 1 2
680P_0402_50V7K

2
2 PR919
47K_0402_1%
+VGA_CORE Under VGA Core 2

2 1 +VGA_CORE Near VGA Core

1P : @ PC941
1U_0603_10V6K
40
39
38
37
36
35
34
33
32
31

+3VS 1 2
PR912 PU901 2P: install 1 2
100K_0402_5%
CLK_EN#
DPRSLPVR

VID6
VID5
VID4
VID3
VID2
VID1
VID0
VR_ON

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M
PSI#_VGA
RBIAS_VGA

1 2

1
20 ACIN_BUF PR913

PC923

PC920

PC921

PC922

PC924

PC925

PC911

PC919
30 1 1 1 1

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

@22U_0805_6.3V6M
BOOT2

1
0_0402_5%

PC930

PC929

PC928

PC927
29
UGATE2 PC926
1 28

2
PC909 @56P_0402_50V8 PGOOD PHASE2 47U_0805_6.3V6M
2 27

2
PSI# VSSP2 PR920 2 2 2 2
1 2 3 26
VGA_VR_TT# RBIAS LGATE2 VCCP_VGA11 VCCP_VGA
4 25 2 1 2 +5VS
PR914 4.02K_0402_1% PH902 NTC_MOSFET_VGA VR_TT# VCCP 0_0402_5%
5 24
NTC PWM3
1 2NTC_MOS_VGA 1 2 VW_VGA 6 23 PR921
COMP_VGA VW LGATE1 0_0402_5%
7 22
470K_0402_5%_TSM0B474J4702RE FB_VGA COMP VSSP1
8 21

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M
@4.7U_0603_6.3V6M

@4.7U_0603_6.3V6M

@4.7U_0603_6.3V6M

@4.7U_0603_6.3V6M

@4.7U_0603_6.3V6M
FB PHASE1
1 2ISEN3_VGA 9
ISEN3
1

1
UGATE1

PC943

PC912

PC913

PC914

PC915

PC916

PC917

PC918

PC931

PC932

PC933

PC934

PC935
10
BOOT1
ISUM+

ISEN2
ISEN1

ISUM-
VSEN

IMON

PC942 1U_0603_10V6K
8.06K_0402_1%

VDD
1000P_0402_50V7K

RTN

VIN

@22P_0402_50V8J 41
@249K_0402_1%

2
2

AGND
PC944

ISL62883CHRTZ-T_TQFN40_5X5
PR922

PR923

11
12
13
14
15
16
17
18
19
20

PR924 PR946
2

499_0402_1% PC945 1 2
ISUM-_VGA

1 2FB1_VGA1 2 @0_0402_5%
1

VDD_VGA
RTN_VGA

680P_0402_50V7K
PC946 PR926 PR925 0_0402_5%

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

@0.1U_0402_10V7K

@0.1U_0402_10V7K

@0.1U_0402_10V7K

@0.1U_0402_10V7K
47P_0402_50V8J 3.48K_0402_1% IMON_VGA 1 2 +5VS (20W ~ 35W
VGA bulk cap330uF_9m * 4)

1
VSEN_VGA

PC968

PC965

PC966

PC967

PC969

PC970

PC963

PC964
1 2 1 2
PR927 0_0402_5% 35W--> 5 * 0.1uF +15 * 4.7u + 22u * 3 + 330_9m * 4
VIN_VGA 1 2 +VGA_B+

2
ISEN2_VGA
1 2FB2_VGA1 2 PR929
ISEN1_VGA 1_0402_5%
3
PC947 PR928 1 2 +VGA_B+ 3
+5VS
0.22U_0402_10V6K

0.22U_0402_10V6K
1

150P_0402_50V8J 267K_0402_1%
1

1
PC948

PC949

PC950

PC951
1U_0603_10V6K

0.22U_0603_25V7K

1P: 120K PR930

249K_0402_1%

2200P_0402_50V7K
2

2
2

2P: @249K
BOOT1_VGA

1P: 68nF PQ906

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6
2

5
PR944 PQ901
@0_0402_5% 2P: 0.022uF

1
S TR AON7518 1N DFN

PC952
PR916

PC953

PC905

PC906
1P: install
1

1P: @ 0_0603_5%

2
2P: @ 2P: 0.22u VSUM+_VGA UGATE1_VGA 2 1 UGATE1_VGA1 4 4
+5VS VSUM-_VGA
1 2
@82.5_0402_5%

+VGA_CORE
PR934 PC954
1

PR931 2.2_0603_5% 0.22U_0603_10V7K

PR932

3
2
1

3
2
1
1

10_0402_5% 2 1 BOOT1_1_VGA 1 2
2.61K_0402_1%

@S TR AON7518 1N DFN PL901

PR933

0.36UH_VMPI1004AR-R36M-Z03_30A_20%
22 VCCSENSE_VGA 1 2
2

PHASE1_VGA 1 4 +VGA_CORE
2

5
PR935
VSUM_VGA_N001

0.22U_0603_10V7K

0.022U_0603_25V7K
1

0_0402_5% PQ902 LF1_VGA 2 3 V1N_VGA

NTC_VGA

PC955
1

1
@330P_0402_50V7K
PC956

PC957

10K_0402_1%
3.65K_0805_1%
2

1
PR937
1 1

330U_D2_2V_Y

330U_D2_2V_Y
LGATE1_VGA 4 PR939
2

PR936 1_0402_1% + +

PR938

PC901

PC902
@0.01U_0402_25V7K
@330P_0402_50V7K

2
1

4.7_1206_5%
PC959

PC960

11K_0402_1%

2
1

PC958 PH901 2 2
PR941

3
2
1
PR940 0.01U_0402_50V7K 10K_0402_1%_TSM0A103F34D1RZ S TR FDMS0309S 1N POWER56-8

SNUB1_VGA
0_0402_5%
2

22 VSSSENSE_VGA 1 2 1P : @ VSUM-_VGA
2

Layout Note: VSUM+_VGA 2P: install

PR942 PR943 Place near Phase1 Choke ISEN1_VGA
10_0402_5% 1.58K_0402_1%

1
4 4
1 2 1 2 VSUM-_VGA
PC961
680P_0402_50V7K

2
1

1P: @ 1P: 866 1P: 0.1uF PC962

0.1U_0402_16V7K
2P: 1.58K 2P: 0.22uF 20W 25W ~30W
2

solution:1P solution:2P
OCP:38A OCP:75A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/09/15 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR - VGA_COREP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-8221P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 26, 2011 Sheet 54 of 58
A B C D
 5 4 3 2 1

Power block
CPU OTP
Page 56
D Turn Off D

Input B+
DC IN +3VALWP: TDC:6A
Switch Page 57 +5VALWP: TDC:6.1A Always

RT8205LZQW(2) WQFN Page 52

CHARGER
CC:0A~3.64A +1.8VP: TDC:1.2A SUSP#
CV:12.6V(6cell) SY8033BDBC
BQ24725RGRR Page 59

Page 57

C C
+VCCPP: TDC:8.5A SUSP#

Battery TPS51212DSCR Page 60

+V1.05SP: TDC:7.9A SUSP#

TPS51212DSCR Page 61

+1.5VP: TDC:16A SYSON

TPS51212DSCR
Page 62
+VGA_CORE
DGPU_PWR_EN
TDC:23A
B TPS51212DSCR B

Page 65 +0.75VSP: TDC:2A +3VALW

APL5331KAC-TRL
Page 62

+VCCSAP: TDC:4.2A +V1.05S_VCCP_PWRGOOD

+VCC_CORE TPS51461RGER
VR_ON
TDC: 52A Page 63

ISL95832HRTZ-T
Page 64

+VCC_GFXCORE_AXG
VR_ON
A TDC: 38A A

ISL95832HRTZ-T
Page 64

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/08/03 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
POWER BLOCK DIAGRAM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-8221P
Date: Wednesday, October 26, 2011 Sheet 55 of 58
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5HTXHVW
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D D

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/09/15 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR - PIR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-8221P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 26, 2011 Sheet 56 of 58
5 4 3 2 1
 5 4 3 2 1

7LPLQJ'LDJUDPIRU*RU60RII6XVSHQG:HOO2IIWR60>QRQ'HHS663ODWIRUP@

$&,1%$77,1

9$/:9$/:

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9&&686 D

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6863 7!"PV

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3&+B$3:52.

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CPU SVID BUS

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Security Classification Compal Secret Data

Issued Date 2009/12/01 Deciphered Date 2011/12/31 Title
Power Sequence
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-8221P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 26, 2011 Sheet 57 of 58
5 4 3 2 1
 5 4 3 2 1

9HUVLRQ&KDQJH/LVW3,5/LVW 3DJH

,WHP )L[HG,VVXH 5HDVRQIRUFKDQJH 5HY 3* 0RGLI\/LVW 'DWH 3KDVH

(5
D D
HW Design (TMDS_B_HPD) 0.2 14 Delete R205 09/21

36 Add ASM1042 co-lay

(5
Add USB3.0(ASM1042) & 0.2 09/21
non AI co-lay 37 AI parts change to AI@
13 Delete Q3. ( connect pin S & D ) remove R135, R137
(5
+3VS Leakage HW Design (SMBus leakage) 0.2 09/21
40 Del R552, R556
Add Q20,R773,R775
(5
Design change for card reader 0.2 34 Reserve R768,R774. 09/21
Change Net name at Card reader Conn

(5
HW Design (PURC demand) 0.2 29 Change to Q3(AO3404L) from U22(AO4430L) 09/21

(5
HW Design (PURC demand) 0.2 42 Change Q33 to AO3413L from AP2301GN 09/21

Change R433 to 0 ohm un-stuff C396

(5
Fine-tune GPU timing 0.2 29 Change R432 to 10K 09/21
Change R435 to 200 ohm

(5
HW Design (reserve) 0.2 18 Reserve R290 09/21

(5
C C
KB connector reverse HW Design (change) 0.2 39 Reverse JKB1 connector 09/30

(5
HW Design 0.2 40 Del Y5 , C545 , C546 09/30

Del R229,R230 (10K) Add R776~R783 (10K)

(5
HW Design (PURC demand) 0.2 15 09/30
Del R237,R239,R242 (8.2K) Add R784~R793 (8.2K)
29,31 Change P/N C387,C389,C399,C436,C447,C602
(5
HW Design (PURC demand) 0.2 37,38 Change P/N C509,C515,C518,C526.(0402) 10/03
10,11 Change P/N C99,C109,C118,C120,C140,C141.(0402)
42,12 Change R607 to 10 ohm Change Y3,C241,C242.
(5
HW Design(XTAL fine-tune) 0.2 13,32 Change Y1,C144,C145 Change Y4,C469,C473. 10/07
20,36 Change Y2,C163,C164 Change Y9
13 Reserve R750
(5
HW Design for instant on function 0.2 5 R576 pin2 change to +3V_PCH from +3VS 10/07
Change R576 to 0
38
(5
HW Design ( power jumper change to +3VL) 0.2 40 jumper PJP302 (change +3VLP to +3VL @P38,P40) 10/07

Change P/N Q7,U20,U21.

(5
HW Design (PURC demand) 0.2 Change P/N Q14~Q19,Q25,Q27~Q29,Q32,Q34~Q37,Q40~Q43,
Q46~Q51,Q55~Q57,Q60,Q61,Q902,Q903,Q905. 10/14
B B

Change P/N Q23

(5
EMI solution 0.2 5 Add R684 to 0 (H_CPUPWRGD) 10/14

(5
Refer to ORB design 0.2 14 un-stuff D2, Add R751
40 un-stuff D32, R547, Add R752 10/14
Assign U33.18 to AC_PRESENT signal.

change for GPU H/W strapping STRAP1 to PL 45K

(5 ohm to enhanced the PCIe PEG driving. 0.2 22 Change R349 from 34.8K to 45.3K 10/14

09 Add R242 Add C149 0.1uf

modify parts for Intel review feedback message. 0.2 18 Del L6, Add R289 , un-stuff C212
(5
17 Del L4, Add R387 10/14
14 Add R230
15 Stuff R244

(5
Modify H2 size
0.2 38 Modify H2 size 10/17

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/12/01 Deciphered Date 2011/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EE-PIR-1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-8221P
Date: Wednesday, October 26, 2011 Sheet 58 of 58
5 4 3 2 1
 5 4 3 2 1

9HUVLRQ&KDQJH/LVW3,5/LVW 3DJH

,WHP )L[HG,VVXH 5HDVRQIRUFKDQJH 5HY 3* 0RGLI\/LVW 'DWH 3KDVH

(5
D D
Refer to Intel review feedback item 45. 0.2 16 Add R807 10/19

(5
14,16 Add unstuff R800,R801,R802,R803,R804,R805 10/19
Reserve for Deep Sx 0.2
40 Add PCH_DPWROK,DS_WAKE#,SUSACK#,SUSWARN#

(5 Reserve for ROM protect 0.2 40 Add unstuff R806 10/19

(5
For Instant On function control by EC 0.2 06 Stuff R44, Unstuff R43 10/19

(5
For EMI request 0.2 36 Reserve R1082 , C1045 10/19

(5
For LED issue 0.2 39 change LED3 footprint to LED_HT-210UD-UYG_3P 10/20

38
(5
For PRUC request 0.2 Change SW3,SW4,SW5 P/N 10/20
39

(5
C
For PRUC request 0.2 39 Change U36 P/N 10/20 C

(5
For EMI request (without MS_CLK) 0.2 34 Remove R637,C611,R631,C620. 10/20

20 Add R428, Revise U11 I/O signal.

(5
dGPU thermal throttling. 0.2 40 10/20
Un-stuff R730.
12 Add Q63, R135, R137.
(5
SPI flash data crisis prevention. 0.2 10/20
40 Change U33.41 net to EC_SPI_WP. remove R806.

(5
Power switch EOS issue prevention. 0.2 37 Change C510, C516, C519 to 0.22uF/16V. 10/20

32 Change R485 , R486 to 0.1uF

(5
For EMI request 0.2 10/20
35 Reserve C641~C648
37,35 Change D27,D29,D24,D25.
(5
For ESD request 0.2 10/20
30,39 Change D6,D7,D9,D10,D33,D34.

(5
Modify X76 table (N13P-GS) 0.2 22 update X76 table (Strap1,Strap2,Strap3) 10/24

update X76 table (add ZZZ9 ~ZZZ12 for N13P-GS &

(5
B
Modify X76 table (N13P-GS & N13M-GE1 x8) 0.2 3 N13M-GE1 x8) & update P/N 10/25 B

(5
Modify PCH_SPI_WP# singal control by EC 0.2 12 Stuff R135 10/26

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/12/01 Deciphered Date 2011/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EE-PIR-2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-8221P
Date: Wednesday, October 26, 2011 Sheet 59 of 59
5 4 3 2 1
www.s-manuals.com