Application Note

Manual PostRoute Clock Transition

Fixing

EDI 14.1
September 6, 2016
Copyright Statement

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 Manual Post Route Transition Fixing

Contents
Purpose ....................................................................................................................... 4
Audience...................................................................................................................... 4
Overview ...................................................................................................................... 4
Identifying Clock Transition Violations ......................................................................... 4
Fixing Clock Transition Violations ................................................................................ 5
Checking Timing Impact ............................................................................................... 7
Summary ..................................................................................................................... 8
Support ........................................................................................................................ 8
Feedback ..................................................................................................................... 8

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 Manual Post Route Transition Fixing

Purpose
Post-route transition fixing is a must fix design reliability issue before taping out a design.
While this is the same issue for both datapath and clock nets, the requirements and
impacts to fix the clock nets are far more stringent and sensitive from a design timing
point of view, and hence it needs to be addressed carefully. Many designs already has
the clock transition fixed at the end of CTS stage. This document describes a process to
identify such violations and the process to fix them manually. Fixing is targeting only the
nets which are getting a bit detoured at the post route stage due to congestion, or
congestion due to ECO.

Audience
This document is intended for EDI System users who need to fix the clock transition at
the post-route stage in order to tapeout a chip that meets the design reliability
requirements.

Overview
Post-route clock transition fixing involves several steps. Firstly, the nets need to be
qualified that they truly violate the design intent, so that they are not over-fixed or under-
fixed. Secondly, such violations need to be fixed effectively without incurring further timing
damage to the design, and lastly but equally important that the fixes need to be verified
for setup and hold timing robustness.

Identify Clock Transition Violations

The user can report the clock transition violation using the reportTranViolation
command in EDI System, or referring to the existing *.tran report generated by the
timeDesign command at various stages of the design flow. Either way, please make
sure that clock transition limit is set so that EDI System can report violations above the
tolerance as intended. Here are the commands:-

#Set the clock transition tolerance.

set_max_transition <value> clock_path [get_clocks *]
reportTranViolation outfile <violation report>

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 Manual Post Route Transition Fixing

The transition violations of the clock nets can be identified from the C remark at the
end of line in the report. After generating the clock transition report, the user may need to
do additional filtering. Since the clock transition violations are typically closely dependent
on the frequency of the logical clock that the design operates, the higher the clock
frequency is, the tighter (smaller) the transition slew requirement. Hence, the violated nets
need to be filtered from the transition report to eliminate clock nets associated with low
frequency clock, or treated differently, as they have more relaxed transition targets.

Here is a sample net in clock transition violation report:-

# Net / InstPin MaxTranTime TranTime TranSlack CellPort Remark

netA
instPin/a 0.035r/0.035f 0.047r/0.048f -0.012r/-0.013f cgc6X/clk_in C
instPin/b 0.035r/0.035f 0.047r/0.047f -0.012r/-0.012f cgc6X/clk_in C
instPin/c 0.035r/0.035f 0.046r/0.046f -0.011r/-0.011f cgc6X/clk_in C
instPin/d 0.035r/0.035f 0.046r/0.046f -0.011r/-0.011f cgc6X/clk_in C
instPin/e 0.035r/0.035f 0.046r/0.046f -0.011r/-0.011f cgc6X/clk_in C
instPin/f 0.035r/0.035f 0.042r/0.042f -0.007r/-0.007f cbuf12X/a C
instPin/g 0.035r/0.035f 0.040r/0.040f -0.005r/-0.005f cgc6X/clk_in C

Fixing Clock Transition Violations

There are few ways that the clock transition violations can be fixed. The easiest approach
is to size the driver of the net to a bigger drive strength using ecoChangeCell. However,
this method is effective only provided that the transition violation is mostly due to the load
(capacitance) but not a long wire or jogging (resistance). Most of the time, the post-route
transition violations are caused by a resistance issue, and hence it cannot be effectively
fixed by sizing. To resolve transition violations due to long wires or jogging, the user can
do additional manual strategic buffering on the net to reduce the resistance effect on clock
transition significantly. This is an effective method to fix many violations relatively quickly
without perturbing the original routing topology. Sometimes, a net can be straightened too
from the route itself using the Wire Editor, provided routing resources are available to do
so. But straightening may not be achievable in congested spots, or dealing with complex
routing topology, or may disturb nearby routing topology of others beyond intentions.

To illustrate the manual buffering on the clock net, lets walk through the same sample
net in the report above. Assuming that a tapeout criteria requires fixing all the clock
transition greater than 45ps. According to the report, there are five pins that violate this
transition requirement.

To assist in clock transition fixing, it is important to analyze the physical topology for the
violated cells and potential buffer location by selecting the net. Here is the physical net

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 Manual Post Route Transition Fixing

topology of the net, the five cells with the inputs pins that violate the requirement are
highlighted in pink:

Source

In order to fix the transition of the inputs pin of those five cells, the net needs to be
buffered while maintaining the original topology to minimize the timing perturbation on
the related timing paths. The command to achieve that operation is:

ecoAddRepeater -net netA -offLoadAtLoc "1000 1200" \

-cell cbuf6X cutWire

This instructs EDI to insert a buffer to the specified location to offload the violated pins
by cutting wires and maintain the original routing topology.

As a side note, it is preferable to pick a moderate drive strength buffer to minimize the
impact of the clock path delay. In addition, as the goal here is to buffer for resistance, it
doesnt require a high drive cell.

After the buffer(s) are inserted run ecoRoute to connect the new buffers.

Below is the new connectivity and topology of the original net after inserting the buffer:

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 Manual Post Route Transition Fixing

New Buffer
Inserted Source
Here

Comparing the above with the original routing topology, it confirms that EDI System
preserves the routing topology while successfully adding buffers for the sinks that violate
the transition limit.

Checking Timing Impact

To ensure the timing integrity of the transition fix, it is important to check timeDesign
postRoute to make sure that the timing profile is not degraded compared to the timing
before fixing. This is very important as buffer insertion may increase the insertion delay
of the clock path, and slightly perturb the timing. If this happens to be the timing path with
negative setup and hold violations, then the transition fix has caused setup/hold
violations. In that case, the fix may need to be adjusted to eliminate such impact. Or, the
user can choose to fix the timing in the datapath if margin is available there.

It is also important to check timing against all the major corners of interest as the timing
impact may not show up in one single corner.

From the same post-route timing report, the user can also review the transition violation
fixes.
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 Manual Post Route Transition Fixing

Summary
Post-route clock transition violations are a must fix design reliability issue, but it needs to
be tackled carefully and effectively to minimize the setup/hold timing impact on the design.
This document illustrates that process, from identifying the clock transition violations,
fixing the violations, and performing checks to ensure the fixes achieve the intended
transition, setup and hold time specifications.

Support
Cadence Online Support provides access to support resources, including an extensive
knowledge base, access to software updates for Cadence products, and the ability to
interact with Cadence Customer Support. Visit https://support.cadence.com.

Feedback
Email comments, questions, and suggestions to content_feedback@cadence.com.

Additional Resources
Application Note can be found at Related Solutions sections below the PDF. This pdf
can be searched with the document title on https://support.cadence.com .

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