Innovus Implementation System

Meet PPA and TAT targets at advanced nodes

At advanced nodes, theres a deep conflict between power, performance, and area (PPA) and
design turnaround time (TAT). New physical and electrical design challenges emerge, and
structures such as FinFETs create new considerations. To remain competitive, you cant afford
to make any tradeoffs to either PPA or TAT. With the features and functions available in the
Cadence Innovus Implementation System, you wont have to.

Overview Key Features and Benefits Full-flow multi-objective technology

to support concurrent electrical and
A physical implementation tool for Massively parallel architectures physical optimization
high-density designs at advanced and for handling large designs and
established process nodes, the Innovus supporting multi-threading on A customizable flow via a common
Implementation System delivers a multi-core workstations, as well as UI and user commands across
typical 10%-20% PPA advantage along distributed processing over networks synthesis, implementation, and
with an up to 10X TAT gain. Providing of computers signoff with robust reporting and
the industrys first massively parallel visualization, which facilitates design
New GigaPlace solver-based efficiency and productivity
solution, the Innovus Implementation
placement technology, which is
System can effectively handle blocks as
slack-driven and topology-, pin
large as 5-10 million instances or more. New Slack-Driven Placement
access-, and color-aware to provide
Technique
The Innovus Implementation System optimal pipeline placement, wire
provides new capabilities in placement, length, utilization, and PPA The Innovus Implementation System
optimization, routing, and clocking. features the new GigaPlace engine,
Advanced, multi-threaded,
Its unique architecture accounts for which changes the way placement is
layer-aware optimization engine
upstream and downstream steps done and enhances PPA. Placement
that is timing- and power-driven to
and effects in the design flow to has traditionally been timing-aware
reduce dynamic and leakage power
minimize design iterations and provide and lightly integrated with other
a runtime boost. Using the Innovus Unique concurrent clock and engines in the implementation system,
Implementation System, youll be datapath optimization engine for such as timing analysis and optimi-
equipped to build integrated, better cross-corner variability and zation. The GigaPlace engine, on the
differentiated systems with less risk. performance with reduced power other hand, is slack driven and tightly
integrated. With this approach, the
Next-generation slack-driven routing engine helps place the cells in a timing-
with track-aware timing optimi- driven mode by building up the slack
zation, which addresses signal profile of the paths and performing the
integrity early on and improves placement adjustments based on these
post-route correlation timing slacks.
 Innovus Implementation System

The GigaPlace engine models accurate

electrical constraints and physical
constraints, such as floorplan, route
topology-based wire length, and
congestion. It also integrates the mathe-
matical model of Cadences timing- and
power-driven optimization engine,
another component of the Innovus
Implementation System. This integration
makes concurrent, convergent optimi-
zation of electrical and physical metrics
possible. You are also equipped to extract
your design intent automatically from the
electrical constraints, so you can achieve
better optimization for physical metrics.

The Innovus Implementation System

features a global optimization strategy and
a novel numerical solver to avoid the trap
of local minima. This avoids costly design Figure 1: The GigaPlace engine accounts for pin density as well as pin access.
iterations between different steps of the
flow and results in a faster design closure considers both horizontal and vertical cell With these capabilities, you can maintain
with the best PPA. spreading, and theres an in-row space critical layer assignments during the entire
juggling function during legalization. pre-route optimization flow. These assign-
In addition to solving for overlap and wire
ments are passed on to the systems
length, the GigaPlace engine solves for The GigaPlace engine, with its automatic
next-generation massively parallel global
slack that is driven by gate delay, false/ density screen technology, simplifies
routing engine so that the final routing
multi-cycle paths, layer assignment, and the process of resolving congestion by
will also have the correct layer assignment.
congestion timing effects. As a result, automatically adding density screens in
you get better total negative slack (TNS)/ floorplan-induced high traffic areas. The The optimization engine also helps reduce
worst negative slack (WNS), wire length, algorithm analyzes floorplans, traffic dynamic and leakage power while facili-
congestion, spreading, and power. In patterns, and congestion maps to keep tating optimal performance. A decision
summary, the GigaPlace engine is: standard cells away from the congested engine inside the system makes use of a
area, such as narrow channels, notches, rich library of power-aware transforms to
Electrically driven, accounting for
and macro boundaries. This helps reduce step through the available options and
multi-mode/multi-corner (MMMC)
congestion without requiring you to add reclaim power without affecting timing.
slack, skew, and power
these density screens yourself. This minimizes leakage, as well as internal
Physically driven, accounting for routing and switching power globally.
topology, layer, color, and pin access Advanced Timing- and Power-
The engine supports multiple formats:
Optimization driven, accounting for
Driven Optimization
VCD, TCF, SAF, and SAIF. If switching
gate sizing and buffering Through its route-aware optimization activity data is unavailable, the engine
capability, the next-generation, multi- employs probability-based propagation.
Pin access has become a new design
threaded advanced timing- and power- The engine thus makes the best judgment
closure metric. The GigaPlace engine,
driven optimization engine in the Innovus in terms of finding the optimal power
as shown in Figure 1, accounts for pin
Implementation System can: solution to lower power of an SoC
density, providing an adaptive pin access
without compromising on performance or
flow that automatically spaces cells based Identify long timing-critical nets area.
on the neighboring instances pin-access
restrictions, and not just high local pin Query a new congestion-tracking
density. A proprietary algorithm in the tool infrastructure to ensure that theres
globally plans how the router will access space available on the upper layers
each pin (this is based on instances, not Rebuffer these nets on the upper layers
library cells). The GigaPlace engine has a in order to improve timing
cell spreading cost function that considers
more design rule check (DRC) rules and
pre-routes. An optimization cost function

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 Innovus Implementation System

Clock Concurrent Optimization

with True Multithreading
The Innovus Implementation System
features a next-generation clock
concurrent optimization engine with true
multithreading, enhanced useful skew,
and flow integration. The engine merges
physical optimization with clock-tree
synthesis (CTS), simultaneously building
clocks and optimizing logic delays based
directly on a propagated clocks model. All
the optimization decisions are based on
true propagated clocks and account for
clock gates, inter-clock paths, and on-chip
variation (OCV) derates.

A new FlexH feature in the implemen-

tation system provides a structure that
is topologically as close to an H-tree as Figure 2: Concurrent clock and datapath optimization, along with a clock-tree debugger.
possible, with tradeoffs between different
soft and hard constraints. This feature
The Early Global Route (eGR) feature instance count, the flow can scale over
democratizes the H-tree approach to
brings further improvements in TNS and a larger number of CPUs. The systems
a real-world SoC design environment.
WNS, along with predictable design advanced timing- and power- driven
Without this capability, designers would
closure. The routing and interconnect optimization engine provides threaded
typically use mesh or a hand-created
optimization engine also: MMMC timing. As the number of MMMC
treearchitecturally limited and power-
views increases, the engine delivers a
hungry approaches. The FlexH feature Fixes signal integrity issues before detail
sub-linear speedup.
employs an advanced heuristic search route
algorithm, which explores millions of The systems routing engine is designed
Reduces timing jump between pre-route
different possible tree structures to find such that routing and post-route closure
and post-route
the best compromise between avoiding are handled on additional CPUsmore
blockages and power rails. The algorithm Allows change in netlist and cell than 100 if needed for larger designs.
adheres to partition, module, and power- locations Backed by its processing speed, the
domain constraints and optimizes insertion routing engine simultaneously evaluates
delay, power, and skew. The NanoRoute tool also provides a and optimizes interconnect topology
structured router capability that can be based on the effects on timing, area,
used for selective pre-routes, shielding,
Routing and Interconnect power, manufacturability, and yield. With
and high-frequency bus routing, as well as
Optimization Engine its correct-by-construction approach,
for nets having length/resistance matching the engine can resolve potential double-
The Innovus Implementation System requirements. patterning conflicts on the fly to create
features a proven routing and interconnect a routing topology that is correct for
optimization engine that facilitates total Accelerating TAT double patterning and DRC the first time
routing convergence on timing, area, and also more area efficient. The engine
The Innovus Implementation System
power, signal integrity, and manufacturing is equipped with a deterministic multi-
accelerates digital design TAT through
goals. This engine, with its massively threaded backplane, provides full-flow
various features, including its full-flow
parallel architecture, provides full-flow timing correlations, and offers a flexible
massively parallel architecture. The archi-
timing correlation, deterministic multi- 2D/3D congestion mode. It also features a
tecture, which supports multi-threaded
threading, and a flexible 2D/3D congestion track-based optimization algorithm, which
tasks simultaneously on multiple CPUs,
mode. fixes signal integrity issues before detail
is designed such that the system can
produce best-in-class TAT with standard routing, reduces the timing jump between
hardware, which is normally 8-16 CPUs per pre-route and post-route, and enables
box. In addition, for designs with a larger faster design closure.

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 Innovus Implementation System

Advanced-Node Implementation
Features
The Innovus Implementation System has
a complete feature set to address the
requirements needed for implementation
at advanced FinFET nodes. Special features
are available to handle the placement
needs for macros and standard cells early
in the floorplanning stage. The placement
engine has updates to handle pin access
requirements for advanced-node libraries
and the NanoRoute tool can handle and
optimize routes for self-aligned double
patterning technology. The new Via
Pillar insertion flow and methodology
allow you to push performance while
meeting electromigration requirements.
The updated optimization engine can
accurately model the low voltage effects Figure 3: Cross-probing design layout with schematic viewer
to give near signoff quality static timing
results for faster design convergence. methods have been added to run, define, Cadence Services and Support
and deploy reference flows. These updated
Cadence application engineers can
Common UI for Ease of Use interfaces and reference flows increase
answer your technical questions by
productivity by delivering a familiar
The Innovus Implementation System is telephone, email, or Internet. They can
interface across core implementation and
integrated with Cadences Tempus static also provide technical assistance and
signoff products. You can take advantage
timing analysis, Quantus extraction, and custom training.
of consistently robust RTL-to-signoff
Voltus power integrity technologies,
reporting and management, as well as a Cadence certified instructors teach
so you can accurately model the timing,
customizable environment. more than 70 courses and bring their
parasitics, and signal and power integrity
real-world experience into the classroom
issues at the early stage of physical imple-
mentation. This facilitates faster conver- More than 25 Internet Learning
gence on these electrical metrics, resulting Series (iLS) online courses allow you
in faster design closure. the flexibility of training at your own
computer via the Internet
The implementation system has a common
UI with Cadences Genus Synthesis Cadence Online Support gives you 24x7
Solution and the Tempus Timing Signoff online access to a knowledge base of
Solution. The system simplifies command the latest solutions, technical documen-
naming and aligns common implemen- tation, software downloads, and more
tation methods across these Cadence
digital and signoff tools. For example, the For more information, please visit
processes of design initialization, database www.cadence.com/support for support
access, command consistency, and metric and www.cadence.com/training for
collection have all been streamlined and training
simplified. In addition, updated and shared

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