Circuit Verification

Calibre PERC D A T A S H E E T

Benefits of Ownership
• Next Generation Circuit
Verification — Calibre PERC
provides the capability for advanced
circuit verification. It performs
necessary checks to address ESD
issues, errors arising from designing
across multiple power domains, and
advanced ERC concerns.
• Improve Design Reliability —
Calibre PERC is uniquely capable of
verifying complex rules and reveal-
ing potential electrical violations that
might otherwise result in short-term,
long-term, or even catastrophic elec-
trical failure.
• Improve Design Accuracy — De­vice
Recommended rule specified by the Industry Council on ESD Target Levels is implemented recognition accuracy is crucial for
with Calibre PERC, and an ESD violation is displayed in Calibre RVE. topological ERC iden­tification. Built
over Calibre LVS, Calibre PERC
delivers the same trusted device rec-
Calibre’s Programmable Electrical Rule Checking — ognition accuracy and timely execu-
the Next Level in Circuit Verification tion required for world-class silicon
Reliability is a growing concern for integrated circuit designers; however, this is delivery.
an area that could be better served by the electronic design automation industry. • Improve Runtime — Automated
In response to this growing need, Mentor Graphics has developed Calibre® PERC proprietary hierarchical and logic
(Programmable Electrical Rule Checker) to address reliability challenges that injection technologies provide vir­
arise during the circuit and electrical verification process. PERC is specifically tually unlimited design scope with
designed to perform electrostatic discharge (ESD) and multiple power domain fast runtimes.
checks. Calibre PERC allows you to customize ERC checks at the schematic
• Easy-to-Use and Fully Customizable
level as well as geometrical and electrical checks at layout, which gives you more
— Similar to other Calibre products,
power and flexibility to handle emerging circuit verification demands for design
PERC uses TCL + standard SVRF
implementa­tion.
com­mands. This interface can be used
to address proprietary methodologies
ESD, advanced ERC, and multiple power domains are top issues on a long list
for capturing electrical violations.
of complex new geometrical and electrical verification requirements. All of these
Calibre PERC runs on any netlist,
advanced requirements can only be described by a topological view rather than either extracted or source-originated.
single device/pin to net relation. A topological view incorporates many layout-
related parameters as well as circuitry-dependant checks. Calibre PERC is the • Zero Risk Performance, Investment,
first industry tool to fulfill these complex verification requirements. and Quality — Fully compatible with
the Calibre Physical Verification Plat-
The PERC tool, through its programmable entry, is able to automatically identify form, Calibre PERC integrates easily
into existing customer signoff flows.
complex circuit topology on a design netlist either streamed out from the sche-
matic or extracted from the layout. Then, PERC examines the specific constraints • Superior Support Quality — the only
defined by you, whether they are electrical or geometrical. Built over industry 5-Star support in EDA.

www.mentor.com/
 Schematic and
Layout Flow
Calibre PERC can run from the
schematic only or from the layout.
The implication is that by run-
ning on the schematic you can
identify electrical errors earlier in
the design cycle and correct them
before layout is implemented. If
schematic checking has been done,
then checking of the layout can
be considered a verification step
or used to verify geometrical con-
straints that cannot be checked on
the schematic. To run post-layout,
complex geometrical parameters
Calibre PERC can run from the schematic only or from the layout. can be calculated and incorporated
into the PERC check, thereby
standard Calibre nmLVS, PERC is uniquely capable of incorporating both electrical and geometrical data into this
device-grouping recognition and performing accurate layout verification step.
advanced measurements efficiently.
With the continuing move to smaller geometries, accurate
Electrostatic Discharge extraction of advanced device parameters becomes increas-
ESD rules verification is needed to obviate chip catastrophic ingly important for safe ERC implementation. As you imple-
failures. In complex designs, sophisticated ESD protection ment high-end process nodes, 90 nm down to 65 nm and 45
device structures have to be verified. Usually, these struc- nm, you may find that successful implementation of your
tures are formed from a group of devices to construct better small process node designs requires custom measurement for
ESD prevention circuitry. Other considerations also have critical ERC rules.
to be added, such as the geometrical constraints of device
dimensions, the number of fingers, and distance from supply In a layout-based flow, Calibre PERC provides automatic
pads, as well as the different circuitry combination on mul- device recognition and parameter extraction for standard
tiple power domains. Calibre PERC handles these complex devices with typical BSIM3/4 and PSP parameters, as well
requirements with a straight-forward methodology. as a user-defined option when more complex requirements
are needed.
Multiple Power Domains
In multiple power domains, system integration and IP reuse Comprehensive Solution
complicates the circuit verification problem because of the Calibre PERC is the only comprehensive solution capable of
various connections between different domains. Design hi- checking constraints across the board, whether geometrical,
erarchy and constraints need to be considered where specific electrical, or both. Calibre PERC integrates easily into exist-
rules are applied on a top cell and/or pad frame but others are ing customer signoff flows, including using Calibre Interac-
applied between blocks that cross multiple power domains. tive for invocation and displaying results with Calibre RVE.
PERC helps you identify where there are inappropriate con-
nectors between different power domains. Platforms Supported
32 and 64 bit Linux Redhat, SUN Solaris, and HP-UX.
* “White Paper 1: A Case for Lowering Component Level HBM/MM ESD Specifications and
Visit our website at www.mentor.com Requirements” from the Industry Council on ESD Target Levels

Copyright © 2009 Mentor Graphics Corporation. Mentor products and processes are registered trademarks of Mentor Graphics Corporation.
All other trademarks mentioned in this document are trademarks of their respective owners.

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