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    VHDL - Xilinx Exercises Compilation

    Uploaded by

    Nicko Casi
    This document contains 7 problems involving VHDL code for digital logic circuits. The problems include: 1) Creating an up/down counter, 2) Performing an AND operation on two 8-bit inputs, 3) Adding two 4-bit inputs, 4) Subtracting two 8-bit inputs, 5) Dividing two 8-bit inputs, 6) Converting between BCD and decimal formats for a 12-bit input, 7) Counting the number of ones in a 16-bit input. VHDL code and test simulations are provided for each problem.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd

    VHDL - Xilinx Exercises Compilation

    Uploaded by

    Nicko Casi
    68 views19 pages
    This document contains 7 problems involving VHDL code for digital logic circuits. The problems include: 1) Creating an up/down counter, 2) Performing an AND operation on two 8-bit inputs, 3) Adding two 4-bit inputs, 4) Subtracting two 8-bit inputs, 5) Dividing two 8-bit inputs, 6) Converting between BCD and decimal formats for a 12-bit input, 7) Counting the number of ones in a 16-bit input. VHDL code and test simulations are provided for each problem.

    Original Description:

    VHDL sample exercises for Xilinx

    Original Title

    Vhdl_xilinx Exercises Compilation

    Copyright

    © © All Rights Reserved

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    This document contains 7 problems involving VHDL code for digital logic circuits. The problems include: 1) Creating an up/down counter, 2) Performing an AND operation on two 8-bit inputs, 3) Adding two 4-bit inputs, 4) Subtracting two 8-bit inputs, 5) Dividing two 8-bit inputs, 6) Converting between BCD and decimal formats for a 12-bit input, 7) Counting the number of ones in a 16-bit input. VHDL code and test simulations are provided for each problem.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    68 views19 pages

    VHDL - Xilinx Exercises Compilation

    Uploaded by

    Nicko Casi
    This document contains 7 problems involving VHDL code for digital logic circuits. The problems include: 1) Creating an up/down counter, 2) Performing an AND operation on two 8-bit inputs, 3) Adding two 4-bit inputs, 4) Subtracting two 8-bit inputs, 5) Dividing two 8-bit inputs, 6) Converting between BCD and decimal formats for a 12-bit input, 7) Counting the number of ones in a 16-bit input. VHDL code and test simulations are provided for each problem.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 19

    VHDL EXERCISES COMPILATION

    By

    Nicko D. Casi/ ECE-4

    MICROELECTRONICS TRACK 3

    Bachelor of Science in
    Electronics Engineering
    PROBLEM I: COUNTER

    Create a Counter based from XILINX Quick Start Tutorial using VHDL
    Language. When Clock =1, then the counter would count to 15 but when the
    Clock=0, then the counter would count down from where it started.

    VHDL Code:

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;
    -- Uncomment the following library declaration if
    instantiating
    -- any Xilinx primitive in this code.
    --library UNISIM;
    --use UNISIM.VComponents.all;
    entity counter is
    Port ( CLOCK : in STD_LOGIC;
    DIRECTION : in STD_LOGIC;
    COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0));
    end counter;

    architecture Behavioral of counter is


    signal count_int : std_logic_vector(3 downto 0) :=
    "0000";

    begin
    process (CLOCK)
    begin
    if CLOCK='1' and CLOCK'event then
    if DIRECTION='1' then
    count_int <= count_int + 1;
    else
    count_int <= count_int - 1;
    end if;
    end if;
    end process;
    COUNT_OUT <= count_int;
    end Behavioral;
    SIMULATION:
    PROBLEM II: ANDING

    Create a two 8-bit inputs that would do an ANDing operation.

    VHDL Code:
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    ---- Uncomment the following library declaration if


    instantiating
    ---- any Xilinx primitives in this code.
    --library UNISIM;
    --use UNISIM.VComponents.all;

    entity sample is
    Port ( ina : in STD_LOGIC_VECTOR (7 downto 0);
    inb : in STD_LOGIC_VECTOR (7 downto 0);
    clk : in STD_LOGIC;
    outa : out STD_LOGIC_VECTOR (7 downto 0));
    end sample;

    architecture Behavioral of sample is

    begin
    process(clk)
    begin
    if clk='1' and clk'event then
    outa <= ina and inb;
    end if;
    end process;

    end Behavioral;
    SIMULATION:
    PROBLEM III: ADDITION

    Perform the addition of two 8-bit inputs.

    VHDL Code:

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    -- Uncomment the following library declaration if --


    instantiating
    -- any Xilinx primitive in this code.
    --library UNISIM;
    --use UNISIM.VComponents.all;

    entity addition is
    Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
    B : in STD_LOGIC_VECTOR (3 downto 0);
    clk : in STD_LOGIC;
    Y : out STD_LOGIC_VECTOR (3 downto 0));
    end addition;

    architecture Behavioral of addition is

    begin
    process (clk)
    begin
    if clk = '1' and clk'event then
    Y <= A + B;
    end if;
    end process;
    end Behavioral;
    SIMULATION:
    PROBLEM IV: SUBTRACTION

    Perform the subtraction of two 8-bit inputs.

    VHDL Code:
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    ---- Uncomment the following library declaration if


    instantiating
    ---- any Xilinx primitives in this code.
    --library UNISIM;
    --use UNISIM.VComponents.all;

    entity subtract is
    Port ( A : in STD_LOGIC_VECTOR (7 downto 0);
    B : in STD_LOGIC_VECTOR (7 downto 0);
    clk : in STD_LOGIC;
    Y : out STD_LOGIC_VECTOR (7 downto 0));
    end subtract;

    architecture Behavioral of subtract is

    begin
    process (clk,A,B)
    begin
    if clk ='1' and clk'event then
    Y <= A - B;
    end if;
    end process;
    end Behavioral;
    SIMULATION:
    PROBLEM V: DIVISION

    Perform the division of two 8-bit inputs.

    VHDL Code:

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    ---- Uncomment the following library declaration if


    instantiating
    ---- any Xilinx primitives in this code.
    --library UNISIM;
    --use UNISIM.VComponents.all;

    entity division_in is
    Port ( A : in STD_LOGIC_VECTOR (7 downto 0);
    B : in STD_LOGIC_VECTOR (7 downto 0);
    clk : in STD_LOGIC;
    Y : out STD_LOGIC_VECTOR (7 downto 0);
    err : out STD_LOGIC);
    end division_in;

    architecture Behavioral of division_in is

    begin

    process(clk)

    begin
    if clk='1' and clk'event then
    Y <=
    conv_std_logic_vector(conv_integer(A)/conv_integer(B),8
    );
    err <= '0';
    end if;
    if B = 0 then
    err <= '1';
    end if;

    end process;

    end Behavioral;

    SIMULATION
    PROBLEM VI: BCD TO DECIMAL

    Determine if the input of 12-bits is valid for converting to BCD. If each 4-bit
    of the 12-bit input is less than 10, then it is BCD thus, the error is equal to zero and
    the output display the BCD of the input. If one or all of the 4-bits in a 12-bit input is
    greater than or equal to 10, then the error is equal to one and no BCD output will be
    displayed.

    VHDL Code:
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    ---- Uncomment the following library declaration if


    instantiating
    ---- any Xilinx primitives in this code.
    --library UNISIM;
    --use UNISIM.VComponents.all;

    entity bcd is
    Port ( A : in STD_LOGIC_VECTOR (11 downto 0);
    clk : in STD_LOGIC;
    B : out STD_LOGIC_VECTOR (9 downto 0);
    err : out STD_LOGIC);
    end bcd;

    architecture Behavioral of bcd is

    begin
    process(clk)
    begin

    if clk='1' and clk'event then


    if (conv_integer(A(11 downto 8)) >= 10) or
    (conv_integer(A(7 downto 4)) >= 10)
    or (conv_integer(A(3 downto 0)) >=10)
    then
    err <= '1';

    else
    B <=
    conv_std_logic_vector(100*(conv_integer(A(11 downto
    8)))
    + 10*(conv_integer(A(7 downto 4))) +
    (conv_integer(A(3 downto 0))),10);
    err <= '0';
    end if;

    end if;
    end process;

    end Behavioral;

    SIMULATION:
    PROBLEM VI: DECIMAL TO BCD

    Convert the 10-bit input decimal (Max of 1023) to Binary-Coded-Decimal.


    Hint: Use the Modulo function.
    VHDL Code:
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    entity dec_to_bcd is
    Port ( Ina : in STD_LOGIC_VECTOR (9 downto 0);
    clk : in STD_LOGIC;
    Outa : out STD_LOGIC_VECTOR (15 downto 0);
    err : out STD_LOGIC);
    end dec_to_bcd;

    architecture Behavioral of dec_to_bcd is

    begin
    process (clk)
    begin
    if clk='1' and clk'event then
    if (conv_integer(Ina) >= 1024) then
    err <= '1';
    else
    Outa(15 downto 12) <=
    conv_std_logic_vector((conv_integer(Ina) / 1000),4);
    Outa(11 downto 8) <=
    conv_std_logic_vector((conv_integer(Ina) / 100)MOD
    10,4);
    Outa(7 downto 4) <=
    conv_std_logic_vector((conv_integer(Ina) / 10)MOD 10,4);
    Outa(3 downto 0) <=
    conv_std_logic_vector((conv_integer(Ina))MOD 10,4);
    end if;

    end if;
    end process;
    end Behavioral;

    SIMULATION:
    PROBLEM VII: COUNTING THE NUMBER OF ONES

    With the input of 16-bits, create a program where the output displays the
    number of ones. Hint: use Loop.

    VHDL Code:
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    entity count_ones is
    Port ( ones : in STD_LOGIC_VECTOR (15 downto 0);
    clk : in STD_LOGIC;
    number_of_ones : out integer);
    -- err : out STD_LOGIC);
    end count_ones;

    architecture Behavioral of count_ones is

    begin
    process (clk, ones)
    variable c: integer;
    begin
    if clk='1' and clk'event then
    c:=0;
    ones1: for i in 0 to 15 loop
    if (ones(i)='1') then
    c:=c+1;
    end if;
    end loop ones1;
    end if;
    number_of_ones<=c;
    end process;
    end Behavioral;
    SIMULATION:

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