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    Verilog HDL Basics

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    Syed Ashmad
    Verilog HDL Basics document discusses several key topics: 1) It describes the basic elements and data types in Verilog such as modules, ports, nets, registers, parameters, numbers, strings, and memory. 2) It discusses important Verilog concepts like scope and reference, event-driven simulation, and system tasks and functions for simulation control and output display. 3) It provides examples of different operator types in Verilog like arithmetic, bitwise, logical, relational, shift, concatenation, replication, and conditional operators.

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    © All Rights Reserved
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    Verilog HDL Basics

    Uploaded by

    Syed Ashmad
    94 views73 pages
    Verilog HDL Basics document discusses several key topics: 1) It describes the basic elements and data types in Verilog such as modules, ports, nets, registers, parameters, numbers, strings, and memory. 2) It discusses important Verilog concepts like scope and reference, event-driven simulation, and system tasks and functions for simulation control and output display. 3) It provides examples of different operator types in Verilog like arithmetic, bitwise, logical, relational, shift, concatenation, replication, and conditional operators.

    Original Description:

    Verilog Operators and Types

    Original Title

    d22 Veriloghdlbasic 090415040304 Phpapp02

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    Verilog HDL Basics document discusses several key topics: 1) It describes the basic elements and data types in Verilog such as modules, ports, nets, registers, parameters, numbers, strings, and memory. 2) It discusses important Verilog concepts like scope and reference, event-driven simulation, and system tasks and functions for simulation control and output display. 3) It provides examples of different operator types in Verilog like arithmetic, bitwise, logical, relational, shift, concatenation, replication, and conditional operators.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    94 views73 pages

    Verilog HDL Basics

    Uploaded by

    Syed Ashmad
    Verilog HDL Basics document discusses several key topics: 1) It describes the basic elements and data types in Verilog such as modules, ports, nets, registers, parameters, numbers, strings, and memory. 2) It discusses important Verilog concepts like scope and reference, event-driven simulation, and system tasks and functions for simulation control and output display. 3) It provides examples of different operator types in Verilog like arithmetic, bitwise, logical, relational, shift, concatenation, replication, and conditional operators.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
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    of 73

    Verilog HDL Basics

    What we already learned


     Verilog can model: behavioral, RTL structure
     Module: basic unit in Verilog
     A tutorial: Module instantiation, stimulus, respone
     Procedure block: initial, always
    Verilog HDL Basics

    Basic Element and Data Type


    4 Vaules Logic System
    Module
    Moudle Port Mapping
     In Order
    − counter dut (count, clk, reset);

     By Name
    − counter dut (.count(count), .clk(clk), .reset(reset));
    Comment and White Space
    module MUX2_1 (out, sel, inb, ina);
    // Port declarations, single line comments space, tab,
    output out; and newline

    input sel, inb, ina; // terminated with ; CASE Sensitive


    /* multiple lines comments
    The netlist logic selects input "ina" when
    sel is 0 and it selects ”inb” when sel is 1.
    */
    not (sel_, sel);
    and (sela, ina, sel_),
    (selb, inb, sel );
    or (out, sela, selb);
    endmodule
    Identifiers and Keywords

    Identifier:
    Names of instances, modules, nets, ports, and variables
    Keyword:
    Language construct, lower case

    module MUX2_1 (out,sel,inb,ina);


    output out; // names you provide such
    as
    input sel,inb,ina; // ina, inb, sel, sel_, sela, selb, out,
    not (sel_, sel); // and MUX2_1 are identifiers.
    and (sela, ina, sel_),
    (selb, inb, sel );
    Module ports

    // input [msb:lsb] list_of_port_identifier


    Data Type

    Devices/Blocks

    Storage

    Module parameters -Configure module


    instances
    Net
     Nets are continuously driven by the devices that
    drive them. Ex, module or gate instantiation
     Continuous assignments, primitives, and registers
    can drive nets.
     Initial default value “z”
    Types of Net

    Examples // bit select


    wire [7:0] out ; assign out[1] =0
    tri enable; // part-select
    wire a, b, c;
    Logic Conflicts

    Always be cautious about 『 multiple driver 』 on a net.


    Register
    A register maintains its value between discrete
    assignments.
     assignments to registers in procedural code
    blocks, task or function.
     Can't be output of “assign” statement.
     Doesn't imply a storage element in the hardware.
     Initial default value “x”
    Type of Register

    Examples:
    reg a; // single bit
    reg [3:0] b; // 4 bits
    reg [7:0] c, d; // two 8bits regs
    Parameters
     Use module parameters to configure module
    instances: parameter list_of_assignments
    − A parameter is an un-typed constant
    − You can use a parameter anywhere that you can use a
    constant or liter
    Correct Data Type
    Number
     [[<size>]’<radix>]<value>
    − size is the size in bits
    − B or B (binary), o or O (octal), d or D (decimal), h or H (hexadecimal)
     Examples
    12 unsized decimal (extended to 32 bits with "0")
    'H83a unsized hexadecimal (extended to 32 bits with "0")
    8'b1100_0001 8-bit binary, _ for readability
    8'h61 8-bit hex
    64'hff01 64-bit hexadecimal (extended to 64 bits with "0")
    16'h456a 16-bit hex
    9'O17 9-bit octal
    32'bz01x extended to 32 bits with "z"
    3’b1010_1101 3-bit number, truncated to 3’b101
    6.3 decimal notation
    32e-4 scientific notation for 0.0032
    4.1E3 scientific notation for 4100
    String
     string constants, but has no explicit string data
    type.
     Store ASCII character strings in a reg array
     Example:
    − $monitor("This string formats a value: %b", monitored_object);

    integer kkk;
    kkk = $fopen(file);
    Compiler Directives
    `define Define a text replacement macro
    `ifdef Conditionally compile source code,
    `else dependent upon which text macros
    `endif are defined
    `include Include a file of source code
    `resetall Reset all compiler directives
    `timescale Establish a simulation timescale
    `undef Undefine a text replacement macro
    timescale
    `timescale 1ns/100ps //time_unit, time_precision
     Place the directive outside of a module definition
     seconds (s), milliseconds (ms), microseconds (us), nanoseconds (ns),
    picoseconds (ps), or femtoseconds (fs)
     to advance 1 ns simulation time
    `timescale 1 ns / 100 ps
    10 steps
    `timescale 1 ns / 1 ps
    1000 steps

    Delays are multiples of time_unit


    rounded to time_precision.
    `timescale 10ns/1ns
    #1.55 a = b;
    'a' gets 'b' after 16 ns because
    10ns*1.55 = 15.5 ns = 16ns rounded to nearest 1ns
    Memory: array of registers
     reg [MSB:LSB] memory_name [first_addr:last_addr];

    reg [31:0] video_ram [0:7]


    // 8 words by 32 bit wide memory
    parameter wordsize = 16;
    parameter memsize = 1024;
    reg [wordsize-1:0] mem [0:memsize-1];
    // arrays of integer and time data types:
    integer int_array [0:1]; // array of 2 integer variables
    time time_array [8:1]; // array of 8 time variables
    video_ram[2] = 1; // the 3rd
    $display(“video_ram[2] = %h”, video_ram[2]);

    // bit select not allowed for reg array


    Verilog Primitives
    Scope and Reference

    Module test_bench; dut


    Module ALU

    aa
    $monitor($time,"wire in A =%b",
    dut.aa.a_in);
    Module A
    wire a_in

    bb

    Module B
    LAB
    Verilog HDL Basics

    Simulator, IO
    Event-Driven Simulation
     The simulation scheduler
    − keeps track of when events occur, communicates events to
    appropriate parts of the model,
    − executes the model of those parts, and
    − as a result, possibly schedules more events for a future time.
    − Event-based simulation algorithms process only the changes in
    circuit state.
    − it maintains “simulated time” (sometimes “virtual time”) and the
    event list.
    − The simulation propagates values forward, through the circuit, in
    response to input pin events or autonomous event generators
    (such as clocks).
    Event-Driven Simulation
     The simulator creates the initial queues upon
    compiling the data structures
     The simulator processes all events on the current
    queue, then advances
     The simulator moves forward through time, never
    backward
     A simulation time queue represents concurrent
    hardware events
    System Tasks and Functions

     names start with a dollar sign ($) character


     Commonly used: Simulation Control, Display, File
     Example
    $display $display("out=%b",out); // Display argument values
    $finish $finish; // Terminate the simulation
    $monitor $monitor($time,sel,a,b,out); // Monitor signal changes
    $stop $stop; // Suspend the simulation
    $time time_var = $time; // Get the simulation time

     Check doc see ModelSim support


    <install_dir>\docs\pdf\oem_man.pdf
    chap5
     But... what is %b.......
    IO Format Specifier

    escape

    $monitor ($time, "%b \t %h \t %d \t %o", sig1, sig2, sig3, sig4);

    $display("Hello World, count = %d ", count ); // new line added


    $write("Hello World, count = %d \n", count ); // need escape
    Verilog HDL Basics

    Operator
    Operator: Arithmetic
    Operator: Arithmetic Example
     Integer division discards any remainder
     A modulus operation retains the sign of the first operand
     The integer register data type is signed.
     The reg and time register data types are unsigned

    reg [3:0] A, B; wire [4:0] sum, diff1, diff2, neg


    assign sum = A+B; assign diff1 = A-B; assign diff2 = B-A; assign neg = -A;
    $display(“%d %d %d %d %d %d”, A, B, sum, diff1, diff2, neg);
    $display(“%b %b %b %b %b %b”, A, B, sum, diff1, diff2, neg);
    -------------------------------------------------------------
    A B A+B A-B B-A -A Stored in 2's
    complement
    5 2 7 3 29 27 but .....unsigned.
    0101 0010 00111 00011 11101 11011
    If result is same size
    carry lost
    Operator: Bit Wise

    module bitwise_xor (y, a, b);


    input [7:0] a,b;
    output [7:0] y;
    assign y= a ^ b;
    //(0101_0101)^(0011_0000) = 0110_0101
    Operators: Unary Reduction
    Operator: Logic

    reg [3:0] A, B
    1. if (!A) // false if all of its bits are 0
    if (A) // true if any of its bits are 1
    Operator: Equality
    Operator: Relational
    Operators: Shift

    result = (start << 1); // right operand treated as unsigned


    // so always use positive number
    Operator: Conditional

    if (conditional_expression)
    LHS = true_expression;
    else
    LHS = false_expression;"

    module driver(O,I,E); module mux41(O,S,A,B,C,D);


    output O; input I,E; output O;
    assign O = E ? I : 'bz; input A,B,C,D; input [1:0] S;
    endmodule assign O = (S == 2'h0) ? A :
    (S == 2'h1) ? B :
    (S == 2'h2) ? C : D;
    endmodule
    Operator: Concatenation
    Operator: Replication
    Operator Precedence
    Highest

    Lowest
    Verilog HDL Basics

    Assignment, timing control


    Sequential and Concurrent
    Blocks
    Continuous Assignment
    Example
     Use continuous assignments outside of a procedural block

    Delay
    wire #5 eq = (a == b);

    Conditional
    forece..release
     Apply to net as well as reg
     Primarily used in testbench
     force sig_a = 1;
     release sig_a = 0;
    Procedure Assignment
    Initial Bloclk
    Always Block
    Example#1
    To reg
    Example #2

    When to start
    this block

    Cout = ( a & b) |
    ( a & !b &cin) |
    ( );
    Sequential
    Procedural Timing Control: #
     #0 IN1=0;IN2=1; // t=0
     #100 IN3=1; // t=100
     #100 IN4=1 // t=200
    Procedural Timing Control: @

    Sensitivity List
    happened when signal transition

    Clock qualifier
    posedge, negedge

    ?? non-blocking assignment, later in this section


    Procedural Timing Control:
    wait

    // suspend here
    // until (ack || rst) true
    Missing Timing Control

    A zero-delay behavioral loop is a common coding error.


    In a zero-delay loop, the simulator continuously adds events to the
    same queue. As the queue never empties, the simulator appears to
    hang
    Timing Control Examples
    Blocking and Nonblocking
    Example
    Initial Initial
    begin begin
    A=1; A=1;
    B=0; B=0;
    .... ....
    A=B; // Uses B=0 A<=B; // Uses B=0
    B=A; // Uses A=0 B<=A; // Uses A=1
    end end
    // A=0 // A=0
    // B=0 // B=1
     The simulator completes a  The simulator completes a nonblocking
    blocking assignment (=) in one assignment (<=) in two passes: It
    pass: It evaluates the RHS evaluates the RHS expression and
    expression and stores the schedules the LHS assignment. It
    value in the LHS register updates the LHS only after evaluating all
    the RHS expressions in the design
    Example
    Intra-Assignment Delay
    A = #5 B; always @(a or b) begin
    #5 y = a | b; // value of a, b, 5 times steps later
    C = D;
    end // #5; y=a | b

    always @(a or b) begin


    y = #5 a | b; // value of a, b, #0
    end // y updated delayed, blocked

    always @(a or b) begin


    y <= #5 a | b; // value of a, b, #0
    end // y updated delayed, non-blocked
    intra-assignment timing control, which delays the LHS
    update, but not the RHS evaluation.
    Verilog HDL Basics

    Flow Control, loop


    Conditional Statement: if
     if ( expression ) statement_or_null [ else statement_or_null ]
     If (a<b) sum = sum +1;
     If (k==1)
    begin
    ........
    end
     If (a <b)
    sum = sum + 1;
    else
    sum = sum +2
     If (a>=b)
    begin
    ..... if (cond1) begin
    end if (cond2) do_c1_c2;
    What is your
    else end LOGIC?
    begin else
    ..... do_not_c1;
    Example: if

    Priority
    Conditional Statement: case

    The Verilog case statement automatically breaks after the


    first match
    The case statement does a bit-by-bit comparison for an
    exact match.
    Parallel
    Conditional Statement: casez,
    casex
    Loop: for
    Loop: forever, repeat
    Loop: while
    Summary
     What we learned:
     Verilog basic Element, Data Type (net and reg)
     Event Driven Simulator Algorithm, IO supported
    system task
     Operator
     Continuous assignment, Procedure assignment
     Procedure timing control
     Flow control, loop
    LAB2
    Appendix

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