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    2-1 Internal Microprocessor Architecture

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    This document summarizes the internal architecture of a programmable device, including its programming model and modes of operation. It describes the device's registers including multipurpose registers like RAX, RBX, RCX, RDX and special purpose registers like RIP, RSP, RFLAGS. It also covers the segment registers CS, DS, ES, SS, FS and GS. Finally, it discusses real mode memory addressing where all addresses consist of a segment address plus an offset, and default segment and offset registers.

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    2-1 Internal Microprocessor Architecture

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    36 views3 pages
    This document summarizes the internal architecture of a programmable device, including its programming model and modes of operation. It describes the device's registers including multipurpose registers like RAX, RBX, RCX, RDX and special purpose registers like RIP, RSP, RFLAGS. It also covers the segment registers CS, DS, ES, SS, FS and GS. Finally, it discusses real mode memory addressing where all addresses consist of a segment address plus an offset, and default segment and offset registers.

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    Original Title

    Introduction

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    This document summarizes the internal architecture of a programmable device, including its programming model and modes of operation. It describes the device's registers including multipurpose registers like RAX, RBX, RCX, RDX and special purpose registers like RIP, RSP, RFLAGS. It also covers the segment registers CS, DS, ES, SS, FS and GS. Finally, it discusses real mode memory addressing where all addresses consist of a segment address plus an offset, and default segment and offset registers.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    36 views3 pages

    2-1 Internal Microprocessor Architecture

    Uploaded by

    scouttype
    This document summarizes the internal architecture of a programmable device, including its programming model and modes of operation. It describes the device's registers including multipurpose registers like RAX, RBX, RCX, RDX and special purpose registers like RIP, RSP, RFLAGS. It also covers the segment registers CS, DS, ES, SS, FS and GS. Finally, it discusses real mode memory addressing where all addresses consist of a segment address plus an offset, and default segment and offset registers.

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    of 3

    INTRODUCTION

     programmable device
     internal programming model
     real, protected, and flat modes of operation
    2-1 INTERNAL MICROPROCESSOR ARCHITECTURE
    task or thread
    The Programming Model
     program visible
     program invisible
    Multipurpose Registers
     RAX – 64-bit register(RAX), 32-bit(accumulator)(EAX), 16-bit(AX), and two
    8-bit registers (AH and AL)
     RBX – RBX, EBX, BX, BH, BL. – BX register (base index)
     RCX, as RCX, ECX, CX, CH, or CL. (count)
     RDX, as RDX, EDX, DX, DH, or DL. (data)
     RBP, as RBP, EBP, or BP. (Base Pointer)
     RDI addressable as RDI, EDI, or DI. (destination index)
     RSI used as RSI, ESI, or SI. (Source Index)
     R8 – R15 found in the Pentium 4 and Core2 if 64-bit extensions are
    enabled.
    Special-Purpose Registers
     RIP, RSP, and RFLAGS
     RIP defined as Register instruction pointer.
     RSP defined as Register stack pointer
     RFLAGS
    List of Each Flag bit, with a brief description of function.
     C (carry) holds the carry after addition or borrow after subtraction.
     P (parity) is the count of ones in a number expressed as even or odd. Logic
    0 for odd parity; logic 1 for even parity.
     A (auxiliary carry) positions 3 and 4.
     Z (zero) shows that the result of an arithmetic or logic operation is zero.
     S (sign) flag holds the arithmetic sign of the result after an arithmetic or
    logic instruction executes.
     T (trap) The trap flag enables trapping through an on-chip debugging
    feature.
     I (interrupt) controls operation of the INTR
     D (direction) selects increment or decrement
     O (overflow)
     IOPL used in protected mode operation to select the privilege level for I/O
    devices.
     NT (nested task) flag indicates the current task is nested within another
    task in protected mode operation.
     RF (resume) used with debugging to control resumption of execution after
    the next instruction.
     VM (virtual mode) flag bit selects virtual mode operation in a protected
    mode system.
     AC, (alignment check) flag bit activates if a word or doubleword is
    addressed on a non-word or non-doubleword boundary.
     VIF is a copy of the interrupt flag bit available to the Pentium 4-(virtual
    interrupt)
     VIP (virtual) provides information about a virtual mode interrupt for
    (interrupt pending) Pentium.
     ID (identification) flag indicates that the Pentium microprocessors support
    the CPUID instruction.
    Segment Registers
     Generate memory addresses
     Four or six Segment registers
     CS (code) segment holds code (programs and procedures) used by the
    microprocessor.
     DS (data) contains most data used by a program.
     ES (extra) an additional data segment used by some instructions to hold
    destination data.
     SS (stack) defines the area of memory used for the stack.
     FS and GS segments are supplemental segment registers available in 80386
    – Core2 microprocessor. – allow two additional memory segments for
    access by programs.
     Windows uses these segments for internal operations, but no definition of
    their usage is available.
    2-2 REAL MODE MEMORY ADDRESSING
     Real mode operation, - memory, conventional memory, or DOS memory
    system.
    Segments and Offsets
     All real mode memory addresses must consist of a segment address plus an
    offset address. – segment address, - offset address
     Segment plus offset
     Ending address
    Default Segment and Offsets Registers
     The code segment register defines the start of the code segment.
     The instruction pointer locates the next instruction within the code
    segment.

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