TCL Script: Gen - Netlist - TCL:: TCLSH Auto - Synth - TCL Mul - 8 - Bit.v Mul - 8 - Bit - TB.V

DARSHIL SHAH TASK-6 17MVD0091
Q-1 Write a TCL Script which when executed will automatically compile your design
modules and test-bench modules (select any medium complex designs), perform the
simulation and then synthesize the design module. The TCL script should also create a
separate directory to dump the log files and a separate directory to write the netlist file.
IMPLEMENTATION:
Below command used to execute the Verilog file as a command line argument for synthesis and
simulation purpose by calling the Synopsys server. Here I have attached two Verilog file of my ASIC
project which is 8-bit approximate multiplier.
tclsh auto_synth.tcl mul_8_bit.v mul_8_bit_tb.v
TCL SCRIPT:
GEN_NETLIST.TCL:
set sub_file_names [glob *]
if {[lsearch $sub_file_names netlist] != -1} {
set sub_file_index [lsearch $sub_file_names netlist]
cd [lindex $sub_file_names $sub_file_index]
file delete [glob *]
cd ..
} else {
puts [exec mkdir netlist]
}
set NETLIST_DIR netlist

set LOG_DIR log
read_verilog mul_8_bit.v
analyze -library WORK -format verilog {mul_8_bit.v}
elaborate mul_8_bit -architecture verilog -library DEFAULT
link
check_design
compile -exact_map
report_area > ${LOG_DIR}/area.rpt

report_constraint > ${LOG_DIR}/constraint.rpt
report_timing > ${LOG_DIR}/timing.rpt
write -hierarchy -format verilog -output ${NETLIST_DIR}/

mul_8_bit_dc.v
exit
pg. 1
AUTO_SYNTH.TCL:
#!/usr/bin/tclsh
set sub_file_names [glob *]
if {[lsearch $sub_file_names log] != -1} {
set sub_file_index [lsearch $sub_file_names log]
cd [lindex $sub_file_names $sub_file_index]
#exec cd [lindex $sub_file_names $sub_file_index]
file delete [glob *]
cd ..
} else {
puts [exec mkdir log]
}
set LOG_DIR log

puts [exec vcs -v -R [lindex $argv 0] [lindex $argv 1] -full64 -
debug_all >$LOG_DIR/compile.log]
puts [exec ./simv >$LOG_DIR/sim.log]
puts [exec dc_shell -f ./synth.tcl >$LOG_DIR/synth.log]
SETUP.TCL:
set search_path .
set link_library "* saed90nm_typ_ht.db"
set target_library "saed90nm_typ_ht.db"
SYNTH.TCL:
set LOG_DIR log
source ./setup.tcl > ${LOG_DIR}/setup.log
source ./gen_netlist.tcl > ${LOG_DIR}/gen_netlist.log
pg. 2
RESULT:
AREA LOG FILE:
****************************************
Report : area
Design : mul_8_bit_1
Version: I-2013.12-SP5-10
Date : Thu Feb 22 17:40:48 2018
****************************************
Information: Updating design information... (UID-85)

Library(s) Used:
saed90nm_typ_ht (File:
/home/userdata/17mvd0091/materials/saed90nm_typ_ht.db)
Number of ports: 32
Number of nets: 133
Number of cells: 79
Number of combinational cells: 56
Number of sequential cells: 0
Number of macros/black boxes: 0
Number of buf/inv: 6
Number of references: 29
Combinational area: 1857.024013

Buf/Inv area: 176.947205
Noncombinational area: 0.000000
Macro/Black Box area: 0.000000
Net Interconnect area: 82.910888
Total cell area: 1857.024013

Total area: 1939.934901
1
CONSTRAINT LOG FILE:

****************************************
Report : constraint
Date : Thu Feb 22 17:40:48 2018
****************************************
Constraint Cost
-----------------------------------------------------
min_capacitance 0.00 (MET)
max_transition 0.00 (MET)
max_capacitance 0.00 (MET)
pg. 3
TIMING LOG FILE:

****************************************
Report : timing
-path full
-delay max
-max_paths 1
Date : Thu Feb 22 17:40:48 2018
****************************************
Operating Conditions: TYPICAL Library: saed90nm_typ_ht

Wire Load Model Mode: enclosed
Startpoint: a[1] (input port)

Endpoint: p[14] (output port)
Path Group: (none)
Path Type: max
Des/Clust/Port Wire Load Model Library

------------------------------------------------
mul_8_bit_1 8000 saed90nm_typ_ht
fadd_12 ForQA saed90nm_typ_ht
RC_adder 8000 saed90nm_typ_ht
Point Incr Path

-----------------------------------------------------------
input external delay 0.00 0.00 r
a[1] (in) 0.00 0.00 r
U105/ZN (INVX0) 0.10 0.10 f
U104/QN (NOR2X0) 0.22 0.31 r
U97/Q (AO22X1) 0.26 0.57 r
f1_9/x3 (APP_FA_11) 0.00 0.57 r
f1_9/U1/Q (XNOR2X1) 0.28 0.85 r
f1_9/sum (APP_FA_11) 0.00 0.85 r
r_1/a23 (RC_adder) 0.00 0.85 r
r_1/f4/a (fadd_12) 0.00 0.85 r
r_1/f4/U3/Q (XOR2X1) 0.23 1.08 f
r_1/f4/U2/Q (AO22X1) 0.18 1.26 f
r_1/f4/cout (fadd_12) 0.00 1.26 f
r_1/f5/cin (fadd_11) 0.00 1.26 f
r_1/f5/U2/Q (AO22X1) 0.17 1.43 f
r_1/f5/cout (fadd_11) 0.00 1.43 f
r_1/f6/cin (fadd_10) 0.00 1.43 f
r_1/f6/U2/Q (AO22X1) 0.17 1.60 f
r_1/f6/cout (fadd_10) 0.00 1.60 f
r_1/f7/cin (fadd_9) 0.00 1.60 f
r_1/f7/U2/Q (AO22X1) 0.17 1.78 f
r_1/f7/cout (fadd_9) 0.00 1.78 f
r_1/f8/cin (fadd_8) 0.00 1.78 f
r_1/f8/U2/Q (AO22X1) 0.17 1.95 f
r_1/f8/cout (fadd_8) 0.00 1.95 f
r_1/f9/cin (fadd_7) 0.00 1.95 f
r_1/f9/U2/Q (AO22X1) 0.17 2.13 f
pg. 4
r_1/f9/cout (fadd_7) 0.00 2.13 f

r_1/f10/cin (fadd_6) 0.00 2.13 f
r_1/f10/U2/Q (AO22X1) 0.17 2.30 f
r_1/f10/cout (fadd_6) 0.00 2.30 f
r_1/f11/cin (fadd_5) 0.00 2.30 f
r_1/f11/U2/Q (AO22X1) 0.17 2.47 f
r_1/f11/cout (fadd_5) 0.00 2.47 f
r_1/f12/cin (fadd_4) 0.00 2.47 f
r_1/f12/U2/Q (AO22X1) 0.17 2.65 f
r_1/f12/cout (fadd_4) 0.00 2.65 f
r_1/f13/cin (fadd_3) 0.00 2.65 f
r_1/f13/U2/Q (AO22X1) 0.17 2.82 f
r_1/f13/cout (fadd_3) 0.00 2.82 f
r_1/f14/cin (fadd_2) 0.00 2.82 f
r_1/f14/U2/Q (AO22X1) 0.17 3.00 f
r_1/f14/cout (fadd_2) 0.00 3.00 f
r_1/f15/cin (fadd_1) 0.00 3.00 f
r_1/f15/U1/Q (XOR2X1) 0.21 3.20 f
r_1/f15/s (fadd_1) 0.00 3.20 f
r_1/s34 (RC_adder) 0.00 3.20 f
p[14] (out) 0.00 3.20 f
data arrival time 3.20
-----------------------------------------------------------
(Path is unconstrained)
NETLIST:
module APP_HA_0 ( x1, x2, sum, carry );

input x1, x2;
output sum, carry;
wire n1, n2;
NAND2X0 U1 ( .IN1(n1), .IN2(n2), .QN(sum) );

NOR2X0 U2 ( .IN1(n2), .IN2(n1), .QN(carry) );
INVX0 U3 ( .INP(x2), .ZN(n1) );
INVX0 U4 ( .INP(x1), .ZN(n2) );
endmodule
module APP_FA_0 ( x1, x2, x3, sum, carry );

input x1, x2, x3;
output sum, carry;
wire n1, n2;
XNOR2X1 U1 ( .IN1(n1), .IN2(x3), .Q(sum) );

INVX0 U3 ( .INP(x3), .ZN(n2) );
NOR2X0 U4 ( .IN1(x1), .IN2(x2), .QN(n1) );
pg. 5
endmodule
module compressor4_2_0 ( x1, x2, x3, x4, sum, carry );

input x1, x2, x3, x4;
output sum, carry;
wire n1, n2, n3, n4;

XNOR2X1 U2 ( .IN1(x1), .IN2(x2), .Q(n2) );
MUX21X1 U3 ( .IN1(n3), .IN2(n4), .S(x3), .Q(n1) );
NOR2X0 U4 ( .IN1(x1), .IN2(n3), .QN(n4) );
INVX0 U5 ( .INP(x4), .ZN(n3) );
AO22X1 U6 ( .IN1(x3), .IN2(x4), .IN3(x1), .IN4(x2), .Q(carry) );
endmodule
module fadd_0 ( a, b, cin, s, cout );

input a, b, cin;
output s, cout;
wire n1;
XOR2X1 U1 ( .IN1(cin), .IN2(n1), .Q(s) );

AO22X1 U2 ( .IN1(a), .IN2(b), .IN3(cin), .IN4(n1), .Q(cout) );
XOR2X1 U3 ( .IN1(a), .IN2(b), .Q(n1) );
endmodule

input a, b, cin;
output s, cout;
wire n1;

XOR2X1 U3 ( .IN1(a), .IN2(b), .Q(n1) );
endmodule

input a, b, cin;
output s, cout;
wire n1;

XOR2X1 U3 ( .IN1(a), .IN2(b), .Q(n1) );
endmodule

input a, b, cin;
output s, cout;
wire n1;
pg. 6

XOR2X1 U3 ( .IN1(a), .IN2(b), .Q(n1) );
endmodule

input a, b, cin;
output s, cout;
wire n1;

XOR2X1 U3 ( .IN1(a), .IN2(b), .Q(n1) );
endmodule

input a, b, cin;
output s, cout;
wire n1;

XOR2X1 U3 ( .IN1(a), .IN2(b), .Q(n1) );
endmodule

input a, b, cin;
output s, cout;
wire n1;

XOR2X1 U3 ( .IN1(a), .IN2(b), .Q(n1) );
endmodule

input a, b, cin;
output s, cout;
wire n1;

XOR2X1 U3 ( .IN1(a), .IN2(b), .Q(n1) );
endmodule

input a, b, cin;
output s, cout;
wire n1;

pg. 7
XOR2X1 U3 ( .IN1(a), .IN2(b), .Q(n1) );

endmodule

input a, b, cin;
output s, cout;
wire n1;

XOR2X1 U3 ( .IN1(a), .IN2(b), .Q(n1) );
endmodule

input a, b, cin;
output s, cout;
wire n1;

XOR2X1 U3 ( .IN1(a), .IN2(b), .Q(n1) );
endmodule

input a, b, cin;
output s, cout;
wire n1;

XOR2X1 U3 ( .IN1(a), .IN2(b), .Q(n1) );
endmodule

input a, b, cin;
output s, cout;
wire n1;

XOR2X1 U3 ( .IN1(a), .IN2(b), .Q(n1) );
endmodule

input a, b, cin;
output s, cout;
wire n1;

XOR2X1 U3 ( .IN1(a), .IN2(b), .Q(n1) );
pg. 8
endmodule

input a, b, cin;
output s, cout;
wire n1;

XOR2X1 U3 ( .IN1(a), .IN2(b), .Q(n1) );
endmodule
module RC_adder ( a20, a21, a22, a23, a24, a25, a26, a27, a28, a29,
a30, a31,
a32, a33, a34, b20, b21, b22, b23, b24, b25, b26, b27, b28,
b29, b30,
b31, b32, b33, b34, cin2, s20, s21, s22, s23, s24, s25, s26,
s27, s28,
s29, s30, s31, s32, s33, s34, cout2 );
input a20, a21, a22, a23, a24, a25, a26, a27, a28, a29, a30, a31,
a32, a33,
a34, b20, b21, b22, b23, b24, b25, b26, b27, b28, b29, b30,
b31, b32,
b33, b34, cin2;
output s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31,
s32, s33,
s34, cout2;
wire c1, c2, c3, c4, c5, c6, c7, c8, c9, c10, c11, c12, c13,
c14;
fadd_0 f1 ( .a(a20), .b(b20), .cin(cin2), .s(s20), .cout(c1) );

fadd_14 f2 ( .a(a21), .b(b21), .cin(c1), .s(s21), .cout(c2) );
fadd_1 f15 ( .a(a34), .b(b34), .cin(c14), .s(s34), .cout(cout2) );
endmodule

input x1, x2, x3;
output sum, carry;
wire n1, n2;
pg. 9

INVX0 U3 ( .INP(x3), .ZN(n2) );
NOR2X0 U4 ( .IN1(x1), .IN2(x2), .QN(n1) );
endmodule

input x1, x2, x3;
output sum, carry;
wire n1, n2;

INVX0 U3 ( .INP(x3), .ZN(n2) );
NOR2X0 U4 ( .IN1(x1), .IN2(x2), .QN(n1) );
endmodule

input x1, x2, x3;
output sum, carry;
wire n1, n2;

INVX0 U3 ( .INP(x3), .ZN(n2) );
NOR2X0 U4 ( .IN1(x1), .IN2(x2), .QN(n1) );
endmodule

input x1, x2, x3;
output sum, carry;
wire n1, n2;

INVX0 U3 ( .INP(x3), .ZN(n2) );
NOR2X0 U4 ( .IN1(x1), .IN2(x2), .QN(n1) );
endmodule

input x1, x2, x3;
output sum, carry;
wire n1, n2;

INVX0 U3 ( .INP(x3), .ZN(n2) );
NOR2X0 U4 ( .IN1(x1), .IN2(x2), .QN(n1) );
endmodule

input x1, x2, x3;
pg. 10
output sum, carry;

wire n1, n2;

INVX0 U3 ( .INP(x3), .ZN(n2) );
NOR2X0 U4 ( .IN1(x1), .IN2(x2), .QN(n1) );
endmodule

input x1, x2, x3;
output sum, carry;
wire n1, n2;

INVX0 U3 ( .INP(x3), .ZN(n2) );
NOR2X0 U4 ( .IN1(x1), .IN2(x2), .QN(n1) );
endmodule

input x1, x2, x3;
output sum, carry;
wire n1, n2;

INVX0 U3 ( .INP(x3), .ZN(n2) );
NOR2X0 U4 ( .IN1(x1), .IN2(x2), .QN(n1) );
endmodule

input x1, x2, x3;
output sum, carry;
wire n1, n2;

INVX0 U3 ( .INP(x3), .ZN(n2) );
NOR2X0 U4 ( .IN1(x1), .IN2(x2), .QN(n1) );
endmodule

input x1, x2, x3;
output sum, carry;
wire n1, n2;

INVX0 U3 ( .INP(x3), .ZN(n2) );
NOR2X0 U4 ( .IN1(x1), .IN2(x2), .QN(n1) );
endmodule
pg. 11

input x1, x2, x3;
output sum, carry;
wire n1, n2;

INVX0 U3 ( .INP(x3), .ZN(n2) );
NOR2X0 U4 ( .IN1(x1), .IN2(x2), .QN(n1) );
endmodule

input x1, x2, x3;
output sum, carry;
wire n1, n2;

INVX0 U3 ( .INP(x3), .ZN(n2) );
NOR2X0 U4 ( .IN1(x1), .IN2(x2), .QN(n1) );
endmodule

input x1, x2, x3;
output sum, carry;
wire n1, n2;

INVX0 U3 ( .INP(x3), .ZN(n2) );
NOR2X0 U4 ( .IN1(x1), .IN2(x2), .QN(n1) );
endmodule

input x1, x2, x3;
output sum, carry;
wire n1, n2;

INVX0 U3 ( .INP(x3), .ZN(n2) );
NOR2X0 U4 ( .IN1(x1), .IN2(x2), .QN(n1) );
endmodule

input x1, x2;
output sum, carry;
wire n1, n2;
pg. 12

INVX0 U3 ( .INP(x2), .ZN(n1) );
INVX0 U4 ( .INP(x1), .ZN(n2) );
endmodule

input x1, x2;
output sum, carry;
wire n1, n2;

INVX0 U3 ( .INP(x2), .ZN(n1) );
INVX0 U4 ( .INP(x1), .ZN(n2) );
endmodule

input x1, x2;
output sum, carry;
wire n1, n2;

INVX0 U3 ( .INP(x2), .ZN(n1) );
INVX0 U4 ( .INP(x1), .ZN(n2) );
endmodule

output sum, carry;

XNOR2X1 U2 ( .IN1(x1), .IN2(x2), .Q(n2) );
NOR2X0 U4 ( .IN1(x1), .IN2(n3), .QN(n4) );
INVX0 U5 ( .INP(x4), .ZN(n3) );
endmodule

output sum, carry;

XNOR2X1 U2 ( .IN1(x1), .IN2(x2), .Q(n2) );
NOR2X0 U4 ( .IN1(x1), .IN2(n3), .QN(n4) );
INVX0 U5 ( .INP(x4), .ZN(n3) );
endmodule
pg. 13
module mul_8_bit_1 ( a, b, p );
input [7:0] a;
input [7:0] b;
output [15:0] p;
wire \pp3[3] , \pp4[4] , a1, b1, e1, f1, a11, b11, c11, g11,
h11, i11, m11,
n11, o11, p11, u11, v11, w11, i1, j1, k1, o1, p1, s1, t1,
G3, G4, G5,
G6, G7, G8, G9, G10, G11, n8, n9, n10, n12, n13, n14, n15;
wire [7:0] pp0;
wire [7:0] pp1;
wire [7:0] pp2;
wire [7:0] pp5;
wire [7:0] pp6;
wire [7:0] pp7;
wire [21:0] s_t;
wire [21:0] cout_t;
APP_HA_0 h1_1 ( .x1(e1), .x2(f1), .sum(s_t[0]), .carry(cout_t[0])

);
APP_FA_0 f1_2 ( .x1(a11), .x2(b11), .x3(c11), .sum(s_t[1]),
.carry(cout_t[1]) );
compressor4_2_0 c1_1 ( .x1(g11), .x2(h11), .x3(i11), .x4(\pp3[3]
), .sum(
s_t[2]), .carry(cout_t[2]) );
compressor4_2_2 c1_2 ( .x1(m11), .x2(n11), .x3(o11), .x4(p11),
.sum(s_t[3]),
compressor4_2_1 c1_3 ( .x1(u11), .x2(v11), .x3(w11), .x4(\pp4[4]
), .sum(
s_t[4]), .carry(cout_t[4]) );
APP_FA_14 f1_3 ( .x1(i1), .x2(j1), .x3(k1), .sum(s_t[5]),
.carry(cout_t[5])
);
APP_FA_13 f1_4 ( .x1(o1), .x2(p1), .x3(pp5[5]), .sum(s_t[6]),
.carry(
cout_t[6]) );
APP_HA_3 h1_5 ( .x1(s1), .x2(t1), .sum(s_t[7]), .carry(cout_t[7])
);
APP_HA_2 h1_6 ( .x1(pp7[5]), .x2(pp5[7]), .sum(s_t[8]),
APP_HA_1 h1_7 ( .x1(pp1[0]), .x2(pp0[1]), .sum(s_t[9]),
APP_FA_12 f1_8 ( .x1(pp2[0]), .x2(pp0[2]), .x3(pp1[1]),
.sum(s_t[10]),
APP_FA_11 f1_9 ( .x1(a1), .x2(b1), .x3(G3), .sum(s_t[11]),
APP_FA_10 f1_10 ( .x1(s_t[0]), .x2(pp2[2]), .x3(G4),
.sum(s_t[12]), .carry(
cout_t[12]) );
APP_FA_9 f1_11 ( .x1(s_t[1]), .x2(G5), .x3(cout_t[0]),
.sum(s_t[13]),
pg. 14

.sum(s_t[14]),
.sum(s_t[15]),
.sum(s_t[16]),
.sum(s_t[17]),
.sum(s_t[18]),
.sum(s_t[19]),
APP_FA_2 f1_18 ( .x1(s_t[8]), .x2(pp6[6]), .x3(cout_t[7]),
.sum(s_t[20]),
APP_FA_1 f1_19 ( .x1(pp7[6]), .x2(pp6[7]), .x3(cout_t[8]),
.sum(s_t[21]),
RC_adder r_1 ( .a20(pp0[0]), .a21(s_t[9]), .a22(s_t[10]),
.a23(s_t[11]),
.a24(s_t[12]), .a25(s_t[13]), .a26(s_t[14]), .a27(s_t[15]),
.a28(
s_t[16]), .a29(s_t[17]), .a30(s_t[18]), .a31(s_t[19]),
.a32(s_t[20]),
.a33(s_t[21]), .a34(pp7[7]), .b20(1'b0), .b21(cout_t[9]),
.b22(
cout_t[10]), .b23(cout_t[11]), .b24(cout_t[12]),
.b25(cout_t[13]),
.b26(cout_t[14]), .b27(cout_t[15]), .b28(cout_t[16]),
.b29(cout_t[17]),
.b30(cout_t[18]), .b31(cout_t[19]), .b32(cout_t[20]),
.b33(cout_t[21]),
.b34(1'b0), .cin2(1'b0), .s20(p[0]), .s21(p[1]), .s22(p[2]),
.s23(p[3]), .s24(p[4]), .s25(p[5]), .s26(p[6]), .s27(p[7]),
.s28(p[8]), .s29(p[9]),
.s30(p[10]), .s31(p[11]), .s32(p[12]), .s33(p[13]),
.s34(p[14]),
.cout2(p[15]) );
AO22X1 U58 ( .IN1(b[3]), .IN2(a[5]), .IN3(b[5]), .IN4(a[3]),
.Q(w11) );
.Q(v11) );
.Q(u11) );
AO22X1 U61 ( .IN1(a[6]), .IN2(b[5]), .IN3(b[6]), .IN4(a[5]),
.Q(t1) );
AO22X1 U62 ( .IN1(b[4]), .IN2(a[7]), .IN3(a[4]), .IN4(b[7]),
.Q(s1) );
AND2X1 U63 ( .IN1(a[6]), .IN2(b[7]), .Q(pp7[6]) );
AND2X1 U64 ( .IN1(a[5]), .IN2(b[7]), .Q(pp7[5]) );
pg. 15
AND2X1 U65 ( .IN1(b[6]), .IN2(a[7]), .Q(pp6[7]) );

AND2X1 U66 ( .IN1(b[5]), .IN2(a[7]), .Q(pp5[7]) );
NOR2X0 U67 ( .IN1(n8), .IN2(n9), .QN(pp2[0]) );
.Q(p11) );
.Q(p1) );
.Q(o11) );
.Q(o1) );
.Q(n11) );
.Q(m11) );
.Q(k1) );
.Q(j1) );
.Q(i11) );
.Q(i1) );
.Q(h11) );
.Q(g11) );
.Q(f1) );
.Q(e1) );
.Q(c11) );
.Q(b11) );
.Q(b1) );
.Q(a11) );
.Q(a1) );
AO222X1 U90 ( .IN1(pp6[6]), .IN2(\pp3[3] ), .IN3(pp7[7]),
.IN4(pp2[2]),
.IN5(pp5[5]), .IN6(\pp4[4] ), .Q(G9) );
AO222X1 U91 ( .IN1(pp6[6]), .IN2(pp2[2]), .IN3(pp1[1]),
.IN4(pp7[7]), .IN5(
pp5[5]), .IN6(\pp3[3] ), .Q(G8) );
AO221X1 U92 ( .IN1(pp5[5]), .IN2(pp2[2]), .IN3(\pp4[4] ),
.IN4(\pp3[3] ),
.IN5(n15), .Q(G7) );
.IN4(pp7[7]), .Q(n15)
);
pg. 16

.IN4(pp6[6]), .IN5(
\pp4[4] ), .IN6(pp2[2]), .Q(G6) );
.IN4(pp5[5]),
.IN5(\pp3[3] ), .IN6(pp2[2]), .Q(G5) );
.IN4(\pp4[4] ), .Q(
G4) );
.IN4(\pp3[3] ), .Q(G3) );
INVX0 U99 ( .INP(a[0]), .ZN(n9) );
INVX0 U100 ( .INP(b[0]), .ZN(n13) );
INVX0 U102 ( .INP(a[2]), .ZN(n12) );
INVX0 U103 ( .INP(b[2]), .ZN(n8) );
INVX0 U105 ( .INP(a[1]), .ZN(n14) );
INVX0 U106 ( .INP(b[1]), .ZN(n10) );
AO22X1 U107 ( .IN1(pp5[5]), .IN2(pp6[6]), .IN3(\pp4[4] ),
.IN4(pp7[7]), .Q(
G11) );
AND2X1 U108 ( .IN1(a[5]), .IN2(b[5]), .Q(pp5[5]) );
AO22X1 U109 ( .IN1(\pp4[4] ), .IN2(pp6[6]), .IN3(\pp3[3] ),
.IN4(pp7[7]),
.Q(G10) );
AND2X1 U110 ( .IN1(a[7]), .IN2(b[7]), .Q(pp7[7]) );
AND2X1 U111 ( .IN1(b[3]), .IN2(a[3]), .Q(\pp3[3] ) );
AND2X1 U112 ( .IN1(a[6]), .IN2(b[6]), .Q(pp6[6]) );
AND2X1 U113 ( .IN1(b[4]), .IN2(a[4]), .Q(\pp4[4] ) );
endmodule
pg. 17

TCL Script: Gen - Netlist - TCL:: TCLSH Auto - Synth - TCL Mul - 8 - Bit.v Mul - 8 - Bit - TB.V

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DARSHIL SHAH TASK-6 17MVD0091

tclsh auto_synth.tcl mul_8_bit.v mul_8_bit_tb.v

set NETLIST_DIR netlist

analyze -library WORK -format verilog {mul_8_bit.v}

elaborate mul_8_bit -architecture verilog -library DEFAULT

report_area > ${LOG_DIR}/area.rpt

write -hierarchy -format verilog -output ${NETLIST_DIR}/

set LOG_DIR log

Information: Updating design information... (UID-85)

Combinational area: 1857.024013

Total cell area: 1857.024013

CONSTRAINT LOG FILE:

TIMING LOG FILE:

Operating Conditions: TYPICAL Library: saed90nm_typ_ht

Startpoint: a[1] (input port)

Des/Clust/Port Wire Load Model Library

Point Incr Path

r_1/f9/cout (fadd_7) 0.00 2.13 f

module APP_HA_0 ( x1, x2, sum, carry );

NAND2X0 U1 ( .IN1(n1), .IN2(n2), .QN(sum) );

module APP_FA_0 ( x1, x2, x3, sum, carry );

XNOR2X1 U1 ( .IN1(n1), .IN2(x3), .Q(sum) );

module compressor4_2_0 ( x1, x2, x3, x4, sum, carry );

NAND2X0 U1 ( .IN1(n1), .IN2(n2), .QN(sum) );

module fadd_0 ( a, b, cin, s, cout );

XOR2X1 U1 ( .IN1(cin), .IN2(n1), .Q(s) );

module fadd_1 ( a, b, cin, s, cout );

XOR2X1 U1 ( .IN1(cin), .IN2(n1), .Q(s) );

module fadd_2 ( a, b, cin, s, cout );

XOR2X1 U1 ( .IN1(cin), .IN2(n1), .Q(s) );

module fadd_3 ( a, b, cin, s, cout );

XOR2X1 U1 ( .IN1(cin), .IN2(n1), .Q(s) );

AO22X1 U2 ( .IN1(a), .IN2(b), .IN3(cin), .IN4(n1), .Q(cout) );

module fadd_4 ( a, b, cin, s, cout );

XOR2X1 U1 ( .IN1(cin), .IN2(n1), .Q(s) );

module fadd_5 ( a, b, cin, s, cout );

XOR2X1 U1 ( .IN1(cin), .IN2(n1), .Q(s) );

module fadd_6 ( a, b, cin, s, cout );

XOR2X1 U1 ( .IN1(cin), .IN2(n1), .Q(s) );

module fadd_7 ( a, b, cin, s, cout );

XOR2X1 U1 ( .IN1(cin), .IN2(n1), .Q(s) );

module fadd_8 ( a, b, cin, s, cout );

XOR2X1 U1 ( .IN1(cin), .IN2(n1), .Q(s) );

XOR2X1 U3 ( .IN1(a), .IN2(b), .Q(n1) );

module fadd_9 ( a, b, cin, s, cout );

XOR2X1 U1 ( .IN1(cin), .IN2(n1), .Q(s) );

module fadd_10 ( a, b, cin, s, cout );

XOR2X1 U1 ( .IN1(cin), .IN2(n1), .Q(s) );

module fadd_11 ( a, b, cin, s, cout );

XOR2X1 U1 ( .IN1(cin), .IN2(n1), .Q(s) );

module fadd_12 ( a, b, cin, s, cout );

XOR2X1 U1 ( .IN1(cin), .IN2(n1), .Q(s) );

module fadd_13 ( a, b, cin, s, cout );

XOR2X1 U1 ( .IN1(cin), .IN2(n1), .Q(s) );

module fadd_14 ( a, b, cin, s, cout );

XOR2X1 U1 ( .IN1(cin), .IN2(n1), .Q(s) );

fadd_0 f1 ( .a(a20), .b(b20), .cin(cin2), .s(s20), .cout(c1) );

module APP_FA_1 ( x1, x2, x3, sum, carry );