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    FinFET TEchnologies

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    surya teja
    The document reviews FinFET technology as a promising substitute for conventional MOSFETs. It discusses the structure and benefits of FinFETs, including low power consumption and reduced short channel effects. Methodology of simulating logic gates using FinFET models on HSPICE is also summarized.

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    FinFET TEchnologies

    Uploaded by

    surya teja
    173 views2 pages
    The document reviews FinFET technology as a promising substitute for conventional MOSFETs. It discusses the structure and benefits of FinFETs, including low power consumption and reduced short channel effects. Methodology of simulating logic gates using FinFET models on HSPICE is also summarized.

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    This document provides the Brief info of FinFET device

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    The document reviews FinFET technology as a promising substitute for conventional MOSFETs. It discusses the structure and benefits of FinFETs, including low power consumption and reduced short channel effects. Methodology of simulating logic gates using FinFET models on HSPICE is also summarized.

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    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    173 views2 pages

    FinFET TEchnologies

    Uploaded by

    surya teja
    The document reviews FinFET technology as a promising substitute for conventional MOSFETs. It discusses the structure and benefits of FinFETs, including low power consumption and reduced short channel effects. Methodology of simulating logic gates using FinFET models on HSPICE is also summarized.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 2

    International Journal of Technical Research (IJTR)

    Vol. 5, Issue 2, July-Aug 2016

    FinFET Technology: A Review Paper


    Shweta Kataria1, Poonam Beniwal2
    1 2
    MTech Scholar, Assistant Professor, Department of Electronics and Communication,
    Om Institute of Technology & Management, Hisar Haryana
    1
    kataria.shweta12@gmail.com, 2poonammittan249@gmail.com

    Abstract: For the improvement of performance and


    power in VLSI logic circuits, FinFET Technology is II. FINFET TECHNOLOGY- A LITERATURE SURVEY
    reviewed over conventional bulk MosFET. FinFETs are A double gate transistor is built on an SOI substrate,
    promising substitutes of MosFET over 32nm technology,
    and is based on the earlier DELTA (single gate)
    as short channel effects increase issues below 32nm
    technology. Conventional cmos logic circuits can be easily
    transistor design. The distinguishing characteristic of
    implemented using short gate or independent gate the FinFET is that the conducting channel is wrapped
    FinFET logic circuit designs. by a thin silicon “fin”, which forms the body of the
    device [3]. Over 32nm technology, there is significant
    Keywords: FinFET, Power Consumption, Delay reduction in Average power consumption when
    FinFET is used instead of MOSFET. The basic
    structure of FinFET is shown in Figure 1.
    I. INTRODUCTION
    The scaling of conventional MOSFET transistor has
    become increasingly difficult because of its large short
    channel effects below 32nm Technology. Scaling down
    of MOS device dimensions’ width and length also
    leads to lower performance and higher average power
    consumption.
    Fin-type field effect transistors (FinFET) are promising Figure 1: Structure of FinFET [5]
    substitute for bulk MOS at the nanoscale. This is
    because the fabrication technology of FinFET is almost The FinFET device structure consists of a
    the same as that of the conventional MOS transistor silicon fin surrounded by shorted or independent gate
    [1]. Due to the fact, fabrication process is similar, on either side of the fin, typically on silicon insulator
    FinFETs can easily substitute Mosfets in the near substrate. FinFET has two gates, which can be operated
    future. FinFETs are the double gate (DG) transistors independently or tied together. The threshold voltage at
    family and are basically quasi-planar in nature. They one gate can be controlled with the help of voltage at
    are termed as quasi-planar because of the fact that the the other gate. Figure 2, shows the FinFET in different
    current direction is parallel to its wafer and the channel configurations and Figure 3 shows the ID-VDS
    is formed perpendicular to it. characteristics with varying VGS in n-type FinFET
    FinFETs gate terminal can either be shorted or device [9].
    independently controlled to offer rich design space [3]. In the single-gate mode, the short channel
    The two electrically coupled gates and thin silicon effects (threshold voltage roll- off, sub threshold swing
    body of the FinFET are known very well from degradation and drain induced barrier lowering) are
    literature to suppress the short channel effects [10]. actually less severe than those of the device in the
    Dynamic MOS logic circuits are used in high double-gate mode [2].
    performance VLSI chips in order to achieve very high
    system performance. Noise is a major issue in design
    of dynamic logic circuits. In deep submicron region
    noise tolerance of dynamic logic circuit is very poor
    and they are more prone to logic failure [4]. There are
    various noise sources in dynamic logic circuits which
    are charge sharing noise, leakage noise, crosstalk noise,
    power and ground noise, substrate noise, etc. FinFETs
    Figure 2: FinFET Configurations (a) Independent
    having diverse design options and better control over Gates (b) Shorted Gates [9]
    channel provides low power configurations and higher
    noise tolerance [10]. FinFET devices can be used to increase the
    performance by reducing the leakage current and

    ISSN 2278-5787 Page 35


    International Journal of Technical Research (IJTR)
    Vol. 5, Issue 2, July-Aug 2016

    power dissipation, because front and back gates both To quantify the power and performance of the logic
    can be controlled independently or both gates and ALU techniques, certain metrics are
    simultaneously. considered. The parameters used for comparison are
    Average Power Consumption and Delay. The proposed
    logic gates using FinFET technique is compared with
    MosFET based logic gates. A comparative study of
    proposed technique using FINFET and MOSFET will
    also be analyzed on the basis of average power
    consumption and delay.
    IV. CONCLUSION
    According to the literature review, and the design space
    offered by FinFETs. It is highly possible for FinFETs
    to replace conventional MosFET under 32nm
    technology, as FinFETs based logic circuits are
    promising substitutes for conventional Mos.
    REFERENCES
    Figure 3: ID-VDS double-gate n-type FinFET Device [1] Junki Kato, CES, 2014 “Circuit design of 2 i/p
    of gate length L = 32 nm [9] reconfigurable Dynamis Logic based on DG
    MOSFETs with whole set of 16 functions”
    The effective width of a FinFET device is [2] Zhichao Lu, IEEE, Vol 28, Feb- 2007, “Short
    quantized due to the vertical gate structure. The fin Channel Effects in FinFet”
    height determines the minimum width with the two [3] Ajay N. Bhoj and Niraj K. Jha, IEEE, 2013 ,
    gates tied together, Wmin is given by, “Design of Logic Gates and Flip-Flops in High-
    Wmin = 2.Hfin + tsi performance FinFet Technology”
    Where, Hfin is fin height and tsi is the thickness of [4] R.Rajprabu, IOSR-JVSP, Vol 2, Apr- 2013,
    silicon body [6]. Typically, the fin thickness is kept “Performance analysis of CMOS and FinFet
    smaller than the fin height to reduce the short channel Logic”
    effects. The FinFET height Hfin, together with the fin [5] Sherif A.Tawfika, Elsevier, 2011, “FinFET
    pitch (determined by photolithography) defines the domino logic with independent gate keepers ”
    FinFET device width Wfin within the given silicon [6] Mahender Veshala , IJEIT 2013, “Reduction of
    width of the planar device, to get the same or better Short-Channel Effects in FinFET”
    device strength [8]. [7] V Narendar , IJCA, 2012 , “Design of High-
    The key benefits of FinFET technology over performance Digital Logic Circuits based on
    MOSFET includes low off currents, higher on currents, FinFET Technology ”
    lower average power consumption and reduces short [8] PC Rajashree, ICIET-2014, “Deep Submicron
    channel effects (SCEs) . 50nm CMOS Logic Design With FINFET”
    Research groups and companies such as Intel, IBM, [9] Tushar Surwadkar, IJETT-2014, “Upgrading the
    have shown interest in developing similar devices, as performance of VLSI Circuits using FinFETs”
    well as mechanisms to migrate mask layouts from bulk [10] Sneha Arora, Umesh Dutta, Vipin Kumar Sharma,
    MOSFET to FinFET . "A Noise Tolerant and Low Power Dynamic Logic
    Circuit Using Finfet Technology"Vol. 5 - Issue 12
    III. METHODOLOGY
    (December - 2015), International Journal of
    The methodology used for thesis work is reviewed
    Engineering Research and Applications (IJERA),
    deeply in this paper. The logic gates used in ALU are
    simulated on HSPICE Software tool. The model used ISSN: 2248-9622, www.ijera.com
    for FinFET circuit analysis on HSPICE is BSIM-CMG
    for 32nm FinFET Technology.
    BSIM-CMG is a transistor model by BSIM for Multi-
    Gate transistors and is implemented in Verilog-A. This
    model describes all the important characteristic
    behavior of Multi gate transistors. It is physics based
    model which is scalable and predictive over a wide
    range of device parameters [10].

    ISSN 2278-5787 Page 36

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