Thi Nghiem 4 (Ta)
Thi Nghiem 4 (Ta)
Thi Nghiem 4 (Ta)
I. Target:
_ To design a Nios II Processor system for showing the last 3 bytes received from
PS/2 gates on LCD screen
The project name has to be the same with folder name lab4.
6. Click Next
7. Select Cyclone II
Available devices : Select Chọn EP2C35F672C6
Click Next
8. Click Next.
9. Click Finish.
10. Click New
11. Select Verilog HDL File -> click OK
III. Create SOPC:
1. Click SOPC Builder to create SOPC
9. Select University Program -> Generic IO -> PS2 Controller -> Finish.
10. Click on Auto-Assign Base Addresses in tab System 11. Choose Generate.
If system generation was successful, save and then exit SOPC builder
IV. Verilog code:
module lab4(
// Inputs
CLOCK_50,
CLOCK_27,
EXT_CLOCK,
KEY,
SW,
// Communication
UART_RXD,
// Audio
AUD_ADCDAT,
/******************************************************************
***********/
// Bidirectionals
GPIO_0,
GPIO_1,
// Memory (SRAM)
SRAM_DQ,
// Memory (SDRAM)
DRAM_DQ,
// PS2 Port
PS2_CLK,
PS2_DAT,
// Audio
AUD_BCLK,
AUD_ADCLRCK,
AUD_DACLRCK,
// AV Config
I2C_SDAT,
/******************************************************************
***********/
// Outputs
TD_RESET,
// Simple
LEDG,
LEDR,
HEX0,
HEX1,
HEX2,
HEX3,
HEX4,
HEX5,
HEX6,
HEX7,
// Memory (SRAM)
SRAM_ADDR,
SRAM_CE_N,
SRAM_WE_N,
SRAM_OE_N,
SRAM_UB_N,
SRAM_LB_N,
// Communication
UART_TXD,
// Memory (SDRAM)
DRAM_ADDR,
DRAM_BA_1,
DRAM_BA_0,
DRAM_CAS_N,
DRAM_RAS_N,
DRAM_CLK,
DRAM_CKE,
DRAM_CS_N,
DRAM_WE_N,
DRAM_UDQM,
DRAM_LDQM,
// Audio
AUD_XCK,
AUD_DACDAT,
// VGA
VGA_CLK,
VGA_HS,
VGA_VS,
VGA_BLANK,
VGA_SYNC,
VGA_R,
VGA_G,
VGA_B,
// AV Config
I2C_SCLK,
);
/******************************************************************
***********
* Parameter Declarations *
******************************************************************
***********/
/******************************************************************
***********
* Port Declarations *
******************************************************************
***********/
// Inputs
input CLOCK_50;
input CLOCK_27;
input EXT_CLOCK;
input [3:0] KEY;
input [17:0] SW;
// Communication
input UART_RXD;
// Audio
input AUD_ADCDAT;
// Bidirectionals
inout [35:0] GPIO_0;
inout [35:0] GPIO_1;
// Memory (SRAM)
inout [15:0] SRAM_DQ;
// Memory (SDRAM)
inout [15:0] DRAM_DQ;
// PS2 Port
inout PS2_CLK;
inout PS2_DAT;
// Audio
inout AUD_BCLK;
inout AUD_ADCLRCK;
inout AUD_DACLRCK;
// AV Config
inout I2C_SDAT;
// Outputs
output TD_RESET;
// Simple
output [8:0] LEDG;
output [17:0] LEDR;
// Memory (SRAM)
output [17:0] SRAM_ADDR;
output SRAM_CE_N;
output SRAM_WE_N;
output SRAM_OE_N;
output SRAM_UB_N;
output SRAM_LB_N;
// Communication
output UART_TXD;
// Memory (SDRAM)
output [11:0] DRAM_ADDR;
output DRAM_BA_1;
output DRAM_BA_0;
output DRAM_CAS_N;
output DRAM_RAS_N;
output DRAM_CLK;
output DRAM_CKE;
output DRAM_CS_N;
output DRAM_WE_N;
output DRAM_UDQM;
output DRAM_LDQM;
// Audio
output AUD_XCK;
output AUD_DACDAT;
// VGA
output VGA_CLK;
output VGA_HS;
output VGA_VS;
output VGA_BLANK;
output VGA_SYNC;
output [ 9: 0] VGA_R;
output [ 9: 0] VGA_G;
output [ 9: 0] VGA_B;
// AV Config
output I2C_SCLK;
/******************************************************************
***********
* Internal Wires and Registers Declarations *
******************************************************************
***********/
// Internal Wires
// Used to connect the Nios 2 system clock to the non-shifted output of the PLL
wire system_clk;
// Internal Registers
/******************************************************************
***********
* Finite State Machine(s) *
******************************************************************
***********/
/******************************************************************
***********
* Sequential Logic *
******************************************************************
***********/
/******************************************************************
***********
* Combinational Logic *
******************************************************************
***********/
// Output Assignments
assign TD_RESET = 1'b1;
assign GPIO_0[ 0] = 1'bZ;
assign GPIO_0[ 2] = 1'bZ;
assign GPIO_0[16] = 1'bZ;
assign GPIO_0[18] = 1'bZ;
assign GPIO_1[ 0] = 1'bZ;
assign GPIO_1[ 2] = 1'bZ;
assign GPIO_1[16] = 1'bZ;
assign GPIO_1[18] = 1'bZ;
/******************************************************************
***********
* Internal Modules *
******************************************************************
***********/
nios_system NiosII(
// 1) global signals:
.clk_0(CLOCK_50),
.reset_n(KEY[0]),
// the_PS_2
.PS2_CLK_to_and_from_the_PS_2(PS2_CLK),
.PS2_DAT_to_and_from_the_PS_2(PS2_DAT),
// the_SRAM
.SRAM_ADDR_from_the_SRAM(SRAM_ADDR),
.SRAM_CE_N_from_the_SRAM(SRAM_CE_N),
.SRAM_DQ_to_and_from_the_SRAM(SRAM_DQ),
.SRAM_LB_N_from_the_SRAM(SRAM_LB_N),
.SRAM_OE_N_from_the_SRAM(SRAM_OE_N),
.SRAM_UB_N_from_the_SRAM(SRAM_UB_N),
.SRAM_WE_N_from_the_SRAM(SRAM_WE_N),
// the_character_lcd_0
.LCD_BLON_from_the_character_lcd_0(LCD_BLON),
.LCD_DATA_to_and_from_the_character_lcd_0(LCD_DATA),
.LCD_EN_from_the_character_lcd_0(LCD_EN),
.LCD_ON_from_the_character_lcd_0(LCD_ON),
.LCD_RS_from_the_character_lcd_0(LCD_RS),
.LCD_RW_from_the_character_lcd_0(LCD_RW)
)
;
wire a, b;
// sdram_pll neg_3ns (CLOCK_50, DRAM_CLK, system_clk);
//temp_pll aud_clk (1'b0, CLOCK_27, a, AUD_XCK, b);
endmodule
3. Start COMPILE
#include "altera_up_avalon_character_lcd.h"
#include "altera_up_avalon_ps2.h"
#include "altera_up_ps2_keyboard.h"
#include "sys/alt_stdio.h"
#include "system.h"
#include <string.h>
#include <unistd.h>
int main(){
char text_top_row[40] = "Digital System\0";
char text_bottom_row[40] = "Lab4 Ps2\0";
//char buffer[50];
//int delay;
alt_up_character_lcd_dev *lcd_dev;
alt_up_ps2_dev *ps2_dev;
ps2_dev=alt_up_ps2_open_dev("/dev/PS_2");
alt_up_ps2_init(ps2_dev);
/*used for PS_2 port data*/
alt_u8 byte1;
char byte2;
KB_CODE_TYPE decode_mode;
case 0x45:
alt_up_character_lcd_set_cursor_pos(lcd_dev,0,0);
alt_up_character_lcd_string(lcd_dev,first_row26);
break;
case 0x16:
alt_up_character_lcd_set_cursor_pos(lcd_dev,0,0);
alt_up_character_lcd_string(lcd_dev,first_row27);
break;
case 0x1e:
alt_up_character_lcd_set_cursor_pos(lcd_dev,0,0);
alt_up_character_lcd_string(lcd_dev,first_row28);
break;
case 0x26:
alt_up_character_lcd_set_cursor_pos(lcd_dev,0,0);
alt_up_character_lcd_string(lcd_dev,first_row29);
break;
case 0x25:
alt_up_character_lcd_set_cursor_pos(lcd_dev,0,0);
alt_up_character_lcd_string(lcd_dev,first_row30);
break;
case 0x2e:
alt_up_character_lcd_set_cursor_pos(lcd_dev,0,0);
alt_up_character_lcd_string(lcd_dev,first_row31);
break;
case 0x36:
alt_up_character_lcd_set_cursor_pos(lcd_dev,0,0);
alt_up_character_lcd_string(lcd_dev,first_row32);
break;
case 0x3d:
alt_up_character_lcd_set_cursor_pos(lcd_dev,0,0);
alt_up_character_lcd_string(lcd_dev,first_row33);
break;
case 0x3e:
alt_up_character_lcd_set_cursor_pos(lcd_dev,0,0);
alt_up_character_lcd_string(lcd_dev,first_row34);
break;
case 0x46:
alt_up_character_lcd_set_cursor_pos(lcd_dev,0,0);
alt_up_character_lcd_string(lcd_dev,first_row35);
break;
}
}
}
7. Save and right click on lab4 -> Build Project
1. USB Blaster:
2. Run as