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    Load Electric

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    roxy8marie8chan
    1. The document describes simulating NOR and NAND gates with different widths for the PMOS and NMOS transistors. 2. Tables are included that show propagation delay times for the gates with varying transistor widths. 3. The simulations are done in a library and the circuits are verified against truth tables to check functionality.

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    Load Electric

    Uploaded by

    roxy8marie8chan
    43 views7 pages
    1. The document describes simulating NOR and NAND gates with different widths for the PMOS and NMOS transistors. 2. Tables are included that show propagation delay times for the gates with varying transistor widths. 3. The simulations are done in a library and the circuits are verified against truth tables to check functionality.

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    1. The document describes simulating NOR and NAND gates with different widths for the PMOS and NMOS transistors. 2. Tables are included that show propagation delay times for the gates with varying transistor widths. 3. The simulations are done in a library and the circuits are verified against truth tables to check functionality.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    43 views7 pages

    Load Electric

    Uploaded by

    roxy8marie8chan
    1. The document describes simulating NOR and NAND gates with different widths for the PMOS and NMOS transistors. 2. Tables are included that show propagation delay times for the gates with varying transistor widths. 3. The simulations are done in a library and the circuits are verified against truth tables to check functionality.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
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    1.

    Load Electric

    .
    2. Open the library Exercise.

    3. Create new facet NOR_sch in library Exercise with schematic as the facet view. Draw
    the NOR schematic in Figure 3-a.
    Note: Lp, Ln = 0.35μm; Wp = 3.2μm; Wn = 0.8μm
    4. Save the NOR schematic.

    5. Create an icon for the NOR_sch{sch}. Save the icon facet. Close the NOR_sch{ic}
    and the NOR_sch{sch} design windows.

    6. Create new facet NOR_sch_tst with schematic as the facet view.


    7. Click on Edit → New Facet Instance. Choose library Exercise. Select NOR_sch{ic}
    from this library. Click on the design window.
    Note: Lp, Ln = 0.35μm; Wp = 3.2μm; Wn = 0.8μm

    8. Click on Export → Re-Export Everything. Add other necessary components for


    simulation. Please refer to Figure 3-b. Save the schematic.

    9. Create a SPICE netlist of your circuit. Simulate the circuit using WinSpice. Verify if
    the circuit is working properly by referring to the truth table of a NOR gate.

    10. Fill-up the table below. Round off your answers to two decimal places.
    Wn Wp TPHL TPLH
    0.80μm 3.20μm 0.71ns 0.45ns
    0.80μm 1.60μm 0.65ns 0.82ns
    0.80μm 0.80μm 0.62ns 1.75ns

    Wp = 3.20 μm

    Wp = 1.60 μm
    Wp = 0.80μm
    11. Repeat procedures 3 - 9 for a NAND gate (Figure 3-c and 3-d). Verify if the circuit is
    working properly by referring to the truth table of a NAND gate (Table 3-a).
    Note: Lp, Ln = 0.35μm; Wp = 3.2μm; Wn = 1.6μm
    12. Fill-up the table below. Round off your answers to two decimal places.
    Wn Wp TPHL TPLH
    1.6μ 3.20μ 0.46ns 0.33ns
    1.6μ 1.60μ 0.40ns 0.55ns
    1.6μ 0.80μ 0.37ns 1.07ns
    Wp = 3.20 μ

    Wp = 1.60μ
    Wp = 0.80μ

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