Pulse-Width Modulated Rectifiers: Fundamentals of Power Electronics Chapter 18: PWM Rectifiers

Chapter 18
Pulse-Width Modulated Rectifiers
18.1 Properties of the ideal rectifier

18.2 Realization of a near-ideal rectifier
18.3 Control of the current waveform
18.4 Single-phase converter systems employing ideal rectifiers
18.5 RMS values of rectifier waveforms
18.6 Modeling losses and efficiency in CCM high-quality rectifiers
18.7 Ideal three-phase rectifiers
Fundamentals of Power Electronics 1 Chapter 18: PWM Rectifiers

18.1 Properties of the ideal rectifier
It is desired that the rectifier present a resistive load to the ac power

system. This leads to
• unity power factor
• ac line current has same waveshape as voltage
vac(t) iac(t)
i ac(t) =
Re +
Re is called the emulated resistance vac(t) Re

Control of power throughput
V 2ac,rms iac(t)
Pav =
Re(vcontrol)
+
vac(t) Re(vcontrol)
Power apparently “consumed” by Re
is actually transferred to rectifier dc
output port. To control the amount –
of output power, it must be possible
to adjust the value of Re. vcontrol

Output port model
The ideal rectifier is iac(t) Ideal rectifier (LFR) i(t)

lossless and contains + 2 +
p(t) = vac /Re
no internal energy
storage. Hence, the
vac(t) Re(vcontrol) v(t)
instantaneous input
power equals the
instantaneous output – –
power. Since the ac dc
instantaneous power is input output
independent of the dc vcontrol
load characteristics, the
output port obeys a
power source v 2ac(t) v 2ac(t)
p(t) = v(t)i(t) = p(t) =
characteristic. Re(vcontrol(t)) Re

The dependent power source
i(t)
i(t) i(t) v(t)i(t) = p(t)

+ +
p(t) v(t) v(t) p(t)

v(t)
– –
power power
source sink
i-v characteristic

Equations of the ideal rectifier / LFR
Defining equations of the When connected to a

ideal rectifier: resistive load of value R, the
input and output rms voltages
and currents are related as
vac(t) follows:
i ac(t) =
Re(vcontrol)
Vrms R
=
v(t)i(t) = p(t) Vac,rms Re
v 2ac(t)
p(t) = I ac,rms R
Re(vcontrol(t)) =
I rms Re

18.2 Realization of a near-ideal rectifier
Control the duty cycle of a dc-dc

converter, such that the input current
is proportional to the input voltage:
dc–dc converter
ig(t) 1 : M(d(t)) i(t)
iac(t) + +
vac(t) vg(t) v(t) C R
– –
d(t)
ig
Controller
vg

Waveforms
vac(t) ig(t)
VM
v(t) V
iac(t)
VM /Re
t M(t)
Mmin
vg(t)
VM
v(t) V
vac(t) = VM sin (ωt) M(d(t)) = =
vg(t) VM sin (ωt)
vg(t) = VM sin (ωt)
M min = V
VM
Output-side current
Averaged vg(t)i g(t) v 2g(t) Averaged

over i(t) = = V 2M
V VRe over ac line I = i(t) =
switching TL 2VRe
V 2M period V 2M
period i(t) = sin 2 (ωt) P=
VRe 2Re
V 2M
= 1 – cos (2ωt)
2VRe dc–dc converter
ig(t) 1 : M(d(t)) i(t)
iac(t) + +
vac(t) vg(t) v(t) C R
– –
d(t)
ig
Controller
vg
Choice of converter
v(t) V M(t)
M(d(t)) = =
vg(t) VM sin (ωt)
Mmin
• To avoid distortion near line voltage zero crossings, converter should

be capable of producing M(d(t)) approaching infinity
• Above expression neglects converter dynamics
• Boost, buck-boost, Cuk, SEPIC, and other converters with similar
conversion ratios are suitable
• We will see that the boost converter exhibits lowest transistor
stresses. For this reason, it is most often chosen

18.2.1 CCM Boost converter
with controller to cause input current to follow input voltage
Boost converter
ig(t) i(t)
iac(t) + +
L D1
vac(t) vg(t) Q1 C v(t) R
– –
vg(t) ig(t) d(t)
Controller
• DC output voltage ≥ peak AC input voltage

• Controller varies duty cycle as necessary to make ig(t) proportional
to vg(t)

Variation of duty cycle in boost rectifier
v(t) V
M(d(t)) = =
vg(t) VM sin (ωt)
Since M ≥ 1 in the boost converter, it is required that V ≥ VM

If the converter operates in CCM, then
M(d(t)) = 1
1 – d(t)
The duty ratio should therefore follow
vg(t)
d(t) = 1 – in CCM
V

CCM/DCM boundary, boost rectifier
Inductor current ripple is

vg(t)d(t)Ts
∆i g(t) =
2L
Low-frequency (average) component of inductor current waveform is
vg(t)
i g(t) =
Ts Re
The converter operates in CCM when
i g(t) > ∆i (t) ⇒ d(t) < 2L

g
Ts ReTs
Substitute CCM expression for d(t):
Re < 2L for CCM
vg(t)
Ts 1 –
V
CCM/DCM boundary
Re < 2L for CCM

vg(t)
Ts 1 –
V
Note that vg(t) varies with time, between 0 and VM. Hence, this
equation may be satisfied at some points on the ac line cycle, and not
at others. The converter always operates in CCM provided that
Re < 2L
Ts
The converter always operates in DCM provided that
Re > 2L
VM
Ts 1 –
V
For Re between these limits, the converter operates in DCM when vg(t)
is near zero, and in CCM when vg(t) approaches VM.
Static input characteristics
of the boost converter
A plot of input current ig(t) vs input voltage vg(t), for various duty cycles
d(t). In CCM, the boost converter equilibrium equation is
vg(t)
= 1 – d(t)
V
The input characteristic in DCM is found by solution of the averaged
DCM model (Fig. 11.12(b)):
p(t)
V – vg(t)
ig(t) Solve for input current:
+ vg(t) p(t)
i g(t) = +
2L V – vg(t)
+ 2L +
vg(t)
– d 2T s
p(t) –
V
d 2T s
– v 2g(t)
with p(t) =
Beware! This DCM Re(d) from 2L
Chapter 11 is not the same as the d 2T s
rectifier emulated resistance Re = vg/ig
Static input characteristics
of the boost converter
Now simplify DCM current expression, to obtain
2L i (t) 1 – vg(t) = d 2(t) vg(t)

VTs g V V
CCM/DCM mode boundary, in terms of vg(t) and ig(t):
2L i (t) > vg(t) 1–

vg(t)
VTs g V V

Boost input characteristics
with superimposed resistive characteristic
1
d=1
d = 0.8
d = 0.6
d = 0.4
d = 0.2
d=0
CCM:
vg(t)
= 1 – d(t)
0.75 V
jg(t) = 2L i g(t)
DCM:
2L i (t) 1 – vg(t) = d 2(t) vg(t)
VT s
0.5 VTs g V V
t) /R e
= v g(
)
i g(t CCM when
0.25 CCM
2L i (t) > vg(t) 1–
vg(t)
DCM VTs g V V
0
0 0.25 0.5 0.75 1
vg(t)
m g(t) =
V
Open-loop DCM approach
We found in Chapter 11 that the buck-boost, SEPIC, and Cuk

converters, when operated open-loop in DCM, inherently behave as
loss-free resistors. This suggests that they could also be used as
near-ideal rectifiers, without need for a multiplying controller.
Advantage: simple control
Disadvantages: higher peak currents, larger input current EMI
Like other DCM applications, this approach is usually restricted to low
power (< 200W).
The boost converter can also be operated in DCM as a low harmonic
rectifier. Input characteristic is
vg(t) v 2g(t)
i g(t) T = +
s Re R v(t) – v (t)
e g
Input current contains harmonics. If v is sufficiently greater than vg,

then harmonics are small.
Other similar approaches
• Use of other converters (in CCM) that are capable of increasing the
voltage:
SEPIC, Cuk, buck-boost
Flyback, isolated versions of boost, SEPIC, Cuk, etc.
• Boundary or critical conduction mode: operation of boost or other
converter at the boundary between CCM and DCM
• Buck converter: distortion occurs but stresses are low
• Resonant converter such as parallel resonant converter or some
quasi-resonant converters
• Converters that combine the functions of rectification, energy
storage, and dc-dc conversion

18.2.2 DCM flyback converter
EMI filter Flyback converter

ig(t) n:1 i(t)
iac(t) +
+ D1
L
vac(t) v(t) C R
vg(t)
Q1 –
–
Operation in DCM: we found in Chapter 11 that the converter input

port obeys Ohm’s law with effective resistance Re = 2n2L/D2Ts.
Hence, simply connect input port to AC line.

Averaged large-signal model
EMI filter Averaged model

〈 ig(t) 〉T 〈 i(t) 〉T
iac(t) + +
vac(t) vg(t) 2n 2L 〈 p(t) 〉T 〈v(t)〉T C R

D 2T s
– –
• Under steady-state conditions, operate with constant D

• Adjust D to control average power drawn from AC line

Converter design
Select L small enough that DCM i1(t)

operation occurs throughout AC line Area q1 ipk
cycle. DCM occurs provided that
d3 > 0, or
i 1(t) Ts
d 2(t) < 1 – D
But
vg(t) t
d 2(t) = D d1Ts d2Ts d3Ts
nV Ts
Substitute and solve for D:
D< 1 To obtain DCM at all points on
vg(t) input AC sinusoid: worst case is at
1+ maximum vg(t) = VM :
nV
Converter operates in DCM in D< 1
every switching period where V
above inequality is satisfied. 1+ M
nV

Choice of L
to obtain DCM everywhere along AC sinusoid
We have: D< 1 with Vrms R

V =
1+ M
Vac,rms Re
nV
Substitute expression for Re to obtain Worst-case design
D = 2nV L For variations in load
VM RT s resistance and ac input
voltage, the worst case
Solve for L: occurs at maximum load
RT s power and minimum ac input
L < L crit = 2
4 1 + nV voltage. The inductance
VM should be chosen as follows:
Rmin T s
L < L crit-min = 2
4 1 + nV
V M-min

18.3 Control of the Current Waveform
18.3.1 Average current control

Feedforward
18.3.2 Current programmed control
18.3.3 Critical conduction mode and hysteretic control
18.3.4 Nonlinear carrier control

18.3.1 Average current control
ig(t)
+
L
Boost example
vg(t) + v(t)
Low frequency –
(average) component
–
of input current is
controlled to follow
Gate
input voltage driver
+
–
Pulse width
modulator
va(t) Gc(s) Compensator

≈ Rs 〈 ig(t)〉T
s
–
+
Current v (t)
reference r

Block diagram
Boost converter
• Current ig(t) i(t)
reference iac(t) + +
L D1
derived
from input vac(t) vg(t) Q1 C v(t) R
voltage
– –
waveform
vcontrol (t) vg(t) ig(t)
• Multiplier allows Rs
PWM
control of emulated Multiplier X va(t)
resistance value v (t)
+– err Gc(s)
vr (t)
• Compensation of = kx vg(t) vcontrol (t) Compensator
current loop Controller

The emulated resistance
• Current sensor has ig(t)

Boost converter
i(t)
gain Rs : iac(t) + +
L D1
va(t) = Rs i g(t)
Ts vac(t) vg(t) Q1 C v(t) R
• If loop is well – –
designed, then: vcontrol (t) vg(t) ig(t)
va(t) ≈ vr (t) Multiplier X

Rs
PWM
va(t)
• Multiplier: v (t)
+– err Gc(s)
vr (t)
vr(t) = k x vg(t) vcontrol(t) = kx vg(t) vcontrol (t) Compensator
Controller
• Hence the emulated resistance is:
vr (t) which can be simplified to
vg(t) k xvcontrol (t)
Re = = Rs
i g(t) va(t) Re vcontrol(t) =
k xvcontrol(t)
Rs
System model using LFR
Average current control
〈ig(t)〉Ts Ideal rectifier (LFR) 〈i(t)〉T

s
+ +
iac(t) 〈 p(t)〉Ts
vac(t) 〈vg(t)〉T Re C 〈v(t)〉T R

s s
– –
Re(t) vcontrol (t)

Rs
Re(t) =
k x vcontrol(t)

Use of multiplier to control average power
ig(t)
As discussed in Chapter
+
17, an output voltage
feedback loop adjusts the vg(t) + C v(t)
–
emulated resistance Re
such that the rectifier –
power equals the dc load
power: Gate
driver
+
–
V 2g,rms
Pav = = Pload vg(t) Pulse width
Re modulator

An analog multiplier Multiplier
introduces the x
kx xy
vref1(t)
+
– verr(t)
dependence of Re y v(t)
on v(t). vcontrol(t) –
Gcv(s)
+
vref2(t)
Voltage reference

Feedforward
Feedforward is sometimes ig(t)

used to cancel out +
disturbances in the input
+
voltage vg(t). vg(t)
–
v(t)
To maintain a given power –

throughput Pav, the reference
voltage vref1(t) should be Gate
driver
+
–
Pavvg(t)Rs Pulse width
vref 1(t) = vg(t)
modulator
V 2g,rms
multiplier
x
Peak xy vref1(t) –
detector V z kv +
z2
M y
vcontrol(t) –
Gcv(s)
+
vref2(t)
Voltage reference

Feedforward, continued
Controller with feedforward ig(t)
produces the following reference: +
k vvcontrol(t)vg(t) vg(t) + v(t)

vref 1(t) = –
V 2M
–
The average power is then
Gate
given by driver
+
–
k vvcontrol(t) vg(t) Pulse width
Pav = modulator
2Rs
multiplier
x
Peak xy vref1(t) –
detector V z kv +
z2
M y
vcontrol(t) –
Gcv(s)
+
vref2(t)
Voltage reference

Modeling the inner wide-bandwidth
average current controller
Averaged (but not linearized) boost converter model:

L
〈i(t)〉T 〈i1(t)〉T + +
s s
〈vg(t)〉Ts + 〈v1(t)〉Ts + 〈i2(t)〉Ts 〈v2(t)〉Ts C R 〈v(t)〉T

– – s
– –
Averaged switch network
In Chapter 7, vg(t) Ts
= Vg + vg(t) Problem: variations in vg,
we perturbed d(t) = D + d(t) ⇒ d'(t) = D' – d(t)
i1 , and d are not small.
and linearized i(t) T = i 1(t) T = I + i(t) So we are faced with the
s s
using the design of a control
v(t) = v2(t) = V + v(t)
assumptions Ts Ts
system that exhibits
v1(t) = V1 + v1(t)
Ts significant nonlinear
i 2(t) Ts
= I 2 + i 2(t) time-varying behavior.

Linearizing the equations of the boost rectifier
When the rectifier operates near steady-state, it is true that

v(t) Ts
= V + v(t)
with
v(t) << V
In the special case of the boost rectifier, this is sufficient to linearize

the equations of the average current controller.
The boost converter average inductor voltage is
d i g(t) Ts
L = vg(t) – d'(t)V – d'(t)v(t)
dt Ts
substitute:
d i g(t) Ts
L = vg(t) – d'(t)V – d'(t)v(t)
dt Ts

Linearized boost rectifier model
d i g(t) Ts
L = vg(t) – d'(t)V – d'(t)v(t)
dt Ts
The nonlinear term is much smaller than the linear ac term. Hence, it
can be discarded to obtain
d i g(t) Ts
L = vg(t) – d'(t)V
dt Ts
L
Equivalent circuit:
i g(t)
Ts
vg(t) + + d'(t)V
i g(s) V Ts – –
=
d(s) sL

The quasi-static approximation
The above approach is not sufficient to linearize the equations needed to

design the rectifier averaged current controllers of buck-boost, Cuk,
SEPIC, and other converter topologies. These are truly nonlinear time-
varying systems.
An approximate approach that is sometimes used in these cases: the
quasi-static approximation
Assume that the ac line variations are much slower than the converter
dynamics, so that the rectifier always operates near equilibrium. The
quiescent operating point changes slowly along the input sinusoid, and we
can find the slowly-varying “equilibrium” duty ratio as in Section 18.2.1.
The converter small-signal transfer functions derived in Chapters 7 and 8
are evaluated, using the time-varying operating point. The poles, zeroes,
and gains vary slowly as the operating point varies. An average current
controller is designed, that has a positive phase margin at each operating
point.

Quasi-static approximation: discussion
• In the literature, several authors have reported success using this

method
• Should be valid provided that the converter dynamics are suffieiently
fast, such that the converter always operates near the assumed
operating points
• No good condition on system parameters, which can justify the
approximation, is presently known for the basic converter topologies
• It is well-understood in the field of control systems that, when the
converter dynamics are not sufficiently fast, then the quasi-static
approximation yields neither necessary nor sufficient conditions for
stability. Such behavior can be observed in rectifier systems. Worst-
case analysis to prove stability should employ simulations.

18.3.2 Current programmed control
Current programmed Boost converter

control is a natural ig(t) L i2(t)
approach to obtain input +
D1
resistor emulation:
vg(t) + Q1 C v(t) R
–
Peak transistor current is
programmed to follow –
input voltage. vg(t)
is(t)
Peak transistor current ma
Clock
differs from average
++
ia(t)
inductor current, 0 Ts
vcontrol(t) S Q
because of inductor
current ripple and +
R
Multiplier X –
artificial ramp. This leads ic(t) Comparator Latch
to significant input = kx vg(t) vcontrol(t)
current waveform Current-programmed controller
distortion.
CPM boost converter: Static input characteristics
Static input characteristics of

Li 2c (t) fs CPM boost, with minimum
vg(t) in DCM
V – vg(t) vg(t) + m a L slope compensation:
i g(t) =
Ts
vg(t) vg(t)
i c(t) – 1 – ma + T s in CCM
V L 1
ma = V
base
base
2L
ase
Re = 0.1R
.2R
0.8 Rbase = 2L
b
Mode boundary: CCM occurs when
0.33R
Ts
Re = 0
Rbase
ase
V
b
0.5R
Re =
TsV vg(t) vg(t)
Ts
0.6
i g(t) > 1–
e
bas
Re =
2L V V
jg(t) = i g(t)
Ts
R
R =
e
bas
e
TsV m a L vg(t) vg(t)
R
0.4
or,
=2
i c(t) > + 1– CCM
L V V V
e
R
e
bas
R
0.2
=4
vg(t) DCM
e
b as
It is desired that
R
i c(t) =
R
10
Re Re =
0
0.0 0.2 0.4 0.6 0.8 1.0
Minimum slope compensation: vg(t)
ma = V V
2L
Input current waveforms
with current mode control
1.0 • Substantial
i g(t)
Peak i g ma = V
distortion can
2L occur
0.8 Rbase = 2L
Ts
• Can meet
ase
id
harmonic limits
b
uso
2R
0.6
if the range of
Sin
Re =
ase
Rb
operating points
0.33
0.4 is not too large

Re =
e
bas
• Difficult to meet
0.1R
0.2
harmonic limits
R =
e
in a universal
0.0 input supply
ωt

18.3.3 Critical conduction mode
and hysteretic control
Variable switching ig(t)

Hysteretic
frequency schemes control
• Hysteretic control
• Critical conduction
mode (boundary
between CCM and ωt
DCM)
ig(t)
Critical
conduction
mode
ωt
ton

An implementation of critical conduction control
EMI filter Boost converter

ig(t) i(t)
iac(t) + +
L D1
vac(t) vg(t) Q1 C v(t) R
– –
vcontrol (t) vg(t)
Rs Zero current
Multiplier X ig detector S Q
va(t)
+
– R
vr (t) Comparator Latch
= kx vg(t) vcontrol (t)
Controller

Pros and cons of critical conduction control
• Simple, low-cost controller ICs

• Low-frequency harmonics are very small, with constant transistor
on-time (for boost converter)
• Small inductor
• Increased peak current
• Increased conduction loss, reduced switching loss
• Requires larger input filter
• Variable switching frequency smears out the current EMI spectrum
• Cannot synchronize converter switching frequencies

Analysis
ig(t)
Transistor is on for fixed time ton

Transistor off-time ends when
inductor current reaches zero
Ratio of vg(t) to 〈ig(t)〉 is
ωt
Re = 2L
t on
ton
Inductor volt-second balance:

On time, as a function of load
power and line voltage: vg t on + vg – V t off = 0
t on = 4LP Solve for toff:
V 2M
vg
t off = t on
V – vg

Switching frequency variations
Solve for how the controller varies the switching frequency over the ac
line period:
T s = t off + t on T s = 4LP 1
V 2M vg(t)
1–
V
For sinusoidal line voltage variations, the switching frequency will
therefore vary as follows:
1 V 2M V
fs = = 1 – M sin (ωt)
T s 4LP V
Minimum and maximum limits on switching frequency:

V 2M V 2M V
max fs = min fs = 1– M
4LP 4LP V
These equations can be used to select the value of the inductance L.

18.3.4 Nonlinear carrier control
• Can attain simple control of input current waveform without sensing

the ac input voltage, and with operation in continuous conduction
mode
• The integral of the sensed switch current (charge) is compared to a
nonlinear carrier waveform (i.e., a nonlinear ramp), on a cycle-by-
cycle basis
• Carrier waveform depends on converter topology
• Very low harmonics in CCM. Waveform distortion occurs in DCM.
• Peak current mode control is also possible, with a different carrier

Controller block diagram
Nonlinear carrier charge control of boost converter
Boost converter
L D1
ig(t) is(t)
+
is(t)
vg(t) + C v(t) R
–
:1
Q1
n
is /n Comparator Latch vc(t)

vi (t)
+
Ci –
R Q
vc(t) S Q vi (t)
– vi (t) +
Nonlinear carrier
generator 0 Ts 0 dTs Ts
vcontrol (t) Clock
Nonlinear-carrier charge controller

Derivation of NLC approach
The average switch current is

t + Ts
i s(t) T = 1 i s(τ)dτ
s Ts t
We could make the controller regulate the average switch current by
• Integrating the monitored switch current
• Resetting the integrator to zero at the beginning of each
switching period
• Turning off the transistor when the integrator reaches a
reference value
In the controller diagram, the integrator follows this equation:
dT s i s(τ)
vi(t) = 1 n dτ for 0 < t < dT s
Ci 0
i.e., is Ts
vi(dT s) = for interval 0 < t < T s
nC i fs
How to control the average switch current
Input resistor emulation:

vg(t)
Ts
i g(t) =
Ts Re(vcontrol)
Relate average switch current to input current (assuming CCM):

i s(t) Ts
= d(t) i g(t)
Ts
Relate input voltage to output voltage (assuming CCM):
vg(t) = d′(t) v(t) Ts

Ts
Substitute above equations to find how average switch current should

be controlled:
v(t) Ts
i s(t) = d(t) 1 – d(t)
Ts Re(vcontrol)

Implementation using nonlinear carrier
v(t) Ts
Desired control, from previous slide: i s(t) = d(t) 1 – d(t)
Ts Re(vcontrol)
Generate carrier waveform as follows (replace d by t/Ts ):
vc(t) = vcontrol t 1 – t for 0 ≤ t ≤ T s
Ts Ts
vc(t + T s) = vc(t)
The controller switches the transistor off when the integrator voltage
equals the carrier waveform. This leads to:
vi(dT s) = vc(dT s) = vcontrol(t) d(t) 1 – d(t)
i s(t) Ts
= vcontrol(t) d(t) 1 – d(t)
nC i f s
v(t) Ts
v(t) Ts
Re(vcontrol) = d(t) 1 – d(t) =
i s(t) nC i fsvcontrol(t)
Ts

Generating the parabolic carrier
Removal of dc
component
vcontrol (t) vc(t)
+–
Integrator with reset Integrator with reset
Clock
(one approach, suitable for discrete circuitry)

Note that no separate multiplier circuit is needed

18.4 Single-phase converter systems
containing ideal rectifiers
• It is usually desired that the output voltage v(t) be regulated with

high accuracy, using a wide-bandwidth feedback loop
• For a given constant load characteristic, the instantaneous load
current and power are then also constant:
pload (t) = v(t)i(t) = VI
• The instantaneous input power of a single-phase ideal rectifier is

not constant:
pac(t) = vg(t)i g(t)
with vg(t)
vg(t) = VM sin (ωt) i g(t) =
Re
V 2M V 2M
so pac(t) = sin ωt =
2
1 – cos 2ωt
Re 2Re

Power flow in single-phase ideal rectifier system
• Ideal rectifier is lossless, and contains no internal energy storage.

• Hence instantaneous input and output powers must be equal
• An energy storage element must be added
• Capacitor energy storage: instantaneous power flowing into
capacitor is equal to difference between input and output powers:
d 1 Cv 2C(t)
d EC(t) 2
pC(t) = = = pac(t) – pload(t)
dt dt
Energy storage capacitor voltage must be allowed to vary, in

accordance with this equation

Capacitor energy storage in 1¿ system
pac(t)
Pload
vc(t)
d 1 Cv 2C(t)
2
= = pac(t) – pload(t)
dt
t
Single-phase system with internal energy storage
ig(t) Ideal rectifier (LFR) i (t) pload(t) = VI = Pload

2
iac(t) + 〈 pac(t)〉T + +
s i(t)
Dc–dc
vac(t) vg(t) Re C vC(t) converter v(t) load
– – –
Energy storage
capacitor
Energy storage capacitor This system is capable of

voltage vC(t) must be
independent of input and • Wide-bandwidth control of
output voltage waveforms, so output voltage
that it can vary according to • Wide-bandwidth control of
1
input current waveform
d 2 Cv 2C(t)
= = pac(t) – pload(t) • Internal independent energy
dt storage
Hold up time
Internal energy storage allows the system to function in other

situations where the instantaneous input and output powers differ.
A common example: continue to supply load power in spite of failure
of ac line for short periods of time.
Hold up time: the duration which the dc output voltage v(t) remains
regulated after vac(t) has become zero
A typical hold-up time requirement: supply load for one complete
missing ac line cycle, or 20 msec in a 50 Hz system
During the hold-up time, the load power is supplied entirely by the
energy storage capacitor

Energy storage element
Instead of a capacitor, and inductor or higher-order LC network could

store the necessary energy.
But, inductors are not good energy-storage elements
Example
100 V 100 µF capacitor
100 A 100 µH inductor
each store 1 Joule of energy
But the capacitor is considerably smaller, lighter, and less
expensive
So a single big capacitor is the best solution

Inrush current
A problem caused by the large energy storage capacitor: the large

inrush current observed during system startup, necessary to charge
the capacitor to its equilibrium value.
Boost converter is not capable of controlling this inrush current.
Even with d = 0, a large current flows through the boost converter
diode to the capacitor, as long as v(t) < vg(t).
Additional circuitry is needed to limit the magnitude of this inrush
current.
Converters having buck-boost characteristics are capable of
controlling the inrush current. Unfortunately, these converters exhibit
higher transistor stresses.

Universal input
The capability to operate from the ac line voltages and frequencies

found everywhere in the world:
50Hz and 60Hz
Nominal rms line voltages of 100V to 260V:
100V, 110V, 115V, 120V, 132V, 200V, 220V, 230V, 240V, 260V
Regardless of the input voltage and frequency, the near-ideal rectifier
produces a constant nominal dc output voltage. With a boost
converter, this voltage is 380 or 400V.

Low-frequency model of dc-dc converter
Dc-dc converter produces well-regulated dc load voltage V.

Load therefore draws constant current I.
Load power is therefore the constant value Pload = VI.
To the extent that dc-dc converter losses can be neglected, then dc-dc
converter input power is Pload , regardless of capacitor voltage vc(t).
Dc-dc converter input port behaves as a power sink. A low frequency
converter model is i (t) p (t) = VI = P
2 load load
+ +
i(t)
C vC(t) Pload V + v(t) load

–
– –
Energy storage Dc-dc

capacitor converter

Low-frequency energy storage process, 1¿ system
A complete low-frequency system model:

ig(t) i2(t) pload(t) = VI = Pload
iac(t) + 〈 pac(t)〉Ts + +
i(t)
vac(t) vg(t) Re C vC(t) Pload V + v(t) load

–
– – –
Ideal rectifier (LFR) Energy storage Dc-dc

capacitor converter
• Difference between rectifier output power and dc-dc converter

input power flows into capacitor
• In equilibrium, average rectifier and load powers must be equal
• But the system contains no mechanism to accomplish this
• An additional feeback loop is necessary, to adjust Re such that the
rectifier average power is equal to the load power
Obtaining average power balance
i(t)

–
– – –

capacitor converter
If the load power exceeds the average rectifier power, then there is a
net discharge in capacitor energy and voltage over one ac line cycle.
There is a net increase in capacitor charge when the reverse is true.
This suggests that rectifier and load powers can be balanced by
regulating the energy storage capacitor voltage.

A complete 1¿ system
containing three feedback loops
Boost converter
ig(t) i2(t)
iac(t) + + +
L D1 i(t)
DC–DC
vac(t) vg(t) Q1 vC(t) C Converter Load v(t)
– – –
vcontrol(t) vg(t) ig(t)
d(t)
PWM
Rs
Multiplier X v(t)
va(t)
v (t)
+– err Gc(s) Compensator –+ vref3
vref1(t) and modulator
= kxvg(t)vcontrol(t) Compensator
Wide-bandwidth input current controller Wide-bandwidth output voltage controller
vC(t)
Compensator –+ vref2
Low-bandwidth energy-storage capacitor voltage controller

Bandwidth of capacitor voltage loop
• The energy-storage-capacitor voltage feedback loop causes the

dc component of vc(t) to be equal to some reference value
• Average rectifier power is controlled by variation of Re.
• Re must not vary too quickly; otherwise, ac line current harmonics
are generated
• Extreme limit: loop has infinite bandwidth, and vc(t) is perfectly
regulated to be equal to a constant reference value
• Energy storage capacitor voltage then does not change, and
this capacitor does not store or release energy
• Instantaneous load and ac line powers are then equal
• Input current becomes
pac(t) p (t) Pload
i ac(t) = = load =
vac(t) vac(t) VM sin ωt

Input current waveform, extreme limit
pac(t) p (t) Pload

i ac(t) = = load =
vac(t) vac(t) VM sin ωt THD → ∞
Power factor → 0
vac(t)
So bandwidth of
capacitor voltage
loop must be
iac(t) limited, and THD
increases rapidly
with increasing
bandwidth
t

18.4.2 Modeling the outer low-bandwidth
control system
This loop maintains power balance, stabilizing the rectifier output

voltage against variations in load power, ac line voltage, and
component values
The loop must be slow, to avoid introducing variations in Re at the
harmonics of the ac line frequency
Objective of our modeling efforts: low-frequency small-signal model
that predicts transfer functions at frequencies below the ac line
frequency

Large signal model
averaged over switching period Ts
〈 ig(t)〉Ts
Ideal rectifier (LFR) 〈 i2(t)〉T
s
〈 p(t)〉T +
s
〈 vg(t)〉T + Re (vcontrol ) C 〈 v(t)〉T Load

s – s
–
ac dc
input output
vcontrol
Ideal rectifier model, assuming that inner wide-bandwidth loop

operates ideally
High-frequency switching harmonics are removed via averaging
Ac line-frequency harmonics are included in model
Nonlinear and time-varying
Predictions of large-signal model
〈 ig(t)〉Ts Ideal rectifier (LFR) 〈 i2(t)〉T

s
If the input voltage is 〈 p(t)〉T +

s
〈 vg(t)〉T + Re (vcontrol ) C 〈 v(t)〉T Load

vg(t) = 2 vg,rms sin ωt s – s
–
ac dc
Then the input output
instantaneous power vcontrol
is:
2
vg(t) Ts v 2g,rms
p(t) T = = 1 – cos 2ωt
s Re(vcontrol(t)) Re(vcontrol(t))
which contains a constant term plus a second-

harmonic term

Separation of power source into its constant and
time-varying components
〈 i2(t)〉T
s
V 2g,rms V 2g,rms
– cos 2 2ωt C 〈 v(t)〉Ts Load
Re Re
Rectifier output port
The second-harmonic variation in power leads to second-harmonic

variations in the output voltage and current

Removal of even harmonics via averaging
v(t)
〈 v(t)〉Ts
〈 v(t)〉T
2L
T2L = 1 2π = π
2 ω ω

Resulting averaged model
〈 i2(t)〉T2L
+
V 2g,rms
C 〈 v(t)〉T2L Load
Re
Time invariant model

Power source is nonlinear

Perturbation and linearization
The averaged model predicts that the rectifier output current is
p(t) T 2L v 2g,rms(t)
i 2(t) T 2L
= =
v(t) T 2L
Re(vcontrol(t)) v(t) T 2L
= f vg,rms(t), v(t) , vcontrol(t))

T 2L
Let with
v(t) T 2L
= V + v(t) V >> v(t)
i 2(t) T 2L
= I 2 + i 2(t) I 2 >> i 2(t)
vg,rms = Vg,rms + vg,rms(t) Vg,rms >> vg,rms(t)
vcontrol(t) = Vcontrol + vcontrol(t)
Vcontrol >> vcontrol(t)

Linearized result
vcontrol(t)
I 2 + i 2(t) = g 2vg,rms(t) + j2v(t) – r2
where
df vg,rms, V, Vcontrol) Vg,rms

g2 = = 2
dvg,rms Re(Vcontrol) V
v g,rms = V g,rms
df Vg,rms, v , Vcontrol)
T 2L
I2
– 1 = =–
r2 d v V
T 2L
v T =V
2L
df Vg,rms, V, vcontrol) V 2g,rms dRe(vcontrol)

j2 = =–
dvcontrol VR 2e (Vcontrol) dvcontrol
v control = V control v control = V control

Small-signal equivalent circuit
i2
+
g 2 vg,rms j2 vcontrol r2 C v R
Predicted transfer functions

v(s) 1
Control-to-output = j2 R||r 2
vcontrol(s) 1 + sC R||r 2
Line-to-output
v(s) 1
= g 2 R||r 2
vg,rms(s) 1 + sC R||r 2
Model parameters
Table 18.1 Small-signal model parameters for several types of rectifier control schemes
Controller type g2 j2 r2
Average current control with Pav V2

0
feedforward, Fig. 18.14 VVcontrol Pav
Current-programmed control, 2Pav Pav V2

Fig. 18.16 VVg,rms VVcontrol Pav
Nonlinear-carrier charge control 2Pav Pav V2

of boost rectifier, Fig. 18.21 VVg,rms VVcontrol 2Pav
Boost with critical conduction mode 2Pav Pav V2

control, Fig. 18.20 VVg,rms VVcontrol Pav
DCM buck-boost, flyback, SEPIC, 2Pav 2Pav V2

or Cuk converters VVg,rms VD Pav

Constant power load
i(t)

–
– – –

capacitor converter
Rectifier and dc-dc converter operate with same average power

Incremental resistance R of constant power load is negative, and is
2
R=– V
Pav
which is equal in magnitude and opposite in polarity to rectifier
incremental output resistance r2 for all controllers except NLC

Transfer functions with constant power load
When r2 = – R, the parallel combination r2 || R becomes equal to zero.

The small-signal transfer functions then reduce to
v(s) j
= 2
vcontrol(s) sC
v(s) g
= 2
vg,rms(s) sC

18.5 RMS values of rectifier waveforms
Doubly-modulated transistor current waveform, boost rectifier:
iQ(t)
Computation of rms value of this waveform is complex and tedious

Approximate here using double integral
Generate tables of component rms and average currents for various
rectifier converter topologies, and compare

RMS transistor current
RMS transistor current is iQ(t)

T ac
I Qrms = 1 i 2Q(t)dt
Tac 0
Express as sum of integrals over

all switching periods contained t
in one ac line period:
T ac/T s nT s
I Qrms = 1 T
Tac s ∑
n=1
1
Ts (n-1)T s
i 2Q(t)dt
Quantity in parentheses is the value of iQ2, averaged over the nth

switching period.

Approximation of RMS expression
T ac/T s nT s
I Qrms = 1 T
Tac s ∑
n=1
1
Ts (n-1)T s
i 2Q(t)dt
When Ts << Tac, then the summation can be approximated by an

integral, which leads to the double-average:
T ac/T s nT s
I Qrms ≈ 1 lim T
Tac T s→0 s ∑
n=1
1
Ts (n-1)T s
i 2Q(τ)dτ
T ac t+T s
= 1 1 i 2Q(τ)dτ dt
Tac 0
Ts t
= i 2Q(t) Ts
T ac

18.5.1 Boost rectifier example
For the boost converter, the transistor current iQ(t) is equal to the input
current when the transistor conducts, and is zero when the transistor
is off. The average over one switching period of iQ2(t) is therefore
t+T
s
i 2
= 1 i 2Q(t)dt
Q T
s Ts t
= d(t)i 2ac(t)
If the input voltage is
vac(t) = VM sin ωt
then the input current will be given by

VM
i ac(t) = sin ωt
Re
and the duty cycle will ideally be
V = 1 (this neglects
vac(t) 1 – d(t) converter dynamics)

Boost rectifier example
Duty cycle is therefore

VM
d(t) = 1 – sin ωt
V
Evaluate the first integral:
V 2M V
i 2
Q T = 2 1 – M sin ωt sin 2 ωt
s Re V
Now plug this into the RMS formula:
T ac
I Qrms = 1 i 2Q dt
Tac 0
Ts
T ac
1 V 2M VM
= 1 – sin ωt sin 2 ωt dt
Tac R 2e V
0
T ac/2
2
I Qrms = 2 V M
sin 2 ωt –
VM
sin 3 ωt dt
Tac R 2
e
V
0

Integration of powers of sin θ over complete half-cycle
π
n 1 sin n (θ)dθ
π 0
1 2
π
2 2⋅4⋅6 (n – 1) if n is odd
π π 1⋅3⋅5 n 2 1
1 n
sin (θ)dθ =
π 0 1⋅3⋅5 (n – 1) 2
if n is even
2⋅4⋅6 n 3 4
3π
4 3
8
5 16
15π
6 15
48

Boost example: transistor RMS current
VM V V
I Qrms = 1– 8 M = I ac rms 1– 8 M
2 Re 3π V 3π V
Transistor RMS current is minimized by choosing V as small as

possible: V = VM. This leads to
I Qrms = 0.39I ac rms
When the dc output voltage is not too much greater than the peak ac
input voltage, the boost rectifier exhibits very low transistor current.
Efficiency of the boost rectifier is then quite high, and 95% is typical in
a 1kW application.

Table of rectifier current stresses for various topologies
Tabl e 18. 3 Summary of rectifier current stresses for several converter topologies
rms Average Peak

CCM boost
I ac rms 2 π2 1 – π M
Transistor VM V I ac rms 2
I ac rms 1 – 8
3π V 8 V
Diode I dc 16 V I dc 2 I dc V
3π V M VM
Inductor I ac rms I ac rms 2 π2 I ac rms 2
CCM flyback, with n:1 isolation transformer and input filter

Transistor,
I ac rms 1+ 8 M
V I ac rms 2 π2 I ac rms 2 1 +
V
xfmr primary 3π nV n
L1 I ac rms I ac rms 2 π2 I ac rms 2
C1 I ac rms 8 VM 0 I ac rms 2 max 1,

VM
3π nV nV
Diode, I dc 3 + 16 nV I dc 2I dc 1 + nV
2 3π V M VM
xfmr secondary

Table of rectifier current stresses
continued
CCM SEPIC, nonisolated

Transistor
I ac rms 1+ 8 M
VM
3π V V
C1
I ac rms 8 VM 0
I ac rms max 1,
VM
3π V V
L2 VM 3 I ac rms V M VM
I ac rms I ac rms 2
V 2 2 V V
Diode I dc 3 + 16 V I dc 2I dc 1 + V
2 3π V M VM
CCM SEPIC, with n:1 isolation transformer

transistor
I ac rms 1+ 8 M
VM
3π nV nV
C1,
I ac rms 8 VM 0
I ac rms 2 max 1,
xfmr primary 3π nV n
Diode, I dc 3 + 16 nV I dc 2I dc 1 + nV
xfmr secondary 2 3π V M VM
I ac rms
with, in all cases, = 2 V , ac input voltage = V M sin(ω t)
I dc VM
dc output voltage = V

Comparison of rectifier topologies
Boost converter
• Lowest transistor rms current, highest efficiency
• Isolated topologies are possible, with higher transistor stress
• No limiting of inrush current
• Output voltage must be greater than peak input voltage
Buck-boost, SEPIC, and Cuk converters
• Higher transistor rms current, lower efficiency
• Isolated topologies are possible, without increased transistor
stress
• Inrush current limiting is possible
• Output voltage can be greater than or less than peak input
voltage
Comparison of rectifier topologies
1kW, 240Vrms example. Output voltage: 380Vdc. Input current: 4.2Arms
Converter Transistor rms Transistor Diode rms Transistor rms Diode rms
current voltage current current, 120V current, 120V
Boost 2A 380 V 3.6 A 6.6 A 5.1 A
Nonisolated 5.5 A 719 V 4.85 A 9.8 A 6.1 A
SEPIC
Isolated 5.5 A 719 V 36.4 A 11.4 A 42.5 A
SEPIC
Isolated SEPIC example has 4:1 turns ratio, with 42V 23.8A dc load

18.6 Modeling losses and efficiency
in CCM high-quality rectifiers
Objective: extend procedure of Chapter 3, to predict the output

voltage, duty cycle variations, and efficiency, of PWM CCM low
harmonic rectifiers.
Approach: Use the models developed in Chapter 3. Integrate over
one ac line cycle to determine steady-state waveforms and average
power.
Boost example
RL DRon VF
ig(t) RL L D1 ig(t) D' : 1 i(t)
i(t)
+
–
+ +
vg(t) + Q1 C R v(t) vg(t) + R v(t)

– –
– –
Dc-dc boost converter circuit Averaged dc model

Modeling the ac-dc boost rectifier
ig(t) id(t) i(t)

Boost iac(t) + +
RL L D1
rectifier
circuit vac(t) vg(t) Q1 C v(t) R
– –
controller
RL d(t) Ron VF
ig(t) id(t) i(t) = I
d'(t) : 1
Averaged
+
–
+
model
vg(t) + C R v(t) = V
– (large)

Boost rectifier waveforms
vg(t) ig(t)
300 10 Typical waveforms
vg(t)
8
200
(low frequency components)
ig(t) 6
4
vg(t)
100 ig(t) =
Re
2
0 0
0° 30° 60° 90° 120° 150° 180°
d(t) 1 6
0.8 5 id(t)
4
0.6
3 i(t) = I
0.4
2
0.2 1
0 0
0° 30° 60° 90° 120° 150° 180° 0° 30° 60° 90° 120° 150° 180°
ωt

Example: boost rectifier
with MOSFET on-resistance
ig(t) d'(t) : 1 i(t) = I

id(t) +
d(t) Ron
– (large)
Averaged model
Inductor dynamics are neglected, a good approximation when the ac
line variations are slow compared to the converter natural frequencies

18.6.1 Expression for controller duty cycle d(t)
Solve input side of ig(t) d'(t) : 1 i(t) = I

model: id(t) +
d(t) Ron
i g(t)d(t)Ron = vg(t) – d'(t)v
vg(t) – (large)
with ig(t) =
Re
–
vg(t) = VM sin ωt
eliminate ig(t): solve for d(t):

vg(t) v – vg(t)
d(t)Ron = vg(t) – d'(t)v d(t) =
Re R
v – vg(t) on
Re
Again, these expressions neglect converter dynamics, and assume
that the converter always operates in CCM.

18.6.2 Expression for the dc load current
Solve output side of ig(t) d'(t) : 1 i(t) = I

model, using charge id(t) +
d(t) Ron
balance on capacitor C:
I = id T vg(t) + C R v(t) = V
ac – (large)
vg(t)
i d (t) = d'(t)i g(t) = d'(t) –
Re
Butd’(t) is:
R hence id(t) can be expressed as
vg(t) 1 – on
Re Ron
d'(t) = 1–
R v 2g(t) Re
v – vg(t) on i d (t) =
Re Re Ron
v – vg(t)
Re
Next, average id(t) over an ac line period, to find the dc load current I.

Dc load current I
Now substitute vg (t) = VM sin ωt, and integrate to find 〈id(t)〉Tac:

T ac/2
Ron
1– sin 2 ωt
V 2M Re
I = id T = 2 dt
ac Tac Re VM Ron
v– sin ωt
Re
0
This can be written in the normalized form

T ac/2
V 2
R sin 2 ωt
I= 2 M
1 – on dt
Tac VRe Re
0
1 – a sin ωt
with VM Ron
a=
V Re

Integration
By waveform symmetry, we need only integrate from 0 to Tac/4. Also,

make the substitution θ = ωt:
π/2
V2
M R 2 sin 2 θ
I= 1 – on π dθ
VRe Re
0
1 – a sin θ
This integral is obtained not only in the boost rectifier, but also in the
buck-boost and other rectifier topologies. The solution is
π/2
4 sin 2 θ 4 sin – 1 a + 2 cos – 1 a

π dθ = F(a) = 22 – 2a – π +
1 – a sin θ aπ 1 – a2
0
• Result is in closed form • a is typically much smaller than

unity
• a is a measure of the loss
resistance relative to Re
The integral F(a)
π/2
4 sin 2 θ 4 sin – 1 a + 2 cos – 1 a

π dθ = F(a) = 22 – 2a – π +
1 – a sin θ aπ 1 – a2
0
Approximation via
1.15
polynomial:
1.1
F(a) ≈ 1 + 0.862a + 0.78a 2
1.05
For | a | ≤ 0.15, this
approximate expression is F(a) 1
within 0.1% of the exact
0.95
value. If the a2 term is
omitted, then the accuracy 0.9
drops to ±2% for | a | ≤ 0.15.
The accuracy of F(a) 0.85
–0.15 –0.10 –0.05 0.00 0.05 0.10 0.15
coincides with the accuracy
of the rectifier efficiency η. a

18.6.3 Solution for converter efficiency η
Converter average input power is

V 2M
Pin = pin(t) T =
ac 2Re
Average load power is
V 2M R F(a) VM Ron
Pout = VI = V 1 – on with a=
VRe Re 2 V Re
So the efficiency is
Pout R
η= = 1 – on F(a)
Pin Re
Polynomial approximation:
2
R V R V R
η ≈ 1 – on 1 + 0.862 M on + 0.78 M on
Re V Re V Re

Boost rectifier efficiency
1
η Pout R
η= = 1 – on F(a)
.05
Pin Re
0.95 R on /R e = 0
= 0.1 • To obtain high

0.9 R on/R e
15
efficiency, choose V
0.
R on /R e = slightly larger than VM
0.85
= 0.2 • Efficiencies in the range
/R e
0.8 R on 90% to 95% can then be
obtained, even with Ron
as high as 0.2Re
0.75
0.0 0.2 0.4 0.6 0.8 1.0 • Losses other than
VM /V MOSFET on-resistance
are not included here

18.6.4 Design example
Let us design for a given efficiency. Consider the following

specifications:
Output voltage 390 V
Output power 500 W
rms input voltage 120 V
Efficiency 95%
Assume that losses other than the MOSFET conduction loss are
negligible.
Average input power is
P
Pin = ηout = 500 W = 526 W
0.95
Then the emulated resistance is
V 2g, rms (120 V) 2
Re = = = 27.4 Ω
Pin 526 W
Design example
Also, VM 120 2 V
= = 0.435
V 390 V 95% efficiency with
1 VM/V = 0.435 occurs
η with Ron/Re ≈ 0.075.
.05
0.95 R on /R e = 0 So we require a
MOSFET with on
= 0.1
0.9 R on/R e resistance of
0.15 Ron ≤ (0.075) Re
R on /R e =
0.85
= 0.2 = (0.075) (27.4 Ω) = 2 Ω
/R e
0.8 R on
0.75
0.0 0.2 0.4 0.6 0.8 1.0
VM /V

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Chapter 18

Pulse-Width Modulated Rectifiers

18.1 Properties of the ideal rectifier

Fundamentals of Power Electronics 1 Chapter 18: PWM Rectifiers

It is desired that the rectifier present a resistive load to the ac power

Re is called the emulated resistance vac(t) Re

Fundamentals of Power Electronics 2 Chapter 18: PWM Rectifiers

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The ideal rectifier is iac(t) Ideal rectifier (LFR) i(t)

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i(t) i(t) v(t)i(t) = p(t)

p(t) v(t) v(t) p(t)

Fundamentals of Power Electronics 5 Chapter 18: PWM Rectifiers

Defining equations of the When connected to a

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Control the duty cycle of a dc-dc

vac(t) vg(t) v(t) C R

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Averaged vg(t)i g(t) v 2g(t) Averaged

vac(t) vg(t) v(t) C R

• To avoid distortion near line voltage zero crossings, converter should

Fundamentals of Power Electronics 10 Chapter 18: PWM Rectifiers

vac(t) vg(t) Q1 C v(t) R

• DC output voltage ≥ peak AC input voltage

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Since M ≥ 1 in the boost converter, it is required that V ≥ VM

The duty ratio should therefore follow

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Inductor current ripple is

i g(t) > ∆i (t) ⇒ d(t) < 2L

Re < 2L for CCM

Now simplify DCM current expression, to obtain

2L i (t) 1 – vg(t) = d 2(t) vg(t)

CCM/DCM mode boundary, in terms of vg(t) and ig(t):

2L i (t) > vg(t) 1–

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We found in Chapter 11 that the buck-boost, SEPIC, and Cuk

Input current contains harmonics. If v is sufficiently greater than vg,

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EMI filter Flyback converter

Operation in DCM: we found in Chapter 11 that the converter input

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EMI filter Averaged model

vac(t) vg(t) 2n 2L 〈 p(t) 〉T 〈v(t)〉T C R

• Under steady-state conditions, operate with constant D

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Select L small enough that DCM i1(t)

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We have: D< 1 with Vrms R

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18.3.1 Average current control

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va(t) Gc(s) Compensator

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• Current sensor has ig(t)

va(t) ≈ vr (t) Multiplier X

〈ig(t)〉Ts Ideal rectifier (LFR) 〈i(t)〉T

vac(t) 〈vg(t)〉T Re C 〈v(t)〉T R