Assembler Reference

Assembly Language
Coding
for
TPF
Copyright Galileo International Partnership 1997 Assembly Language Coding for TPF
500
Assembly Language
Reference for TPF
Applications Programmers
41362878.DOC (12/7/2021) [ 500 - 2 ] ALC Reference for TPF Applications Programmers

Assembler Language Reference

for TPF Applications Programmers
This reference is an alphabetical lexicon of assembly language tools and topics used in the TPF applications
programming environment. Although it is not an all inclusive text regarding assembler instructions, it contains
sufficient information to allow the assembler programmer to determine how and when to use the various instructions.
©Copyright Galileo International Partnership 1996

This course material may not be reproduced in whole or part without prior written permission from:
Galileo International Partnership
Technical Training
5350 South Valentia Way
Englewood, CO 80111
USA
Any products listed are trademarks or registered trademarks of their respective owners and are used here for
informational purposes only.

Table of Contents by Title
Add............................................................................................................................................................................................
Address Constants.....................................................................................................................................................................
Add Halfword............................................................................................................................................................................
Add Registers............................................................................................................................................................................
Branch and Link........................................................................................................................................................................
Branch and Link Register.........................................................................................................................................................
Branch and Save........................................................................................................................................................................
Branch and Save Register.........................................................................................................................................................
Branch on Condition.................................................................................................................................................................
Branch on Condition _..............................................................................................................................................................
Branch on Condition Register...................................................................................................................................................
Branch on Condition _ Register................................................................................................................................................
Branch on Count........................................................................................................................................................................
Branch on Count Register.........................................................................................................................................................
BEGIN Macro...........................................................................................................................................................................
Compare (Arithmetic)...............................................................................................................................................................
Compare Halfword (Arithmetic)...............................................................................................................................................
Compare Logical.......................................................................................................................................................................
Compare Logical Characters.....................................................................................................................................................
Compare Logical Immediate....................................................................................................................................................
Compare Logical Characters Under Mask...............................................................................................................................
Compare Logical Registers.......................................................................................................................................................
Compare Registers (Arithmetic)...............................................................................................................................................
Define Control Section..............................................................................................................................................................
Convert to Binary......................................................................................................................................................................
Convert to Decimal...................................................................................................................................................................
Divide........................................................................................................................................................................................
Define Constant.........................................................................................................................................................................
Divide Registers........................................................................................................................................................................
Drop Base Register(s) Directive...............................................................................................................................................
Define Storage...........................................................................................................................................................................
Define Dummy Section.............................................................................................................................................................
Edit.............................................................................................................................................................................................
Skip to a New Page Directive...................................................................................................................................................
END Source Module Directive.................................................................................................................................................
Equate Directive........................................................................................................................................................................
Execute......................................................................................................................................................................................
FINIS Macro..............................................................................................................................................................................
Insert Character.........................................................................................................................................................................
Insert Characters Under Mask...................................................................................................................................................
Load...........................................................................................................................................................................................
Load Address.............................................................................................................................................................................
Load Halfword..........................................................................................................................................................................
Load Multiple............................................................................................................................................................................
Load Register............................................................................................................................................................................
Literal Origin Directive.............................................................................................................................................................
Load and Test Register.............................................................................................................................................................
Multiply.....................................................................................................................................................................................
Multiply Halfword.....................................................................................................................................................................
Multiply Registers.....................................................................................................................................................................
Move Characters........................................................................................................................................................................
Move Immediate.......................................................................................................................................................................
AND...........................................................................................................................................................................................
AND Characters........................................................................................................................................................................
AND Immediate........................................................................................................................................................................

Table of Contents by Title (cont.)
And Registers............................................................................................................................................................................
OR..............................................................................................................................................................................................
OR Characters...........................................................................................................................................................................
OR Immediate...........................................................................................................................................................................
OR Registers..............................................................................................................................................................................
Origin Directive.........................................................................................................................................................................
Pack...........................................................................................................................................................................................
Print Directive...........................................................................................................................................................................
Subtract......................................................................................................................................................................................
Subtract Halfword.....................................................................................................................................................................
Shift Left Algebraic...................................................................................................................................................................
Shift Left Double Algebraic......................................................................................................................................................
Shift Left Double Logical.........................................................................................................................................................
Shift Left Logical......................................................................................................................................................................
Insert Blank Lines Directive.....................................................................................................................................................
Subtract Registers......................................................................................................................................................................
Shift Right Algebraic................................................................................................................................................................
Shift Right Logical....................................................................................................................................................................
Shift Right Double Algebraic...................................................................................................................................................
Shift Right Double Logical.......................................................................................................................................................
Store...........................................................................................................................................................................................
Store Character..........................................................................................................................................................................
Store Characters Under Mask...................................................................................................................................................
Store Halfword..........................................................................................................................................................................
Store Multiple............................................................................................................................................................................
Test Under Mask.......................................................................................................................................................................
Translate....................................................................................................................................................................................
Translate and Test.....................................................................................................................................................................
Unpack.......................................................................................................................................................................................
Declare Base Register Directive...............................................................................................................................................
Exclusive OR.............................................................................................................................................................................
Exclusive OR Characters..........................................................................................................................................................
Exclusive OR Immediate..........................................................................................................................................................
Exclusive OR Registers.............................................................................................................................................................

Table of Contents by Mnemonic
A................................................................................................................................................................................................
AD CON'S.................................................................................................................................................................................
AH..............................................................................................................................................................................................
AR..............................................................................................................................................................................................
BAL...........................................................................................................................................................................................
BALR.........................................................................................................................................................................................
BAS............................................................................................................................................................................................
BASR.........................................................................................................................................................................................
BC..............................................................................................................................................................................................
B_...............................................................................................................................................................................................
BCR...........................................................................................................................................................................................
B_R............................................................................................................................................................................................
BCT...........................................................................................................................................................................................
BCTR.........................................................................................................................................................................................
BEGIN.......................................................................................................................................................................................
Boolean Algebra........................................................................................................................................................................
Boolean Operations...................................................................................................................................................................
C.................................................................................................................................................................................................
CH..............................................................................................................................................................................................
CL..............................................................................................................................................................................................
CLC...........................................................................................................................................................................................
CLI.............................................................................................................................................................................................
CLM...........................................................................................................................................................................................
CLR...........................................................................................................................................................................................
CR..............................................................................................................................................................................................
CSECT.......................................................................................................................................................................................
CVB...........................................................................................................................................................................................
CVD...........................................................................................................................................................................................
D................................................................................................................................................................................................
DC..............................................................................................................................................................................................
DR..............................................................................................................................................................................................
DROP.........................................................................................................................................................................................
DS..............................................................................................................................................................................................
DSECT.......................................................................................................................................................................................
ED..............................................................................................................................................................................................
EJECT........................................................................................................................................................................................
END...........................................................................................................................................................................................
EQU...........................................................................................................................................................................................
EX..............................................................................................................................................................................................
Expressions................................................................................................................................................................................
FINIS.........................................................................................................................................................................................
IC...............................................................................................................................................................................................
ICM............................................................................................................................................................................................
L.................................................................................................................................................................................................
LA..............................................................................................................................................................................................
LH..............................................................................................................................................................................................
LM.............................................................................................................................................................................................
LR..............................................................................................................................................................................................
LTORG......................................................................................................................................................................................
LTR............................................................................................................................................................................................
M................................................................................................................................................................................................
MH.............................................................................................................................................................................................
MR.............................................................................................................................................................................................
MVC..........................................................................................................................................................................................
MVI............................................................................................................................................................................................

Table of Contents by Mnemonic (cont.)
N................................................................................................................................................................................................
NC..............................................................................................................................................................................................
NI...............................................................................................................................................................................................
NR..............................................................................................................................................................................................
O................................................................................................................................................................................................
OC..............................................................................................................................................................................................
OI...............................................................................................................................................................................................
OR..............................................................................................................................................................................................
ORG...........................................................................................................................................................................................
PACK.........................................................................................................................................................................................
PRINT........................................................................................................................................................................................
Register Usage...........................................................................................................................................................................
S.................................................................................................................................................................................................
SH..............................................................................................................................................................................................
SLA............................................................................................................................................................................................
SLDA.........................................................................................................................................................................................
SLDL.........................................................................................................................................................................................
SLL............................................................................................................................................................................................
SPACE.......................................................................................................................................................................................
SR..............................................................................................................................................................................................
SRA............................................................................................................................................................................................
SRL............................................................................................................................................................................................
SRDA.........................................................................................................................................................................................
SRDL.........................................................................................................................................................................................
ST...............................................................................................................................................................................................
STC............................................................................................................................................................................................
STCM........................................................................................................................................................................................
STH............................................................................................................................................................................................
STM...........................................................................................................................................................................................
TM.............................................................................................................................................................................................
TR..............................................................................................................................................................................................
TRT............................................................................................................................................................................................
UNPK.........................................................................................................................................................................................
USING.......................................................................................................................................................................................
X................................................................................................................................................................................................
XC..............................................................................................................................................................................................
XI...............................................................................................................................................................................................
XR..............................................................................................................................................................................................

A
Add
RX Type Op code = 5A
Adds contents of a 4-byte storage area to the contents of a register. The result in placed in the register. The storage
location is unchanged.
label A R1,D2(X2,B2)
Operand 1 Operand 2
Use Destination Source
Format Register No. Base/Index/Displac
or Symbolic Name of or label
Register or literal
Spec R = Register # D = Decimal value
or Symbolic Name X = Register # or
of Register symbolic Reg name
B = Register # or
symbolic Reg name
Machine code Instruction Length = Fullword

OP CODE R1 X2 B2 D2
0-7 8-11 12-15 16-19 20-31
5A
5AR1X2B2DDD2
The condition code is set according to the results in Operand 1 as follows:
Results Cond code

ZERO 0
MINUS 1
PLUS 2
OVERFLOW 3
Examples:
R2 = X'00000010' R8 = 010816
Addr 012816 = LABEL1 = DC X'0000000C'
A R2,32(R0,R8)
or A R2,LABEL1
Before: Addr 12816

R2 LABEL1
(hex bytes) 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 C
After: Addr 12816

R2 LABEL1
(hex bytes) 0 0 0 0 0 0 1 C 0 0 0 0 0 0 0 C

AD CON'S
Address Constants
Address Constants allow you to define a constant using a storage address or an absolute expression. An A CON
defines a fullword constant. A Y CON defines a halfword constant. When referencing an address, you must use the
A CON. When referencing the length of the data at an address, you can use the A CON or the Y CON. When
specifying an absolute expression, the address constant is equal to the value of the expression. The ADCON is
allocated in storage during LTORG generation.
dALn(c)
where d = Duplication factor (decimal number)

A = A or Y
Ln = Length. Not normally used when (c) is a relocatable expression. If (c) is an
absolute expression, n can be 1 to 4 and no boundary alignment is forced.
(c) = expression, either absolute or relocatable
Defining a halfword constant as the data length of a relocatable expression

Example 1a:
LH R1,=Y(L'LABEL1)
LABEL1 DC C'MY NAME' (length = 7)
This example loads the two least significant bytes of R1 with the halfword X'0007', which is the length of the
relocatable value LABEL1.
Example 1b:
MVC UI2CNF,=AL2(L’MSG)
UI2CNF DS CL2
MSG DC C’GALILEO INTERNATIONAL’(length = 7)
This example loads the 2 byte storage area UI2CNF with X’0015’, the length of the relocatable symbol MSG.
No boundary alignment is forced since a length specifier is used.
Defining a fullword constant as the address of a relocatable expression.

Example 2a:
L R1,=A(LABEL1)
0140 LABEL1 DC C'MY NAME' (length = 7)
This example loads R1 with the fullword X’00000140’, which is the address of LABEL1. A fullword
boundary alignment is forced on the ADCON.
Example 2b:
L R1,=A(LABEL1+20)
.
0140 LABEL1 DC C'MY NAME' (length = 7)
This example loads R1 with the fullword X’00000154’, which is the address of LABEL1 + 1416. A fullword
boundary alignment is forced on the ADCON.

AD CON'S
Address Constants
(cont.)
Example 2c:
L R1,ADDR1
.
0140 ADDR1 DC A(*)
This example loads R1 with the fullword X’00000140’, which is the address of ADDR1. ADDR1 is forced to a fullword
boundary.
Defining a constant using an absolute expression.

Example 3a:
LABEL1 DC AL2(51)
This example defines LABEL1 as the value X’0033’ (51 10). No boundary alignment is forced since the length
specifier is used.
Example 3b:
LABEL1 DC AL2(3*FACTOR-1)
FACTOR EQU 4
This example has the same meaning as a constant defined by X’000B’. No boundary alignment is forced.
Example 3b:
MVC LABEL1(LENTX),ETX
LABEL1 DS CL3
ETX AL1(#CAR)
AL1(#SOM)
AL1(#EOM)
LENTX EQU *-ETX
This example loads the value X’156E4E’ into the storage area LABEL1. The # denotes the use of the system
equates CAR, SOM and EOM which are absolute values ( #CAR = X’15’, #SOM = X’6E’, and #EOM =
X’4E’ ). Note that since the expressions in the adcon statements resolve to absolute values, the address
constants take on the value of the expressions.

AH
Add Halfword
RX Type Op code = 4A
Adds contents of a 2-byte storage area to the contents of a register. The results are placed in the register. The storage
location is unchanged.
label AH R1,D2(X2,B2)
Operand 1 Operand 2
or label
or literal
B = Register # or
symbolic Reg name

OP CODE R1 X2 B2 D2
0-7 8-11 12-15 16-19 20-31
4A
4AR1X2B2DDD2
Results Cond code

ZERO 0
MINUS 1
PLUS 2
OVERFLOW 3
Example:
R2 = X'00000010' R8 = 010816
Addr 012816 = LABEL1 = DC H'12'
AH R2,32(R0,R8) or R2,32(R8) or R2,32(,R8)

or AH R2,LABEL1
or AH R2,=H'12'
Before: Addr 12816

R2 LABEL1
(hex bytes) 0 0 0 0 0 0 1 0 0 0 0 C
After: Addr 012816

R2 LABEL1
(hex bytes) 0 0 0 0 0 0 1 C 0 0 0 C

AR
Add Registers
RR Type Op code = 1A
Adds contents of a two Registers. The result in placed in the register specified in operand 1. The register specified in
operand 2 is unchanged.
label AR R1,R2
Operand 1 Operand 2
Format Register No. Register No.
Spec R = Register # or R = Register # or
symbolic Reg name symbolic Reg name
Machine code Instruction

Length = Halfword
OP CODE R1 R2
0-7 8-11 12-15
1A
1AR1R2
Results Cond code

ZERO 0
MINUS 1
PLUS 2
OVERFLOW 3
Example:
R2 = X'00000010' R8 = X'00000023'
AR R2,R8
Before:
R2 R8
(hex bytes) 0 0 0 0 0 0 1 0 0 0 0 0 0 0 2 3
After:
R2 R8
(hex bytes) 0 0 0 0 0 0 3 3 0 0 0 0 0 0 2 3

BAL
Branch and Link
RX Type Op code = 45
Saves the address of the next sequential instruction in the register specified in operand 1 and branches to the subroutine
specified in operand 2. In order to return from the subroutine, it should end with a branch instruction, such as the BR
(Branch Register), that references the address in the operand 1 register. This allows you to utilize subroutines for
common routines. The BAS instruction replaces the BAL instruction which was used in programs designed for
24-bit architecture .
label BAL R1,D2(X2,B2)
Operand 1 Operand 2
Use Return address Subroutine address
(next instruction
after BAS)
or symbolic label
B = Register # or
symbolic Reg name

OP CODE R1 X2 B2 D2
0-7 8-11 12-15 16-19 20-31
45
45R1X2B2DDD2
Example:
BAL R2,SUBRTNE Save X’78 in R2 & Branch to subroutine
0078 BACKIN . Return here from subroutine
.
.
.
SUBRTNE . Start of subroutine
.
.
.
BR R2 Return to mainline (BACKIN)
Note: If you see BAL in any Galileo assembler coding, it should be

replaced with BAS.

BALR
Branch and Link Register
RR Type Op code = 05
whose address is in the register specified in operand 2. In order to return from the subroutine, it should end with a
branch instruction, such as the BR (Branch Register), that references the address in the operand 1 register. This allows
you to utilize subroutines for common routines. The BASR instruction replaces the BALR instruction which was
used in programs designed for 24-bit architecture.
label BALR R1,R2
Operand 1 Operand 2
(next instruction
after BAL)
Format Register No. Register No
Spec R = Register # R = Register #
or Symbolic Name or Symbolic Name
of Register of Register

Length = Halfword
OP CODE R1 R2
0-7 8-11 12-15
05
05R1R2
Examples:
R3 = 01C216
BALR R2,R3 Save X’78 in R2 & Branch to subroutine
0078 BACKIN . Return here from subroutine;R3 need to
store the subrouinte address
.
.
.
01C2 SUBRTNE . Start of subroutine
.
.
.
Note: If you see BALR in any Galileo assembler coding, it should be

replaced with BASR.

BAS
Branch and Save
RX Type Op code = 4D
specified in operand 2. In order to return from the subroutine, it should end with a branch instruction, such as the BR
(Branch Register), that references the address in the operand 1 register. This allows you to utilize subroutines for
common routines. The BAS instruction replaces the BAL instruction which was used in programs designed for 24-bit
architecture.
label BAS R1,D2(X2,B2)
Operand 1 Operand 2
(next instruction
after BAS)
or symbolic label
B = Register # or
symbolic Reg name

OP CODE R1 X2 B2 D2
0-7 8-11 12-15 16-19 20-31
4D
4DR1X2B2DDD2
Example:
BAS R2,SUBRTNE Save X’78 in R2 & Branch to subroutine
.
.
.
SUBRTNE . Start of subroutine
.
.
.
Note: If you see BAL in any Galileo assembler coding, it should be

replaced with BAS.

BASR
Branch and Save Register
RR Type Op code = 0D
whose address is in the register specified in operand 2. In order to return from the subroutine, it should end with a
branch instruction, such as the BR (Branch Register), that references the address in the operand 1 register. This allows
you to utilize subroutines for common routines. The BASR instruction replaces the BALR instruction which was
used in programs designed for 24-bit architecture.
label BASR R1,R2
Operand 1 Operand 2
(next instruction
after BAL)
Format Register No. Register No

Length = Halfword
OP CODE R1 R2
0-7 8-11 12-15
0D
0DR1R2
Examples:
R3 = 01C216
BASR R2,R3 Save X’78 in R2 & Branch to subroutine
.
.
.
01C2 SUBRTNE . Start of subroutine
.
.
.
Note: If you see BALR in any Galileo assembler coding, it should be

replaced with BASR.

BC
Branch on Condition
Branch to the address specified in operand 2 if the condition code in the PSW satisfies the mask specified in operand 1.
label BC M1,D2(X2,B2)
Operand 1 Operand 2
Use Mask Address
Format Halfword Base/Index/Displac
or Binary or symbolic label
Spec Decimal value or D = Decimal value
Halfword literal X = Register # or
or Binary Number symbolic Reg name
B = Register # or
symbolic Reg name

OP CODE M1 X2 B2 D2
0-7 8-11 12-15 16-19 20-31
47
47M1X2B2DDD2
The condition code (CC) in the PSW indicates the condition after the last compare, arithmetic, or Test Under Mask
operation. The CC also determines which of 4 test bits are to be matched or (non-matched) to the mask, as follows:
Condition(s) Equal Low High Overflow
(bit number to or Zero or or or
match) Minus Plus Ones
Condition Bit Bit Bit Bit Mask
code 0 1 2 3 (Decimal)
00 1 0 0 0 8
01 0 1 0 0 4
10 0 0 1 0 2
11 0 0 0 1 1
The following table shows the branch condition, mask specifier, and machine code for each of the possible conditions
used for BC instruction.
Mask Mask Operation which
Branch Condition (Decimal) (Binary) Machine code set condition
Unconditional 15 1111 47F General
NOP 0 0000 470 "
High 2 0010 472 Compare
Low 4 0100 474 "
Equal 8 1000 478 "
Not High 13 1101 47D '
Not Low 11 1011 47B "
Not Equal 7 0111 477 "
Plus 2 0010 472 Arithmetic
Minus 4 0100 474 "
Zero 8 1000 478 "
Overflow 1 0001 471 "
Not Plus 13 1101 47D "
Not Minus 11 1011 47B "
Not Zero 7 0111 477 "
No Overflow 14 1110 47E "
Ones 1 0001 471 Test Under Mask
Mixed 4 0100 474 "
Zero's 8 1000 478 "
Not Ones 14 1110 47E "
Not Mixed 11 1101 47B '
Not Zero's 7 0111 477 "
Not Zero 4 0100 474 Boolean
Zero 8 1000 478 "

BC
Branch on Condition
(cont.)
Example 1:
(Arithmetic)
.
SR R2,R2 Set R2 to zero
S R2,DATA1 Subtract F'21' from zero
BC 4,PGM40100 Branch to PGM40100 if result is minus
. Else continue here.
B NEXTSEG1 Branch to next segment
PGM40100 EQU * .
.
.
DATA1 DC F'21' Set LABEL1=21
In this example the branch will be taken since the result of the subtract operation is a negative number.
Example 2:
(Compare)
L R3,=F'12' Set R3 = 12
ST R3,DATA1 Save R3 in DATA1
CLC DATA1,=F'12' Compare DATA1 to F'12'
BC 8,PGM40100 Branch to PGM40100 if DATA1 = F'12'
PGM40100 EQU * .
.
.
DATA1 DS F Define fullword variable
In this example the branch will be taken since the result of the compare operation is equal.
Example 3:
(Test Under Mask)
LH R3,H'146' Set R3 = 146 (X'0092') (B'10010010')
STH R3,DATA1 Save H'146' in DATA1
TM DATA1+1,B'00000010' Test under mask using H'2'
BC 1,PGM40100 Branch if TM left any one's
PGM40100 EQU * .
.
.
DATA1 DS H Define Half word variable
In this example the branch will be taken since the result of the test under mask operation leaves a one in bit 6:
DATA1 10010010
Mask 00000010
____________
TM Result 0 0 0 0 0 0 1 0

B_
Branch on Condition _
Branch to the address specified in operand if the condition code in the PSW satisfies the condition specified in the
branch mnemonic.
label B_ D(X,B)
B_ Operand
Use Branch Mnemonic Address
Format See Branch Mnemonic Base/Index/Displac
Table or symbolic label
Spec Characters (see table D = Decimal value
below) X = Register # or
symbolic Reg name
B = Register # or
symbolic Reg name

OP CODE _ X B D
0-7 8-11 12-15 16-19 20-31
47
47_XBDDD
The following table shows the branch condition, branch mnemonic, and machine code for each of the possible branch
conditions.
Branch
Branch Condition Mnemonic Machine code Operation which
(Branch if...) (B_) (47_) set condition
Unconditional B 47F General
NOP NOP 470 "
High BH 472 Compare
Low BL 474 "
Equal BE 478 "
Not High BNH 47D '
Not Low BNL 47B "
Not Equal BNE 477 "
Plus BP 472 Arithmetic
Minus BM 474 "
Zero BZ 478 "
Overflow BO 471 "
Not Plus BNP 47D "
Not Minus BNM 47B "
Not Zero BNZ 477 "
No Overflow BNO 47E "
Ones BO 471 Test Under Mask
Mixed BM 474 "
Zero's BZ 478 "
Not Ones BNO 47E "
Not Mixed BNM 47B '
Not Zero's BNZ 477 "
Not Zero BNZ 474 Boolean"
Zero BZ 478 "

B_
Branch on Condition _
(cont.)
Example 1:
(Arithmetic)
S R2,DATA1 Subtract F'21' from zero
BM PGM40100 Branch to PGM40100 if result is minus
PGM40100 EQU * .
.
.
Example 2:
(Compare)
L R3,F'12' Set R3 = 12
CLC DATA1,F'12' Compare DATA1 to F'12'
BE PGM40100 Branch to PGM40100 if DATA1 = F'12'
PGM40100 EQU * .
.
.
Example 3:
(Test Under Mask)
LH R3,H'146' Set R3 = 146 (X'0092') (B'10010010')
TM DATA1,B'00000010' Test under mask using H'2'
BO PGM40100 Branch if TM left any one's
PGM40100 EQU * .
.
.
DATA1 DS H Define fullword variable
DATA1 10010010
Mask 00000010
____________
TM Result 0 0 0 0 0 0 1 0

BCR
Branch on Condition Register
Branch to the address contained in the register in operand 2 if the condition code in the PSW satisfies the mask
specified in operand 1.
label BCR M,R
Operand 1 Operand 2
Use Mask Address
Format Halfword Register No
or Binary
Spec Decimal value for R = Register #
Halfword literal or Symbolic Name
or Binary Number of Register

Length = Halfword
OP CODE M R
0-7 8-11 12-15
07
07MR
The condition code (CC) in the PSW indicates the condition after the last compare, arithmetic, or Test Under Mask
operation. The CC also determines which of 4 test bits are to be matched or (non-matched) to the mask, as follows:
Condition Bit Bit Bit Bit
code 0 1 2 3 Mask
00 1 0 0 0 8
01 0 1 0 0 4
10 0 0 1 0 2
11 0 0 0 1 1
The following table shows the branch condition, mask specifier, and machine code for each of the possible conditions
used for BCR instruction.
Mask Mask Operation which
Branch Condition (Decimal) (Binary) Machine code set condition
Unconditional 15 1111 07F General
NOP 0 0000 070 "
High 2 0010 072 Compare
Low 4 0100 074 "
Equal 8 1000 078 "
Not High 13 1101 07D '
Not Low 11 1011 07B "
Not Equal 7 0111 077 "
Plus 2 0010 072 Arithmetic
Minus 4 0100 074 "
Zero 8 1000 078 "
Overflow 1 0001 071 "
Not Plus 13 1101 07D "
Not Minus 11 1011 07B "
Not Zero 7 0111 077 "
No Overflow 14 1110 07E "
Ones 1 0001 071 Test Under Mask
Mixed 4 0100 074 "
Zero's 8 1000 078 "
Not Ones 14 1110 07E "
Not Mixed 11 1101 07B '
Not Zero's 7 0111 077 "
Not Zero 4 0100 074 Boolean
Zero 8 1000 078 "

BCR
Branch on Condition Register
(cont.)
Example 1:
(Arithmetic)
LA R4,PGM40100 Load R4 with addr of PGM40100
S. R2,DATA Subtract F'21' from zero
BCR 4,R4 Branch to PGM40100 if result is minus
PGM40100 EQU * .
.
.
Example 2:
(Compare)
L R3,F'12' set R3 = 12
BCR 8,R4 Branch to PGM40100 if DATA1 = F'12'
PGM40100 EQU * .
.
.
Example 3:
(Test Under Mask)
LH R3,H'146' set R3 = 146 (X'0092') (B'10010010')
BCR 1,R4 Branch if TM left any one's
PGM40100 EQU * .
.
.
DATA1 10010010
Mask 00000010
____________
TM Result 0 0 0 0 0 0 1 0

B_R
Branch on Condition _ Register
Branch to the address contained in the register in operand 2 if the condition code in the PSW satisfies the branch
mnemonic.
label B_R R
B_ Operand
Use Branch Mnemonic Address
Format See Branch Mnemonic Register No
Table
Spec Characters (see table R = Register #
below) or Symbolic Name
of Register

Length = Halfword
OP CODE _ R
0-7 8-11 12-15
07
07_R
The following table shows the branch condition, branch mnemonic, and machine code for each of the possible branch
conditions.
Branch
Branch Condition Mnemonic Machine code Operation which
(Branch if...) (B_R (07_) set condition
Unconditional BR 07F General
NOP NOP 070 "
High BHR 072 Compare
Low BLR 074 "
Equal BER 078 "
Not High BNHR 07D '
Not Low BNLR 07B "
Not Equal BNER 077 "
Plus BPR 072 Arithmetic
Minus BMR 074 "
Zero BZR 078 "
Overflow BOR 071 "
Not Plus BNPR 07D "
Not Minus BNMR 07B "
Not Zero BNZR 077 "
No Overflow BNOR 07E "
Ones BOR 071 Test Under Mask
Mixed BMR 074 "
Zero's BZR 078 "
Not Ones BNOR 07E "
Not Mixed BNMR 07B '
Not Zero's BNZR 077 "
Not Zero BNZR 074 Boolean
Zero BZR 078 "

B_R
Branch on Condition _Register
(cont.)
Example 1:
(Arithmetic)
S R2,DATA Subtract F'21' from zero
BMR R4 Branch to PGM40100 if result is minus
PGM40100 EQU * .
.
.
Example 2:
(Compare)
L R3,F'12' Set R3 = 12
BER R4 Branch to PGM40100 if DATA1 = F'12'
PGM40100 EQU * .
.
.
Example 3:
(Test Under Mask)
LH R3,H'146' Set R3 = 146 (X'0092') (B'10010010')
BOR R4 Branch if TM left any one's
PGM40100 EQU * .
.
.
DATA1 10010010
Mask 00000010
____________
TM Result 0 0 0 0 0 0 1 0

BCT
Branch on Count
Branches to the address specified in operand 2 as long as the value in the register specified in operand 1 is not 0. Used
for executing loops a given number of times. The register gets decremented and tested for 0 after each time through the
loop.
label BCT R,D(X,B)
Operand 1 Operand 2
Use No. of times to loop Branch to Addr
or label
B = Register # or
symbolic Reg name

OP CODE R X B D
0-7 8-11 12-15 16-19 20-31
46
46RXBDDD
Example:
LA R4,4 Load R4 with decimal 4
LOOPSTRT EQU * Start of loop
.
.
.
BCT R4,LOOPSTRT Branch to start of loop if R4 not = 0
PGM40100 EQU *
.
.
In this example the LOOPSTRT routine will be executed 4 times. Each time the BCT is executed, R4 is
decremented by 1 and tested for 0. If R4 is not 0 , the program branches back to LOOPSTRT. Once R4 is
decremented to 0, the program logic falls through to the PGM40100 routine. Below is a pictorial
representation of the example.

BCTR
Branch on Count Register
Branches to the address contained in the register specified in operand 2 as long as the value in the register specified in
operand 1 is not 0. Used for executing loops a given number of times. The register gets decremented and tested for 0
after each time through the loop. No branch occurs if the value in the contents of the second register equal 0.
label BCTR R1,R2
Operand 1 Operand 2
Use No. of times to loop Branch to Addr

Length = Halfword
OP CODE R1 R2
0-7 8-11 12-15
06
06AR1R2
Example 1:
LA R2,LOOPSTRT Load R2 with addr of LOOPSTRT
LA R4,4 Load R4 with decimal 4
LOOPSTRT EQU * Start of loop
.
.
.
BCTR R4,R2 Branch to start of loop if R4 not = 0
PGM40100 EQU *
.
.
In this example the LOOPSTRT routine will be executed 4 times. Each time the BCT is executed, R4 is
decremented by 1 and tested for 0. If R4 is not 0 , the program branches back to LOOPSTRT. Once R4 is
decremented to 0, the program logic falls through to the PGM40100 routine. Below is a pictorial
representation of the example.
This instruction can also be used to subtract 1 from a register, since no branch occurs if the contents of the second
register equals 0.
Example 2:
BCTR R7,R0 Decrement R7 and don't branch since R0=0
.......... Next Instruction performed
similarly
BCTR R7,0 Decrement R7 and don't branch since 2nd
operand = 0
.......... Next Instruction performed

BEGIN
BEGIN Macro
BEGIN NAME=Program Name
where Program Name = 6 character Component (Segment) name and version number of your
program.
The BEGIN macro establishes the standard base registers and linkages for your program. The BEGIN statement must
be the first statement in your source code beginning at column 10. The program name must start at column 16.
Example:
1 2 3
STMT 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0
001 B E G I N N A M E = P G M 4 T 3
002 P R I N T N O G E N
003 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
004 * T H I S P R O G R A M C H E C K S T H E S T A T
005 * O F T H E I N C O M I N G M E S S A G E A F T E
006 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
007 *

Boolean Algebra
LOGICAL 'OR' TRUTH TABLE
SOURCE BIT "OR"ed RESULTING
(Mask) AGAINST TARGET BIT Equals TARGET BIT
0 0 0
0 1 1
1 0 1
1 1 1
LOGICAL 'AND' TRUTH TABLE

SOURCE BIT "AND"ed RESULTING
0 0 0
0 1 0
1 0 0
1 1 1
LOGICAL 'XOR' (Exclusive OR) TRUTH TABLE

SOURCE BIT "XOR"ed RESULTING
0 0 0
0 1 1
1 0 1
1 1 0

Boolean Operations
Use OR to selectively turn target bits ON. A 1 turns the target bit on, and a 0 leaves the target bit as it was.
Example:
LABEL1 DC B'10100110'
OI LABEL1,H'16' OR Immediate LABEL1 with B'00010000'
Before: LABEL1 After: LABEL1

Bit # 0 1 2 3 4 5 6 7 Bit # 0 1 2 3 4 5 6 7
(bits) 1 0 1 0 0 1 1 0 (bits) 1 0 1 1 0 1 1 0
OR H’16’ 0 0 0 1 0 0 0 0
This example turns on bit 3 of the LABEL1 storage area.
____________________________________________________________________________________________
Use AND to selectively turn target bits OFF. A 0 turns the target bit off, and a 1 leaves the target bit as it was.
Example:
LABEL1 DC B'10100110'
NI LABEL1,H'251' AND Immediate LABEL1 with
B'11111011'

Bit # 0 1 2 3 4 5 6 7 Bit # 0 1 2 3 4 5 6 7
(bits) 1 0 1 0 0 1 1 0 (bits) 1 0 1 0 0 0 1 0
AND H’251’ 1 1 1 1 1 0 1 1
This example turns off bit 5 of the LABEL1 storage area.
____________________________________________________________________________________________
Use XOR to selectively TOGGLE target bits. A 1 toggles the target bit, and a 0 leaves the target bit as it was.
Example:
LABEL1 DC B'10100110'
XI LABEL1,H'3' XOR Immediate LABEL1 with
B'00000011'

Bit # 0 1 2 3 4 5 6 7 Bit # 0 1 2 3 4 5 6 7
(bits) 1 0 1 0 0 1 1 0 (bits) 1 0 1 0 0 1 0 1
XOR H’3’ 0 0 0 0 0 0 1 1
This example toggles bits 7 & 8 of the LABEL1 storage area.
____________________________________________________________________________________________
The XOR operation can be used to SWAP the contents of two storage areas (XC instruction), two registers (XR
instruction), or between a register and storage (X instruction).
Example:
DOG DC C'DOG'
CAT DC C'CAT'
XC DOG,CAT
XC CAT,DOG
XC DOG,CAT
This example swaps the contents of the storage areas DOG and CAT.
____________________________________________________________________________________________
The XOR operation can also be used to CLEAR a storage area
Example:
XC DOG,DOG
This example clears the storage area DOG.

C
Compare (Arithmetic)
Compares the contents of a 4-byte storage area to the contents of a register. The compare treats the two numbers as
signed binary numbers. The result is saved in the Condition code bits of the PSW. The storage location is unchanged.
label C R1,D2(X2,B2)
Operand 1 Operand 2
Use Register Storage Area
Register or literal
B = Register # or
symbolic Reg name

OP CODE R1 X2 B2 D2
0-7 8-11 12-15 16-19 20-31
59
59R1X2B2DDD2
The condition code is set according to the results as follows:
Results Cond code

EQUAL 0
1st Opr LOW 1
1st Opr HIGH 2
N/A 3
Example 1:
R2 = X'00000010' R8 = 010816
Addr 012816 = LABEL1 = DC X'00000010' (or F'16')
C R2,32(R8)
or C R2,LABEL1
In this example, the condition code would be set to 0 since the contents of R2 and LABEL1 are equal.
Example 2:
R2 = F'27' R8 = 010816
Addr 012816 = LABEL1 = DC F'-27'
C R2,32(R8)
or C R2,LABEL1
In this example, the condition code would be set to 2 since the contents of R2 is greater then the contents of
LABEL1.

CH
Compare Halfword (Arithmetic)
Compares the contents of a 2-byte storage area to the 2 low-order bytes of a register. The compare treats the two
numbers as signed binary numbers. The result is saved in the Condition code bits of the PSW. The storage location is
unchanged.
label CH R1,D2(X2,B2)
Operand 1 Operand 2
Register or literal
B = Register # or
symbolic Reg name

OP CODE R1 X2 B2 D2
0-7 8-11 12-15 16-19 20-31
49
49R1X2B2DDD2
Results Cond code

EQUAL 0
1st Opr LOW 1
1st Opr HIGH 2
N/A 3
Example1:
R2 = X'00000010' R8 = 010816
Addr 012816 = LABEL1 = DC X'0010' (or H'16')
CH R2,32(R8)
or CH R2,LABEL1
In this example, the condition code would be set to 0 since the contents of R2 (2 low-order bytes) and
LABEL1 are equal.
Example2:
R2 = X'00000010' R8 = 010816
Addr 012816 = LABEL1 = DC H'-16'
CH R2,32(R8)
or CH R2,LABEL1
In this example, the condition code would be set to 2 since the contents of R2 (2 low-order bytes) is greater
then the contents of LABEL1.

CL
Compare Logical
Compares the contents of a 4-byte storage area to the contents of a register. The compare is made left to right, bit for
bit. The two numbers are treated as unsigned binary numbers. The result is saved in the Condition code bits of the
PSW. The storage location is unchanged.
label CL R1,D2(X2,B2)
Operand 1 Operand 2
Register or literal
B = Register # or
symbolic Reg name

OP CODE R1 X2 B2 D2
0-7 8-11 12-15 16-19 20-31
55
55R1X2B2DDD2
Results Cond code

EQUAL 0
1st Opr LOW 1
1st Opr HIGH 2
N/A 3
Example 1:
R2 = C’ABCD' R8 = 010816
Addr 012816 = LABEL1 = DC C’ABCD’
CL R2,32(R8)
or CL R2,LABEL1
In this example, the condition code would be set to 0 since the contents of R2 and LABEL1 are equal.
Example 2:
R2 = C'ABCD' (X’C1C2C3C4’) R8 = 010816
Addr 012816 = LABEL1 = DC C’1234’ (X’F1F2F3F4’)
CL R2,32(R8)
or CL R2,LABEL1
In this example, the condition code would be set to 1 since the contents of R2 is less then the contents of
LABEL1. Note that the sign of the number in LABEL1 is negative, but since sign is not taken into
consideration, the contents of LABEL1 are greater then the contents of R2.

CLC
Compare Logical Characters
SS Type Op code = D5
Compares the contents of two storage areas. The compare is made left to right, bit for bit. The two numbers are treated
as unsigned binary numbers. The result is saved in the Condition code bits of the PSW. The storage locations are
unchanged.
label CLC D1(L,B1),D2(B2)
Operand 1 Operand 2
Use Storage Area 1 Storage Area 2
Format Base/ILength/Displa Base/Displacement
or label or label
Spec D = Decimal value D = Decimal value
L* = Decimal value B = Register # or
B = Register # or symbolic Reg name
symbolic Reg name
* Length may also be specified by a length attribute (e.g. LABEL1(L'LABEL2)). If length is not specified, the length of the
operation defaults to the length of the first operand.

OP CODE L B2 D1 B2 D2
0-7 8-15 16-19 20-31 32-35 36-48
D5
D5LLB1DDD1B2DDD2
Results Cond code
EQUAL 0
1st Opr LOW 1
1st Opr HIGH 2
N/A 3
Example 1:
R8 = 000A16
Addr 010A16 = LABEL1 = DC C'CODE'
Addr 012816 = LABEL2 = DC C'CODED'
CLC 256(4,R8),286(R8)
In this example, the condition code would be set to 0 since the first 4 bytes of LABEL1 and the first 4 bytes of
LABEL2 are equal. The length of the compare is 4 bytes.
Example 2:
= LABEL1 = DC C'DEAR'
= LABEL2 = DC C'DEER'
CLC LABEL1,LABEL2
In this example, the condition code would be set to 1 since the first 4 bytes of LABEL1 are lower in value than
first 4 bytes of LABEL2. The length of the compare defaults to the length of LABEL1 as it was defined (4
bytes)..
Example 3:
= LABEL1 = DC C'DEAR'
= LABEL2 = DC C'DEER'
CLC LABEL1(2),LABEL2
or
CLC LABEL1(L'LABEL2-2),LABEL2
In this example, the condition code would be set to 0 since the first 2 bytes of LABEL1 are equal to the first 2
bytes of LABEL2. The length of the compare is 2 bytes.

CLI
Compare Logical Immediate
SI Type Op code = 95
Compares the 1-byte of storage area to immediate data. The compare is made left to right, bit for bit. The two
numbers are treated as unsigned binary numbers. The result is saved in the Condition code bits of the PSW. The
storage location is unchanged.
label CLI D1(B1),I2
Operand 1 Operand 2
Use Storage Area Source Data
(Immediate)
Format Base/Displacement Literal
or Label
Spec D = Decimal value Absolute expression
B = Register # or such as:
symbolic Reg name C’..’, X’..’, B’..’, or a
decimal value.
* Length is fixed at 1 byte.

OP CODE I I B2 D2
0-7 8-15 16-19 20-31

95
95II2B1DDD1
Results Cond code

EQUAL 0
1st Opr LOW 1
1st Opr HIGH 2
N/A 3
Example 1:
R8 = 010816 = LABEL1 = DC X'0F'
CLI 0(R8),X'0F'
or CLI LABEL1,X'0F'
In this example, the condition code would be set to 0 since the contents of LABEL1 is equal to the immediate
data, X'0F'
( Notice, the immediate data is specified as X’0F’and not with an equal sign, i.e. =X’0F’ )
Example 2:
R8 = 010816 addr of LABEL1 = DC C'B'
CLI 0(R8),C'A'
or CLI LABEL1,C'A'
In this example, the condition code would be set to 2 since the immediate data ('A'=EBCDIC C1) is less then
the contents of LABEL1 ('B'=EBCDIC C2).

CLM
Compare Logical Characters Under Mask
RS Type Op code = BD
Compares the contents of selected bytes of a register with the left most 1 to 4 bytes of a storage area. The two numbers
are treated as unsigned binary numbers. The result is saved in the Condition code bits of the PSW. The storage
location is unchanged. The bits of the mask correspond one-to-one with the bytes of the register.
label CLM R1,M,D3(B3)
Operand 1 Operand 2 Operand 3

Use Register Mask Storage Area
Format Register No. Binary, Hex, or Decimal Base/Index/Displac
or Symbolic Name of Value or label
Register 0-15 or literal
Spec R = Register # Binary, Hex, or Decimal D = Decimal value
or Symbolic Name Value X = Register # or
of Register 0-15 symbolic Reg name
B = Register # or
symbolic Reg name

OP CODE R1 M B3 D3
0-7 8-11 12-15 16-19 20-31
BD
BDR1X2B3DDD3
Results Cond code

EQUAL 0
or
Mask = 0
1st Opr LOW 1
1st Opr HIGH 2
N/A 3
Example 1:
or CLM R2,B'1010',LABEL1
Mask 1 0 1 0
R2 F A 6 0
compare these bytes
LABEL1 F 6 1 D
In this example, the condition code would be set to 0 since the bytes 1 and 3 of R2 are equal to the first two
bytes of LABEL1.

CLR
Compare Logical Registers
Compares the contents of two registers. The compare is made left to right, bit for bit. The two numbers are treated as
unsigned binary numbers. The result is saved in the Condition code bits of the PSW. The storage location is
unchanged..
label CLR R1,R2
Operand 1 Operand 2
Use Address Address
Format Register No Register No

Length = Halfword
OP CODE R1 R2
0-7 8-11 12-15
15
15R1R2
Results Cond code
EQUAL 0
1st Opr LOW 1
1st Opr HIGH 2
N/A 3
Example 1:
R2 = X'000000FF' R3 = X’000000FF’
CLR R2,R3
In this example, the condition code would be set to 0 since the contents of R2 and R3 are equal.
Example 2:
R2 = X'000000FF' R3 = X’F00000F4’
CLR R2,R3
In this example, the condition code would be set to 1 since the contents of R2 is less than the contents of R3.
Note that the sign of the number in R3 is negative, but since sign is not taken into consideration, the contents
of R3 are greater then the contents of R2.

CR
Compare Registers (Arithmetic)
Compares the contents of a register to the contents of another register. The compare treats the two numbers as signed
binary numbers. The result is saved in the Condition code bits of the PSW. The storage location is unchanged.
label CR R1,R2
Operand 1 Operand 2
Use Address Address
Format Register No Register No

Length = Halfword
OP CODE R1 R2
0-7 8-11 12-15
19
19R1R2
Results Cond code
EQUAL 0
1st Opr LOW 1
1st Opr HIGH 2
N/A 3
Example 1:
R2 = X'000000FF' R3 = X’000000FF’
CR R2,R3
In this example, the condition code would be set to 0 since the contents of R2 and R3 are equal.
Example 2:
R2 = X'000000FF' R3 = X’F00000F4’
CR R2,R3
In this example, the condition code would be set to 2 since the contents of R2 is greater than the contents of
R3. Note that the sign of the number in R3 is negative.

CSECT
Define Control Section
(Assembler Directive)
The CSECT directive indicates the beginning of the program. When preceded by a dummy section (DSECT), CSECT
also indicates the end of the DESCT and the beginning of the program. The CSECT directive statement must contain a
label, and the label must the same as the program name, for example, PGM4.
label CSECT
Example:
BEGIN NAME=PGM4,VER=T3
PRINT NOGEN
* P R O G R AM D E S CR I P T I O N A R E A *
* . *
* . *
* . *
***********************************************************************
***********************************************************************
* F L I G H T R E C OR D D S E CT *
* . *
***********************************************************************
F L T RE C DSECT
FFHDR DS CL18 HEADER INFO
.
.
.
.
*----------------------------------------------------------------------
* P A S S E N G ER I N F O R M A T I O N *
*----------------------------------------------------------------------
FPITM DS XL140 1 0 P A S S E N G ER I T E M S
* ( 1 4 B Y T ES P E R I T E M )
ORG FPITM
*
FPIND1 DS XL1 S W I T C H B Y T E N U M B ER 1
.
.
.
.
.
FPLEN EQU *-FPIND1
*----------------------------------------------------------------------
* E N D O F F L I G H T R E C O RD D S E CT *
*----------------------------------------------------------------------
***********************************************************************
PGM4 C S E CT
***********************************************************************
* B E G I N M A I N L I N E P O R T I O N O F P R O G R AM *
***********************************************************************
PGM40000 EQU *
U S I N G F L T RE C , R 7
.
.
This example show the use of the CSECT directive to end the DSECT and begin the control section of the
program Note the label of the CSECT statement is PGM4, the same as the program name.

CVB
Convert to Binary
RX Type Op code = 4F
Converts a packed decimal storage area specified in Operand 2 to binary and places it in the register specified by
Operand 1. All 8 bytes of the doubleword specified by Operand 2 must be in packed decimal format or a program
check will result.
label CVB R1,D2(X2,B2)
Operand 1 Operand 2*
or label
or literal
B = Register # or
symbolic Reg name
* The effective address of Operand 2 must be on a double word boundary.

OP CODE R1 X2 B2 D2
0-7 8-11 12-15 16-19 20-31
4F
4FR1X2B2DDD2
The condition code is not affected by the CVB instruction.
Example:
PNUM DS D
CVB R2,PNUM
Sign = C or F for Positive numbers, D for negative numbers

Before R2 PNUM
(hex bytes) C 3 C 4 C 7 C 1 0 0 0 0 0 0 0 0 0 0 1 2 3 4 5 F
(Packed Decimal Format)
After R2 PNUM
(hex bytes) 0 0 0 0 3 0 3 9 0 0 0 0 0 0 0 0 0 0 1 2 3 4 5 F

CVD
Convert to Decimal
RX Type Op code = 4E
Converts a binary number in the register specified by Operand 1 to a packed decimal number and places it in the
doubleword storage area specified by Operand 2.
label CVD R1,D2(X2,B2)
Operand 1 Operand 2*
or label
or literal
B = Register # or
symbolic Reg name
* The effective address of Operand 2 should be on a double word boundary.

OP CODE R1 X2 B2 D2
0-7 8-11 12-15 16-19 20-31
4E
4ER1X2B2DDD2
The condition code is not affected by the CVD instruction.
Example:
PNUM DS D
CVD R2,PNUM
Before R2 PNUM
(hex bytes) 0 0 0 0 3 0 3 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
After R2 PNUM
(hex bytes) 0 0 0 0 3 0 3 9 0 0 0 0 0 0 0 0 0 0 1 2 3 4 5 C
(Packed Decimal Format)
Sign = C for Positive numbers, D for negative numbers

D
Divide
RX Type Op code = 5D
Divides a 64 bit integer (dividend), contained in two registers starting with the register (even numbered) specified in
Operand 1., by a 32 bit integer (divisor) contained in fullword of storage. The quotient and the remainder replace the
dividend in the registers. The storage location remains unchanged. R 1 must be an even numbered register and the
Operand 2 must be on a fullword boundary. Dividing by 0 will produce a dump.
label D R1,D2(X2,B2)
Operand 1 Operand 2
Register or literal
B = Register # or
symbolic Reg name

OP CODE R1 X2 B2 D2
0-7 8-11 12-15 16-19 20-31
5D
5DR1X2B2DDD2
The condition code is not affected by the Divide instruction.
Example : (11 / 4 = 2, remainder 3)

R2 = X'00000000' R3 = X’0000000B’
LABEL1 = DC X'00000004'
D R2,LABEL1
Dividend Divisor
Before: R2 R3 LABEL1
(hex bytes) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B 0 0 0 0 0 0 0 4
Remainder Quotient
(hex bytes) 0 0 0 0 0 0 0 3 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 4

DC
Define Constant
The DC directive is used to allocate storage, establish values to that storage to be used as initial values or constants, and
to optionally assign a symbolic label to the address of that storage. Use DCs only in the Define Constants area of your
program. You must assign an initial value to the constants.
label DC dTl’C’
where:
label = (Optional) 1 to 8 Alpha-Numeric characters by which you refer to the constant
d = Duplication (Optional) (default=1) - Unsigned decimal value that expresses number
of times you want this storage to be repeated
T = Type (Required) - The type of constant that you want the assembler to define (See
Summary of Constants table below)
l = Length (Optional) - The character ‘L’ plus a decimal value indicating how many
bytes you want this constant to be. If this value is omitted, the length will be
implied by the specified constant
‘C’ = Constant (Required) - The initial value for this area of storage
Summary of Constants
Implied Max Truncation
Length Length Boundary or
Type (bytes) (bytes) Alignment Format Padding
C 1 256 BYTE Characters Right
X 1 256 BYTE Hexadecimal Digits Left
B 1 256 BYTE Binary Digits Left
F 4 4 WORD Signed Decimal Left
H 2 2 HALFWORD Signed Decimal Left
D 8 8 DOUBLEWORD Signed Decimal Right
P as necc. as necc. BYTE Packed Decimal Left
Z as necc. as necc. BYTE Zoned Decimal Left
A 4 4 WORD Value of Address Left
Y 2 2 HALFWORD Value of Address Left
See examples on next page.

DC (cont.)
Define Constant
Examples: ( = space character - EBCDIC X’40’)
De fi ne Co ns ta nt As se mbl e d As Re ma rk s
S ou rc e S ta te me n t
DC C’1234567’ 1234567 Implied length of 7 bytes

DC 4C’G’ GGGG Duplication factor of 4
DC CL10’1234567’ 1234567 Pad right with spaces
DC CL3’1234567’ 123 Truncate on right
DC X’ABCD’ X’ABCD’ Implied length of 2 bytes
DC XL4’ABCD’ X’0000ABCD’ Pad left with zero’s
DC XL2’ABCDEF’ X’CDEF’ Truncation on left
DC 3XL2’FOFOF1’ X’F0F1F0F1F0F1’ Duplication factor of 3, and truncation on left
DC B’10010111’ B’10010111’ Implied length of 1 byte
DC B’10011’ B’00010011’ Padding on left to keep length a multiple of 8 bytes
DC F’21’ X’00000015’ Stores as Binary, Implied length of 4 bytes
DC F’-1’ X’FFFFFFFF’ Stores in two’s compliment, Implied len. of 4 bytes
DC H’10’ X’000A’ Stores as Binary, Implied length of 2 bytes
DC H’-1’ X’FFFF’ Stores in two’s compliment, Implied len. of 2 bytes
DC P’123’ X’123C’ Implied length of 2 bytes
DC P’1234’ X’01234C’ Pad zero on left
DC PL3’12.3’ X’00123C’ Pad left with zero’s; decimal point ignored
DC PL2’1234’ X’234C’ Truncation on left
DC Z’123’ X’F1F2C3’ Implied length, one byte per decimal digit
DC ZL3’12’ X’F0F1F2’ Pad EBCDIC zero’s (F0) on left; dec. point ignored
DC ZL2’123’ X’F2F3’ Truncation on left
If Addr of LABEL1 = 00AE1234 X’00AE1238’ Length = 4 bytes (fullword)
DC A(LABEL1+4)
If location counter = 00AE1234 X’00AE1234’
DC A(*)

DR
Divide Registers
RR Type Op code = 1D
Divides a 64 bit integer (dividend), contained in a register pair starting with the even numbered register specified in
Operand 1., by a 32 bit integer (divisor) contained in the register specified in Operand 2. The quotient and the
remainder replace the dividend in the Operand 1 register pair. The register specified in Operand 2 remains unchanged.
R1 must be an even numbered register. R 2 must not be part of the R1 register pair. Dividing by 0 will produce a dump.
label DR R1,R2
Operand 1 Operand 2

Length = Halfword
OP CODE R1 R2
0-7 8-11 12-15
1D
1DR1R2
The condition code is not affected by the Divide Register instruction.
Examples : (25 / 4 = 6, remainder 1)

R2 = X'00000000' R3 = X’00000019’ R4 = X’00000004’
DR R2,R4
Dividend Divisor
Before: R2 R3 R4
(hex bytes) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 9 0 0 0 0 0 0 0 4
Remainder Quotient
After: R2 R3 R4
(hex bytes) 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 6 0 0 0 0 0 0 0 4

DROP
Drop Base Register(s) Directive
This assembler directive cancels previous USINGs on one or more registers. Drop only affects those instructions that
physically follow it. An assembler error will occur if a DROP is specified for a register for which a USING was never
in effect. This directive is generally used to terminate the use a particular base register in preparation for establishing
that same register as a base register for another DSECT. If the operand is left blank, all registers will be dropped.
(No label) DROP R1[R2,...] or blank

(operand entries in brackets are optional)
Operand 1
Use Base Register
Format Register No.
Spec R = Register # or
symbolic Reg name
Example:
If FLTREC and PSGDAT are symbolic labels for a DSECTs...
PGM400 EQU *
USING FLTREC,R7 Establishes R7 as base register for FLTREC DSECT
GETCC D4,L2 Get 1055 byte block on Level 4 for DSECT data storage
L R7,CE1CR1 Load Data Level 1 base address in R7
.
.
.
PGM500 EQU *
DROP R7 Cancel previous USING in effect for R7
USING PGGDAT,R7 Establishes R7 as base register for PSGDAT DSECT
This example first establishes R7 as the base register for fields in the DSECT named FLTREC. When the
program reaches PGM500, register R7 is dropped so it can be re-used as a base register for the DSECT named
PSGDAT.

DS
Define Storage
The DS directive is used to allocate storage without initializing the contents of the reserved bytes, and to optionally
assign a symbolic label to the address of that storage.
label DS dTl
where:
label = (Optional) 1 to 8 Alpha-Numeric characters by which you refer to the storage
d = Duplication (Optional) (default = 1) - Unsigned decimal value that expresses

number of times you want this storage to be repeated.
A value of 0 indicates that no storage will be reserved but the label will be
referenced to the current value of the location counter. If the duplication factor is 0
and the constant type is D, F, or H, alignment to the indicated boundary occurs.
When the DS is used with a duplication factor of 0 in the program’s Define Constant
area, it is usually followed by a number of DC directives whose length values total
the length value of the leading DS directive.
T = Type (Required) - The type of constant that you want the assembler to define for the
storage area (See Summary of Constants table below)
l = Length (Optional) - The character ‘L’ plus a decimal value indicating how many
bytes you want this storage area to be. If this value is omitted, the length will be
implied by the specified constant
Summary of Constants
Implied Max
Length Length Boundary
Type (bytes) (bytes) Alignment Format
C 1 256 BYTE Characters
X 1 256 BYTE Hexadecimal Digits
B 1 256 BYTE Binary Digits
F 4 4 WORD Signed Decimal
H 2 2 HALFWORD Signed Decimal
D 8 8 DOUBLEWORD Signed Decimal
P as necc. as necc. BYTE Packed Decimal
Z as necc. as necc. BYTE Zoned Decimal
A 4 4 WORD Value of Address
Y 2 2 HALFWORD Value of Address
See examples on next page.

DS (cont.)
Define Storage
Examples:
De fi ne Cons ta n t Remarks
S o urc e S ta teme nt
DS CL10 Reserves 10 consecutive bytes

DS 4CL10 Reserves 40 consecutive bytes
HOLD DS 0CL16 References label HOLD to current location count
B1 DS CL8 and reserves storage for two 8-bytes storage areas
B2 DS CL8 labeled B1 & B2
DS XL8 Reserves 8 consecutive bytes
DS 100XL4 Reserves 400 consecutive bytes
DS B Reserves 1 byte
DS 6B’ Reserves 6 consecutive bytes
DS D Reserves a doubleword for numeric data
DS 0D’ Forces doubleword alignment
DS 3F Reserves 3 consecutive fullwords for numeric data
DS 0F’ Forces fullword alignment
DS 6H Reserves 6 consecutive halfwords for numeric data
DS 0H Forces halfword alignment
DS PL3’ Reserves 3 bytes for a packed decimal number
DS ZL2 Reserves 3 bytes for a zoned decimal number

DSECT
Define Dummy Section
The DSECT directive initiates the definition of dummy section. A dummy section allows you to describe the layout of
data in a storage area without actually reserving any storage. Storage layout is defined using only the Define Storage
(DS) directive. To use the symbols defined in a dummy section, include in the mainline portion of the code a USING
statement that designates the label of the DSECT statement and a register to be used as the base register when
referencing the symbols.
label DSECT
Example:
BEGIN NAME=PGM4,VER=T3
PRINT NOGEN
***********************************************************************
* P R O G R AM D E S CR I P T I O N A R E A *
* . *
* . *
***********************************************************************
***********************************************************************
* F L I G H T R E C OR D D S E CT *
***********************************************************************
F L T RE C DSECT
FFHDR DS CL18 HEADER INFO
ORG FFHDR.
FFNUM DS CL5 F L I G H T N U M BE R
FFAIRE DS CL3 A I R C R AF T E Q U I P M E N T
FAVLS DS H A V A I L A B LE S E A T S
FROUT DS CL6 CITY ROUTING (FROM/TO)
FNPIT DS H N U M BE R O F P S G R I T E M S
*----------------------------------------------------------------------
* P A S S E N G ER I N F O R M A T I O N F O R E A C H P A S S E N G ER I T E M *
*----------------------------------------------------------------------
FPITM DS XL140 1 0 P A S S E N G ER I T E M S
* ( 1 4 B Y T ES P E R I T E M )
ORG FPITM
*
F P M E A LS D S XL1 R E Q U E ST E D M E A L S
* X’80’ = SALT FREE
* X’40’ = VEGITARIAN
* X’20’ = CHILD’S MEAL
* X ’ 1 0 ’ = K O S H ER
F P C L A SS D S XL1 CLASS OF SERVICE
* X’80’ = F
* X’40’ = Y
* X’20’ = M
* X’10’ = (NOT USED)
FPNUM DS H N U M BE R I N P A R T Y
FPNAM DS CL9 P A S S E N G ER N A M E
FPSPA DS XL1 UNUSED BYTE (FUTURE)
.
FPLEN E Q U * - F M E A LS LENGTH OF ONE ITEM
*
*----------------------------------------------------------------------
PGM4 C S E CT
***********************************************************************
* B E G I N M A I N L I N E P O R T I O N O F P R O G R AM *
***********************************************************************
PGM40000 EQU *
U S I N G F L T RE C , R 7
.
.
.
.
This example shows the use of the DSECT directive used to define an area of storage called the Flight Record
(FLTREC). The Flight record consists of an 18 character header area and ten 14-byte passenger information
records. The passenger information area of the DSECT defines the typical layout for each of the 10 passenger
records to be stored, one after the other. The USING statement at PGM40000 directs the assembler to use R7
as the base register whenever referring to any of the symbols in the FLTREC DSECT. Accessing a particular
passenger record’s data is done by bumping R7 through the records FPLEN at a time until you are at the
desired record, and then using the appropriate symbolic label such as FPNUM in your assembler statement(s).

ED
Edit
SS Type Op code = DE
The Edit instruction uses a pattern to convert a packed-decimal number into a printable field that can blank leading
zeros and include punctuation such as commas and decimal points. The packed-decimal field is edited one byte at a
time, left to right, and the result replaces the pattern. The pattern must be the same size or longer than the source
packed-decimal field. The length attribute of first operand must be the length of the pattern.
label ED D1(L,B1),D2(B2)
Operand 1 Operand 2
Use Destination and Pattern Packed-Decimal Source
Address Address
or label or label
symbolic Reg name
Machine code Instruction Length = One and a Half Words

0-7 8-15 16-19 20-31 32-35 36-48
DE
DELLB1DDD1B2DDD2
Length value is 1 less than source statement length .
The condition code reflects the status of the last or only packed decimal field edited, and is set as follows:
Status of Last or Only Packed-Decimal Field

Cond code
ZERO
or 0
no Digit Selector or Significance Starter codes encountered
NON-ZERO 1
and Significance Indicator is ON (Negative Number)
NON-ZERO 2
and Significance Indicator is OFF (Positive number)
Pattern Characters:
Name Hex code Notation
Fill Character (FC) X’40’
Digit Selector (DS) X’20’ d
Significance Starter (SS) X’21’ [
Field Separator (FS) X’22’ ]
Message Character (MC) Any EBCDIC character code The Character
Pattern Example:
HEX 40 20 20 6B 20 21 20 4B 20 20
CHAR d d , d [ d . d d
First character of the pattern is the FILL character (FC),
in this case, the space character

ED
Edit
(cont.)
Significance Indicator (SI):

The Significance Indicator indicates the significance of source digits or message characters and is turned off at the start
of the edit process. It is turned on after the edit process either encounters the first non-zero source digit or a
significance starter in the pattern. After the process encounters a plus sign code (X’C’) in the rightmost 4 bits of a byte,
the Significance Indicator is turned off, otherwise it is left on.
Digit Selector (DS) :

The Digit Selector causes the Edit instruction to process the next source digit. If the source digit is zero and the
Significance Indicator is off, the fill character replaces the Digit Selector in the pattern. If the source digit is non-zero
or the Significance Indicator is on, the source digit replaces the Digit Selector in the pattern.
Significance Starter (DS):

Use the Significance Starter to force leading zeros and message characters. When the Significance Starter is
encountered, it is replaced with the fill character if the Significance Indicator is off, or replaced with the next source
digit if the Significance Indicator is on. After the Significance Starter is encountered in the pattern, the Significance
Indicator is turned on. This will cause subsequent source digits to replace subsequent Digit Selectors in the pattern, and
cause subsequent message characters in the pattern to remain unchanged.
Field Separator (FS):

The Field Separator enables a single Edit instruction to process several packed-decimal fields that are defined in
contiguous storage bytes. The pattern consists of several sub-patterns--one per packed-decimal field--that are separated
by Field Separator codes. The Edit instruction always replaces the Field Separator with the fill character and then turns
the Significance Separator off. The fill character is the leftmost character of the pattern sequence and applies to all
sub-patterns.
Message Characters (MC):

You can insert characters such as dollar signs, commas, periods, and percent signs anywhere within the pattern to
punctuate or label the output field. The message character is left unchanged if the Significance Indicator is on, and
replaced with the fill character if the Significance Indicator is off.
Example 1: Edit the number X’5DF’ (1503 10) which is in Register 2...
CVD R2,PNUM
ED PATTERN,PNUM+5
PATTERN DC X’402020202020’
PATTERN PNUM (after CVD)

Before: HEX 40 20 21 20 20 20 00 00 00 00 00 01 50 3C
Char d [ d d d
FC DS DS DS DS DS
PATTERN (Output Field) PNUM

After: HEX 40 40 F1 F5 F0 F3 00 00 00 00 00 01 50 3C
Char 1 5 0 3
. SI Off SI On SI Off
Condition code = 2
Note that the source operand PNUM+5 points to the sixth byte, so that the five digits 0,1,5,0,3 will be
processed. Also note that there are five digit selectors (X’20’) in the pattern, one for each of the digits to be
processed.

ED
Edit
(cont.)
Example 2: Edit the number X’5DF’ (1503 10) which is in Register 2 and insert commas where appropriate...
CVD R2,PNUM
ED PATTERN,PNUM+5
PATTERN DC X’4020206B202020’

Before: HEX 40 20 20 6B 20 20 20 00 00 00 00 00 01 50 3C
Char d d , d d d
FC DS DS MC DS DS DS

After: HEX 40 40 F1 6B F5 F0 F3 00 00 00 00 00 01 50 3C
Char 1 , 5 0 3
Condition code = 2
Note that the source operand PNUM+5 points to the sixth byte, so that the five digits 0,1,5,0,3 will be
processed. Also note that in addition to the comma message character (X’6B’), there are five digit selectors
(X’20’) in the pattern, one for each of the digits to be processed.
Example 3: Edit the number X’3’ (310) which is in Register 2 so that the result is 0.03...
CVD R2,PNUM
ED PATTERN,PNUM+5
PATTERN DC X’402021204B2020’

Before: HEX 40 20 21 20 4B 20 20 00 00 00 00 00 00 00 3C
Char d [ d . d d
FC SS MC DS DS

After: HEX 40 40 40 F0 4B F0 F3 00 00 00 00 00 00 00 3C
Char 0 . 0 3
Condition code = 2
Note that the source operand PNUM+5 points to the sixth byte, so that the five digits 0, 0, 0, 0, 3 will be
processed. Also note that there are four digit selectors (X’20’) and a significant starter (X’21’) in the pattern..
These five characters will each process one digit in PNUM. This type of pattern is used to produce leading
zeros in a number field.

ED
Edit
(cont.)
Example 4: The following shows the effect of a pattern on different packed decimal numbers. The pattern
(PATTERN) will produce numbers in a fixed place two decimal format and is capable of handling any positive packed
decimal number (PNUM) that resides in a doubleword of storage (up to 15 digits). Note that the significant starter also
functions as a digit selector. There are 14 digit selectors and 1 significant starter in PATTERN, each processing 1 of 15
digits in PNUM.
If PATTERN = X’40 20 6B 20 20 20 6B 20 20 20 6B 20 20 20 6B 20 21 20 4B 20 20 ,
the instruction ED PATTERN,PNUM would produce the following results
(Note: = space [blank])
Example 4a.
If PNUM = X’00 00 00 00 00 00 00 3C’, then...
PATTERN (after EDIT instruction) =

X’40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 F0 4B F0 F3’, and
PATTERN will print as... 0.03 (17 leading spaces)
Example 4b.
If PNUM = X’00 00 00 00 00 02 01 4C’, then...

X’40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 F2 F0 4B F1 F4’, and
PATTERN will print as... 20.14 (16 leading spaces)
Example 4c.
If PNUM = X’00 00 00 00 01 02 01 4C’, then...

X’40 40 40 40 40 40 40 40 40 40 40 40 40 F1 6B F0 F2 F0 4B F1 F4’, and
PATTERN will print as... 1,020.14 (13 leading spaces)
Example 4d.
If PNUM = X’00 09 87 65 43 21 01 2C’, then...

X’40 40 40 40 40 F9 6B F8 F7 F6 6B F5 F4 F3 6B F2 F1 F0 4B F1 F2’, and
PATTERN will print as... 9,876,543,210.12 (5 leading spaces)

EJECT
Skip to a New Page Directive
EJECT
The EJECT directive instructs the assembler to skip to a new page and print the next line at the top of the new page.
The EJECT directive must be coded beginning in column 10.

END
END Source Module Directive
END
The END directive signals the end of a control section or program. END is normally coded as the last statement in
your source code beginning at column 10.

EQU
Equate Directive
The Equate directive is used to define a symbol (label). Once defined with an Equate, the symbol is treated as an
absolute value equal to the value of expression. Equated symbols can represent quantities or addresses. Equated
symbols do not use storage and the Equate directive does not generate machine language. In other words, when
the assembler encounters an Equate directive, it is processed but the location counter is not altered. The symbol is
assigned a length attribute which is the length of the symbol itself, except when using * (location counter reference) as
the expression. In this case the length is 1. Any symbols used in the expression operand must have been previously
defined.
label EQU expression
where label = 1-31 character name by which the value of expression will be known
expression = (required) An absolute expression or a relocatable expression
Example 1: (use of a relocatable expression)
001000 MVC DEST(L’SOURCE),SOURCE

BASR R3,PGM10100
.
.
.
001062 B PGM10020 GET NEXT LINE.
*
**********************************************
* ROUTINE TO EDIT INPUT LINE *
**********************************************
PGM10100 EQU *
001066 LA R1,L’SOURCE LOAD LOOP COUNT
.
.
.
In this example, the symbol PGM10100 is equated to the value X’001066’. The * (location counter
reference) is a relocatable expression which represents the address of the next available byte. The
location counter is at X’ 001065’ when the assembler reaches the equate statement and the address of
the next available byte is X’001066’. It is good practice to use the Equate statement in this manner to
label sections of your code, especially those that will be referenced elsewhere in the code, such as IN
branch instructions.
Example 2: (use of a relocatable expression)
001060 MVC DEST(MSGLEN),MSG

.
.
001270 MSG DC C’THIS IS A MESSAGE’
MSGLEN EQU *-MSG
001281 TABLE DC C’C1C2C3C4C5C6’
In this example, the symbol MSGLEN is equated to the value X’11’ (X’010281’ minus X’001270). The
* (location counter reference) is a relocatable expression which represents the address of the next
available byte. The location counter is at X’ 001280’ when the assembler reaches the equate statement
and the address of the next available byte is X’001281’. It is good practice to use the Equate statement
in this manner to avoid hard coding length values.

EQU
Equate Directive
(cont.)
Example 3: (use of an absolute expression)
R5 EQU 5
In this example, the symbol R5 is equated to the value 5 and R5 now becomes an absolute symbol. This
Equate directive is actually performed in the BEGIN macro that is seen at the beginning of all code
segments. It allows you to use the symbol R5 when specifying Register 5 (represented by the number 5)
in instruction statements.
Example 4: (use of an absolute expression)
LABEL1 EQU X’0F’
In this example, the symbol LABEL1 is equated to the value of the self-defining term X’0F’ and
LABEL1 now becomes an absolute symbol.

EX
Execute
The Execute instruction allows you to alter bits 8-15 of another instruction at run time and then execute that instruction.
The rightmost byte of the source operand register is OR’d with the second byte of the target instruction and then the
target instruction is executed. The next instruction is the one following the EX instruction unless the target instruction
is a branch instruction 1. Typically, you would place the target instruction somewhere near the EX instruction and
branch around it. You can use the EX instruction to dynamically alter the length of the fields involved in SS type
instructions (eg., MVC), alter the immediate data portion (e.g., OI) or mask data portion (e.g., TM) of SI type
instructions.
label EX R1,D2(X2,B2)
Operand 1 Operand 2
Use Target Instruction Source
Register or literal
B = Register # or
symbolic Reg name

OP CODE R1 X2 B2 D2
0-7 8-11 12-15 16-19 20-31
44
44R1X2B2DDD2
The condition code is not affected by the Execute instruction.
1
Note: if the target instruction is a branch instruction, the four right most bits of the register (R1) must be zeros.
Example 1: (using EX with SS type instructions)
31 ***********************************************************************
32 * BEGIN MAINLINE PORTION OF PROGRAM *
33 ***********************************************************************
.
.
.
000CA 89 EXI1010 EQU *
90 * MOVE LAST NAME AND FIRST NAME TO OUTPUT LINE
0000CA D209 814B 8ID9 0014B 001D9 91 MVC OUTPUT1,BLANKS10 BLANK OUT OUTPUT FIELD 1
0000D0 D209 815F 8ID9 0015F 00ID9 92 MVC OUTPUT2,BLANKS10 BLANK OUT OUTPUT FIELD 2
0000D6 4110 814B 0014B 94 LA R1l,OUTPUT1 ADDRESSABILITY TO OUTPUT AREA 1

0000DA 4130 81C5 001C5 95 LA R3,FNAME ADDRESSABILITY TO FIRST NAME
0000DE 4120 0003 00003 96 LA R2,L'FNAME-1 LENGTH OF FIRST NAME (ADJUSTED)
0000E2 4420 8138 00138 97 EX R2,MOVE MOVE FIRST NAME FOR EXACT LENGTH
0000E6 4110 815F 0015F 99 LA R1,OUTPUT2 ADDRESSABILITY TO OUTPUT AREA 1

0000EP 4130 B1CD 001CD l00 LA R3,LNAME ADDRESSABILITY TO LAST NAME
0000EE 4120 0005 00005 101 LA R2,L'LNAME-1 LENGTH OF LAST NAME (ADJUSTED)
0000F2 4420 B138 00138 102 EX R2,MOVE MOVE LAST NAME FOR EXACT LENGTH
104 XPRNT OUTPUT,L'OUTPUT PRINT
0012A 122 EXI1900 EOU * END OF PROGRAM

123 BACKC RETURN CONTROL TO CMS
128 *
000138 D200 1000 3000 00000 00000 129 MOVE MVC 0(0,R1),0(R3) TARGET OF EXECUTE INSTRUCTION
130 *
131 ***********************************************************************
132 * "WORKING STORAGE" DEFINITION BEGINS HERE *
133 ***********************************************************************
000140 134 WORKAREA DS 0D ALIGN ON DOUBLE WORD
135 *
000140 136 OUTPUT DS 0CL133 OUTPUT LINE
000140 FO 137 OUTCC DC CL1’0’ CARRAGE CONTROL, DOUBLE SPACE
000141 4040404040404040 138 DC CL10’ ’ INDENT 10
00014B 4040404040404040 139 OUTPUT1 DC CL10’ ’ OUTPUT FIELD1, 10 BYTES
000155 4040404040404040 140 DC CL10’ ’ INDENT 10
00015F 4040404040404040 141 OUTPUT2 DC CL10’ ’ OUTPUT FIELD2, 10 BYTES
000169 4040404040404040 142 DC CL(L’OUTPUT-(*-OUTPUT))’ ’ REST OF OUTPUT RECORD
143 *
0001C5 144 FNAME DC C’JANE’
0001C9 145 HYPH1 DC C’----’
0001CD 146 LNAME DC C’CODERS’
0001D3 147 HYPH2 DC C’------’
0001D9 4040404040404040 148 BLANKS10 DC CL10’ ’


EX
Execute
(cont.)
This example uses one MVC instruction (statement 129) to move variable length fields to the output fields for printing.
Note that the MVC instruction is coded with a length of 0 and that the length values placed in Register 2 (statements 96
and 101) for the Execute instruction (statements 97 and 102) are one less than the actual length of the source fields.
This adjustment must be made since field length values in machine code must be one less that actual field length
values.
FNAME LNAME
J A N E C O D E R S
OUTPUT1 OUTPUT2
J A N E C O D E R S
41362878.doc 12/7/2021 [ 500 - 60 ] ALC Reference for TPF Applications Programmers

Expressions
Expressions can be used to specify:
1 An address
2 An explicit length
3 A modifier
4 A duplication factor
5 A complete operand
5
For example:
EQU X-Y+13-P/Q
1 2
MVC TO+L’TO-L’FROM(L’FROM),FROM
DS (X-Y)XL(P/Q-10)
4 3
Expressions can be written with a simple term or as an arithmetic combination of terms.
Expressions are said to be either absolute or relocatable.
Absolute expressions are those whose values are independent of the actual starting address of the program. A self-
defining term is absolute. For example the value of the self-defining term is 3 regardless of where the program starts.
Absolute expressions typically represent quantities rather than addresses.
Relocatable expressions depend on the starting address of the program and typically represent an address value. For
example, in the statement...
PRTLINE DS CL133
the address of PRTLINE depends on the program’s starting address.

FINIS
FINIS Macro
FINIS
The FINIS macro creates the work storage required for other commonly used macros. It also generates the register
equates “R0” through “R15”. (See Register Usage). The FINIS is normally coded after the LTORG and before the
END statements at the end of your program beginning in column 10.

IC
Insert Character
Inserts a storage byte into a register’s low-order byte. The register’s high order byte and the source address data remain
unchanged.
label IC R1,D2(X2,B2)
Operand 1 Operand 2
Register or literal
B = Register # or
symbolic Reg name

OP CODE R1 X2 B2 D2
0-7 8-11 12-15 16-19 20-31
43
43R1X2B2DDD2
The condition code is not affected by the Insert Character instruction.
Examples:
R2 = X'0EF20010'
LABEL1 = DC X’C1C2C3C4’'
IC R2,LABEL1
Before:
R2 LABEL1
(hex bytes) 0 E F 2 0 0 1 0 C 1 C 2 C 3 C 4
After:
R2 LABEL1
(hex bytes) 0 E F 2 0 0 C 1 C 1 C 2 C 3 C 4

ICM
Insert Characters Under Mask
RS Type Op code = BF
Inserts the contents of the left most 1 to 4 bytes of a storage area into selected bytes of a register. The storage location
is unchanged. The bits of the mask correspond one-to-one with the bytes of the register.
label ICM R1,M,D3(B3)

Register 0-15 or literal
B = Register # or
symbolic Reg name

OP CODE R1 M B3 D3
0-7 8-11 12-15 16-19 20-31
BF
BFR1MB3DDD3
The condition code is set according to the results of the inserted bytes as follows:
Results of
Inserted Bytes Cond code
Only
ZERO
or 0
Mask = 0
Leftmost bit of inserted 1
bytes = 1
Not ZERO but 2
Leftmost bit of inserted
bytes = 0
Example 1: R2 = X’C1C2C3C4’
LABEL1 DC X’F1F2F3F4’
ICM R2,B'1010',LABEL1
R2 Byte # 0 1 2 3
MASK (bits) 1 0 1 0
SELECTED R2 BYTES
Byte # 0 1 2 3
R2 (HEX) F 1 C 2 F 2 C 4
LABEL1 (HEX) F 1 F 2 F 3 F 4
CONDITION CODE = 1
In this example, the condition code would be set to 1 since the leftmost bit of the inserted bytes (F1 & F2) is 1.
ICM can be used in place of a LH when the storage area is not halfword aligned. For example...
SR R2,R2
ICM R2,B’0011’,LABEL1

L
Load
Copies fullword (4 bytes) from storage to a register. The storage location is unchanged.
label L R1,D2(X2,B2)
Operand 1 Operand 2
Register or literal
B = Register # or
symbolic Reg name

OP CODE R1 X2 B2 D2
0-7 8-11 12-15 16-19 20-31
58
58R1X2B2DDD2
The condition code is not affected by the Load instruction.
Examples:
R2 = X'000F0B1E' R8 = 010816
Addr 012816 = LABEL1 = DC X'0000000C'
L R2,32(R0,R8) or R2,32(,R8)
or L R2,LABEL1
Before: Addr 12816

R2 LABEL1
(hex bytes) 0 0 0 F 0 B 1 E 0 0 0 0 0 0 0 C
After: Addr 12816

R2 LABEL1
(hex bytes) 0 0 0 0 0 0 0 C 0 0 0 0 0 0 0 C

LA
Load Address
Places the effective address of the Operand 2 into the register specified Operand 1..The load address instruction also
provides a good way to load a register with a constant.
label LA R1,D2(X2,B2)
Operand 1 Operand 2
Register or literal
B = Register # or
symbolic Reg name

OP CODE R1 X2 B2 D2
0-7 8-11 12-15 16-19 20-31
41
41R1X2B2DDD2
The condition code is not affected by the Load instruction.
Example 1:
R2 = X'00000010' R8 = 010816
Addr 012816 = LABEL1 = DC X'0000000C'
LA R2,32(R0,R8) or R2,32(,R8)
or LA R2,LABEL1
Before: Addr 12816

R2 LABEL1
(hex bytes) 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 C
After: Addr 12816

R2 LABEL1
(hex bytes) 0 0 0 0 0 1 2 8 0 0 0 0 0 0 0 C
Example 2: (Loads a Register 2 with a constant)

R2 = X'00000010'
LA R2,5
Before: R2 After: R2
(hex bytes) 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 5
Example 3: (Bumps the value in Register 2 by 1)

R2 = X'00000010'
LA R2,1(R2) (Note: The displacment value for operand 2 can be any value from 1 to 4096.)
Before: R2 After: R2
(hex bytes) 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1

LH(EXCEPTIONAL INSTRUCTION)
Load Halfword
Copies halfword (2 storage bytes) to the 2 low order bytes of a register. The high order bit of Operand 2 is propagated
in the 2 high order bytes of the register. The storage location is unchanged.
label LH R1,D2(X2,B2)
Operand 1 Operand 2
Register or literal
B = Register # or
symbolic Reg name

OP CODE R1 X2 B2 D2
0-7 8-11 12-15 16-19 20-31
48
48R1X2B2DDD2
The condition code is not affected by the Load Halfword instruction.
Example 1: R2 = X'000F0B1E'
LABEL1 = DC X'0ECD2A98'
LH R2,LABEL1+2
Before: R2 LABEL1
(hex bytes) 0 0 0 F 0 B 1 E 0 E C D 2 A 9 8
After: R2 LABEL1
(hex bytes) 0 0 0 0 2 A 9 8 0 E C D 2 A 9 8
0010 1010 .....
high order bit of Opr2 is propagated in high order halfword : PROPAGATION HAPPENES MEANS THE MS
NIBBLE OF 2 BYTES WE HAVE MOVED WILL BE CONVERTED TO BINARY FIRST AND THE MS BIT OF THAT BINARY
NUMBER IS PROPAGATED IN THE REMAINING BYTES OF THE REGISTER.
Example 2: R2 = X'000E34B8’
LABEL1 = DC X'0EA3B490’
LH R2,LABEL1+2
Before: R2 LABEL1
(hex bytes) 0 0 0 E 3 4 B 8 0 E A 3 B 4 9 0
After: R2 LABEL1
(hex bytes) F F F F B 4 9 0 0 E A 3 B 4 9 0
1011 0100 ....
high order bit of Opr2 is propagated in high order halfword

LM
Load Multiple
RS Type Op code = 98
Load several consecutively numbered registers from consecutive fullwords of storage. If the R 1 value is greater than
the R2 value, the load operation will wrap around after reaching the count of 15 to the count of 0 and continue.
label LM R1,R2,D3(B3)
Use Beginning Register Ending Register Source Address
Format Register No. Register No. Base/Index/Displac
or Symbolic Name of or Symbolic Name of or label
Register Register or literal
Spec R = Register # R = Register # D = Decimal value
or Symbolic Name or Symbolic Name X = Register # or
of Register of Register symbolic Reg name
B = Register # or
symbolic Reg name

OP CODE R1 R2 B3 D3
0-7 8-11 12-15 16-19 20-31
98
98R1R2B3DDD3
The condition code is not affected by the Load Multiple instruction.
Example 1:
LM R2,R4,DATA
.
.
.
DATA DC F’10’
DC F’-1’
DC F’194’
In this example, Registers 2,3, and 4 are loaded with the contents of the fullwords at the addresses DATA,
DATA + 4, and DATA + 8.
Example 2: (wraparound)
LM R14,R1,DATA
.
.
.
DATA DC F’10’
DC F’-1’
DC F’194’
DC F’14’
In this example, Registers 14, 15, 0, and 1 are loaded with the contents of the fullwords at the addresses
DATA, DATA + 4, DATA + 8, and DATA +12.

LR
Load Register
Replace the contents of the register specified in operand 1with the contents of the register specified in operand 2.
Operand 2’s contents remain unchanged.
label LR R1,R2
Operand 1 Operand 2

Length = Halfword
OP CODE R1 R2
0-7 8-11 12-15
18
18R1R2
The condition code is not affected by the Load Register instruction.
Example:
R2 = X'00000010' R3 = X'00000023'
LR R2,R3
Before:
R2 R3
(hex bytes) 0 0 0 0 0 0 1 0 0 0 0 0 0 0 2 3
After:
R2 R3
(hex bytes) 0 0 0 0 0 0 2 3 0 0 0 0 0 0 2 3

LTORG
Literal Origin Directive
The LTORG directive positions the literal pool, which was created since the beginning of the program or since the
last LTORG, at the next doubleword boundary after the occurrence of the LTORG in the program.
The LTORG is usually coded right before the FINIS and END statements in your source code, for example...
L R3,=F’5’
.
.
.
LTORG The literal constant that is defined by =F’5’ is assembled and printed here on the listing
FINIS
END
To avoid addressability problems, you should code a LTORG directive at the end of each control section (CSECT).

LTR
Load and Test Register
Load one register from a second register, test the result in the first register and set the condition code accordingly.
label LTR R1,R2

Operand 1 Operand 2

Length = Halfword
OP CODE R1 R2
0-7 8-11 12-15
12
12R1R2
Results Cond code Approp. Branch Ext.

if value in R1 is… Mnemonic
Zero 0 BZ, BNM, BNP
Less than Zero 1 BM, BNZ
Greater than Zero 2 BP, BNZ
Example1 :
R2 = X'00C1C2C3' R3 = X’F0000002’
LTR R2,R3
BM LABEL1
LA R2,LABEL2
Before:
R2 R3
(hex bytes) 0 0 C 1 C 2 C 3 F 0 0 0 0 0 0 2
After:
R2 R3
(hex bytes) F 0 0 0 0 0 0 2 F 0 0 0 0 0 0 2
Condition code=1
After execution, R2 contains a negative value which sets the condition code to 1. The branch on minus test in
the BM instruction will be successful and the branch to LABEL1 will be taken.
Example 2: (comparing a register with zero)

This form is the preferred way of comparing the contents of
R5 = X'00000000' a register with zero. The LTR is an RR type instruction and
is shorter and faster than the Compare (C) instruction. The
LTR R5,R5
branch to LABEL1 will be taken since R5 contains zero
BZ LABEL1
after execution of the LTR instruction.
LA R2,LABEL2

M
Multiply
RX Type Op code = 5C
Multiplies a 32 bit integer (multiplicand), contained in the odd numbered register of the pair beginning with the even
numbered register specified in Operand 1, by a 32 bit integer (multiplier) contained in the fullword of storage specified
in Operand 2. The product is a 64 bit integer which is placed in the register pair specified in Operand 1. Any value in
the even numbered register before the multiply operation is ignored and will be overwritten by the product after the
multiply. The storage area is unchanged.
label M R1,D2(X2,B2)
Operand 1 Operand 2
Register or literal
B = Register # or
symbolic Reg name

OP CODE R1 X2 B2 D2
0-7 8-11 12-15 16-19 20-31
5C
5CR1X2B2DDD2
The condition code is not affected by the Multiply Instruction.
Example : (5 * 2 = 10)
R2 = X'00C1C2C3' R3 = X’00000005’
LABEL1 = DC X'00000002'
M R2,LABEL1
Multiplicand Multiplier
(hex bytes) 0 0 C 1 C 2 C 3 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 2
Product
After: R2 R3 LABEL1
(hex bytes) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A 0 0 0 0 0 0 0 2

MH
Multiply Halfword
RX Type Op code = 4C
Multiplies a 32 bit integer (multiplicand), contained in the register specified in Operand 1, by a 16 bit integer
(multiplier) contained in the halfword of storage specified in Operand 2. The product is a 32 bit integer which is placed
in the register specified in Operand 1. The storage area remains unchanged.
label MH R1,D2(X2,B2)
Operand 1 Operand 2
or label
or literal
B = Register # or
symbolic Reg name

OP CODE R1 X2 B2 D2
0-7 8-11 12-15 16-19 20-31
4C
4CR1X2B2DDD2
The condition code is not affected by the Multiply Halfword instruction.
Example 1: (16* 2 =32)

R3 = X'00000010'
LABEL1 = DC H’2’
MH R3,LABEL1
Before: R3 LABEL1
(hex bytes) 0 0 0 0 0 0 1 0 0 0 0 2
After: R3 LABEL1
(hex bytes) 0 0 0 0 0 0 2 0 0 0 0 2
Example 2: (8* 10 = 80)

R3 = X'00000008’
MH R3,=H’10’
Before: R3
(hex bytes) 0 0 0 0 0 0 0 8 0 0 0 A
After: R3
(hex bytes) 0 0 0 0 0 0 5 0 0 0 0 A

MR
Multiply Registers
RR Type Op code = 1C
Multiplies a 32 bit integer (multiplicand), contained in the odd numbered register of the pair beginning with the even
numbered register specified in Operand 1, by a 32 bit integer (multiplier) contained in the register specified in Operand
2. The product is a 64 bit integer which is placed in the register pair specified in Operand 1. Any value in the even
numbered register before the multiply operation is ignored and will be overwritten by the product after the multiply.
The R2 register remains unchanged. The R2 register must not be part of the R 1 register pair.
label MR R1,R2
Operand 1 Operand 2

Length = Halfword
OP CODE R1 R2
0-7 8-11 12-15
1C
1CR1R2
The condition code is not affected by the Multiply Register Instruction.
Example : (5 * 2 = 10)
R2 = X'00C1C2C3' R3 = X’00000005’ R4 = X’00000002’
MR R2,R4
Before: R2 R3 R4
(hex bytes) 0 0 C 1 C 2 C 3 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 2
Product
After: R2 R3 R4
(hex bytes) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A 0 0 0 0 0 0 0 2

MVC
Move Characters
Moves (duplicates) characters (one at a time) from the source address to the destination address.
label MVC D1(L,B1),D2(B2)
Operand 1 Operand 2
Use Destination Address Source Address
or label or label
symbolic Reg name

0-7 8-15 16-19 20-31 32-35 36-48
D2
D2LLB1DDD1B2DDD2
Actual length value is 1 less than source statement length .
The condition code is not affected by the MVC instruction.

Example 1:
R8 = 000A16
Addr 012816 = DC C'CODED'
MVC 256(4,R8),286(R8)
In this example, the characters, CODE, located at base/displacement 128 would be duplicated at the first four
bytes beginning at base/displacement 10A. Since the stated length of the move operation is 4 bytes, only the
first 4 bytes of the first operand are moved. The source field remains unchanged.
Example 2:
LABEL1 = DC C'1234’
LABEL2 = DC C’DEAR’
MVC LABEL1,LABEL2 (MVC LABEL1,=C’DEAR’ would produce the same results)
In this example, the characters, DEAR, located at the address equated to LABEL2 would be duplicated at the
first four bytes beginning at the address equated to LABEL1. Since there is no stated length, the length of the
move operation defaults to the length of the constant located at LABEL1, in this case 4 bytes. The source
field remains unchanged.
Example 3:
LABEL1 = DC C'1234567'
LABEL2 = DC C'HOUSEBOAT'
MVC LABEL1(5),LABEL2
or
MVC LABEL1(L'LABEL2-4),LABEL2
In this example, the characters HOUSE located at LABEL2 would be duplicated at the first five bytes
beginning at LABEL1. The length of the move operation is overridden by a length attribute which follows
Operand 1, in this case 5 bytes which is the length of LABEL2 minus 4. The source field remains unchanged.
Example 4: (Propogation Move) These two lines of code will clear the storage area named LABEL1 to spaces
(X’40’).
MVI LABEL1,X’40’
MVC LABEL1+1(L’LABEL1-1),LABEL1

MVI
Move Immediate
Moves (duplicates) the specified byte of data to the destination address.
label MVI D1(B1),I2
Operand 1 Operand 2
Use Destination Address Source Data (Immediate)
or label
decimal value.
OP CODE I2 B1 D1
0-7 8-15 16-19 20-31
92
92II2B1DDD
The condition code is not affected by the MVI instruction.
Example 1:
R8 = 0000000A16
MVI 256(R8),C’?’
In this example, the character (one byte) “?” would be duplicated at the storage byte whose address is
base/displacement 10A16.
Example 2:
MVI LABEL1,X’0F’
In this example, hex 0F would be duplicated at the storage byte address equated to LABEL1.
Example 3:
MVI PRINT,C’ ‘
or
MVI PRINT,X’40’
In this example, a space character would be duplicated at the storage byte address equated to PRINT.

N
AND
Turn one or more bits OFF in a register that are off in another fullword storage area according to the truth table shown
below.
label N R1,D2(X2,B2)
Operand 1 Operand 2
Use Destination Mask
Register or literal
B = Register # or
symbolic Reg name

OP CODE R1 X2 B2 D2
0-7 8-11 12-15 16-19 20-31
54
54R1X2B2DDD2
Results Cond code Branch On Condition Approp. Branch Ext.

Mask Value Mnemonic
Zero 0 8 BZ
Non-Zero 1 4 BNZ

Destination Bit Mask Bit Resulting Destin. Bit
0 0 0
0 1 0
1 0 0
1 1 1
Example:
N R2,LABEL1
Before:
R2
Hexadecimal C 4
Binary Bits 1 1 0 0 0 1 0 0
LABEL1 (Mask)
Hexadecimal F B
Binary Bits 1 1 1 1 1 0 1 1
After:
R2
Hexadecimal C 0
Binary Bits 1 1 0 0 0 0 0 0
CONDTION CODE = 1 (Non-Zero Result)

NC
AND Characters
Turn one or more bits OFF in a storage area that are off in another storage area according to the truth table shown
below. The process proceeds left to right, one byte at a time.
label NC D1(L,B1),D2(B2)
Operand 1 Operand 2
(Mask)
Format Base/ILength/Displ Base/Displacement
or label or label
symbolic Reg name

0-7 8-15 16-19 20-31 32-35 36-48
D4
D4LLB1DDD1B2DDD2

Mask Value Mnemonic
Zero 0 8 BZ
Non-Zero 1 4 BNZ

0 0 0
0 1 0
1 0 0
1 1 1
Example:
NC LABEL1(1),LABEL2
Before:
LABEL1
Hexadecimal C 4
Binary Bits 1 1 0 0 0 1 0 0
Immediate Data (Mask)

Hexadecimal F B
Binary Bits 1 1 1 1 1 0 1 1
After:
LABEL1
Hexadecimal C 0
Binary Bits 1 1 0 0 0 0 0 0

NI
AND Immediate
Turn one or more bits OFF in a storage area that are off in the specified immediate data according to the truth table
shown below.
label NI D1(B1),I2
Operand 1 Operand 2
Use Destination Mask Value
Format Base/Displacement Immediate
or Label
decimal value.
OP CODE I2 B1 D1
0-7 8-15 16-19 20-31
94
94II2B1DDD1
Results Cond code Branch On Appropriate

Condition Branch Ext.
Mask Value Mnemonic
Zero 0 8 BZ
Non-Zero 1 4 BNZ

0 0 0
0 1 0
1 0 0
1 1 1
Example:
NI LABEL1,X'7F'
Before:
LABEL1
Hexadecimal C 4
Binary Bits 1 1 0 0 0 1 0 0

Hexadecimal 7 F
Binary Bits 0 1 1 1 1 1 1 1
After:
LABEL1
Hexadecimal 4 4
Binary Bits 0 1 0 0 0 1 0 0

NR
And Registers
Turn one or more bits OFF in a register that are off in another register according to the truth table shown below.
label NR R1,R2
Operand 1 Operand 2

Length = Halfword
OP CODE R1 R2
0-7 8-11 12-15
14
14R1R2

Mask Value Mnemonic
Zero 0 8 BZ
Non-Zero 1 4 BNZ

0 0 0
0 1 0
1 0 0
1 1 1
Example:
NR R2,R3
Before:
R2
Hexadecimal C 4
Binary Bits 1 1 0 0 0 1 0 0
R3 (Mask)
Hexadecimal B F
Binary Bits 1 0 1 1 1 1 1 1
After:
R2
Hexadecimal 8 4
Binary Bits 1 0 0 0 0 1 0 0

O
OR
Turn one or more bits ON in a register that are on in another fullword storage area according to the truth table shown
below.
label O R1,D2(X2,B2)
Operand 1 Operand 2
Register or literal
B = Register # or
symbolic Reg name

OP CODE R1 X2 B2 D2
0-7 8-11 12-15 16-19 20-31
56
56R1X2B2DDD2

Mask Value Mnemonic
Zero 0 8 BZ
Non-Zero 1 4 BNZ

0 0 0
0 1 1
1 0 1
1 1 1
Example:
O R2,LABEL1
Before:
R2
Hexadecimal C 4
Binary Bits 1 1 0 0 0 1 0 0
LABEL1 (Mask)
Hexadecimal 2 0
Binary Bits 0 0 1 0 0 0 0 0
After:
R2
Hexadecimal E 4
Binary Bits 1 1 1 0 0 1 0 0

OC
OR Characters
Turn one or more bits ON in a storage area that are on in another storage area according to the truth table shown below.
The process proceeds left to right, one byte at a time.
label OC D1(L,B1),D2(B2)
Operand 1 Operand 2
(Mask)
or label or label
symbolic Reg name

0-7 8-15 16-19 20-31 32-35 36-48
D6
D6LLB1DDD1B2DDD2

Mask Value Mnemonic
Zero 0 8 BZ
Non-Zero 1 4 BNZ

0 0 0
0 1 1
1 0 1
1 1 1
Example:
OC LABEL1(1),LABEL2
Before:
LABEL1
Hexadecimal C 4
Binary Bits 1 1 0 0 0 1 0 0
LABEL2 (Mask)
Hexadecimal 0 1
Binary Bits 0 0 0 0 0 0 0 1
After:
LABEL1
Hexadecimal C 5
Binary Bits 1 1 0 0 0 1 0 1

OI
OR Immediate
Turn one or more bits ON in a storage area that are on in the specified immediate data according to the truth table
shown below.
label OI D1(B1),I2
Operand 1 Operand 2
or Label
decimal value.
OP CODE I2 B1 D1
0-7 8-15 16-19 20-31
96
96II2B1DDD1

Mask Value Mnemonic
Zero 0 8 BZ
Non-Zero 1 4 BNZ

0 0 0
0 1 1
1 0 1
1 1 1
Example:
OI LABEL1,X'08'
Before:
LABEL1
Hexadecimal C 4
Binary Bits 1 1 0 0 0 1 0 0
Immediate Data
Hexadecimal 0 8
Binary Bits 0 0 0 0 1 0 0 0
After:
LABEL1
Hexadecimal C C
Binary Bits 1 1 0 0 1 1 0 0

OR
OR Registers
Turn one or more bits ON in a register that are on in another register according to the truth table shown below.
label OR R1,R2
Operand 1 Operand 2

Length = Halfword
OP CODE R1 R2
0-7 8-11 12-15
16
16R1R2

Mask Value Mnemonic
Zero 0 8 BZ
Non-Zero 1 4 BNZ

0 0 0
0 1 1
1 0 1
1 1 1
Example:
OR R2,R3
Before:
R2
Hexadecimal C 4
Binary Bits 1 1 0 0 0 1 0 0
R3 (Mask)
Hexadecimal 0 2
Binary Bits 0 0 0 0 0 0 1 0
After:
R2
Hexadecimal C 6
Binary Bits 1 1 0 0 0 1 1 0

ORG
Origin Directive
The Origin directive instructs the assembler to change the value of the location counter to the address of LABEL 1. If
the operand is left blank, the location counter is reset to the highest value obtained so far in the current control section..
LABEL1 must be defined before the ORG that specifies it and within the current control section of the code.
Typically, you use ORG to redefine areas of storage either in a DSECT or within the Constants Section (DCs) of the
program.
label ORG Label1 or left blank
Example:
Hex Line
Loc No.
Cntr
***********************************************************************
* FLIGHT RECORD DSECT *
***********************************************************************
0000 000 FLTREC DSECT
0000 001 FFHDR DS CL18 RESERVE HEADER INFO STORAGE AREA
0012 002 ORG FFHDR RESET LOC COUNTER TO HEADER AREA
0000 003 FFNUM DS CL5 FLIGHT NUMBER
0005 004 FFAIRE DS CL3 AIRCRAFT EQUIPMENT
0008 005 FAVLS DS H AVAILABLE SEATS
000A 006 FROUT DS CL6 CITY ROUTING (FROM/TO)
0010 007 FNPIT DS H NUMBER OF PSGR ITEMS
008 *----------------------------------------------------------------------
009 * PASSENGER INFORMATION FOR EACH PASSENGER ITEM *
010 *----------------------------------------------------------------------
0012 011 FPITM DS XL140 10 PSGR ITEMS,(14 BYTES PER ITEM)
009E 012 ORG FPITM
013 *
0012 014 FPMEALS DS XL1 REQUESTED MEALS
015 * X’80’ = SALT FREE
016 * X’40’ = VEGITARIAN
017 * X’20’ = CHILD’S MEAL
018 * X’10’ = KOSHER
0013 019 FPCLASS DS XL1 CLASS OF SERVICE
020 * X’80’ = F
021 * X’40’ = Y
022 * X’20’ = M
023 * X’10’ = (NOT USED)
0014 024 FPNUM DS H NUMBER IN PARTY
0016 025 FPNAM DS CL9 PASSENGER NAME
001F 026 FPSPA DS XL1 UNUSED BYTE (FUTURE)
027 *
028 FPLEN EQU *- FMEALS LENGTH OF ONE ITEM
029 *
030 *----------------------------------------------------------------------
In this example, an 18 byte storage area is reserved for the DSECT header area beginning at location 0000
(FFHDR). Then an ORG is done back to FFHDR which resets the location counter back to 0000. The 18 byte
area is defined or “patterned” in lines 3 through 7. Next, ten 14 byte storage areas (140 bytes) are reserved for
passenger information beginning at location 0012 (FPITM). Then an ORG is done back to FPITM which
resets the location counter back to 0012. The 14 byte pattern that will be used for each of the 10 passenger
information areas is defined in lines 14 through 26.

PACK
Pack
SS Type Op code = F2
Convert the EBCDIC or Zoned number located at the storage area specified by Operand 2 to pack decimal format and
places it in the storage area specified by Operand 1.
label PACK D1(L,B1),D2(L2,B2)
Operand 1** Operand 2***

or label or label
L* = Decimal value L* = Decimal value
B = Register # or B = Register # or
operation defaults to the length of the operand. Maximum length of the operation is 16 bytes.
The minimum length of the receiving field in bytes is calculated by...

PACKED LENGTH = (ZONED LENGTH ÷ 2) + 1
(Disregard any remainder resulting from division portion of formula)
** The data stored at the address specified by Operand 2 must be in zoned or EBCDIC for mat.

OP CODE L1 L2 B1 D1 B2 D2
0-7 8-11 12-15 16-19 20-31 32-35 36-48
F2
F2L1L2B1DDD1B2DDD2
Length values are 1 less than source statement lengths .
The condition code is not affected by the PACK instruction.
Example 1:
DWD DC D’0’ or DC PL8’0’
NOPTYHLD DC C'12345' or DC Z’12345’
PACK DWD,NOPTYHLD(4)
Explicit length of 4
NOPTYHLD = F1 F2 F3 F4 F5
DWD (after PACK) = 00 00 00 00 00 01 23 4F

Zero fill unused portion
Sign = C or F for Positive numbers, D for negative numbers
This example packs the first four EBCDIC characters stored at NOPTYHLD into the double word DWD.

PACK
Pack
(cont.)
Performing Binary Arithmetic on EBCDIC or Zoned Numbers
INPUT
DATA
EBCDIC
PACK OI
UNPK w/ X'F0'
PACKED
PACKED PACKED Zoned
DECIMAL EBCDIC OUTPUT
DECIMAL ARITHMETIC DECIMAL Decimal
CVB CVD
BINARY BINARY BINARY

INTEGER ARITHMETIC INTEGER
A, S, M, D
AH, SH, MH

PRINT
Print Directive
PRINT GEN or NOGEN
The PRINT directive instructs the assembler to either print or suppress the printing of macro expansions in the program
listing. Thus the PRINT directive (beginning at column 10) normally appears in the source code right before a macro
call.

Register Usage
TPF Old PARS

Equated Equated Register
Label Label No. Use
R0*† RAC 0 Application Program Register
R1* RG1 1 Application Program Register
R2* RGA 2 Application Program Register
R3* RGB 3 Application Program Register
R4* RGC 4 Application Program Register
R5* RGD 5 Application Program Register
R6* RGE 6 Application Program Register
R7* RGF 7 Application Program Register
R8 RAP 8 Active Program Base Register

R9 REB 9 Active ECB Base Register
R10 RLA 10 Application Program Register - Not saved through TPF macros
R11 RLB 11 TPF System Base Register

R12 RLC 12 TPF System Base Register
R13 RLD 13 Application Program Register - Not saved through TPF macros
R14 RDA 14 Application Program Register - Not saved through TPF macros
R15 RDB 15 Application Program Register - Not saved through TPF macros
The equated name shown for each register are defined by the FINIS macro that is normally coded between the
LTORG and END assembler directives.
† R0 should not be used as a base register. Referencing R0 as an address pointer is

equivalent to the value of zero.
* These registers are saved across TPF macros

S
Subtract
RX Type Op code = 5B
Subtracts contents of a fullword storage area from the contents of a register. The result in placed in the register. The
storage location is unchanged.
label S R1,D2(X2,B2)
Operand 1 Operand 2
Register or literal
B = Register # or
symbolic Reg name

OP CODE R1 X2 B2 D2
0-7 8-11 12-15 16-19 20-31
5B
5BR1X2B2DDD2
Results Cond code

ZERO 0
MINUS 1
PLUS 2
OVERFLOW 3
Examples:
R2 = X'00000010' R8 = 010816
Addr 012816 = LABEL1 = DC X'0000000C'
S R2,32(R0,R8)
or S R2,LABEL1
Before: Addr 12816

R2 LABEL1
(hex bytes) 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 C
After: Addr 12816

R2 LABEL1
(hex bytes) 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 C

SH
Subtract Halfword
RX Type Op code = 4B
Subtract the contents of a 2-byte halfword storage area from the contents of a register. The results are placed in the
register. The storage location is unchanged.
label SH R1,D2(X2,B2)
Operand 1 Operand 2
or label
or literal
B = Register # or
symbolic Reg name

OP CODE R1 X2 B2 D2
0-7 8-11 12-15 16-19 20-31
4B
4BR1X2B2DDD2
Results Cond code

ZERO 0
MINUS 1
PLUS 2
OVERFLOW 3
Example:
R2 = X'00000010' R8 = X’00000108’
Addr 012816 = LABEL1 = DC H'12'
SH R2,32(R0,R8) or R2,32(R8) or R2,32(,R8)

or SH R2,LABEL1
o r SH R2,=H'12'
Before: Addr 12816

R2 LABEL1
(hex bytes) 0 0 0 0 0 0 1 0 0 0 0 C
After: Addr 012816

R2 LABEL1
(hex bytes) 0 0 0 0 0 0 0 4 0 0 0 C

SLA
Shift Left Algebraic
Shifts the contents of the register specified in Operand 1 to the left by the number of bits specified in Operand
2. The most significant bit (sign) remains unchanged to preserve the sign of the number and only the least
significant 31 bits are shifted. Although the effective address specified in Operand 2 is calculated, the
resulting value is not used as an address but as a count for the number of bit shifts to perform. The value used
for this count is actually the least significant 6 bits of the calculated effective address, and should never be
higher then 3110 for a single register shift.
label SLA R1,D2(B2)
Operand 1 Operand 2
Use Destination No. of Bit Shifts
Register or literal
or Symbolic Name or symbolic Reg
of Register name
B = Register # or
symbolic Reg name

OP CODE R1 0 B2 D2
0-7 8-11 12-15 16-19 20-31
89
89R10B2DDD2
Bits 12-15 not used
Results Cond code

ZERO 0
NEGATIVE 1
POSITIVE 2
OVERFLOW* 3
*An overflow condition will occur if a bit that differs from the sign bit is shifted out of the register.
Effect of Shift Left Algebraic (SLA)...

REGISTER
Sign Bit
s 0s
Bits shifted
out are lost
Examples:
SLA R2,3
Before R2
(hex bytes) 8 0 0 0 2 1 4 A
(Binary) 1000 0000 0000 0000 0010 0001 0100 1010
SIGN
Before R2
(hex bytes) 0 0 0 1 0 A 5 0
(Binary) 1000 0000 0000 0001 0000 1010 0101 0000
Condition code = 3 (Overflow)

SLDA
Shift Left Double Algebraic
RS Type Op code = 8F
Shifts the contents of the even/odd register pair specified in Operand 1 to the left by the number of bits
specified in Operand 2. The register pair are treated is if they made up one 64-bit register. The most
significant bit (sign) of the even register remains unchanged and the remaining 63bits are shifted. Although
the effective address specified in Operand 2 is calculated, the resulting value is not used as an address but as a
count for the number of bit shifts to perform. The value used for this count is actually the least significant 6
bits of the calculated effective address, and should never be higher then 63 10 for a double register shift.
label SLDA R1,D2(B2)
Operand 1 Operand 2
Register or literal
of Register name
B = Register # or
symbolic Reg name

OP CODE R1 0 B2 D2
0-7 8-11 12-15 16-19 20-31
8F
8FR10B2DDD2
Bits 12-15 not used
Results Cond code

ZERO 0
NEGATIVE 1
POSITIVE 2
OVERFLOW* 3
*An overflow condition will occur if a bit that differs from the sign bit is shifted out of the even register.
Effect of Shift Left Double Algebraic (SLDA)...

EVEN REGISTER ODD REGISTER
S 0s
Bits shifted
out are lost
Examples:
SLDA R2,3
Before R2 R3
(hex bytes) 9 2 0 0 0 4 7 F 8 0 0 0 2 1 4 A
(Binary) 1001 0010 0000 0000 0000 0100 0111 1111 1000 0000 0000 0000 0010 0001 0100 1010
SIGN
After R2 R3
(hex bytes) 9 0 0 0 2 3 F C 0 0 0 1 0 A 5 0
(Binary) 1001 0000 0000 0000 0010 0011 1111 1100 0000 0000 0000 0001 0000 1010 0101 0000
Condition code = 3 (Overflow)

SLDL
Shift Left Double Logical
RS Type Op code = 8D
Shifts the contents of the even/odd register pair specified in Operand 1 to the left by the number of bits
specified in Operand 2. The register pair are treated is if they made up one 64-bit register and all 64 bits are
shifted. Although the effective address specified in Operand 2 is calculated, the resulting value is not used as
an address but as a count for the number of bit shifts to perform. The value used for this count is actually the
least significant 6 bits of the calculated effective address, and should never be higher then 63 10 for a double
register shift.
label SLDL R1,D2(B2)
Operand 1 Operand 2
Register or literal
of Register name
B = Register # or
symbolic Reg name

OP CODE R1 0 B2 D2
0-7 8-11 12-15 16-19 20-31
8D
8DR10B2DDD2
Bits 12-15 not used
The condition code is not affected by the SLDL instruction.
Effect of Shift Left Double Logical (SLDL)...

Bits shifted 0s
out are lost
Examples:
R2 = X'9200047F’ R3 = X’8000214A’
SLDL R2,3
Before R2 R3
(hex bytes) 9 2 0 0 0 4 7 F 8 0 0 0 2 1 4 A
(Binary) 1001 0010 0000 0000 0000 0100 0111 1111 1000 0000 0000 0000 0010 0001 0100 1010
After R2 R3
(hex bytes) 9 0 0 0 2 3 F C 0 0 0 1 0 A 5 0
(Binary) 1001 0000 0000 0000 0010 0011 1111 1100 0000 0000 0000 0001 0000 1010 0101 0000

SLL
Shift Left Logical
Shifts the contents of the register specified in Operand 1 to the left by the number of bits specified in Operand
2. All 32 bits are shifted. Although the effective address specified in Operand 2 is calculated, the resulting
value is not used as an address but as a count for the number of bit shifts to perform. The value used for this
count is actually the least significant 6 bits of the calculated effective address, and should never be higher then
3110 for a single register shift.
label SLL R1,D2(B2)
Operand 1 Operand 2
Register or literal
of Register name
B = Register # or
symbolic Reg name

OP CODE R1 0 B2 D2
0-7 8-11 12-15 16-19 20-31
89
89R10B2DDD2
Bits 12-15 not used
The condition code is not affected by the SLL instruction.
Effect of Shift Left Logical (SLL)...
REGISTER
Bits shifted 0s
out are lost
Examples:
R2 = X'8000214A'
SLL R2,3
Before R2
(hex bytes) 8 0 0 0 2 1 4 A
(Binary) 1000 0000 0000 0000 0010 0001 0100 1010
Before R2
(hex bytes) 0 0 0 1 0 A 5 0
(Binary) 0000 0000 0000 0001 0000 1010 0101 0000

SPACE
Insert Blank Lines Directive
SPACE [n]
(n is defaulted to 1 if omitted)
The SPACE directive instructs the assembler to insert n blank lines into the program listing. The SPACE directive
must be coded beginning in column 10.

SR
Subtract Registers
RR Type Op code = 1B
Subtract the contents of a the register specified in Operand 2 from the contents of the register specified in Operand 1.
The result in placed in the register specified in operand 1. The register specified in operand 2 is unchanged.
label SR R1,R2
Operand 1 Operand 2

Length = Halfword
OP CODE R1 R2
0-7 8-11 12-15
1B
1BR1R2
Results Cond code

ZERO 0
MINUS 1
PLUS 2
OVERFLOW 3
Example 1:
R2 = X'00000033' R8 = X'00000023'
SR R2,R8
Before:
R2 R8
(hex bytes) 0 0 0 0 0 0 3 3 0 0 0 0 0 0 2 3
After:
R2 R8
(hex bytes) 0 0 0 0 0 0 1 0 0 0 0 0 0 0 2 3
Example 1: (Clearing a Register)
This line of code will clear Register 2
SR R2,R2

SRA
Shift Right Algebraic
RS Type Op code = 8A
Shifts the contents of the register specified in Operand 1 to the right by the number of bits specified in
Operand 2. Only the least significant 31 bits are shifted and copies of the most significant bit (sign) fills in
the vacancies that are introduced on the left. Although the effective address specified in Operand 2 is
calculated, the resulting value is not used as an address but as a count for the number of bit shifts to perform.
The value used for this count is actually the least significant 6 bits of the calculated effective address, and
should never be higher then 3110 for a single register shift.
label SRA R1,D2(B2)
Operand 1 Operand 2
Register or literal
of Register name
B = Register # or
symbolic Reg name

OP CODE R1 0 B2 D2
0-7 8-11 12-15 16-19 20-31
89
8AR10B2DDD2
Bits 12-15 not used

Results Cond code
ZERO 0
NEGATIVE 1
POSITIVE 2
OVERFLOW* N/A
*An overflow condition is impossible with the SRA instruction.
Effect of Shift Right Algebraic (SRA)...

REGISTER
Sign Bit
s
Sign fills in vacancies
Bits shifted
out are lost
Examples:
SRA R2,3
Before R2
(hex bytes) 8 0 0 0 2 1 4 A
(Binary) 1000 0000 0000 0000 0010 0001 0100 1010
SIGN
Before R2
(hex bytes) F 0 0 0 0 4 2 9
(Binary) 1111 0000 0000 0000 0000 0100 0010 1001
Condition code = 1 (Negative)

SRL
Shift Right Logical
Shifts the contents of the register specified in Operand 1 to the right by the number of bits specified in
Operand 2. All 32 bits are shifted. Although the effective address specified in Operand 2 is calculated, the
resulting value is not used as an address but as a count for the number of bit shifts to perform. The value used
for this count is actually the least significant 6 bits of the calculated effective address, and should never be
higher then 3110 for a single register shift.
label SRL R1,D2(B2)
Operand 1 Operand 2
Register or literal
of Register name
B = Register # or
symbolic Reg name

OP CODE R1 0 B2 D2
0-7 8-11 12-15 16-19 20-31
88
88R10B2DDD2
Bits 12-15 not used
The condition code is not affected by the SRL instruction.
Effect of Shift Right Logical (SRL)...
REGISTER
Bits shifted
0s out are lost
Examples:
R2 = X'8000214A'
SRL R2,3
Before R2
(hex bytes) 8 0 0 0 2 1 4 A
(Binary) 1000 0000 0000 0000 0010 0001 0100 1010
Before R2
(hex bytes) 1 0 0 0 0 4 2 9
(Binary) 0001 0000 0000 0000 0000 0100 0010 1001

SRDA
Shift Right Double Algebraic
RS Type Op code = 8E
Shifts the contents of the even/odd register pair specified in Operand 1 to the right by the number of bits
specified in Operand 2. The register pair are treated is if they made up one 64-bit register. . The most
significant bit (sign) of the even register remains unchanged and the remaining 63bits are shifted. Although
the effective address specified in Operand 2 is calculated, the resulting value is not used as an address but as a
count for the number of bit shifts to perform. The value used for this count is actually the least significant 6
bits of the calculated effective address, and should never be higher then 63 10 for a double register shift.
label SRDA R1,D2(B2)
Operand 1 Operand 2
Register or literal
of Register name
B = Register # or
symbolic Reg name

OP CODE R1 0 B2 D2
0-7 8-11 12-15 16-19 20-31
8E
8ER10B2DDD2
Bits 12-15 not used
Results Cond code

ZERO 0
NEGATIVE 1
POSITIVE 2
OVERFLOW* N/A
*An overflow condition is impossible with the SRDA instruction.
Effect of Shift Right Double Algebraic (SRDA)...

Bits shifted
S out are lost
Sign fills in vacancies
Examples:
SRDA R2,3
Before R2 R3
(hex bytes) 9 0 0 0 2 3 F C 0 0 0 1 0 A 5 0
(Binary) 1001 0000 0000 0000 0010 0011 1111 1100 0000 0000 0000 0001 0000 1010 0101 0000
After R2 R3
(hex bytes) F 2 0 0 0 4 7 F 8 0 0 0 2 1 4 A
(Binary) 1111 0010 0000 0000 0000 0100 0111 1111 1000 0000 0000 0000 0010 0001 0100 1010
Condition code = 1 (Negative)
SRDL
Shift Right Double Logical
RS Type Op code = 8C
Shifts the contents of the even/odd register pair specified in Operand 1 to the right by the number of bits
specified in Operand 2. The register pair are treated is if they made up one 64-bit register and all 64 bits are
shifted. Although the effective address specified in Operand 2 is calculated, the resulting value is not used as
an address but as a count for the number of bit shifts to perform. The value used for this count is actually the
least significant 6 bits of the calculated effective address, and should never be higher then 63 10 for a double
register shift.
label SRDL R1,D2(B2)
Operand 1 Operand 2
Register or literal
of Register name
B = Register # or
symbolic Reg name

OP CODE R1 0 B2 D2
0-7 8-11 12-15 16-19 20-31
8C
8CR10B2DDD2
Bits 12-15 not used
The condition code is not affected by the SRDL instruction.
Effect of Shift Right Double Logical (SRDL)...

0s Bits shifted
out are lost
Examples:
R2 = X'900023FC’ R3 = X’00010A50'
SRDL R2,3
Before R2 R3
(hex bytes) 9 0 0 0 2 3 F C 0 0 0 1 0 A 5 0
(Binary) 1001 0000 0000 0000 0010 0011 1111 1100 0000 0000 0000 0001 0000 1010 0101 0000
After R2 R3
(hex bytes) 1 2 0 0 0 4 7 F 8 0 0 0 2 1 4 A
(Binary) 0001 0010 0000 0000 0000 0100 0111 1111 1000 0000 0000 0000 0010 0001 0100 1010
ST
Store
Copies fullword (4 bytes) from a register to storage. The contents of the register are unchanged.
label ST R1,D2(X2,B2)
Operand 1 Operand 2
Use Source Destination
Register or literal
B = Register # or
symbolic Reg name

OP CODE R1 X2 B2 D2
0-7 8-11 12-15 16-19 20-31
50
50R1X2B2DDD2
The condition code is not affected by the Store instruction.
Example:
R2 = X'000F0B1E
LABEL1 = DC X'0000000C'
ST R2,LABEL1
Before:
R2 LABEL1
(hex bytes) 0 0 0 F 0 B 1 E 0 0 0 0 0 0 0 C
After:
R2 LABEL1
(hex bytes) 0 0 0 F 0 B 1 E 0 0 0 F 0 B 1 E
STC
Store Character
Copy’s a register’s low-order byte to a storage byte. The register’s high order byte remains unchanged.
label STC R1,D2(X2,B2)
Operand 1 Operand 2
Register or literal
B = Register # or
symbolic Reg name

OP CODE R1 X2 B2 D2
0-7 8-11 12-15 16-19 20-31
42
42R1X2B2DDD2
The condition code is not affected by the Store Character instruction.
Examples:
R2 = X'0EF20010'
LABEL1 = DC X’C1C2C3C4’'
STC R2,LABEL1
Before:
R2 LABEL1
(hex bytes) 0 E F 2 0 0 1 0 C 1 C 2 C 3 C 4
After:
R2 LABEL1
(hex bytes) 0 E F 2 0 0 1 0 1 0 C 2 C 3 C 4
STCM
Store Characters Under Mask
RS Type Op code = BE
Stores the contents of selected bytes of a register into the left most 1 to 4 bytes of a storage area. The bits of the mask
correspond one-to-one with the bytes of the register.
label STCM R1,M,D3(B3)

Register 0-15(RANGE) or literal
B = Register # or
symbolic Reg name

OP CODE R1 M B3 D3
0-7 8-11 12-15 16-19 20-31
BF
BFR1MB3DDD3
The condition code is not affected by the STCM instruction.
Example 1: R2 = X’C1C2C3C4’
LABEL1 DC X’F1F2F3F4’
STCM R2,B'1010',LABEL1
LABEL1 Byte # 0 1 2 3
VALUE(HEX) F1 F2 F3 F4
R2 Byte # 0 1 2 3
MASK (bits) 1 0 1 0
SELECTED R2 BYTES
Byte # 0 1 2 3
R2 (HEX) C 1 C 2 C 3 C 4
LABEL1 (HEX) C 1 C 3 F 3 F 4
STH
Store Halfword
Copies a register’s 2 low order bytes to a halfword storage area. The contents of the register remain unchanged.
label STH R1,D2(X2,B2)
Operand 1 Operand 2
Register or literal
B = Register # or
symbolic Reg name

OP CODE R1 X2 B2 D2
0-7 8-11 12-15 16-19 20-31
40
40R1X2B2DDD2
The condition code is not affected by the Store Halfword instruction.
Example: R2 = X'000F0B1E'
LABEL1 = DC X'0ECD2A98'
STH R2,LABEL1
Before: R2 LABEL1
(hex bytes) 0 0 0 F 0 B 1 E 0 E C D 2 A 9 8
After: R2 LABEL1
(hex bytes) 0 0 0 F 0 B 1 E 0 B 1 E 2 A 9 8
STM
Store Multiple
Copies the contents of consecutively numbered registers to consecutive fullwords of storage. If the R 1 value is greater
than the R2 value, the store operation will wrap around after reaching the count of 15 to the count of 0 and continue.
label STM R1,R2,D3(B3)

Use Beginning Register Ending Register Destination Address
Format Register No. Register No. Base/Index/Displac
or Symbolic Name of or Symbolic Name of or label
Register Register or literal
Spec R = Register # R = Register # D = Decimal value
or Symbolic Name or Symbolic Name X = Register # or
of Register of Register symbolic Reg name
B = Register # or
symbolic Reg name

OP CODE R1 R2 B3 D3
0-7 8-11 12-15 16-19 20-31
90
90R1R2B3DDD3
The condition code is not affected by the Store Multiple instruction.
Example 1:
STM R2,R4,DATA
.
.
.
DC F’10’
DC F’-1’
DC F’194’
In this example the contents of Registers 2, 3, and 4 are stored off the fullword addresses of DATA, DATA +
4, and DATA + 8.
Example 2: (wraparound)
STM R14,R1,DATA
.
.
.
DC F’10’
DC F’-1’
DC F’194’
DC F’14’
In this example, the contents of Registers 14, 15, 0, and 1 are stored at the fullword addresses of DATA,
DATA + 4, DATA + 8 and DATA +12.
TM
Test Under Mask
Test one or more selected bits in a byte of storage for a ONE condition.
label TM D1(B1),I2
Operand 1 Operand 2
Use Storage Area Mask
(Immediate)
or Label
decimal value.

OP CODE I2 B1 D1
0-7 8-15 16-19 20-31
91
91II2B1DDD1
Results Cond code Branch On Single Bit Multi-Bit Approp. Branch Ext.
of Condition Test Test Mnemonic
Tested Bits Mask Value (e.g., 2 bits)
Ones [ All 1s ] 3 1 1 11 BO (Branch Ones)
Mixed [ (1s) and (0s) ] 1 4 N/A 01 or 10 BM (Branch Mixed)
Zeros [ All 0s ] 0 8 0 00 BZ (Branch Zeros)
Not Ones [ Not all 1s ] 1 or 0 14 (X,E,) 0 00 or 01 or 10 BNO (Branch Not Ones)
Not Mixed [ (All 0s) or (All 1s) ] 0 or 3 11 (‘X’B’) 0 or 1 00 or 11 BNM (Branch Not Mixed)
Not Zeros [ (All 1s) or (All 1s and 0s) ] 1 or 3 7 1 10 or 01 or 11 BNZ (Branch Not Zeros)
Example:
TM LABEL1,X’05’
Test:
LABEL1
Hexadecimal C 5
Binary Bits 1 1 0 0 0 1 0 1
Test these bits for ONEs

Hexadecimal 0 5
Binary Bits 0 0 0 0 0 1 0 1
Results:
Tested Bits Were ONE ONE
CONDTION CODE = 3 (Ones)
TR
Translate
SS Type Op code = DC
Replaces 8-bit quantities with other 8-bit quantities that are determined according to a translation table of your design.
label TR D1(L,B1),D2(B2)
Operand 1 Operand 2
Use Destination Address Table Address
or label or label
operation defaults to the length of the first operand. Maximum length of the operation is 16 bytes.

0-7 8-15 16-19 20-31 32-35 36-48
DC
DCLLB1DDD1B2DDD2
The condition code is not affected by the TR instruction.
Example:
ARG DC X’010003040105060404
TABLE DC X’C1C2C3C440D6E8C8'
TR ARG(7),TABLE
ARG (HEX BYTES) 01 00 03 04 01 05 06 04 04
TABLE (HEX BYTES) C1 C2 C3 C4 40 D6 E8 C8
ARG (HEX BYTES) C2 C1 C4 40 C2 D6 E8 04 04
TRT
Translate and Test
SS Type Op code = DD
Scans up to a 256 consecutive storage byte argument for a particular byte value. Translation proceeds from left to right
in the argument and stops when the first non-zero byte value is encountered in the translation table. The address of the
translated non-zero byte in the argument is stored in Register 1 and the corresponding byte found the translation table is
stored in the low-order byte of Register 2. The three high order bytes of Register 2 remain unchanged.
label TRT D1(L,B1),D2(B2)
Operand 1 Operand 2
Use Argument Address Table Address
or label or label

0-7 8-15 16-19 20-31 32-35 36-48
DD
DDLLB1DDD1B2DDD2
The condition code is set as follows:

Condition after Execution Condition code
All argument bytes considered and all table bytes referenced are zero 0*
Non-zero table byte found and argument byte is not the last (rightmost) one 1
Non-zero table byte found and argument byte is the last (rightmost) one 2
For Condition code of 0, Registers 1 and 2 remained unchanged
Example:
Register 1 = X’00000000’ (before execution)
Register 2 = X’00000000’ (before execution)
Addr 00010400 ARG DC X’030006040105060404’
TABLE DC X’00000000FF000000000000'
TRT ARG(7),TABLE
Addr 00010400
ARG (HEX BYTES) 03 00 06 04 01 05 06 04 04
TABLE (HEX BYTES) 00 00 00 00 FF 00 00 00 00 00

Table + 0 1 2 3 4 5 6 7 8 9
Register 1 = X’00010403 (after execution) Register 2 = X’000000FF’ (after execution)
This example shows how to scans the first 7 bytes of ARG and look for the hex value X’04’. It is scanning for
X’04’ because the byte at address TABLE + 4 is a non-zero value. When the scan encounters the fourth byte
in ARG, ( address 00010403 16 ), the translated value for X’04’ ( TABLE + 04 ) is X’FF’ and the operation
stops since it is a non-zero value. The address of the X’04’ in ARG is placed in Register 1 and the value found
in the translation table (X’FF’) is place in the low order byte of Register 2. The 3 high order bytes of Register
2 are unchanged.
UNPK
Unpack
SS Type Op code = F3
Converts the packed decimal number located at the doubleword specified by Operand 2 to zoned format and places it in
the storage area specified by Operand 1. If the destination storage area is longer than needed the instruction will pad
left with X’F0’s.
label UNPK D1(L,B1),D2(L2,B2)
Operand 1** Operand 2***

or label or label
The minimum length of the receiving field in bytes is calculated by...

CHARACTER LENGTH = (PACKED LENGTH x 2) - 1
** The data stored by the instruction at the address specified by Operand 1will be in zoned EBCDIC for mat.
*** The effective address of Operand 2 should be on a double word boundary.

OP CODE L1 L2 B1 D1 B2 D2
0-7 8-11 12-15 16-19 20-31 32-35 36-48
F3
F32L1L2B1DDD1B2DDD2
Length values are 1 less than source statement lengths .
The condition code is not affected by the UNPK instruction.
Example 1:
DWD DC X’00 00 00 00 00 12 34 5C’
NOPTYHLD DC CL7’0’ or DC ZL7’0’
UNPK NOPTYHLD,DWD
DWD = 00 00 00 00 00 12 34 5C
NOPTYHLD = F0 F0 F1 F2 F3 F4 C5
Pad left with X’F0s Sign = C for Positive numbers, D for negative numbers
(See NOTE below)
This example unpacks the pack decimal number stored at DWD as a zoned number into the five bytes at
NOPTYHLD.
NOTE: To convert the zoned number at NOPTYHLD to EBCDIC, the sign (C or D) must be changed to F. This is done by OR’ing
the sign and its digit with the hex value F0 using the Or Immediate instruction as follows...
OI NOPTYHOLD+6,X’F0’
USING
Declare Base Register Directive
Causes the assembler to assume that the specified register is a base register and that it contains the address of the
symbolic label specified in the first operand. At the time of assembly, R 1 does not contain this address and the USING
directive does not load the base register; you must do that with a separate instruction such as a Load (L). This directive
is typically used to establish a base register for referencing symbolically named fields in a DSECT.
(No label) USING LABEL1,R1
Operand 1 Operand 2
Use Storage Address Base Register
Format Symbolic Label Register No.
Spec Base address in R = Register # or
symbolic form symbolic Reg name
The instruction tells the assembler to use register R 1.as the base register and to assume that the register will contain the
address of LABEL 1 which is usually the name of a DSECT. The USING instruction does not generate machine
language instructions; it only provides information to the assembler. If R 1 is already being used as a base register for
another DSECT due to a previous USING directive, the previous USING is canceled and R 1 will be the base register for
the newly specified DSECT. To re-establish that register as a base for the first DSECT, a new USING directive must
be used.
Example:
If FLTREC is the symbolic label for a DSECT...
PGM400 EQU *
USING FLTREC,R7 Establishes R7 as base register for FLTREC DSECT
This example establishes R7 as the base register to be used when referencing symbolic labels for fields in the
DSECT named FLTREC. The DSECT’s data will be stored in the Level 1 data block whose address is stored at
the field labeled CE1CR1*. This address is loaded into R7. From this point on (or until another USING is coded
for FLTREC), the base displacement calculation for any of the fields in FLTREC will use the contents of R7 as a
base address.
* CE1CR1 is actually a symbolic label for the address of a fullword field in the ECB DSECT named EBOEB.
The contents of the fullword stored at CE1CR1 is the storage address of the data block obtained on level 1 when
the GETCC macro was executed.
X
Exclusive OR
Toggle bits in a register based on bits in a fullword storage area according to the truth table shown below.
label X R1,D2(X2,B2)
Operand 1 Operand 2
Register or literal
B = Register # or
symbolic Reg name

OP CODE R1 X2 B2 D2
0-7 8-11 12-15 16-19 20-31
57
57R1X2B2DDD2

Mask Value Mnemonic
Zero 0 8 BZ
Non-Zero 1 4 BNZ
LOGICAL 'XOR' TRUTH TABLE

0 0 0
0 1 1
1 0 1
1 1 0
Example:
X R2,LABEL1
Before:
R2
Hexadecimal C 4
Binary Bits 1 1 0 0 0 1 0 0
LABEL1 (Mask)
Hexadecimal 4 0
Binary Bits 0 1 0 0 0 0 0 0
After:
R2
Hexadecimal 8 4
Binary Bits 1 0 0 0 0 1 0 0
XC
Exclusive OR Characters
Toggle bits in a storage area based on bits in another storage area according to the truth table shown below. . The
process proceeds left to right, one byte at a time.
label XC D1(L,B1),D2(B2)
Operand 1 Operand 2
or label or label
symbolic Reg name

0-7 8-15 16-19 20-31 32-35 36-48
D7
D7LLB1DDD1B2DDD2

Mask Value Mnemonic
Zero 0 8 BZ
Non-Zero 1 4 BNZ

0 0 0
0 1 1
1 0 1
1 1 0
Example 1:
XC LABEL1(2),LABEL2
Before:
LABEL1
Hexadecimal C 4
Binary Bits 1 1 0 0 0 1 0 0

Hexadecimal 2 0
Binary Bits 0 0 1 0 0 0 0 0
After:
LABEL1
Hexadecimal E 4
Binary Bits 1 1 1 0 0 1 0 0
Example 2: (Clearing a storage area to zero’s)
This line of code will clear the storage area named LABEL1 to zero’s. XC LABEL1,LABEL1
XI
Exclusive OR Immediate
Toggle bits in a storage area based on bits in the specified immediate data according to the truth table shown below.
label XI D1(B1),I2
Operand 1 Operand 2
or Label
decimal value.
OP CODE R1 X2 B2 D2
0-7 8-11 12-15 16-19 20-31
97
97II2B1DDD1

Mask Value Mnemonic
Zero 0 8 BZ
Non-Zero 1 4 BNZ

0 0 0
0 1 1
1 0 1
1 1 0
Example:
XI LABEL1,X'02'
Before:
LABEL1
Hexadecimal A 4
Binary Bits 1 0 1 0 0 1 0 0

Hexadecimal 0 2
Binary Bits 0 0 0 0 0 0 1 0
After:
LABEL1
Hexadecimal A 6
Binary Bits 1 0 1 0 0 1 1 0
XR
Exclusive OR Registers
Turn one or more bits ON in a register that are on in another register according to the truth table shown below.
label XR R1,R2
Operand 1 Operand 2

Length = Halfword
OP CODE R1 R2
0-7 8-11 12-15
17
17R1R2

Mask Value Mnemonic
Zero 0 8 BZ
Non-Zero 1 4 BNZ

0 0 0
0 1 1
1 0 1
1 1 0
Example:
XR R2,R3
Before:
R2
Hexadecimal C 4
Binary Bits 1 1 0 0 0 1 0 0
R3 (Mask)
Hexadecimal 0 8
Binary Bits 0 0 0 0 1 0 0 0
After:
R2
Hexadecimal C C
Binary Bits 1 1 0 0 1 1 0 0

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Assembly Language

41362878.DOC (12/7/2021) [ 500 - 2 ] ALC Reference for TPF Applications Programmers

Assembler Language Reference

©Copyright Galileo International Partnership 1996

41362878.DOC (12/7/2021) [ 500 - 3 ] ALC Reference for TPF Applications Programmers

Table of Contents by Title

41362878.DOC (12/7/2021) [ 500 - 4 ] ALC Reference for TPF Applications Programmers

Table of Contents by Title (cont.)

41362878.DOC (12/7/2021) [ 500 - 5 ] ALC Reference for TPF Applications Programmers

Table of Contents by Mnemonic

41362878.DOC (12/7/2021) [ 500 - 6 ] ALC Reference for TPF Applications Programmers

Table of Contents by Mnemonic (cont.)

41362878.DOC (12/7/2021) [ 500 - 7 ] ALC Reference for TPF Applications Programmers

Machine code Instruction Length = Fullword

Results Cond code

Before: Addr 12816

After: Addr 12816

41362878.DOC (12/7/2021) [ 500 - 8 ] ALC Reference for TPF Applications Programmers

where d = Duplication factor (decimal number)

Defining a halfword constant as the data length of a relocatable expression

LABEL1 DC C'MY NAME' (length = 7)

Defining a fullword constant as the address of a relocatable expression.

0140 LABEL1 DC C'MY NAME' (length = 7)

41362878.DOC (12/7/2021) [ 500 - 9 ] ALC Reference for TPF Applications Programmers

Defining a constant using an absolute expression.

41362878.DOC (12/7/2021) [ 500 - 10 ] ALC Reference for TPF Applications Programmers

Machine code Instruction Length = Fullword

Results Cond code

AH R2,32(R0,R8) or R2,32(R8) or R2,32(,R8)

Before: Addr 12816

After: Addr 012816

41362878.DOC (12/7/2021) [ 500 - 11 ] ALC Reference for TPF Applications Programmers

Machine code Instruction

Results Cond code

41362878.DOC (12/7/2021) [ 500 - 12 ] ALC Reference for TPF Applications Programmers

label BAL R1,D2(X2,B2)

Machine code Instruction Length = Fullword

Note: If you see BAL in any Galileo assembler coding, it should be

41362878.DOC (12/7/2021) [ 500 - 13 ] ALC Reference for TPF Applications Programmers

label BALR R1,R2

Machine code Instruction

Note: If you see BALR in any Galileo assembler coding, it should be

41362878.DOC (12/7/2021) [ 500 - 14 ] ALC Reference for TPF Applications Programmers

label BAS R1,D2(X2,B2)

Machine code Instruction Length = Fullword

Note: If you see BAL in any Galileo assembler coding, it should be

41362878.DOC (12/7/2021) [ 500 - 15 ] ALC Reference for TPF Applications Programmers

label BASR R1,R2

Machine code Instruction

Note: If you see BALR in any Galileo assembler coding, it should be

41362878.DOC (12/7/2021) [ 500 - 16 ] ALC Reference for TPF Applications Programmers

Machine code Instruction Length = Fullword

41362878.DOC (12/7/2021) [ 500 - 17 ] ALC Reference for TPF Applications Programmers

41362878.DOC (12/7/2021) [ 500 - 18 ] ALC Reference for TPF Applications Programmers

Machine code Instruction Length = Fullword

41362878.DOC (12/7/2021) [ 500 - 19 ] ALC Reference for TPF Applications Programmers

41362878.DOC (12/7/2021) [ 500 - 20 ] ALC Reference for TPF Applications Programmers

label BCR M,R

Machine code Instruction

41362878.DOC (12/7/2021) [ 500 - 21 ] ALC Reference for TPF Applications Programmers