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    Machines, Machine Languages, and Digital Logic: Accumulator Machines Have A Sharply Limited Number of Data

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    Zanz Projectz
    This document discusses machine languages and digital logic. It begins by classifying computers as accumulator machines, stack machines, or general register machines based on their register structure. It then discusses computer instruction sets, including data movement, ALU, and branch instructions. The remainder of the document describes addressing modes, an informal description of a simple RISC computer, a formal description using register transfer notation, and how register transfers relate to logic circuits and hardware implementation.

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    Machines, Machine Languages, and Digital Logic: Accumulator Machines Have A Sharply Limited Number of Data

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    Zanz Projectz
    59 views6 pages
    This document discusses machine languages and digital logic. It begins by classifying computers as accumulator machines, stack machines, or general register machines based on their register structure. It then discusses computer instruction sets, including data movement, ALU, and branch instructions. The remainder of the document describes addressing modes, an informal description of a simple RISC computer, a formal description using register transfer notation, and how register transfers relate to logic circuits and hardware implementation.

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    Arkom Tugas 1

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    This document discusses machine languages and digital logic. It begins by classifying computers as accumulator machines, stack machines, or general register machines based on their register structure. It then discusses computer instruction sets, including data movement, ALU, and branch instructions. The remainder of the document describes addressing modes, an informal description of a simple RISC computer, a formal description using register transfer notation, and how register transfers relate to logic circuits and hardware implementation.

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    Attribution Non-Commercial (BY-NC)
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    Download as docx, pdf, or txt
    59 views6 pages

    Machines, Machine Languages, and Digital Logic: Accumulator Machines Have A Sharply Limited Number of Data

    Uploaded by

    Zanz Projectz
    This document discusses machine languages and digital logic. It begins by classifying computers as accumulator machines, stack machines, or general register machines based on their register structure. It then discusses computer instruction sets, including data movement, ALU, and branch instructions. The remainder of the document describes addressing modes, an informal description of a simple RISC computer, a formal description using register transfer notation, and how register transfers relate to logic circuits and hardware implementation.

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    CHAPTER 2

    MACHINES, MACHINE LANGUAGES, AND DIGITAL LOGIC

    2.1. Classification of Computers and Their Instruction


    Accumulator machines have a sharply limited number of data
    accumulators, often just one, in addition to the address registers within the
    CPU. They are called accumulators because they serve both as resource of one
    operand and as the destination for arithmetic instructions, and thus they serve
    to accumulate data.
    Stack machines do away with register names or numbers altogether.
    Operands are “pushed” onto the stack from memory as plates are pushed onto
    dispenser and “popped” off of the stack in reverse order: last-in-first-out.
    General register machines have a set of numbered registers within the
    CPU.

    2.2. Computer Instruction Set


    The instruction set of a computer is nothing more or less than its
    repertoire: the entire collection of instructions it can interpret and the actions
    is thereby effects. The most important are the arithmetic, or ALU, instructions,
    as they “get the job done”. The data movement instructions move data within
    the machine and to or from input/output devices.
    Either explicitly or implicitly:
     Which operation to perform
     Where to find the operand or operands, if there are operands
     Where to put the result, if there is a result
     Where to find the next instruction

    1
    a) Data Movement Instructions
    From the staging point, information is moved into the CPU, where
    it becomes part of the processor state, residing in one or another CPU
    register.
    And additional data type that some machine distinguish is the
    address data type.
    b) ALU Instruction
    In subsequent machines, operands and results of ALU operations
    could be located in registers or memory.
    c) Branch Instructions
    A transfer of control, or a branch, to an instruction other than the
    next one in sequence requires computation of a target address, which
    is the address to which control is to be transferred.
    The bit or bits that described the condition are stored in a register
    variously called the processor status word (PSW), the condition code
    (CC) register, or the status register.
    d) 4-,3-,2-,1-, and 0-Address and General Register Machine Classes
    The 4-Address Machines and Operations Memory accesses
    required when the instruction execute. In a microcoded design, the
    steps requires to execute an instruction are themselves stored as
    sequence of microcode instructions that are executed to effect
    instruction execution.
    The 3-Address Machines and Operations The inclusion within
    the CPU of a program counter that always points to the next
    instruction eliminates the need to specify the address of the next
    instruction in all but the class of branch instructions.
    The 2-Address Machines and Operations A reduction to two
    addresses can be obtained by storing the result into the memory
    address of one of the operands.

    2
    The 1-Address (Accumulator) Machines and Instructions
    requires additional operand to load and store the accumulator’s
    contents, however.
    The 0-Address (Stack) Computers and Address Formats Notice
    that the push and pop operations still require a memory address, and
    the word count for the code above is bytes for each push and pop, and
    additional byte for expression evaluation, for a total bytes.
    e) Access Path to Operands: Addressing Modes
    The many different kinds of data structures and program variable
    references possible in modern high-level languages have driven
    machine architects to develop many sophisticated ways of providing
    access paths to operands in memory and CPU registers: addressing
    modes.
    To access an operand in memory, the CPU must first generate an
    address, which it then issues to the memory subsystem. That address is
    referred to as an effective address.
    The immediate addressing mode, is used to access constants stored
    in the instruction.

    2.3. Informal Description of the Simple RISC Computer, SRC


    In informal description there is a:
    a) Register and Memory Structure
    b) Instruction Formats
    c) Arithmetic and Logic Instruction
    d) Branch Instruction
    e) Miscellaneous Instructions

    2.4. Formal Description of SRC Using Register Transfer Notation, RTN


    The importance of moving data among registers and memory cells in a
    computer, sometimes transforming that data in the process, makes notation

    3
    schemes known as register transfer (RT) languages a good method for
    incorporating the right level of precision into a computer specification.

    a. An RTN Description of the Simple RISC Computer, SRC


    Memory The most significant memories are the processor-state items,
    which are used by many instructions. The next most important memory
    elements are those of the large set or identical storage cells known as the
    main memory.
    Effective Address Calculations Some of the most important formats that
    name expressions using register fields instead of just renaming bits are
    those used to compute the effective address for a memory load or store.
    Instruction Interpretation and the Fetch-Execute Cycle The actions
    that occur for every instruction before the specific instruction is ever
    decode are known as instruction interpretation.
    Instruction Execution It takes the form of a long list of conditional
    operations.
    Memory Reference Instruction Instructions can be divided into different
    classes based on what kind of action they perform. The following
    instruction use a memory address, so their description includes the names
    defined in the effective address section.
    Branch Instructions Some special formatting on the constant field of the
    instruction is used only with branches.
    ALU Instructions For the time being we will limit this simple SRC
    computer to add, subtract, and negate on 32-bit 2’s complement numbers.
    Miscellaneous Instructions The nop instruction causes no action to take
    place, and the stop instruction halts the computer until the next start signal
    is received.
    b. Formal versus Informal Description
    RTN should be considered a metalanguage, a language that is used to
    describe languages. RTN helps prevent two kinds of errors that can arise
    during design and implementation:

    4
    1) Errors caused by a misinterpretation of the machine description
    2) Errors of design and implementation

    2.5. Describing Addressing Modes with RTN


    The need for different addressing modes is based on common ways of
    structure data in computer programs. A simple variable in memory can be
    addressed by a constant whose value is known when the instruction is
    generated.

    2.6. Register Transfers and Logic Circuits: From Behavior to Hardware


    In logic circuits courses, AND, OR, and NOT gates are thought of as
    components of Boolean expressions and flip-flops as state variables in
    sequential circuits.
    a. Logic Circuits to Implement Register Transfer
    The data bit “moves” (is copied) into A when the Strobe signal is
    activated. Strobe signals are seldom directly connected to the machine
    clock, so the term strobe input may be less confusing.
    Multiple-Bit Transfers The fact that Strobe is only one wire implies a
    parallel connection to the corresponding inputs of all m flip-flops in the A
    register.
    Data Transmission in the Computer Logic gates and flip-flops can be
    viewed in terms of their data transmission behavior.
    Merging and Extracting Data The real utility of this viewpoint comes
    when we adopt the multidevice and multiwire conventions.
    Controlled Extraction of Data If we have m wires on which the data x
    and y are multiplexed, x can be separated from y by a set of m AND gates
    gated by Gx.
    Multiple Register Transfers Multiplexer and timing are the key to
    transferring data from one of several source registers to one several
    destinations.

    5
    b. The Bus as Data Highway
    Eliminating the Multiplexer by Open-Collector Gates To simplify a
    brief excursion into electronics.
    Eliminating Multiplexer By Using Tri-State Gates A slightly different
    form is more commonly used for the present purpose of multiplexed
    register transfers.
    Register Transfer Using a Tri-State Bus An m-wire tri-state bus can be
    used to connect n registers together.
    A Register Transfer Bus with Arithmetic Capability Although a single
    bus can interconnect registers so that the register transfer Dst Src can
    be done for any source and destination register.
    Abstract RTN, Concrete RTN, and Control Signals An abstract RTN
    describes the register transfer in terms of its effects only. A concrete RTN
    it refers to how the register transfer happens in a particular hardware
    implementation. The control sequence is a translation of the concrete RTN
    to the sequence of control signals needed to accomplish the concrete RTN.
    c. Register Transfer Operations and Data Path
    Hardware structures that interconnect registers, including arithmetic units
    and other data transformers, constitute the data path of a computer. A
    collection of register transfers between different sources and destinations
    may be implemented by a shared bus connection, provided that two source
    values do not need to be moved at the same time.
    RTN statements involving data transformation imply the existence of
    arithmetic units in the data path.

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