The document contains 6 questions about cache memory systems including direct mapped, associative, and set associative caches. It asks for address formats, parameters like number of blocks and lines, and cache hits and misses given example page reference streams and replacement policies.
The document contains 6 questions about cache memory systems including direct mapped, associative, and set associative caches. It asks for address formats, parameters like number of blocks and lines, and cache hits and misses given example page reference streams and replacement policies.
The document contains 6 questions about cache memory systems including direct mapped, associative, and set associative caches. It asks for address formats, parameters like number of blocks and lines, and cache hits and misses given example page reference streams and replacement policies.
The document contains 6 questions about cache memory systems including direct mapped, associative, and set associative caches. It asks for address formats, parameters like number of blocks and lines, and cache hits and misses given example page reference streams and replacement policies.
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ASSIGNMENT NUMBER3
MAPPING ASSIGNMENT Submission Date :Tuesday 23.4.2016
Q1.Consider a memory system that uses a 32-bit address to address
at the byte level, plus a cache that uses a 16-byte line size. a. Assume a direct mapped cache with a tag field in the address of 20 bits. Show the address format and determine the following parameters: number of addressable units, number of blocks in main memory, number of lines in cache, size of tag. b. Assume an associative cache. Show the address format and determine the following parameters: number of addressable units, number of blocks in main memory, number of lines in cache, size of tag. c. Assume a four-way set-associative cache with a tag field in the address of 9 bits. Show the address format and determine the following parameters: number of addressable units, number of blocks in main memory, number of lines in set, number of sets in cache, number of lines in cache, size of tag.
Q2.A set associative cache consists of 32 lines divided into four-line
sets. Main memory contains 8K blocks of 128 words each. Show the format of memory addresses.(tag slot/set word bit) a).Find out bits required to address MM b) Find out the capacity of cache c) Findout the set size and no. of sets
Q3.Consider a machine with a byte addressable main memory of
2^16 bytes and block size of 8 bytes. Assume that a direct mapped cache consisting of 32 lines is used with this machine Q4.Let us consider a memory hierarchy (main memory + cache) given by: - Memory size 2 Giga Byte (Byte addressed) - Cache size 512 K Byte (Byte addressed) - Cache block size = line size=512 Byte Calculate the number of cache blocks and the structure of the addresses for the following cache 3. Calculate the number of sets for the previous set associative caches. structures: - direct mapped cache; - fully associative cache - 4-way set-associative cache; 8-way set–associative cache. Q5. Consider a computer with the following characteristics: total of 1Mbyte of main memory; word size of 1 byte; block size of 16 bytes; and cache size of 64 Kbytes. a. For the main memory addresses of F0010, 01234, and CABBE, give the corresponding tag, cache line address, and word offsets for a direct- mapped cache. c. For the main memory addresses of F0010 and CABBE, give the corresponding tag and offset values for a fully-associative cache(associative). d. For the main memory addresses of F0010 and CABBE, give the corresponding tag, cache set, and offset values for a two-way set- associative cache Q6. (A) Assume you have the following page reference stream: A, B, C, D, A, B, E, A, B, C, D, E. Assuming a page cache of size 3 pages and a FIFO replacement policy, how many misses will there be? (B) Assuming a page cache of size 4 pages and a FIFO replacement policy, how many misses will there be? (C) Findout the hit ratio=? (D) Which policy gives the best hit ratio LRU FIFO LFU=?
