Simplified MIPS Datapath: Add Sub and or SLT Beq LW SW

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Simplified MIPS Datapath Critical Path 1

Consider the simplified MIPS datapath below, which supports the add, sub, and, or,
slt, beq, lw and sw instructions:

CS@VT October 2009 Computer Organization I ©2006-09 McQuain, Feng & Ribbens
Latency Critical Path 2

latency a measure of the time delay experienced in a system

The latency of the register file could be:


the time delay between the input bits
specifying a read register becoming
stable and the read data bits becoming
stable
the time delay between the input bits
specifying the write register and write
data becoming stable and the specified
bits being written to the specified write
register

Or, more likely, the larger of the two…

CS@VT October 2009 Computer Organization I ©2006-09 McQuain, Feng & Ribbens
Execution Paths in the Data Path Critical Path 3

For a given instruction, some datapath components are relevant (logically necessary) and
some are not.
Take add: 7

2
3
4

5 6

CS@VT October 2009 Computer Organization I ©2006-09 McQuain, Feng & Ribbens
Execution Paths in the Data Path Critical Path 4

For a given instruction, some datapath components are relevant (logically necessary) and
some are not.
Take add: 2
1

CS@VT October 2009 Computer Organization I ©2006-09 McQuain, Feng & Ribbens
Path Latency Critical Path 5

The latency of a path is the sum of the component latencies.


Assume the following latencies:
register fetch 50ps
add 50ps
2
mux 15ps 1

register file 100ps


memory write 400ps
3
memory read 300ps
ALU operation 100ps
Control unit 50ps

The latency of this path is then 115ps.

CS@VT October 2009 Computer Organization I ©2006-09 McQuain, Feng & Ribbens
Path Latency Critical Path 6

Assuming the same component latencies, what is the latency of this path?

2
3
4

5 6

CS@VT October 2009 Computer Organization I ©2006-09 McQuain, Feng & Ribbens
Instruction Latency Critical Path 7

The latency of an instruction is the latency of the longest path necessary for the execution
of that instruction.

That's called the critical path for the instruction.

For the add instruction in this datapath, the latency would be…?

CS@VT October 2009 Computer Organization I ©2006-09 McQuain, Feng & Ribbens
Datapath Latency Critical Path 8

The latency of of the datapath is the maximum latency among the instructions that the
datapath supports.

So, for this datapath, the latency would be…?

CS@VT October 2009 Computer Organization I ©2006-09 McQuain, Feng & Ribbens

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