Power MOSFET Maximum Ratings

Application Note

Power MOSFET
Maximum Ratings

Description
This document explains absolute maximum ratings, thermal resistance and safe operating area
(SOA) of power MOSFETs.

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Table of Contents
Description............................................................................................................................................1

Table of Contents .................................................................................................................................2

1. Absolute Maximum Ratings............................................................................................................3

1.1. Definition ............................................................................................................................................... 3

1.2. Parameters Specified as Absolute Maximum Ratings .................................................................... 3

1.2.1. Drain-source voltage (VDSS) ................................................................................................................4

1.2.2. Gate-source voltage (VGSS) ..................................................................................................................4

1.2.3. Drain current (ID) ..................................................................................................................................4

1.2.4. Power dissipation (PD) ..........................................................................................................................5

1.2.5. Avalanche current (IAS) and avalanche energy (EAS) ......................................................................5

1.2.6. Channel temperature (Tch) and storage temperature (Tstg) ..........................................................8

1.2.7. Isolation voltage (VISO(RMS)) .................................................................................................................8

1.2.8. Tightening torque (TOR) .....................................................................................................................8

2. Thermal Resistance.........................................................................................................................9

2.1. What Is Thermal Resistance? ............................................................................................................ 9

2.2. Thermal Resistance Calculation ........................................................................................................ 9

2.3. Transient Thermal Impedance and Steady-State Thermal Resistances .................................. 10

3. Safe Operating Area (SOA) .......................................................................................................... 11

3.1. Forward-Bias Safe Operating Area ..................................................................................................11

3.2. Restrictions of a Safe Operating Area .............................................................................................11

RESTRICTIONS ON PRODUCT USE.................................................................................................. 13

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1. Absolute Maximum Ratings
1.1. Definition
For power MOSFETs, the maximum allowable current, voltage, power dissipation and other
characteristics are specified as maximum ratings.
In circuit design, understanding maximum ratings is very important in order to obtain the best
performance from power MOSFETs and maintain device reliability throughout the target
operating life.
Maximum ratings must not be exceeded in order to guarantee the lifespan and reliability of
devices. For power MOSFETs, maximum ratings are defined using an absolute maximum rating
system.
Maximum ratings are the highest absolute values that must not be exceeded even
instantaneously under any conditions.
A device may not be able to recover from stress that exceeds a specified maximum rating. None
of the absolute maximum ratings may be exceeded. Care should therefore be exercised
regarding bounces in supply voltage, variations in the characteristics of electronic devices,
possible exposure to stress higher than maximum ratings during circuit adjustment, changes in
ambient temperature, fluctuations in the input signal, and other such factors.
For example, power MOSFETs are rated in terms of drain current, pin-to-pin voltage, power
dissipation, channel temperature, and storage temperature. These characteristics are
interrelated and cannot be considered separately. They also depend on external circuit
conditions.
1.2. Parameters Specified as Absolute Maximum Ratings
(The specified characteristics differ from product to product. Ta=25°C unless otherwise
specified.)
Characteristic Symbol Unit Description

Drain-source voltage VDSS V The maximum voltage that can be applied across drain and
source, with gate and source short-circuited
Gate-source voltage VGSS V The maximum voltage that can be applied across gate and
source, with drain and source short-circuited
Drain DC ID A The maximum DC current that can pass through the drain to
current source
Pulse IDP The maximum allowable peak drain current for pulsed
operation
Power dissipation PD W The maximum power that can be dissipated by a MOSFET
(Tc=25°C)
Avalanche current IAS A The maximum peak non-repetitive current that is permitted
under avalanche conditions
Avalanche energy EAS mJ The maximum non-repetitive energy that the MOSFET can
dissipate under avalanche breakdown conditions
Channel temperature Tch ºC The maximum allowable chip temperature at which a MOSFET
operates
Storage temperature Tstg ºC The maximum temperature at which a MOSFET may be stored
range without voltage applying
Isolation voltage VISO(RMS) V The maximum voltage at which a MOSFET can maintain
isolation between the designated point on the case and
electrode leads
Tightening torque TOR N∙m The maximum torque that may be applied in the axial direction
when tightening a screw

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1.2.1. Drain-source voltage (VDSS)

The drain-source breakdown voltages of a power MOSFET are defined as follows according to
the gate-source bias conditions:
(1) VDSS: Drain-source voltage with gate and source short-circuited. Applying a voltage higher
than the rated value may cause a MOSFET to enter the breakdown region and be
permanently damaged.
(2) VDSX: Drain-source voltage with gate and source reverse-biased
In addition to VDSS and VDSX, VDSR and VDSO are defined for power MOSFETs. (VDSR is the
drain-source voltage with a resistor inserted between gate and source. VDSO is drain-source
voltage with gate open-circuited.) Since power MOSFETs have very high input impedance, they
should not be used in VDSO mode. In this mode, power MOSFETs are biased between gate and
source due to electrostatic induction and enter the conduction mode. Consequently, there is a
high probability that they will be permanently damaged.

1.2.2. Gate-source voltage (VGSS)

VGSS is the maximum allowable gate-to-source voltage with drain and source short-circuited.
This rating depends on the dielectric strength of the gate oxide. For MOSFETs, a permissible
value is specified, taking practical voltage and reliability into consideration.

1.2.3. Drain current (ID)

Generally, the maximum continuous (DC) current that the power MOSFET can pass in the
forward direction is specified as ID, whereas the pulsed current that the power MOSFET can pass
in the forward direction is specified as IDP. Likewise, the DC and pulsed currents in the reverse
(diode) direction are specified as IDR and IDRP, respectively (under ideal heat dissipation
conditions).
However, the maximum current values in the forward direction are limited by the power loss
caused by drain-source on-state resistance, and those in the reverse direction are limited by the
power loss due to the forward voltage across the diode. Since current ratings are affected by
heat dissipation conditions, maximum allowable current values are specified so that the channel
temperature will not exceed the rated Tch(max) value.
𝑇𝑇𝑐𝑐ℎ (𝑚𝑚𝑚𝑚𝑚𝑚) − 𝑇𝑇𝑐𝑐
𝐼𝐼𝐷𝐷 = �
𝑅𝑅𝐷𝐷𝐷𝐷(𝑜𝑜𝑜𝑜) (𝑚𝑚𝑚𝑚𝑚𝑚) × 𝑅𝑅𝑡𝑡ℎ(𝑐𝑐ℎ−𝑐𝑐)

𝑇𝑇𝑐𝑐ℎ (𝑚𝑚𝑚𝑚𝑚𝑚) − 𝑇𝑇𝑐𝑐

𝐼𝐼𝐷𝐷𝑃𝑃 = �
𝑅𝑅𝐷𝐷𝐷𝐷(𝑜𝑜𝑜𝑜) (𝑚𝑚𝑚𝑚𝑚𝑚) × 𝑟𝑟𝑡𝑡ℎ(𝑐𝑐ℎ−𝑐𝑐) (𝑡𝑡)

Tch(max): Maximum channel temperature

Tc: Case temperature (25°C)
Rth(ch-c): Steady-state thermal resistance
rth(ch-c)(t): Transient thermal resistance
RDS(ON)(max): Maximum drain-source on-state resistance at the maximum channel

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temperature
The drain current ID that the MOSFET device can carry is restricted not only by power loss but
also by the current-carrying capability of a package, the maximum channel temperature, the
safe operating area and other factors.

1.2.4. Power dissipation (PD)

PD is the maximum power that the MOSFET can dissipate continuously under the specified
thermal conditions.
The allowable power dissipation varies with the conditions under which the MOSFET is used
(such as ambient temperature and heat dissipation conditions).
PD is calculated as the maximum power dissipation for a device with an infinite heat sink at 25°C
ambient.
𝑇𝑇𝑐𝑐ℎ (𝑚𝑚𝑚𝑚𝑚𝑚) − 25℃
𝑃𝑃𝐷𝐷 =
𝑅𝑅𝑡𝑡ℎ(𝑐𝑐ℎ−𝑐𝑐)
PDP, the maximum transient power dissipation, is calculated as follows using the transient
thermal resistance value shown in individual MOSFET datasheets.
𝑇𝑇𝑐𝑐ℎ (𝑚𝑚𝑚𝑚𝑚𝑚) − 25℃
𝑃𝑃𝐷𝐷𝐷𝐷 =
𝑟𝑟𝑡𝑡ℎ(𝑐𝑐ℎ−𝑐𝑐) (𝑡𝑡)

1.2.5. Avalanche current (IAS) and avalanche energy (EAS)

When a power MOSFET operates at high speed as a switching device, a high surge voltage is
applied across drain and source at the time of turn-off due to the self-inductance of a circuit and
stray inductances. This surge voltage occasionally exceeds the rated voltage of the MOSFET,
causing it to enter the breakdown region. At this time, avalanche current passes through the
power MOSFET. Avalanche current exceeding the current or energy limit causes permanent
damage to the MOSFET. This phenomenon is called avalanche breakdown. IAS is the maximum
allowable avalanche current, and EAS is the maximum allowable avalanche energy.

(1) MOSFET Equivalent Circuit

Figure 1.1 and Figure 1.2 show the cross section and equivalent circuit of a MOSFET.

Drain

N-Channel
MOSFET

NPN Gate

Source

Figure 1.1 Cross Section of a MOSFET Figure 1.2 MOSFET Equivalent Circuit
(Parasitic NPN Transistor)
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(3) Avalanche operation

Avalanche breakdown occurs in the following two modes. Figure 1.3 shows an equivalent
circuit model for avalanche current.
(a). Avalanche current breakdown
If a voltage higher than the withstand voltage is applied across drain and source,
current i flows through resistor Rb. As a result, a forward voltage, i × Rb, appears
across the base and emitter of the transistor. If current i exceeds the permissible level,
the parasitic NPN transistor turns on. When this happens, a large current flows
through the transistor, resulting in the destruction of the device.
(b). Avalanche energy breakdown
If a voltage higher than the withstand voltage is applied across drain and source,
current i flows. Because of this current and the applied voltage (i × BVDSS), a power
loss occurs. The resulting energy causes the device temperature to increase. The
device is destroyed if it exceeds the rated channel temperature.

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(4) Avalanche ruggedness and its measurement

Figure 1.4 shows the test circuit for the avalanche
Drain
capability of a power MOSFET. Figure 1.5 shows
waveforms during avalanche breakdown.
If the gate voltage VGS drops below the threshold at
turn-off, the drain current flowing through inductor L i
decreases, causing a sharp increase in drain-source Q Gate
D1
voltage VDS. When VGS is higher than the threshold
NPN
voltage, ID flows through the channel region of a power
Rb
MOSFET. However, when VGS drops below the threshold
voltage, the channel is shut off, causing ID to flow through
Source
the diode between drain and base (Figure 1.3). When
Figure 1.3 Equivalent Circuit
this happens, VDS begins to increase. When it reaches Model for Avalanche Current
the self-breakdown voltage, BVDSS (actual value), the
power MOSFET experiences avalanche breakdown, and VDS levels off.
The energy stored in L is transformed into heat, causing a rise in device temperature. As
a result, ID drops to zero, and VDS becomes equal to the supply voltage, VDD. Avalanche
current, IAS, is the peak current allowed during avalanche breakdown. Avalanche energy,
EAS, is the maximum energy permissible at this time.

L Gate Voltage

VDS
DUT BVDSS
VGS ID VDS IAS*
VDD iD VDD
0
t
0 t1
* IAS is the current value
Figure 1.4 Typical Avalanche Test
MOSFET Voltage and Drain Current
Circuit
Figure 1.5 Waveforms During Avalanche
(5) Avalanche energy calculation Breakdown
Avalanche energy is calculated as follows:
𝑑𝑑𝑖𝑖𝐷𝐷
From ∆V = −L
𝑑𝑑𝑑𝑑
𝑑𝑑𝑖𝑖𝐷𝐷
BV𝐷𝐷𝐷𝐷𝐷𝐷 − 𝑉𝑉𝐷𝐷𝐷𝐷 = −𝐿𝐿
𝑑𝑑𝑑𝑑
𝐵𝐵𝐵𝐵𝐷𝐷𝐷𝐷𝐷𝐷 − 𝑉𝑉𝐷𝐷𝐷𝐷
d𝑖𝑖𝐷𝐷 = − dt
𝐿𝐿

𝐵𝐵𝐵𝐵𝐷𝐷𝐷𝐷𝐷𝐷 − 𝑉𝑉𝐷𝐷𝐷𝐷
𝑖𝑖𝐷𝐷 (𝑡𝑡) = 𝐼𝐼𝐴𝐴𝐴𝐴 − � � 𝑡𝑡
𝐿𝐿

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𝑡𝑡1
𝐸𝐸𝐴𝐴𝐴𝐴 = � 𝑖𝑖𝐷𝐷 (𝑡𝑡) ∙ 𝐵𝐵𝐵𝐵𝐷𝐷𝐷𝐷𝐷𝐷 𝑑𝑑𝑑𝑑
0
𝑡𝑡1
𝐵𝐵𝐵𝐵𝐷𝐷𝐷𝐷𝐷𝐷 − 𝑉𝑉𝐷𝐷𝐷𝐷
= � �𝐼𝐼𝐴𝐴𝐴𝐴 − � � 𝑡𝑡� ∙ 𝐵𝐵𝐵𝐵𝐷𝐷𝐷𝐷𝐷𝐷 𝑑𝑑𝑑𝑑
0 𝐿𝐿
𝑡𝑡1
1 𝐵𝐵𝐵𝐵𝐷𝐷𝐷𝐷𝐷𝐷 − 𝑉𝑉𝐷𝐷𝐷𝐷 2
= �𝐼𝐼𝐴𝐴𝐴𝐴 𝐵𝐵𝐵𝐵𝐷𝐷𝐷𝐷𝐷𝐷 𝑡𝑡 − � � 𝐵𝐵𝐵𝐵𝐷𝐷𝐷𝐷𝐷𝐷 𝑡𝑡 �
2 𝐿𝐿 0
Substituting the following into t1,
𝐼𝐼𝐴𝐴𝐴𝐴 𝐿𝐿
t1 =
𝐵𝐵𝐵𝐵𝐷𝐷𝐷𝐷𝐷𝐷 − 𝑉𝑉𝐷𝐷𝐷𝐷
and solving the equation gives:
𝟏𝟏 𝑩𝑩𝑩𝑩𝑫𝑫𝑫𝑫𝑫𝑫
𝑬𝑬𝑨𝑨𝑨𝑨 = 𝑳𝑳𝑰𝑰𝑨𝑨𝑨𝑨 𝟐𝟐
𝟐𝟐 𝑩𝑩𝑩𝑩𝑫𝑫𝑫𝑫𝑫𝑫 − 𝑽𝑽𝑫𝑫𝑫𝑫

1.2.6. Channel temperature (Tch) and storage temperature (Tstg)

The materials that constitute a power MOSFET and their reliability determine the maximum
channel temperature Tch(max). The maximum channel temperature must be considered not
only in terms of the functional operation of the power MOSFET, but also in terms of its reliability
such as device degradation and lifetime.
Generally, degradation of the power MOSFET accelerates as the channel temperature increases.
Let A and B be constants intrinsic to a transistor. Then, the average life in hours of operation Lm
and the channel temperature in Kelvin (K) Tch has the following relationship:
𝐵𝐵
log𝐿𝐿𝑚𝑚 = 𝐴𝐴 +
𝑇𝑇𝑐𝑐ℎ
Therefore, for power MOSFETs that must have a long-term guaranteed service life, the
maximum channel temperature is determined, considering the defect rate and reliability
requirements.
Storage temperature Tstg is the temperature range in which a power MOSFET can be stored
without voltage applying. The materials that constitute the power MOSFET and their reliability
also determine the storage temperature range.

1.2.7. Isolation voltage (VISO(RMS))

For devices housed in a fully molded package, isolation voltage represents the level of electrical
isolation between the designated point on the case and the internal circuit and electrode
terminals.
VISO(RMS) is tested by applying AC voltage to the power MOSFET for a specified period of time.
Isolation voltage is specified as the RMS of AC voltage.

1.2.8. Tightening torque (TOR)

When attaching MOSFET devices to a thermal fin, the prescribed tightening torque must be
followed.
If the torque is too low, the mounting screws will loosen. If the torque is too high, the device
could be damaged.

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2. Thermal Resistance
2.1. What Is Thermal Resistance?
Thermal resistance is the ability of a material to resist the flow of thermal energy.
The power consumed by a semiconductor chip is converted into heat, which is transferred to the
case (package) and eventually released into ambient air through a thermal fin or other
thermally conductive material. An increase in power dissipation (PD) causes a further increase in
the device temperature (ΔT).
ΔT can be calculated as ΔT＝Rth× PD. Here, Rth is a constant defining a relationship between ΔT
and PD. This constant is called thermal resistance.

2.2. Thermal Resistance Calculation

The most commonly used thermal resistance values are:
Rth(ch-c): Channel-to-case thermal resistance
𝑇𝑇𝑐𝑐ℎ (𝑚𝑚𝑚𝑚𝑚𝑚) − 25℃
𝑅𝑅𝑡𝑡ℎ(𝑐𝑐ℎ−𝑐𝑐) = (℃/𝑊𝑊)
𝑃𝑃𝐷𝐷 (𝑇𝑇𝑐𝑐 = 25℃)
This is the thermal resistance of a device with an infinite heat sink when the case temperature
is kept constant at an ambient temperature of 25°C.
Rth(ch-a): Channel-to-ambient thermal resistance
𝑇𝑇𝑐𝑐ℎ (𝑚𝑚𝑚𝑚𝑚𝑚) − 25℃
𝑅𝑅𝑡𝑡ℎ(𝑐𝑐ℎ−𝑎𝑎) = (℃/𝑊𝑊)
𝑃𝑃𝐷𝐷 (𝑇𝑇𝑎𝑎 = 25℃)
This is a thermal resistance from the channel to the ambient air at 25°C. It is equal to Rth(ch-c)
+ Rth(c-a).
Note, however, that thermal resistance varies with board assembly condition and other factors.

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2.3. Transient Thermal Impedance and Steady-State Thermal Resistances
Transient thermal impedance is a function of time while the device is affected by thermal
capacitance. It varies with the duty cycle of the pulse being applied.
Steady-state thermal resistance is a property during the time the device is no longer affected by
thermal capacitance.
Figure 2.1 (a) and Figure 2.1 (b) show examples of transient thermal impedance curves as
normalized and absolute values, respectively.

(a) Transient Thermal Impedance (Normalized)

(b) Transient Thermal Impedance (Absolute)

Figure 2.1. Transient Thermal Impedance Curves

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3. Safe Operating Area (SOA)
3.1. Forward-Bias Safe Operating Area
In a power MOSFET, current is not apt to concentrate in a small area. Therefore, unlike bipolar
transistors, power MOSFETs are not generally vulnerable to secondary breakdown in a high
voltage region.
However, as device geometries shrink, some power MOSFET devices have begun to exhibit a
failure mode resembling secondary breakdown. As shown in Figure 3.1, the safe operating area
SOA of such power MOSFETs is not limited by a line of a certain fixed power.

Figure 3.1 Example of an SOA with Varying Power Lines

#3
3.2. Restrictions of a Safe Operating
Area
#1
The safe operating area is limited by current,
on-state resistance, heat, secondary #2
breakdown and voltage as follows:
#4
1. Current limit
#1 defines the area limited by the drain
current rating. For continuous-current
(DC) operation, the SOA is constrained
by IDmax. For pulsed operation, the
SOA is bound by the IDPmax line. #5
2. On-state resistance limit
#2 defines the area that is theoretically
constrained by the on-state resistance
(RDS(ON)max). ID is equal to
VDS/RDS(ON). Figure 3.2 Safe Operating Area
3. Thermal limit
#3 is the area constrained by the power dissipation PD.
PD (power dissipation) = ID×VDS

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4. Limit imposed by secondary breakdown
With shrinking device geometries, some power MOSFETs have exhibited a failure mode
resembling secondary breakdown in recent years. #4 represents the SOA bound by the
secondary breakdown constraint.
5. Voltage limit
#5 defines the area constrained by the drain-source voltage VDSS.

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