F9 1 MOV R1, A

8051 Instruction hex code FA 1 MOV R2, A

FB 1 MOV R3, A
MOVE with immediate data FC 1 MOV R4, A
FD 1 MOV R5, A
Hex Bytes Instruction FE 1 MOV R6, A
74 2 MOV A, #immediate FF 1 MOV R7, A
75 3 MOV direct, #immediate
76 2 MOV @R0, #immediate MOVE with external memory
77 2 MOV @R1, #immediate
78 2 MOV R0, #immediate E0 1 MOVX A, @DPTR
79 2 MOV R1, #immediate E2 1 MOVX A, @R0
7A 2 MOV R2, #immediate E3 1 MOVX A, @R1
7B 2 MOV R3, #immediate F0 1 MOVX @DPTR, A
7C 2 MOV R4, #immediate F2 1 MOVX @R0, A
7D 2 MOV R5, #immediate F3 1 MOVX @R1, A
7E 2 MOV R6, #immediate
7F 2 MOV R7, #immediate MOVE with code memory
90 3 MOV DPTR, #immediate
83 1 MOVC A, @A+PC
MOVE with direct memory location 93 1 MOVC A, @A+DPTR

85 3 MOV direct, direct Bit MOVE

88 2 MOV direct, R0
89 2 MOV direct, R1 92 2 MOV bit, C
8A 2 MOV direct, R2 A2 2 MOV C, bit
8B 2 MOV direct, R3
8C 2 MOV direct, R4 Indirect MOVE with R0 and R1
8D 2 MOV direct, R5
8E 2 MOV direct, R6 86 2 MOV direct, @R0
8F 2 MOV direct, R7 87 2 MOV direct, @R1
A8 2 MOV R0, direct A6 2 MOV @R0, direct
A9 2 MOV R1, direct A7 2 MOV @R1, direct
AA 2 MOV R2, direct
AB 2 MOV R3, direct ADD with Accumulator
AC 2 MOV R4, direct
AD 2 MOV R5, direct 24 2 ADD A, #immediate
AE 2 MOV R6, direct 25 2 ADD A, direct
AF 2 MOV R7, direct 26 1 ADD A, @R0
27 1 ADD A, @R1
MOVE with Accumulator 28 1 ADD A, R0
29 1 ADD A, R1
E5 2 MOV A, direct 2A 1 ADD A, R2
E6 1 MOV A, @R0 2B 1 ADD A, R3
E7 1 MOV A, @R1 2C 1 ADD A, R4
E8 1 MOV A, R0 2D 1 ADD A, R5
E9 1 MOV A, R1 2E 1 ADD A, R6
EA 1 MOV A, R2 2F 1 ADD A, R7
EB 1 MOV A, R3
EC 1 MOV A, R4 ADD with Accumulator & carry flag
ED 1 MOV A, R5
EE 1 MOV A, R6 34 2 ADDC A, #immediate
EF 1 MOV A, R7 35 2 ADDC A, direct
F5 2 MOV direct, A 36 1 ADDC A, @R0
F6 1 MOV @R0, A 37 1 ADDC A, @R1
F7 1 MOV @R1, A 38 1 ADDC A, R0
F8 1 MOV R0, A 39 1 ADDC A, R1
3A 1 ADDC A, R2 B8 3 CJNE R0, #immediate, offset
3B 1 ADDC A, R3 B9 3 CJNE R1, #immediate, offset
3C 1 ADDC A, R4 BA 3 CJNE R2, #immediate, offset
3D 1 ADDC A, R5 BB 3 CJNE R3, #immediate, offset
3E 1 ADDC A, R6 BC 3 CJNE R4, #immediate, offset
3F 1 ADDC A, R7 BD 3 CJNE R5, #immediate, offset
BE 3 CJNE R6, #immediate, offset
Subtract with borrow BF 3 CJNE R7, #immediate, offset

94 2 SUBB A, #immediate D8 2 DJNZ R0, offset

95 2 SUBB A, direct D9 2 DJNZ R1, offset
96 1 SUBB A, @R0 DA 2 DJNZ R2, offset
97 1 SUBB A, @R1 DB 2 DJNZ R3, offset
98 1 SUBB A, R0 DC 2 DJNZ R4, offset
99 1 SUBB A, R1 DD 2 DJNZ R5, offset
9A 1 SUBB A, R2 DE 2 DJNZ R6, offset
9B 1 SUBB A, R3 DF 2 DJNZ R7, offset
9C 1 SUBB A, R4 D5 3 DJNZ direct, offset
9D 1 SUBB A, R5
9E 1 SUBB A, R6
9F 1 SUBB A, R7
JUMP
INC and DEC
01 2 AJMP addr11
04 1 INC A 21 2 AJMP addr11
05 2 INC direct 41 2 AJMP addr11
06 1 INC @R0 61 2 AJMP addr11
07 1 INC @R1 81 2 AJMP addr11
08 1 INC R0 A1 2 AJMP addr11
09 1 INC R1 C1 2 AJMP addr11
0A 1 INC R2 E1 2 AJMP addr11
0B 1 INC R3
0C 1 INC R4 02 3 LJMP addr16
0D 1 INC R5 80 2 SJMP offset
0E 1 INC R6
0F 1 INC R7 JUMP with flag
A3 1 INC DPTR
10 3 JBC bit, offset
14 1 DEC A 20 3 JB bit, offset
15 2 DEC direct 30 3 JNB bit, offset
16 1 DEC @R0 40 2 JC offset
17 1 DEC @R1 50 2 JNC offset
18 1 DEC R0 60 2 JZ offset
19 1 DEC R1 70 2 JNZ offset
1A 1 DEC R2
1B 1 DEC R3 JUMP indirect
1C 1 DEC R4
1D 1 DEC R5 73 1 JMP @A+DPTR
1E 1 DEC R6
1F 1 DEC R7 CALL subroutine and Return

COMPARE with JUMP 11 2 ACALL addr11

31 2 ACALL addr11
B4 3 CJNE A, #immediate, offset 51 2 ACALL addr11
B5 3 CJNE A, direct, offset 71 2 ACALL addr11
B6 3 CJNE @R0, #immediate, offset 91 2 ACALL addr11
B7 3 CJNE @R1, #immediate, offset B1 2 ACALL addr11
D1 2 ACALLaddr11 6C 1 XRL A, R4
F1 2 ACALL addr11 6D 1 XRL A, R5
6E 1 XRL A, R6
12 3 LCALL addr16 6F 1 XRL A, R7
22 1 RET
32 1 RETI BIT logical

ROTATE 72 2 ORL C, bit

82 2 ANL C, bit
03 1 RR A A0 2 ORL C, /bit
13 1 RRC A B0 2 ANL C, /bit
23 1 RL A
33 1 RLC A B2 2 CPL bit
C4 1 SWAP A B3 1 CPL C
C2 2 CLR bit
LOGICAL C3 1 CLR C
D2 2 SETB bit
52 2 ANL direct, A D3 1 SETB C
53 3 ANL direct, #immediate
54 2 ANL A, #immediate Exchange
55 2 ANL A, direct
56 1 ANL A, @R0 C5 2 XCH A, direct
57 1 ANL A, @R1 C6 1 XCH A, @R0
58 1 ANL A, R0 C7 1 XCH A, @R1
59 1 ANL A, R1 C8 1 XCH A, R0
5A 1 ANL A, R2 C9 1 XCH A, R1
5B 1 ANL A, R3 CA 1 XCH A, R2
5C 1 ANL A, R4 CB 1 XCH A, R3
5D 1 ANL A, R5 CC 1 XCH A, R4
5E 1 ANL A, R6 CD 1 XCH A, R5
5F 1 ANL A, R7 CE 1 XCH A, R6
CF 1 XCH A, R71
42 2 ORL direct, A D6 1 XCHD A, @R0
43 3 ORL direct, #immediate D7 1 XCHD A, @R1
44 2 ORL A, #immediate
45 2 ORL A, direct PUSH & POP
46 1 ORL A, @R0
47 1 ORL A, @R1 C0 2 PUSH direct
48 1 ORL A, R0 D0 2 POP direct
49 1 ORL A, R1
4A 1 ORL A, R2 Accumulator
4B 1 ORL A, R3
4C 1 ORL A, R4 A4 1 MUL AB
4D 1 ORL A, R5 84 1 DIV AB
4E 1 ORL A, R6 D4 1 DA A
4F 1 ORL A, R7 E4 1 CLR A
F4 1 CPL A
62 2 XRL direct, A
63 3 XRL direct, #immediate No operation
64 2 XRL A, #immediate
65 2 XRL A, direct 00 1 NOP
66 1 XRL A, @R0
67 1 XRL A, @R1
68 1 XRL A, R0
69 1 XRL A, R1
6A 1 XRL A, R2
6B 1 XRL A, R3 Prepared for 8051 Microcontroller Kit by Wichit Sirichote © 2015
 35 2 ADDC A, direct
8051 Instruction hex code 36 1 ADDC A, @R0
37 1 ADDC A, @R1
Hex Bytes Instruction 38 1 ADDC A, R0
00 1 NOP 39 1 ADDC A, R1
01 2 AJMP addr11 3A 1 ADDC A, R2
02 3 LJMP addr16 3B 1 ADDC A, R3
03 1 RR A 3C 1 ADDC A, R4
04 1 INC A 3D 1 ADDC A, R5
05 2 INC direct 3E 1 ADDC A, R6
06 1 INC @R0 3F 1 ADDC A, R7
07 1 INC @R1 40 2 JC offset
08 1 INC R0 41 2 AJMP addr11
09 1 INC R1 42 2 ORL direct, A
0A 1 INC R2 43 3 ORL direct, #immediate
0B 1 INC R3 44 2 ORL A, #immediate
0C 1 INC R4 45 2 ORL A, direct
0D 1 INC R5 46 1 ORL A, @R0
0E 1 INC R6 47 1 ORL A, @R1
0F 1 INC R7 48 1 ORL A, R0
10 3 JBC bit, offset 49 1 ORL A, R1
11 2 ACALL addr11 4A 1 ORL A, R2
12 3 LCALL addr16 4B 1 ORL A, R3
13 1 RRC A 4C 1 ORL A, R4
14 1 DEC A 4D 1 ORL A, R5
15 2 DEC direct 4E 1 ORL A, R6
16 1 DEC @R0 4F 1 ORL A, R7
17 1 DEC @R1 50 2 JNC offset
18 1 DEC R0 51 2 ACALL addr11
19 1 DEC R1 52 2 ANL direct, A
1A 1 DEC R2 53 3 ANL direct, #immediate
1B 1 DEC R3 54 2 ANL A, #immediate
1C 1 DEC R4 55 2 ANL A, direct
1D 1 DEC R5 56 1 ANL A, @R0
1E 1 DEC R6 57 1 ANL A, @R1
1F 1 DEC R7 58 1 ANL A, R0
20 3 JB bit, offset 59 1 ANL A, R1
21 2 AJMP addr11 5A 1 ANL A, R2
22 1 RET 5B 1 ANL A, R3
23 1 RL A 5C 1 ANL A, R4
24 2 ADD A, #immediate 5D 1 ANL A, R5
25 2 ADD A, direct 5E 1 ANL A, R6
26 1 ADD A, @R0 5F 1 ANL A, R7
27 1 ADD A, @R1 60 2 JZ offset
28 1 ADD A, R0 61 2 AJMP addr11
29 1 ADD A, R1 62 2 XRL direct, A
2A 1 ADD A, R2 63 3 XRL direct, #immediate
2B 1 ADD A, R3 64 2 XRL A, #immediate
2C 1 ADD A, R4 65 2 XRL A, direct
2D 1 ADD A, R5 66 1 XRL A, @R0
2E 1 ADD A, R6 67 1 XRL A, @R1
2F 1 ADD A, R7 68 1 XRL A, R0
30 3 JNB bit, offset 69 1 XRL A, R1
31 2 ACALL addr11 6A 1 XRL A, R2
32 1 RETI 6B 1 XRL A, R3
33 1 RLC A 6C 1 XRL A, R4
34 2 ADDC A, #immediate 6D 1 XRL A, R5
6E 1 XRL A, R6 A6 2 MOV @R0, direct
6F 1 XRL A, R7 A7 2 MOV @R1, direct
70 2 JNZ offset A8 2 MOV R0, direct
71 2 ACALL addr11 A9 2 MOV R1, direct
72 2 ORL C, bit AA 2 MOV R2, direct
73 1 JMP @A+DPTR AB 2 MOV R3, direct
74 2 MOV A, #immediate AC 2 MOV R4, direct
75 3 MOV direct, #immediate AD 2 MOV R5, direct
76 2 MOV @R0, #immediate AE 2 MOV R6, direct
77 2 MOV @R1, #immediate AF 2 MOV R7, direct
78 2 MOV R0, #immediate B0 2 ANL C, /bit
79 2 MOV R1, #immediate B1 2 ACALL addr11
7A 2 MOV R2, #immediate B2 2 CPL bit
7B 2 MOV R3, #immediate B3 1 CPL C
7C 2 MOV R4, #immediate B4 3 CJNE A, #immediate, offset
7D 2 MOV R5, #immediate B5 3 CJNE A, direct, offset
7E 2 MOV R6, #immediate B6 3 CJNE @R0, #immediate, offset
7F 2 MOV R7, #immediate B7 3 CJNE @R1, #immediate, offset
B8 3 CJNE R0, #immediate, offset
80 2 SJMP offset B9 3 CJNE R1, #immediate, offset
81 2 AJMP addr11 BA 3 CJNE R2, #immediate, offset
82 2 ANL C, bit BB 3 CJNE R3, #immediate, offset
83 1 MOVC A, @A+PC BC 3 CJNE R4, #immediate, offset
84 1 DIV AB BD 3 CJNE R5, #immediate, offset
85 3 MOV direct, direct BE 3 CJNE R6, #immediate, offset
86 2 MOV direct, @R0 BF 3 CJNE R7, #immediate, offset
87 2 MOV direct, @R1 C0 2 PUSH direct
88 2 MOV direct, R0 C1 2 AJMP addr11
89 2 MOV direct, R1 C2 2 CLR bit
8A 2 MOV direct, R2 C3 1 CLR C
8B 2 MOV direct, R3 C4 1 SWAP A
8C 2 MOV direct, R4 C5 2 XCH A, direct
8D 2 MOV direct, R5 C6 1 XCH A, @R0
8E 2 MOV direct, R6 C7 1 XCH A, @R1
8F 2 MOV direct, R7 C8 1 XCH A, R0
90 3 MOV DPTR, #immediate C9 1 XCH A, R1
91 2 ACALL addr11 CA 1 XCH A, R2
92 2 MOV bit, C CB 1 XCH A, R3
93 1 MOVC A, @A+DPTR CC 1 XCH A, R4
94 2 SUBB A, #immediate CD 1 XCH A, R5
95 2 SUBB A, direct CE 1 XCH A, R6
96 1 SUBB A, @R0 CF 1 XCH A, R7
97 1 SUBB A, @R1 D0 2 POP direct
98 1 SUBB A, R0 D1 2 ACALL addr11
99 1 SUBB A, R1 D2 2 SETB bit
9A 1 SUBB A, R2 D3 1 SETB C
9B 1 SUBB A, R3 D4 1 DA A
9C 1 SUBB A, R4 D5 3 DJNZ direct, offset
9D 1 SUBB A, R5 D6 1 XCHD A, @R0
9E 1 SUBB A, R6 D7 1 XCHD A, @R1
9F 1 SUBB A, R7 D8 2 DJNZ R0, offset
A0 2 ORL C, /bit D9 2 DJNZ R1, offset
A1 2 AJMP addr11 DA 2 DJNZ R2, offset
A2 2 MOV C, bit DB 2 DJNZ R3, offset
A3 1 INC DPTR DC 2 DJNZ R4, offset
A4 1 MUL AB DD 2 DJNZ R5, offset
A5 undefined DE 2 DJNZ R6, offset
DF 2 DJNZ R7, offset 90 01 00 MOV DPTR,#0100H
E0 1 MOVX A, @DPTR
E1 2 AJMP addr11 4. Bit is location of bit address.
E2 1 MOVX A, @R0
E3 1 MOVX A, @R1 A2 B2 MOV C, P3.2
E4 1 CLR A
E5 2 MOV A, direct 5. OFFSET is the byte distant between current
E6 1 MOV A, @R0 Program counter and the destination.
E7 1 MOV A, @R1
E8 1 MOV A, R0 Finding the OFFSET byte can be done with ALT,
E9 1 MOV A, R1 OFFSET press.
EA 1 MOV A, R2
EB 1 MOV A, R3 6. Addr11 is 11 bits of destination address.
EC 1 MOV A, R4
ED 1 MOV A, R5 Finding the hex code for AJMP or ACALL can be
EE 1 MOV A, R6 done with ALT, AJMP or ACALL press.
EF 1 MOV A, R7
F0 1 MOVX @DPTR, A 7. Long CALL or Long JMP uses 16-bit address.
F1 2 ACALL addr11
F2 1 MOVX @R0, A 02 91 00 LJMP 9100H
F3 1 MOVX @R1, A 12 00 0B LCALL 000B
F4 1 CPL A
F5 2 MOV direct, A
F6 1 MOV @R0, A
F7 1 MOV @R1, A
F8 1 MOV R0, A
F9 1 MOV R1, A
FA 1 MOV R2, A
FB 1 MOV R3, A
FC 1 MOV R4, A
FD 1 MOV R5, A
FE 1 MOV R6, A
FF 1 MOV R7, A

NOTES

1. Direct address is RAM location 00-7F and SFR

80-FF

Hex code Instruction

75 30 55 MOV 30H, #55H

75 90 1F MOV 90H,#1FH

90H is PORT1, Special Function Register (SFR).

2. Indirect address is RAM location 00-FF

78 90 MOV R0,#90H
76 20 MOV @R0,#20H

90H is not PORT1. It is general RAM space in

the upper page 80-FF. The upper page must be
accessed with indirect addressing

3. Immediate data for DPTR will be 16-bit

Prepared for 8051 Microcontroller Kit by Wichit Sirichote © 2015