Unit 3

Basic Computer Organization and Design

Introduction
We introduce here a basic computer whose operation can be specified by the resister transfer
statements. Internal organization of the computer is defined by the sequence of microoperations it
performs on data stored in its resisters. Every different processor type has its own design (different
registers, buses, microoperations, machine instructions, etc). Modern processor is a very complex
device. It contains:
– Many registers
– Multiple arithmetic units, for both integer and floating point calculations
– The ability to pipeline several consecutive instructions for execution speedup.
However, to understand how processors work, we will start with a simplified processor model. M.
Morris Mano introduces a simple processor model; he calls it a “Basic Computer”. The Basic Computer
has two components, a processor and memory
• The memory has 4096 words in it
– 4096 = 212, so it takes 12 bits to select a word in memory
• Each word is 16 bits long

Instruction code and Stored program organization

Question: What do you understand by stored program organization?
Question: What is instruction and instruction format?
Instruction code is a group of bits that instructs the computer to perform a specific operation. It is
usually divided into parts. Most basic part is operation (operation code). Operation code is group of
bits that defines operations as add, subtract, multiply, shift, complement etc. The instructions of a
program, along with any needed data are stored in memory. The CPU reads the next instruction from
memory. It is placed in an Instruction Register (IR). Control circuitry in control unit then translates the
instruction into the sequence of microoperations necessary to implement it. Stored program concept
is the ability to store and execute instructions.

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Instruction Format of Basic Computer
A computer instruction is often divided into two parts
– An opcode (Operation Code) that specifies the operation for that instruction
– An address that specifies the registers and/or locations in memory to use for that
operation
In the Basic Computer, since the memory contains 4096 (= 212) words, we needs 12 bit to specify the
memory address that is used by this instruction. In the Basic Computer, bit 15 of the instruction
specifies the addressing mode (0: direct addressing, 1: indirect addressing). Since the memory words,
and hence the instructions, are 16 bits long, that leaves 3 bits for the instruction’s opcode.

Addressing Modes
The address field of an instruction can represent either
– Direct address: the address operand field is effective address (the address of the
operand) or,
– Indirect address: the address in operand field contains the memory address where
effective address resides.

Effective Address (EA): The address, where actual data resides is called effective address.

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Basic Computer Registers
Computer instructions are normally stored in the consecutive memory locations and are executed
sequentially one at a time. Thus computer needs processor resisters for manipulating data and
holding memory address which are shown in the following table:

Symbol Size Register Name Description

DR 16 Data Register Holds memory operand
AR 12 Address Register Holds address for memory
AC 16 Accumulator Processor register
IR 16 Instruction Register Holds instruction code
PC 12 Program Counter Holds address of instruction
TR 16 Temporary Register Holds temporary data
INPR 8 Input Register Holds input character
OUTR 8 Output Register Holds output character

Since the memory in the Basic Computer only has 4096 (=212) locations, PC and AR only needs 12 bits
Since the word size of Basic Computer only has 16 bit, the DR, AC, IR and TR needs 16 bits. The Basic
Computer uses a very simple model of input/output (I/O) operations
– Input devices are considered to send 8 bits of character data to the processor
– The processor can send 8 bits of character data to output devices
The Input Register (INPR) holds an 8 bit character gotten from an input device and the Output Register
(OUTR) holds an 8 bit character to be sent to an output device.

Common Bus system of Basic computer

The registers in the Basic Computer are connected using a bus. This gives a savings in circuitry over
complete connections between registers. Three control lines, S2, S1, and S0 control which register the
bus selects as its input.

S2 S1 S0 Register
0 0 0 X (nothing)
Either one of the registers will have its load signal
0 0 1 AR activated, or the memory will have its read signal
0 1 0 PC activated which will determine where the data
0 1 1 DR from the bus gets loaded. The 12-bit registers, AR
1 0 0 AC and PC, have 0’s loaded onto the bus in the high
order 4 bit positions. When the 8-bit register OUTR
1 0 1 IR
is loaded from the bus, the data comes from the
1 1 0 TR low order 8 bits on the bus.
1 1 1 Memory

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Fig: Basic computer resister connected in a common bus.

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Instruction Formats of Basic Computer
Question: What are different instruction format used basic computer?
Question: What is instruction set completeness? Is instruction set of basic computer complete?
The basic computer has 3 instruction code formats. Type of the instruction is recognized by the
computer control from 4-bit positions 12 through 15 of the instruction.

Instruction Set Completeness

An instruction set is said to be complete if it contains sufficient instructions to perform operations in
following categories:
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Functional Instructions
 Arithmetic, logic, and shift instructions
 Examples: ADD, CMA, INC, CIR, CIL, AND, CLA
Transfer Instructions
 Data transfers between the main memory and the processor registers
 Examples: LDA, STA
Control Instructions
 Program sequencing and control
 Examples: BUN, BSA, ISZ
Input/output Instructions
 Input and output
 Examples: INP, OUT

Instruction set of Basic computer is complete because:

 ADD, CMA (complement), INC can be used to perform addition and subtraction and CIR
(circular right shift), CIL (circular left shift) instructions can be used to achieve any kind of shift
operations. Addition subtraction and shifting can be used together to achieve multiplication
and division. AND, CMA and CLA (clear accumulator) can be used to achieve any logical
operations.
 LDA instruction moves data from memory to register and STA instruction moves data from
register to memory.
 The branch instructions BUN, BSA and ISZ together with skip instruction provide the
mechanism of program control and sequencing.
 INP instruction is used to read data from input device and OUT instruction is used to send data
from processor to output device.

Instruction Processing & Instruction Cycle (of Basic computer)

Control Unit
Control unit (CU) of a processor translates from machine instructions to the control signals for the
microoperations that implement them. There are two types of control organization:
Hardwired Control
 CU is made up of sequential and combinational circuits to generate the control signals.
 If logic is changed we need to change the whole circuitry
 Expensive
 Fast
Microprogrammed Control
 A control memory on the processor contains microprograms that activate the necessary
control signals
 If logic is changed we only need to change the microprogram
 Cheap
 Slow

NOTE: Microprogrammed control unit will be discussed in next chapter.

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Question: How basic computer translates machine instructions to control signals using hardwired
control? Explain with block diagram. (OR Discuss hardwired control unit of basic computer?)
The block diagram of a hardwired control unit is shown below. It consists of two decoders, a sequence
counter, and a number of control logic gates.

Mechanism:
 An instruction read from memory is
placed in the instruction resister
(IR) where it is decoded into three
parts: I bit, operation code and bits
0 through 11.
 The operation code bit is decoded
with 3 x 8 decoder producing 8
outputs D0 through D7.
 Bit 15 of the instruction is
transferred to a flip-flop I.
 And operand bits are applied to
control logic gates.
 The 16 outputs of 4-bit sequence
counter (SC) are decoded into 16
timing signals T0 through T15.
This means instruction cycle of basic
computer can not take more than 16
clock cycles.

Fig: Control unit of a basic computer

Timing signals
 Generated by 4-bit sequence counter and 4x16 decoder.
 The SC can be incremented or cleared.
 Example: T0, T1, T2, T3, T4, T0, T1 . . .
Assume: At time T4, SC is cleared to 0 if decoder output D3 is active: D3T4: SC 0
T0 T1 T2 T3 T4 T0
Clock

T0

T1

T2

T3

T4

D3

CLR
SC

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Instruction cycle
In Basic Computer, a machine instruction is executed in the following cycle:
1. Fetch an instruction from memory
2. Decode the instruction
3. Read the effective address from memory if the instruction has an indirect address
4. Execute the instruction
Upon the completion of step 4, control goes back to step 1 to fetch, decode and execute the next
instruction. This process is continued indefinitely until HALT instruction is encountered.

Fetch and decode

The microoperations for the fetch and decode phases can be specified by the following resister
transfer statements:

It is necessary to transfer the

address from PC to AR during
clock transition associated with
the timing signal T0. The
instruction read from memory is
then placed in IR with clock
transition associated with the
timing signal T1. At the same
time, PC is incremented by one
to prepare for the next
instruction in the program. At
time T2, the opcode in IR is
decoded, the indirect bit is
transferred to flip-flop I, and the
address part of the instruction is
transferred to AR.

NOTE: SC is incremented after

each clock pulse to produce the
sequence T0, T1 and T2.

Fig: Resister transfers for the fetch phase

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Determine the type of the instruction
The timing signal that is active after decoding is T3. During time T3, the control unit determines the
type of instruction that was just read from memory. Following flowchart presents an initial
configuration for the instruction cycle and shows how the control determines the instruction type
after decoding.

The three instruction types are subdivided

into four separate paths:

 D'7IT3: AR M[AR] (Indirect address)

 D'7I'T3: Nothing
 D7I'T3: Execute register-reference instrs.
 D7IT3: Execute input-output instructions.

Fig: Flowchart for instruction cycle (Initial configuration)

Resister transfers needed for the execution of resister-reference and memory-reference instructions
are explained below: (I/O instructions will be discussed later)
Resister-reference instructions:
Register Reference Instructions are recognized with
- D7 = 1, I = 0
- Register Ref. Instr. is specified in b0 ~ b11 of IR
- Execution starts with timing signal T3
Let
r = D7 I’T3 => Common to all Register Reference Instruction
Bi = IR (i), i=0, 1, 2... 11. [Bit in IR(0-11) that specifies the operation]

CLA rB11: AC  0, SC  0 Clear AC

CLE rB10: E  0, SC  0 Clear E

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CMA rB9: AC  AC’, SC  0 Complement AC
CME rB8: E  E’, SC  0 Complement E
CIR rB7: AC  shr AC, AC(15)  E, E  AC(0), SC  0 Circulate right
CIL rB6: AC  shl AC, AC(0)  E, E  AC(15), SC Circulate Left
INC rB5: AC  AC + 1, SC  0 Increment AC
SPA rB4: if (AC(15) = 0) then (PC  PC+1), SC  0 Skip if positive
SNA rB3: if (AC(15) = 1) then (PC  PC+1), SC  0 skip if negative
SZA rB2: if (AC = 0) then (PC  PC+1), SC  0 skip if AC zero
SZE rB1: if (E = 0) then (PC  PC+1), SC  0 skip if E zero
HLT rB0: S  0, SC  0 (S is a start-stop flip-flop) Halt computer

Memory-reference instructions
 Once an instruction has been loaded to IR, it may require further access to memory to perform its
intended function (direct or indirect).
 The effective address of the instruction is in the AR and was placed their during:
- Time signal T2 when I = 0 or
- Time signal T3 when I = 1
 Execution of memory reference instructions starts with the timing signal T4.
 Described symbolically using RTL.

Symbol Operation Decoder Symbolic Description

AND D0 AC  AC  M[AR]
ADD D1 AC  AC + M[AR], E  Cout
LDA D2 AC  M[AR]
STA D3 M[AR]  AC
BUN D4 PC  AR
BSA D5 M[AR]  PC, PC  AR + 1
ISZ D6 M[AR]  M[AR] + 1, if M[AR] + 1 = 0 then PC  PC+1

AND to AC
This instruction performs the AND logical operation on pairs of bits on AC and the memory word
specified by the effective address. The result is transferred to AC. Microoperations that execute these
instructions are:
D0T4: DR  M[AR] //Read operand
D0T5: AC AC  DR, SC  0 //AND with AC

ADD to AC
D1T4: DR  M[AR] //Read operand
D1T5: AC  AC + DR, E  Cout, SC  0 //Add to AC and stores carry in E

LDA: Load to AC
D2T4: DR  M[AR] //Read operand
D2T5: AC  DR, SC  0 //Load AC with DR

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STA: Store AC
D3T4: M[AR]  AC, SC  0 // store data into memory location

BUN: Branch Unconditionally

D4T4: PC  AR, SC  0 //Branch to specified address

BSA: Branch and Save Return Address

D5T4: M[AR]  PC, AR  AR + 1 // save return address and increment AR
D5T5: PC  AR, SC  0 // load PC with AR

ISZ: Increment and Skip-if-Zero

D6T4: DR  M[AR] //Load data into DR
D6T5: DR DR + 1 // Increment the data
D6T4: M[AR]  DR, if (DR = 0) then (PC  PC + 1), SC  0
// if DR=0 skip next instruction by incrementing PC

Input-Output and Interrupt

In computer, instructions and data stored in memory come from some input device and
Computational results must be transmitted to the user through some output device.

Input-output configuration
The terminal sends and receives serial information. Each quantity of information has 8 bits of an
alphanumeric code. Two basic computer resisters INPR and OUTR communicate with a communication
interfaces.

 INPR: Input register - 8 bits

 OUTR: Output register- 8 bits
 FGI: Input flag - 1 bit (Is a
control flip-flop, set to 1
when new information is
available)
 FGO: Output flag - 1 bit
 IEN: Interrupt enable - 1 bit

Fig: Input-output configuration

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Scenario1: when a key is struck in the keyboard, an 8-bit alphanumeric code is shifted into INPR and
the input flag FGI is set to 1. As long as the flag is set, the information in INPR can not be changed by
striking another key. The control checks the flag bit, if 1, contents of INPR is transferred in parallel to
AC and FGI is cleared to 0. Once the flag is cleared, new information can be shifted into INPR by
striking another key.
Scenario2: OUTR works similarly but the direction of information flow is reversed. Initially FGO is set
to 1. The computer checks the flag bit; if it is 1, the information is transferred in parallel to OUTR and
FGO is cleared to 0. The output device accepts the coded information, prints the corresponding
character and when operation is completed, it sets FGO to 1.

Input-output Instructions
I/O instructions are needed to transferring information to and form AC register, for checking the flag
bits and for controlling the interrupt facility.

Program Interrupt
• Input and Output interactions with electromechanical peripheral devices require huge
processing times compared with CPU processing times
– I/O (milliseconds) versus CPU (nano/micro-seconds)
• Interrupts permit other CPU instructions to execute while waiting for I/O to complete
• The I/O interface, instead of the CPU, monitors the I/O device.
• When the interface founds that the I/O device is ready for data transfer, it generates an
interrupt request to the CPU
• Upon detecting an interrupt, the CPU stops momentarily the task it is doing, branches to the
service routine to process the data transfer, and then returns to the task it was performing.

Scenario3: consider a computer which completes instruction cycle in 1µs. Assume I/O device that can
transfer information at the maximum rate of 10 characters/sec. Equivalently, one character every
100000µs. Two instructions are executed when computer checks the flag bit and decides not to
transfer information. Which means computer will check the flag 50000 times between each transfer.
Computer is wasting time while checking the flag instead of doing some useful processing task.

 IEN (Interrupt-enable flip-flop)

- can be set and cleared by instructions
- When cleared, the computer cannot be interrupted

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Interrupt cycle
This is a hardware implementation of a branch and save return address operation.

Fig: flowchart of interrupt cycle

 At the beginning of the instruction cycle,

the instruction that is read from memory
is in address 1.
 At memory address 1, the programmer
must store a branch instruction that sends
the control to an interrupt service routine
 The instruction that returns the control to
the original program is "indirect BUN 0"

Fig: Demonstration of interrupt cycle

Resister transfer operations in interrupt cycle

Register Transfer Statements for Interrupt Cycle
- R F/F ← 1 if IEN (FGI + FGO) T0’T1’T2’ ↔ T0’T1’T2’ (IEN) (FGI + FGO): R ← 1
 The fetch and decode phases of the instruction cycle must be modified: Replace T0, T1, T2 with
R'T0, R'T1, R'T2
 The interrupt cycle : RT0: AR ← 0, TR ← PC
RT1: M[AR] ← TR, PC ← 0
RT2: PC ← PC + 1, IEN ← 0, R ← 0, SC ← 0

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Complete computer description
Flowchart
This is the final flowchart of the instruction cycle including interrupt cycle for the basic computer.

Microoperations

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Design of Basic Computer (BC)

Hardware Components of BC
1. A memory unit: 4096 x 16.
2. Registers:
AR, PC, DR, AC, IR, TR, OUTR, INPR, and SC
3. Flip-Flops(Status):
I, S, E, R, IEN, FGI, and FGO
4. Decoders: A 3x8 Opcode decoder
A 4x16 timing decoder
5. Common bus: 16 bits
6. Control logic gates
7. Adder and Logic circuit: Connected to AC
Control Logic Gates
Inputs: Outputs:
1. Input Controls of the nine registers
1. Two decoder outputs 2. Read and Write Controls of memory
2. I flip-flop 3. Set, Clear, or Complement Controls
3. IR(0-11) of the flip-flops
4. AC(0-15) 4. S2, S1, S0 Controls to select a register
 To check if AC = 0 for the bus
 To detect sign bit AC(15) 5. AC, and Adder and Logic circuit
5. DR(0-15)
 To check if DR = 0
6. Values of seven flip-flops

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Control of resisters and memory
The control inputs of the resisters are LD (load), INR (increment) and CLR (clear).

 Address Resister (AR)

To derive the gate structure associated with the control inputs of AR: we find all the
statements that change the contents of AR.

Fig: Control gates associated with AR

Similarly, control gates for the other resisters as well as the read and write inputs of memory
can be derived. Viz. the logic gates associated with the read inputs of memory is derived by
scanning all statements that contain a read operation. (Read operation is recognized by the
symbol M[AR]).

The output of the logic gates that implement the Boolean expression above must be
connected to the read input of memory.

Control of flip-flops
The control gates for the seven flip-flops can be determined in a similar manner.
Example:
 IEN(Interrupt Enable Flag)

These three instructions can cause IEN flag to change its value.

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 Fig: control inputs for IEN
Control of Common Bus
The 16-bit common bus is controlled by the selection inputs S 2, S1 and S0. Binary numbers for S2S1S0 is
associated with a Boolean variable x1 through x7, which must be active in order to select the resister or
memory for the bus.

Fig: Encoder for Bus Selection Circuit

Example: when x1 = 1, S2S1S0 must be 001 and thus output of AR will be selected for the bus.

To determine the logic for each encoder input, it is necessary to find the control functions that place
the corresponding resister onto the bus.
Example: to find the logic that makes x1 = 1, we scan all resister transfer statements that have AR as a
source.

Therefore the Boolean function for x1 is,

Similarly, for memory read operation,

Fig: Encoder for bus selection inputs

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Design of Accumulator Logic
To design the logic associated with AC, we extract all resister transfer statements that change the
contents of AC. The circuit associated with the AC resister is shown below:

Fig: circuits associated with AC

Control of AC Resister
The gate structure that controls the LD, INR and CLR inputs of AC is shown below:

Fig: Gate structure for controlling LD, INR and CLR of AC

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Adder and Logic Circuit
The adder and logic circuit can be subdivided into 16 stages, with each bit corresponding to one bit of
AC.

This is LD output of
the gate structure
which in fact is input
for AC. (see diagram
for gate configuration
for AC register above)

Fig: One stage of adder and logic circuit

 One stage of the adder and logic circuit consists of seven AND gates, one OR gate and a full
adder (FA) as shown above.
 The input is labeled Ii output AC(i).
 When LD input is enabled, the 16 inputs Ii for i = 0, 1, 2… 15 are transferred to AC(i).
 The AND operation is achieved by ANDing AC(i) with the corresponding bit in DR(i).
 The transfer from INPR to AC is only for bits 0 through 7.
 The complement microoperation is obtained by inverting the bit value in AC.
 Shift-right operation transfers bit from AC(i+1) and shift-left operation transfers the bit from
AC(i-1).
HEY! : The complete adder and logic circuit consists of 16 stages connected together.

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EXERCISES: Textbook chapter 5  5.1, 5.2, 5.10, 5.23
5.1(solution)

5.10 (Solution)

5.23 (Solution)

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