Design of Amba Axi-4 Protocol (Version-1.0)

DESIGN OF AMBA AXI-4 PROTOCOL
(Version- 1.0)
REVISION HISTORY
Revision Date Author Description Remarks

1 13/03/2019 Sneha kulkarni AMBA AXI (1.0)
REVIEW HISTORY
Revision Date Author Description Remarks

Objective:
The main objective is to design an AMBA AXI protocol achieving communication between one
master and on slave.
Specifications:
The AMBA AXI-4 protocol is targeted at high-performance:
The features of AXI Module supported by this module are:
 Support of burst lengths up to 256 burst.

 All data access are same size as the width of data bus.
 Acknowledgment indication signal.
 Updated write response requirements.
 1 bit ID tag.
 Supports data bus and address bus width of 32 or 64.
Block diagram of the module:
FIG: Block diagram of System
AMBA AXI-4 has 5 separate channels for read, read response, write, write response and
control signals. The AXI protocol is burst-based. Every transaction has address and control
information on the address channel that describes the nature of the data to be transferred. The
data is transferred between master and slave using a write data channel to the slave or a read
data channel to the master. In write transactions, in which all the data flows from the master
to the slave, the AXI protocol has an additional write response channel to allow the slave to
signal to the master the completion of the write transaction.
FIG: AXI Master to Slave Channel
The write operation process starts when the master sends an address and control
information on the write address channel. The master then sends each item of write data over
the write data channel. The master keeps the VALID signal low until the write data is
available. The master sends the last data item, the WLAST signal goes HIGH. When the slave
has accepted all the data items, it drives a write response signal BRESP[1:0] back to the master
to indicate that the write transaction is complete.
After the read address appears on the address bus, the data transfer occurs on the read
data channel. The slave keeps the VALID signal LOW until the read data is available. For the
final data transfer of the burst, the slave asserts the RLAST signal to show that the last data
item is being transferred. The RRESP[1:0] signal indicates the status of the read transfer.
FIG: Top Level block diagram
Pin Description of the Module:
Input/
Signal Source Description
Output
Aclk Global Input Global Clock Signal
Aresetn Global Input Global Reset Signal
AWID[3:0] Master Input Write address ID
AWADDR[31:0] Master Input Write address
AWLEN[3:0] Master Input Write burst length
AWSIZE[2:0] Master Input Write burst size
AWBURST[1:0] Master Input Write burst type
AWLOCK[1:0] Master Input Write lock type
AWCACHE[1:0] Master Input Write cache type
AWPROT[2:0] Master Input Write protection
WDATA[31:0] Master Input Write data
ARID[3:0] Master Input Read address ID
ARADDR[31:0] Master Input Read address
ARLEN[3:0] Master Input Read burst length
ARSIZE[2:0] Master Input Read burst size
ARLOCK[1:0] Master Input Read lock type
ARCACHE[3:0] Master Input Read cache type
ARPROT[2:0] Master Input Read protection
RDATA[31:0] Master Input Read data
WLAST Master Input Write last
RLAST Slave Output Read last
AWVALID Master Output Write address valid
AWREADY Slave Output Write address ready
WVALID Master Output Write valid
RVALID Slave Output Read valid
BID[3:0] Slave Output Write response ID
RID[3:0] Slave Output Read response ID
BRESP[1:0] Slave Output Write response
RRESP[1:0] Slave Output Read response
BVALID Slave Output Write Response valid
BREADY Master Output Response Ready
RVALID Slave Output Read valid
Memo axi_data_in[31:0] memory Master Data input
Memo axi_addr_in[31:0] Memory Mater Address input
Write_ready Memory Master Control signal
Read_ready Memory Master Control signal
ack_master_out Master Memory Acknowledge signal
Axi_memo_data_read Master Memory Data read signal
axi_memo_data_out[31:0] Slave Memory Data out
axi_memo_addr_out[31:0] Slave Memory Address out
ack_slave_out Slave Memory Acknowledge signal
axi_slave_master_data_read Slave Master Data read signal

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DESIGN OF AMBA AXI-4 PROTOCOL

Revision Date Author Description Remarks

Revision Date Author Description Remarks

The AMBA AXI-4 protocol is targeted at high-performance:

The features of AXI Module supported by this module are:

 Support of burst lengths up to 256 burst.

Block diagram of the module:

FIG: Block diagram of System

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