A Project Report

DESIGN OF DIGITAL CLOCK USING VEROLIG HDL

under the partial fulfillment of

B.Tech (3 Year) during 2018-19

By

G.Meghana ( 160050070)

G..Yasaswi (160050071)

G.Navya (160050074)

Under the guidance of

Dr. T. Narendra Babu

KLEF
Green fields, Vaddeswaram, Guntur Dist.522502

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 DECLARATION

This is to certify that the course based Project entitled is “DESIGN OF DIGITAL CLOCK USING

VERILOG HDL” was carried out by G. Meghana (160050070), G. Yasaswi (160050071),

G. Navya (160050074) by in partial fulfillment of the requirement for the award of degree in BACHELOR

OF TECHNOLOGY in Electronics and Computer Engineering during the academic year 2018-2019.

Signature of the HOD Signature of the Faculty

Dr. P.SATYANARAYANA Dr. T.NARENDRA BABU

Signature of External Examiner

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 ACKNOWLEDGEMENT

It is great pleasure for me to express my gratitude to our honorable President Sri. Koneru
Satyanarayana garu for giving the opportunity and platform with facilities in accomplishing the
project based laboratory report.
I express sincere gratitude to our HOD Dr. P. SATYANARAYANA for his leadership and constant
motivation provided in successful completion of our academic semester.
I express my sincere thanks to our project supervisor Dr. T. Narendra Babu for his novel
association of ideas, encouragement, appreciation and intellectual zeal which motivated us to
venture this project successfully.
Finally, it is pleased to acknowledge the indebtedness to all those who devoted themselves directly
or indirectly to make this project report success.

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 CONTENTS

1. Abstract

2. Introduction

3. Bit serial Multiplier

4. Block Diagram

5. Algorithm

6. Code

7. Result

8. Conclusion

9. References

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 ABSTRACT

In this post, I want to share Verilog code for a simple Digital clock. The module has two inputs - A
Clock at 1 Hz frequency and an active high reset. There are three outputs to tell the time –
seconds,minutes,hours.

The time units are incremented in an always block using Behavioral modelling. At every clock
cycle we increment 'seconds'.Whenever seconds reaches the value '60' we increment 'minutes' by
1.Similarly whenever minutes reach '60' we increment 'hours' by 1.Once hours reaches the value '23'
we reset the digital clock.

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6
 INTRODUCTION

Advances in computer architecture over the past two decades have allowed the performance of digital
computer hardware to continue its exponential growth, despite increasing technological difficulty in
speed improvement at the circuit level. This phenomenal rate of growth, which is expected to
continue in the near future, would not have been possible without theoretical insights,
experimental research, and tool-building efforts that have helped transform computer architecture
from an art into one of the most quantitative branches of computer science and engineering. Better
understanding of the various forms of concurrency and the development of a reasonably efficient
and user- friendly programming model has been key enablers of this success story.

The downside of exponentially rising processor performance is an unprecedented increase in

hardware and software complexity. The trend toward greater complexity is not only at odds with
testability and verifiability but also hampers adaptability, performance tuning, and evaluation of the
various trade-offs, all of which contribute to soaring development costs. A key challenge facing
current and future computer designers is to reverse this trend by removing layer after layer of
complexity, opting instead for clean, robust, and easily certifiable designs, while continuing to try to
devise novel methods for gaining performance and ease-of-use benefits from simpler circuits that
can be readily adapted to application requirements.
In the computer designers’ quest for user-friendliness, compactness, simplicity, high
performance, low cost, and low power, computer arithmetic plays a key role. It is one of
oldest subfields of computer architecture. The bulk of hardware in early digital computers resided in
accumulator and other arithmetic/logic circuits. Thus, first- generation computer designers were
motivated to simplify and share hardware to the extent possible and to carry out detailed cost-
performance analyses before proposing a design. Many of the ingenious design methods that we use
today have their roots in the bulky, power-hungry machines of 30-50 years ago.
In fact computer arithmetic has been so successful that it has, at times, become transparent. Arithmetic
circuits are no longer dominant in terms of complexity; registers, memory and memory
management, instruction issue logic, and pipeline control have become the dominant consumers of
chip area in today’s processors.

The preceding context is changing for several reasons. First ,at very high clock rates, the interfaces
between arithmetic circuits and the rest of the processor become critical. Arithmetic units can no
longer be designed and verified in isolation. Rather, an integrated design optimization is required,
which makes the development even more complex and costly. Second, optimizing arithmetic circuits
to meet design goals by taking advantage of the strengths of new technologies, and making them
tolerant to the weaknesses, requires a reexamination of existing design paradigms .Finally,
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incorporation of higher-level arithmetic primitives into hardware makes the design, optimization, and
verification efforts highly complex and interrelated.

This is why computer arithmetic is alive and well today. Designers and researchers in thisarea
produce no vel structures with amazing regularity. Carry- look ahead adders comprise a case in point.
We used to think, in the not so distant past, that we knew all there was to know about carry-look
ahead fast adders. Yet, new designs, improvements, and optimizations are still appearing. The
ANSI/IEEE standard floating- point format has removed many of the concerns with compatibility
and error control in floating-point computations, thus resulting in new designs and products with mass-
market appeal. Given the arithmetic-intensive nature of many novel application areas (such as
encryption, error checking, and multimedia), computer arithmetic will continue to thrive for years
to come.

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 BIT-SERIAL MULTIPLIER

Bit-serial arithmetic is attractive in view of its smaller pin count, reduced wire length, and lower
floor space requirements in VLSI. In fact, the compactness of the design may allow us to run a
bit-serial multiplier at a clock rate high enough to make the unit almost competitive with much
more complex designs with regard to speed. In addition, in certain application contexts inputs are
supplied bit-serially anyway. In such a case, using a parallel multiplier would be quite wasteful,
since the parallelism may not lead to any speed benefit. Furthermore, in applications that call for a
large number of independent multiplications, multiple bit-serial multipliers may be more cost-
effective than a complex highly pipelined unit.

Bit-serial multipliers can be designed as systolic arrays: synchronous arrays of processing elements
that are interconnected by only short, local wires thus allowing very high clock rates. Let us begin
by introducing a semi systolic multiplier, so named because its design involves broadcasting a
single bit of the multiplier x to a number of circuit elements, thus violating the “short, local wires”
requirement of pure systolic design.
A semi systolic 4 x 4 multiplier. The multiplicand a is supplied in parallel from above and the
multiplier x is supplied bit-serially from the right, with its least significant bit arriving first. Each bit
xi of the multiplier is multiplied by a and the result added to the cumulative partial product, kept in
carry-save form in the carry and sum latches. The carry bit stays in its current position, while the
sum bit is passed on to the neighboring cell on the right. This corresponds to shifting the
partial product to the right before the next addition step (normally the sum bit would stay put and
the carry bit would be shifted to the left). Bits of the result emerge serially from the right as they
become available.
A k-bit unsigned multiplier x must be padded with k zeros to allow the carries to propagate to the
output, yieldingthecorrect2k-bitproduct. Thus, the semi systolic multiplier of Figure 4.4 can perform
one k x k unsigned integer multiplication every 2k clock cycles. If k-bit fractions need to be
multiplied, the first k output bits are discarded or used to properly round the most significant
Kbits.
To make the multiplier of Figure 4.4fully systolic, we must remove the broadcasting of the
multiplier bits. This can be accomplished by a process known as systolic retiming, which is briefly
explained below
Consider a synchronous (clocked) circuit, with each line between two functional parts having an
integral number of unit delays (possibly 0). Then, if we cut the circuit into two parts CL and CR,
we can delay (advance) all the signals going in one direction and advance (delay) the ones going in
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the opposite direction by the same amount without affecting the correct functioning or external
timing relations of the circuit. Of course, the primary inputs and outputs to the two parts CL and
cg must be correspondingly advanced or delayed, too.
For the retiming to be possible, all the signals that are advanced by must have had original delays of
d or more(negative delays are not allowed).Note that all the signals going into CL have been
delayed by d time units. Thus ,CL will work as before, except that everything, including output
production, occurs d time units later than before retiming. Advancing the outputs by d time units will
keep the external view of the circuit unchanged.
We apply the preceding process to the multiplier circuit of Figure 4.4in three successive steps
corresponding to cuts 1, 2, and 3, each time delaying the left-moving signal by one unit and
advancing the right-moving signal by one unit. Verifying that the multiplier in Fig. 12.9 works
correctly is left as an exercise. This new version of our multiplier does not have the fan-out
problem of the design in Figure 4.4but it suffers from long signal propagation delay through the
four FAs in each clock cycle, leading to inferior operating speed. Note that the culprits are zero-
delay lines that lead to signal propagation through multiple circuit elements.
The easiest way to derive a multiplier with both inputs entering bit-serially is to allow k clock
ticks for the multiplicand bits to be put into place in a shift register and then use the design of to
compute the product. This increases the total delay by k cycles. uses dot notation to show the
justification for the bit-serial multiplier design above. depicts the meanings of the various partial
operands and results.

Bit Serial multiplier design in dot notation

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BIT-SERIAL MULTIPLIER; 4X4 MULTIPLICATION IN 8 CLOCK CYCLES

Bit-serial Multiplier Algorithm:

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Bit-Serial multiplier code

SOURCE CODE:
module digitalclk(Clk,reset,seconds,minutes,hours);
input Clk;
input reset;
output [5:0] seconds;
output [5:0] minutes;
output [4:0] hours;
reg [5:0] seconds;
reg [5:0] minutes;
reg [4:0] hours;
always @(posedge(Clk) or posedge(reset))
begin
if(reset) begin //check for active high reset.
//reset the time.
seconds = 0;
minutes = 0;
hours = 0; end
else if(Clk) begin //at the beginning of each second
seconds = seconds + 1; //increment sec
if(seconds == 59) begin //check for max value of sec
seconds = 0; //reset seconds
minutes = 1; //increment minutes
if(minutes == 59) begin //check for max value of min
minutes = 0; //reset minutes
hours = 1; //increment hours
if(hours == 24) begin //check for max value of hours
hours = 0;
minutes=0;
seconds=0; //reset hours
end
end
end
end
end

endmodule

TESTBENCH:

module digitalclk_tb();
// Inputs
reg Clk;
reg reset;

// Outputs
wire [5:0] seconds;
wire [5:0] minutes;
wire [4:0] hours;
digitalclk uut (.Clk(Clk), .reset(reset),.seconds(seconds),.minutes(minutes),.hours(hours));

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 //Generating the Clock with `1 Hz frequency
initial Clk = 0;
always #1 Clk = ~Clk; //Every 0.5 sec toggle the clock.

initial begin
reset = 1;
// Wait 100 ns for global reset to finish
#100;
reset = 0;
end
endmodule

RESULT:

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 CONCLUSIONS

Multipliers play an important role in today’s digital signal processing and various other applications.
With advances in technology, many researchers have tried and are trying to design multipliers
which offer either of the following design targets – high speed, low power consumption,
regularity of layout and hence less area or even combination of them in one multiplier thus
making them suitable for various high speed, low power and compact VLSI implementation.
The common multiplication method is “add and shift” algorithm. In parallel multipliers number of
partial products to be added is the main parameter that determines the performance of the
multiplier. To reduce the number of partial products to be added, Modified Booth algorithm is one
of the most popular algorithms. To achieve speed improvements Wallace Tree algorithm can be
used to reduce the number of sequential adding stages. Further by combining both Modified
Booth algorithm and Wallace Tree technique we can see advantage of both algorithms in one
multiplier. However with increasing parallelism, the amount of shifts between the partial products
and intermediate sums to be added will increase which may result in reduced speed, increase in silicon
area due to irregularity of structure and also increased power consumption due to increase in
interconnect resulting from complex routing. On the other hand “serial-parallel” multipliers
compromise speed to achieve better performance for area and power consumption. The selection
of a parallel or serial multiplier actually depends on the nature of application.
A key challenge facing current and future computer designers is to reverse the trend by removing
layer after layer of complexity, opting instead for clean, robust, and easily certifiable designs, while
continuing to try to devise novel methods for gaining performance and ease-of-use benefits from
simpler circuits that can be readily adapted to application requirements.
This is achieved by using Bit Serial multipliers.

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 REFERENCES

[1] http://verilogcodes.blogspot.com/2015/10/verilog-code-for-digital-clock.html
[2] file:///C:/Users/meghana/Downloads/DESIGN%20OF%20DIGITAL%20CLOCK.pd
f
[3] Ghest, C., Multiplying Made Easy for Digital Assemblies, Electronics, Vol. 44, pp.56-
61. November 22.1971.
[4] Ienne, P., and M. A. Verdean, “Bit-Seria1 Multipliers and Squarer’s,” IEEETrans.
Computers, Vol. 43, No. 12, pp. 1445-1450, 1994
[5] Samir Palnitkar, Verilog HDL: A Guide to Digital Design and

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