CHAPTER 1

INTRODUCTION
1.1 INTRODUCTION OF VLSI:
Very-large-scale integration (VLSI) is the process of creating an integrated circuit (IC) by
combining hundreds of thousands of transistors or devices into a single chip. VLSI began in the
1970s when complex semiconductor and communication technologies were being developed.
The microprocessor is a VLSI device. Before the introduction of VLSI technology most ICs had
a limited set of functions they could perform. An electronic circuit might consist of a CPU,
ROM, RAM and other glue logic. VLSI lets IC designers add all of these into one chip.
The history of the transistor dates to the 1920s when several inventors attempted devices
that were intended to control current in solid-state diodes and convert them into triodes. Success
came after World War II, when the use of silicon and germanium crystals as radar detectors led
to improvements in fabrication and theory. Scientists who had worked on radar returned to solid-
state device development. With the invention of transistors at Bell Labs in 1947, the field of
electronics shifted from vacuum tubes to solid-state device.
With the small transistor at their hands, electrical engineers of the 1950s saw the
possibilities of constructing far more advanced circuits. However, as the complexity of circuits
grew, problems arose.
One problem was the size of the circuit. A complex circuit like a computer was dependent
on speed. If the components were large, the wires interconnecting them must be long. The
electric signals took time to go through the circuit, thus slowing the computer.
The invention of the integrated circuit by Jack Kilby and Robert Noyce solved this
problem by making all the components and the chip out of the same block (monolith) of
semiconductor material. The circuits could be made smaller, and the manufacturing process
could be automated. This led to the idea of integrating all components on a single-crystal silicon
wafer, which led to small-scale integration (SSI) in the early 1960s, medium-scale integration
(MSI) in the late 1960s, and then large-scale integration (LSI) as well as VLSI in the 1970s and

1
1980s, with tens of thousands of transistors on a single chip (later hundreds of thousands, then
millions, and now billions (109)).
The first semiconductor chips held two transistors each. Subsequent advances added
more transistors, and as a consequence, more individual functions or systems were integrated
over time. The first integrated circuits held only a few devices, perhaps as many as ten diodes,
transistors, resistors and capacitors, making it possible to fabricate one or more logic gates on a
single device. Now known retrospectively as small-scale integration (SSI), improvements in
technique led to devices with hundreds of logic gates, known as medium-scale integration (MSI).
Further improvements led to large-scale integration (LSI), i.e. systems with at least a thousand
logic gates. Current technology has moved far past this mark and today's microprocessors have
many millions of gates and billions of individual transistors.
At one time, there was an effort to name and calibrate various levels of large-scale
integration above VLSI. Terms like ultra-large-scale integration (ULSI) were used. But the huge
number of gates and transistors available on common devices has rendered such fine distinctions
moot. Terms suggesting greater than VLSI levels of integration are no longer in widespread use.
In 2008, billion-transistor processors became commercially available. This became more
commonplace as semiconductor fabrication advanced from the then-current generation of 65 nm
processes. Current designs, unlike the earliest devices, use extensive design automation and
automated logic synthesis to lay out the transistors, enabling higher levels of complexity in the
resulting logic functionality. Certain high-performance logic blocks like the SRAM (static
random-access memory) cell, are still designed by hand to ensure the highest efficiency.
Structured VLSI design is a modular methodology originated by Carver Mead and Lynn Conway
for saving microchip area by minimizing the interconnect fabrics area. This is obtained by
repetitive arrangement of rectangular macro blocks which can be interconnected using wiring by
abutment. An example is partitioning the layout of an adder into a row of equal bit slices cells. In
complex designs this structuring may be achieved by hierarchical nesting.

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1.2 VLSI APPLICATIONS:
VLSI stands for Very Large Scale Integration. It's used in creating so many chips and
circuits on a single mini chip of silicon. Its a kind of technique that is used in designing Micro
chips like IC and many more VLSI means very large scale IC(integrated circuit) chips it is use as
a memory element in computers to store data.........A well-structured and controlled design
methodology, along with a supporting hierarchical design system, has been developed to
optimally support the development effort on several programs requiring gate array and
semicustom VLSI design. The methodology makes extensive use of CAD techniques, including
multilevel simulation for all tasks associated with design simulation and layout. The
methodology is intended to totally verify the system during the design phase, prior to the release
of VLSI components for fabrication; the bulk of the effort spent on integration and test in
MSI/SSI systems can thus be applied during the design phase. This paper describes the design
methodology, the hierarchical CAD system, and the pertinent CAD design philosophy with
reference to the MIL-STD-1750 processor design example.
Applications of VLSI circuits to medical imaging
Advanced very-large-scale integration (VLSI) technology is finding widespread
application in medical imaging, as is exemplified by the use of general-purpose digital signal
processing (DSP) ICs, custom VLSI ICs, and microprocessors in 3D image displays and
ultrasound.. GE's Graphic on display processing system demonstrates the great improvements
that VLSI technology makes in 3D display technology. Graphic on, which contains 26 VLSI
chips of 11 design types including two custom ones, can display 3D images at the rate of 10,000
triangles per second. Ultrasound processing will probably be affected by VLSI technology more
than any other medical imaging process, as VLSI is is utilized to implement fully digital front-
ends to real-time ultrasound phased array signal processor. The advent of silicon compiler CAD
tools will also enable the rapid design of custom VLSI image processing ICs

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 CHAPTER 2
AIM OF PROJECT
In this paper we implement Urdhva Tiryagbhyam algorithm using reversible logic
thereby addressing two important issues – speed and power consumption of implementation of
multipliers. In this work, the design of 4*4 Vedic multiplier is optimized by reducing the
number of logic gates, constant inputs, and garbage outputs. This multiplier can find its
application in various fields like convolution, filter applications, cryptography, and
communication.
2.1 THEORY:
A digital signal processor (DSP) is an integrated circuit designed for high-speed data
manipulations, and is used in audio, communications, image manipulation, and other data
acquisition and data-control applications. The arithmetic operations performed by most of the
DSPs are addition, subtraction which are simple and multiplication, division are complex. The
simple multiplication operation may consume many cycles to complete the operation. This
causes the processor to become quite slow. To overcome this problem UT multiplier is used. The
main constraints of any embedded system are low Power dissipation, high Speed, less Area. The
speed of the processor can be increased by using the Vedic Mathematics. The minimum power
dissipation is one of the main requirements of the system. The power dissipated in the system
can be reduced by introducing Reversible logic. The power dissipation of the reversible logic
under idle conditions is Zero. Multiplier is the most chief element in the computing systems such
as Digital signal processing, microprocessor, FIR filter etc.
So the performance of this application can be improved by optimizing the various
parameter of the multiplier such as power, speed, area and fault tolerance property. Since these
parameter are very much important for Reversible logic circuit or information lossless circuit has
zero internal power dissipation and also there are few families of reversible gate that have
inherent fault tolerant.
This tolerant property in reversible circuit have application in variety of emerging
technology such as quantum computing, nanotechnology etc. According to the Moore’s law , by
the 2020 the basic memory components of a computer will the size of the individual atoms.

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 At such scales current theory of computer will be fail and an quantum computing
reinvented the theory of computer science, Quantum computer can complete task in the
breathtakingly time with no internal power dissipation.
Multiplication process involves generation of partial products, addition of partial products
and finally total product is obtained. So the performance of the multiplier depends on the number
of partial products and the speed of the adder.
Vedic mathematics has 16 formulae for performing arithmetic calculation. An Urdhva
Tiryakbahayam formula is used for he multiplication, application for all types for multiplication.
its literal means “ Vertical and Cross-wise” which enhance the speed of multiplication operation.
This paper deals with the survey and comparison of the various multiplier mainly in terms of the
power, delay, quantum cost. From the survey it is find that the reversible Vedic multiplier based
on the Urdhva Tiryagbhyam aphorisms is offer the best results in terms of delay, area, power and
quantum cost.
In the Array Multiplier, generation of partial products and addition of that will take more
time. Time is an important factor for any computing system. So, in this paper we are proposing
the Vedic Multiplier which gives results quicker than array multiplier and also Vedic Multiplier
using reversible gates is designed with less TRLIC to decrease the power dissipation. In this
paper we are also designing the signed Vedic multiplier for multiplication of signed numbers.
Vedic Multiplier using reversible gates was proposed by different authors [2][3][4] and they
had calculated TRLIC. In this paper we are designing the optimized Vedic multiplier and
comparing with that. In this paper, we are discussing basic reversible gates, algorithm of 2x2
Vedic multiplier and 4x4 Vedic multiplier and how it is optimized by reducing number of gates,
garbage outputs, quantum cost, constant inputs.5
2.2 SOFTWARE TOOLS:
For the logic synthesis- Xilinx 9.2ISE simulation.

Verilog HDL programming language.

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 CHAPTER 3
REVERSIBLE LOGIC GATES
3.1 DEFINITION:
One or more operation can be implement in a single unit called Reversible logic gate. A
reversible logic gate is an n – input and n – output device with one – to- one mapping.
These gates are helps to determine the outputs from the inputs and also inputs can be
uniquely recovered from the outputs.
By using these gates lowering the power dissipation.
3.2 ABOUT REVERSIBLE LOGIC:
Everyday new technology which is faster, smaller and more complex than its predecessor is
being developed. The increase in clock frequency to achieve greater speed and increase in
number of transistors packed onto a chip to achieve complexity of a conventional system results
in increased power consumption. Almost all the millions of gates used to perform logical
operations in a conventional computer are irreversible. Reversible logic is gaining interest in the
recent past due to its less heat dissipating characteristics. It has been proved that any Boolean
function can be implemented using reversible gates. That is, every time a logical operation is
performed some information about the input is erased or lost and is dissipated as heat.
Reversible logic has shown potential to have extensive applications in future emerging
technologies such as quantum computing, optical computing, quantum dot cellular automata as
well as ultra low power VLSI circuits, DNA computing to produce zero power dissipation under
ideal conditions. Reversible logic is very essential for the construction of low power, low
loss computational structures which are very essential for the construction of arithmetic circuits
used in quantum computation, nano technology and other low power digital circuits. Recently,
several researchers have focused their efforts on the design and synthesis of efficient reversible
logic circuits. The important reversible gates used for reversible logic synthesis are Feynman
Gate, New Gate and Fredkin gate.
Reversible implementations are also found in thermodynamics and adiabatic CMOS. Power
dissipation in modern technologies is an important issue, and overheating is a serious concern for
both manufacturer (impossibility of introducing new, smaller scale technologies, limited

6
temperature range for operating the product) and customer (power supply, which is especially
important for mobile systems).
3.3 DESIGN PARAMETERS AND CONSTRAINTS OF REVERSIBLE
GATES:
a) Design parameters of reversible logic circuits:
The design effectiveness of reversible logic circuits is reflected by the factors mentioned below:
 Gate count: Total number of reversible logic gates used to implement the intended
logic circuit
 Constant Inputs: Inputs that are necessary to accomplish a specific function and
remain unaltered all the way through the design.
 Garbage outputs: These are the outputs which are generated due to given inputs but
irrelevant to realize the required logic function. These outputs remain unused in the
design but are vital to preserve the reversibility of the circuit.
 Quantum cost: Quantum cost logic gate is decided by evaluating the number of
primitive gates required to realize that reversible logic gate. Quantum cost of a
reversible circuit is thus the overall quantum cost of all the logic gates used to
construct it.
 Total Reversible Logic Implementation Cost (TRLIC). This refers to the summation
of gate count, constant inputs, garbage outputs and quantum cost of the circuit.
b) Design constraints:
In a reversible logic circuit design two restrictions should be maintain strictly.
 Fan out of each signal including primary inputs will be one i.e. fan out is not allowed
 Feedback loops are also prohibited. Logic synthesis of reversible logic circuits
should have the following objectives to achieve optimized structure:
 Design should use minimum number of logic gates.
 Constant inputs should be minimum.
 Number of garbage output should be minimum.
 Quantum cost should be kept as low as possible.

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3.4 FEYNMAN GATE:
It is 2x2 gate. If the first input i.e. A is given as 1 the second output will be the complement
of the second input i.e. B. so, this gate is also known as Controlled Not Gate. It
can also be used to copy inputs. Quantum cost of this gate is one.

Fig 3.1. Feynman gate

Internal structure of Feynman gate:

Fig 3.2. Internal structure of Feynman gate

The input vector I(A,B) and the output vector is Q(P,Q). The outputs are defined by P=A, Q=A
XOR B. Quantum cost of a Feynman gate is 1. Feynman gate can be used as a copying gate.
Since a fan–out is not allowed in reversible logic, this gate is useful for duplication of required
output.

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Truth table:
Table 3.1. Truth table for Feynman gate

A B P Q
0 0 0 0
0 1 0 1
1 0 1 1
1 1 1 0

3.5 PERES GATE: It is a 3x3 gate. It can be used as a half adder with third input i.e. c as
0.It also serves the purpose of fan out. Quantum cost of this gate is four.

Fig 3.4. Peres gate

Internal structure of Peres gate:

Fig 3.5. Internal structure of Peres gate

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The input vector is I(A,B,C) and the output vector is O(P,Q,R). the output is defined by P=A,
Q=A XOR B, and R=AB XOR C. Quantum of Peres gate is 4. In the proposed design the Peres
gate is used because of its lowest quantum cost.
Truth table for Peres gate:
Table 3.2. Truth table for Peres gate
A B C P Q R
0 0 0 0 0 0
0 0 1 0 0 1
0 1 0 0 1 0
0 1 1 0 1 1
1 0 0 1 1 0
1 0 1 1 1 1
1 1 0 1 0 1
1 1 1 1 0 0

3.6 HNG GATE: It is a 4x4 gate. A single HNG gate can serve as a one bit full adder.
Quantum cost of this gate is six.

Fig 3.8. HNG gate

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3.7 BVPPG GATE: In this 5x5 reversible gate is proposed. It is basically for multiplication
and can generate two partial products at a time. Quantum cost of this gate is ten. The basic
reversible gates are shown in Fig

Fig 3.9. BVPPG gate

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3.8 APPLICATIONS OF REVERSIBLE LOGIC GATES:
 Computer security
 Transaction processing
 Field programmable gate arrays (FPGAs) in CMOS technology
 Computer graphics
 The design of low power arithmetic and data path for digital signal processing (DSP)
 Low power CMOS
 Nanotechnology
 Optical computing
 DNA computing
 Computer graphics
 Communication.

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 CHAPTER 4
VEDIC MATHEMATICS
Vedic mathematics is the name given to the ancient system of Indian mathematics
which was rediscovered from the Vedas between 1911 and 1918 by Sri Bharathi Krishna
Tirthaji. In the Vedic system difficult problems or huge sums can often be solved immediately by
the Vedic method.
Only 16 sutras are used to solve the mathematical problem. Sutras are basically word
formulae that describe normal way of solving mathematical problems. Instead of learning by
repetition, Vedic mathematics involves logic and understanding the fundamental concepts.
4.1 MULTIPLICATION USING URDHVA TIRYAGBHYAM SUTRA:
A Vedic maths offers two sutras – Urdhva Tiryagbhyam sutra and Nikhilam Sutra for
multiplication. Nikhilam sutra is best used for numbers which are nearer to the base of 10,100,
1000 and increased power of 10, whereas Urdhva Tiryagbhyam can be used for any
multiplication. The most powerful Vedic multiplication sutra Urdhva Tiryagbhyam means
“Vertically and Crosswise”. This technique is applicable for any type of number system. General
procedure for Urdhva Tiryagbhyam.
Algorithm:
Let us consider two digit (for binary number system consider 2 bits) multiplicand and
multiplier as “A1 A0” and “B1 B0” respectively and the result as R3R2R1R0.
• Multiplication starts with LSB of the operands i.e. vertical multiplication of A0 and B0 will
generate the LSB of the result i. e. R0. For binary numbers no carry will be generated at this
stage.
R0 = A0 B0.................................. (1)
• R1 is obtained by crosswise multiplication of A0, B1 and A1, B0 and then adding the two
products. In this stage crosswise multiplication and simultaneous addition of the product
generates sum and carry say C1.
C1 R1=A0 B1+A1 B0.................................. (2)
• Again the vertical multiplication between two MSB of the operands i. e. A1 and B1 takes place
and product is added with the generated carry C1 in the previous stage to give the third bit of
result e. R3 as sum and fourth bit R4 as carry.

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 R3 R2 = A1 B1 + C1 ......................(5)
• Final result is obtained by concatenating R3, R2, R1, and R0. This method is applicable for n
Number of bits.
4.2 EXAMPLES:

Verticall and cross wise multiplication

procedure of 4x4 multiplication

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 CHAPTER 5
2x2 VEDIC MULTIPLIER

The 2x2 bit Vedic multiplier is performing very well in terms of delay, power consumption
and output voltage with a full swing when using a 13T hybrid full adder as compared to the other
2 adders. The proposed 2x2 Vedic multiplier is further used to implement a 4x4 and 8x8 bit
multipliers.
The 2x2 Vedic multiplier is implemented using 4 equations mentioned below and the logical
diagram is shown in fig.
q0 = a0.b0 ....................................................(6)
q1= (a1.b0) xor (a0.b1) ................................(7)
q2= (a0.a1.b0.b1) xor (a1.b1) ......................(8)
q3=a0.a1.b0.b1.............................................(9)

Fig 5.1. 2x2 binary Vedic multiplier

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5.1 NON OPTIMIZED 2x2 VEDIC MULTIPLIER:
In this we propose different multiplier architectures based on Urdhva Tiryakbhayam Vedic
mathematics sutra which are designed using different reversible logic gates.
Designed using only Peres reversible logic gates. The design expressions can be logically
modified so as to optimize the design. The new design makes use of only Peres gates which
results in uniqueness for the fabrication of the circuit. The design also takes into account the fan
outs. One of the major design constraints of reversible logic is the fan out , other being loops not
permitted. This design as 10 garbage outputs, 6 gates and the 6 constant inputs.

Fig 5.2. Non optimized 2x2 Vedic multiplier

The reversible implementation the circuit uses five Peres gates and one Feynman gate.
This design has a total quantum cost of 21, number of garbage outputs as 11 and number of
constant inputs 4. The gate count is 6. This design does not take into consideration the fan outs.
The overall performance of the UT multiplier is scaled up by optimizing each individual unit in
terms of quantum cost and garbage outputs etc.

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5.2 OPTIMIZED 2x2 VEDIC MULTIPLIER:

Fig 5.3. Optimized 2x2 Vedic multiplier

17
Optimized 2x2 Vedic Multiplier explanation:

Reversible implementation is done using a BVPPG gate, four Peres gates. BVPPG gate
generates two partial products among which, one is Q0. Q1 is obtained from one of the Peres
gates and Q2, Q3 are the outputs from Feynman gate. This design needs five reversible logic
gates, five constant inputs and generates five garbage outputs. Quantum cost and TRLIC of this
implementation are 23 and 38 respectively. In this implementation fan out of every signal
including primary inputs is one.
The output equations are:

q0 = a0.b0 ....................................................(6)
q1= (a1.b0) xor (a0.b1) ................................(7)
q2= (a0.a1.b0.b1) xor (a1.b1) ......................(8)
q3=a0.a1.b0.b1.............................................(9)

In this design the 2x2 Vedic multiplier model is optimized, so as to reduce the number of
reversible logic gates and the garbage outputs. The design utilizes the BVPPG reversible logic
gate along with the PERES gate to achieve the desired design constraints. The design also takes
into account the fan outs. One of the major design constraints of reversible logic is the fan out,
other being loops not permitted.

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 CHAPTER 6
4x4 VEDIC MULTIPLIER

Block diagram of 4x4 is shown in Fig. In this block four 2x2 multipliers are arranged
systematically. Each multiplier accepts four input bits; two bits from multiplicand and other two
bits from multiplier. Addition of partial products are done using two four bit ripple carry adder
and 5bit RCA
6.1 NON OPTIMIZED 4x4 VEDIC MULTIPLIER:

Fig 6.1. Non optimized 4x4 Vedic multiplier

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 Block diagram of 4x4 is shown in fig. In this block four 2x2 multipliers are arranged
systematically. Each multiplier accepts four input bits; two bits from multiplicand and other two
bits from multiplier. Addition of partial products are done using two four bit ripple carry adder, a
two bit ripple carry adder and a half adder. We obtain the final result by concatenating the last
two bits of the first Block diagram of 4x4 is shown in Fig. In this block four 2x2 multipliers are
arranged multiplier, four sum bits of the second four bit ripple carry adder and the sum bits of
two bit ripple carry adder.
6.2 HALF ADDER:

Fig 6.2. Half adder

The half adder is an example of a simple, functional digital circuit built from two logic gates.
The half adder adds two one-bit binary numbers (AB). The output is the sum of the two bits (S)
and the carry (C).

Note how the same two inputs are directed to two different gates. The inputs to the XOR gate
are also the inputs to the AND gate. The input "wires" to the XOR gate are tied to the input
wires of the AND gate; thus, when voltage is applied to the A input of the XOR gate, the A input
to the AND gate receives the same voltage.
Select an input combination from the pull-down selector and view the resulting output.

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Truth table :
Table 6.1. Truth table for Half adder
A B S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

6.3 FULL ADDER:

Fig 6.4. Full adder

A full adder is a logical circuit that performs an addition operation on three one-bit
binary numbers. The full adder produces a sum of the three inputs and carry value. It can be
combined with other full adders (see below) or work on its own.

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Truth table:
Table 6.2 Truth table for Full adder

A B Cin S C
0 0 0 0 0
0 1 0 0 1
1 0 0 0 1
1 1 0 1 0
0 0 1 0 1
0 1 1 1 0
1 0 1 1 0
1 1 1 1 1

Note that the final OR gate before the carry-out output may be replaced by an XOR gate
without altering the resulting logic. This is because the only difference between OR and XOR
gates occurs when both inputs are 1; for the adder shown here, this is never possible. Using only
two types of gates is convenient if one desires to implement the adder directly using common IC
chips.
A full adder can be constructed from two half adders by connecting A and B to the input of
the other input and OR the two carry outputs. Equivalently, S could be made the three-bit XOR
of A, B, and Cin, and Co could be made the three-bit majority function of A, B, and Cin.

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6.4 RIPPLE CARRY ADDER:
Multiple full adder circuits can be cascaded in parallel to add an N-bit number. For an N- bit
parallel adder, there must be N number of full adder circuits. A ripple carry adder is a logic
circuit in which the carry-out of each full adder is the carry in of the succeeding next most
significant full adder. It is called a ripple carry adder because each carry bit gets rippled into the
next stage. In a ripple carry adder the sum and carry out bits of any half adder stage is not valid
until the carry in of that stage occurs. A propagation delay inside the logic circuitry is the reason
behind this. Propagation delay is time elapsed between the application of an input and
occurrence of the corresponding output. Consider a NOT gate, When the input is “0” the output
will be “1” and vice versa. The time taken for the NOT gate’s output to become “0” after the
application of logic “1” to the NOT gate’s input is the propagation delay here. Similarly the carry
propagation delay is the time elapsed between the application of the carry in signal and the
occurrence of the carry out (Cout) signal. Circuit diagram of a 4-bit ripple carry adder is shown
below.
4 BIT RCA:

Fig 6.6. 4 bit RCA

Ripple carry adder Sum out S0 and carry out Cout of the Full Adder 1 is valid only after the
propagation delay of Full Adder 1. In the same way, Sum out S3 of the Full Adder 4 is valid only
after the joint propagation delays of Full Adder 1 to Full Adder 4. In simple words, the final
result of the ripple carry adder is valid only after the joint propagation delays of all full adder
circuits inside it.

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6.5 OPTIMIZED 4X4 VEDIC MULTIPLIER:

Fig 6.7. Optimized 4x4 Vedic multiplier

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4x4 Vedic multiplier explanation:

For 4x4 multiplication we divide both multiplicand and multiplier into two equal section
and consider each section as two bit operand and then we follow the above algorithm for
multiplication of all four sections. Let the 4 bit multiplicand be“A3A2A1A0” and multiplier be
“B3B2B1B0”. The fore sections will be “A3A2”, “A1A0”, „B3B2”, “B1B0”. So we need four
2x2 multiplier for a 4x4 multiplication. After all the partial products are generated from four 2
bit multiplications we need to add them in a systematic way to get the final result. This adder
section may vary from one design to another. Multiplications between all four sections are
depicted in Fig.
Say products generated from four multipliers are “I0 I1 I2 I3”, “J0 J1 J2 J3”,
“K0K1K2K3”, “L0L1L2L3”. In our work we adopted the addition process [18] to get final 8bit
result R7R6R5R4R3R2R1R0. “R1R0” will be same as “I1 I0”. To get “R5R4R3R2” we need
two 4 bit additions. First we add “J3 J2 J1 J0” and “K3K2K1K0” and we get 4bit sum with fifth
bit as carry. This sum is again added with “L1L0I3I2” which we get by concatenating the first
two left hand side bits of fourth multiplier result and last two right hand side bits of first
multiplier result. The second addition results in a 4bit sum with fifth bit as carry. This 4bit sum is
taken as “R5R4R3R2”. Now the two carry generated from two additions will be added and will
give a sum bit and carry bit as result. These two bits are then added with “L2L3”. This addition
result will be equal to “R7R6”. Concatenation of “R7R6”, “R5R4R3R2”, and “R1R0” will give
the 8bit final product “R7R6R5R4R3R2R1R0”. Carry generated in last addition will not be
considered in design.

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6.6 COMPARISION OF OPTIMIZED AND NON - OPTIMIZED VEDIC
MULTPLIERS:
The comparison of optimized and non optimized Vedic multiplier is shown below in Table. By
considering the parameters of reversible gates like number of gates, constant inputs, garbage
outputs and quantum cost. In total we will add this all parameters to find out the total reversible
logic implementation cost [TRLIC].

Table 6.3. Comparison of 4x4 Vedic multiplier

Multiplier No.of Constant Garbage Quantum TRLIC
gates inputs outputs cost

Non optimized 4x4 Vedic multiplier 37 29 62 162 290

using non optimized 2x2 multiplier

Non optimized 4x4 Vedic multiplier 33 33 43 164 273

using optimized 2x2 multiplier
Optimized 4x4 Vedic multiplier using 37 27 52 148 264
non optimized 2x2 multiplier
Optimized4x4 Vedic multiplier using 31 31 40 156 258
optimized 2x2 multiplier

From the comparison Table we can see that our design requires less number of gates compare to
other multipliers. Garbage outputs and quantum cost is also less. Constant inputs required is
lesser than four other multipliers. Significant reduction in quantum cost and TRLIC is observed.
So, we can say our design is optimized as compare to other designs exist in terms of number of
gates, constant inputs, garbage outputs, quantum cost, and TRLIC.

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 CHAPTER 7
SIGNED VEDIC MULTIPLIER

7.1.ALGORITHM FOR SIGNED MULTIPLIER:

Step1: First we are declaring inputs and outputs.
Step2: Now we are taking MSB bits of both inputs which is a sign bit and now we are calculating
XOR of both the bits which indicates sign of the result.
Step 3: Now the negative numbers which are in 2’s complement form should convert to original
Form for this we are subtracting the number with 4 in the case of 2x2 and 16 in the case of 4x4 if
at all MSB bit of number is 1.
Step 4: After converting the numbers we are going to call Reversible Unsigned Vedic Multiplier
We get the multiplier output.
Step 5 : After getting output from the multiplier we are again converting the number in to 2’s
Complement form if and only if output XOR output of MSB’s of input is 1 otherwise We are
taking the direct output.
Signed Vedic Multiplier is used to add signed numbers. Usually in our system negative
numbers will be represented in 2’s complement form. So when we are declaring inputs they will
be in 2’s complement form. The usage of unsigned Vedic multiplier function is good for normal
binary form. To use that function we have to convert 2’s complement to normal form and we can
call unsigned Vedic multiplier. The conversion can be made by subtracting the number excluding
the sign bit with the corresponding 2n like for 2bit number we have to subtract with 4, for 4bit
we have to subtract with 16.
Now we are taking xor of two MSB bits to get the output sign. For example two MSB bits
are 1 and 0 the output sign consists of 1 which represents that result output is negative number.
After converting the negative number to normal form we are going to call corresponding
unsigned multiplier and the result will be normal form.
Now the output result is converted in to normal form if and only if MSB output is
1otherwiswe the output will be taken same. In this signed Vedic multiplier the most important
step is converting negative numbers in to norm

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 CHAPTER 8
RESULTS AND COMPARISON

The 2x2 multiplier and 4x4 multiplier are designed in VHDL and functional verification done
using MODLSIM simulator. For 4x4 multiplier design VHDL program of 2x2 multiplier is used.
Simulation results are shown in fig. we simulated 2x2 and 4x4 multipliers with various inputs
and correct results are obtained. Simulations are carried out using Xilinx and synthesized for
Spartan3e series target board and results are compared for Vedic multiplier implemented with
normal and reversible gates for the parameters path delay, routing delay and total power. The
proposed multiplier is also compared with array multiplier for different word sizes as 4bit, 8bit,
16 bit and 32bit.

Table 8.1. Comparison of 16x16 normal and reversible Vedic multipliers

Parameter Normal Vedic multiplier Vedic multiplier using
reversible logic gates
Path delay(ns) 60.23 49.101
Logic delay(ns) 32.12 28.426
Routing delay(ns) 28.11 20.625
Dynamic power(mw) 2.35 2
Total power(mw) 52.21 49.21

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8.1 SIMULATION OF 2x2 VEDIC MULTIPLIER:

Fig 8.2. Simulation result of 2x2 Vedic multiplier

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8.2 SIMULATION OF 4x4 VEDIC MULTIPLIER:

Fig 8.3. Simulation result of 4x4 Vedic multiplier

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 We compare our design with some of the Vedic and non Vedic reversible 4x4
multiplier.
From the comparison we can see that our design requires less number of gates compare
to other multipliers. Garbage outputs and quantum cost is also less. Constant inputs required is
lesser than four other multipliers. Significant reduction in quantum cost and TRLIC is observed.
So, we can say our design is optimized as compare to other designs exist in terms of number of
gates, constant inputs, garbage outputs, quantum cost, and TRLIC.

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8.3 COMPARISON OF MULTIPLIER DESIGNS:

Table 8.2. Comparison of multiplier designs

4x4 Performance parameters

multiplier
no.of gates Constant Garbage outputs Quantum cost TRLIC
inputs
Our work 31 31 38 150 250
Design[9] 33 33 43 164 274
Design[10] 37 29 62 162 290
Design[12] 52 52 52 152 308
Design[13] 52 52 52 168 324
Design[14] 44 56 64 236 400

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 CHAPTER 9
APPLICATIONS & ADVANTAGES
Applications:
 multiplier may find applications in fast Fourier Transforms (FFTs)
 To provide universal multiplication with low power high speed.
 Applications in system on chip design as technology scales.
 In public key cryptography like AES encryption and decryption.
 Laptop/Handheld/Wearable Computers.
 Implanted Medical Devices.
 Wallet “smart cards”.
Advantages:
 Increase the speed of the system
 To acquire good efficiency of the system
 Reduce the time delay as well as path delay in the multiplier.
 Vedic multiplier is faster than the array multiplier and booth multiplier.
 The area needed for multiplier is very small as compared to other multiplier architecture.
 MAC is used in modern digital signal processing.
 MAC is always lie in the critical path that determines the speed of the overall hardware
system.

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 CONCLUSION

Vedic mathematics is long been known but has not been implemented in the DSP and
ADSP processors employing large number of multiplications in calculating the various
transforms like FFTs and control applications such as P, PI, PID Controller implementing in
FPGA etc. The proposed Vedic multiplier proves to be highly efficient in terms of speed. Due to
its regular and parallel structure it can be realized easily on silicon as well. The main advantage
is delay increases slowly as input bits increase. Vedic multiplier can be efficiently adopted in
designing Fast Fourier Transforms (FFTs) Filters and other applications of DSP like imaging,
software defined radios, wireless communications.

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 FUTURE SCOPE

Vedic Mathematics, developed about 2500 years ago, gives us a clue of symmetric
computation. Vedic mathematics deals with various topics of mathematics such as basic
arithmetic, geometry, trigonometry, calculus etc. All these methods are very efficient as far as
manual calculations are concerned. If all those methods effectively implement hardware, it will
reduce the computational speed drastically. Therefore, it could be possible to implement a
complete ALU using all these methods using Vedic mathematics methods. Vedic mathematics is
long been known but has not been implemented in the DSP and ADSP processors employing
large number of multiplications in calculating the various 5transforms like FFTs and control
applications such as P, PI, PID Controller implementing in FPGA etc.

35