10th International Conference on DEVELOPMENT AND APPLICATION SYSTEMS, Suceava, Romania, May 27-29, 2010

Finite State Machine Design and

VHDL Coding Techniques
Iuliana CHIUCHISAN, Alin Dan POTORAC, Adrian GRAUR
"Stefan cel Mare" University of Suceava
str.Universitatii nr.13, RO-720229 Suceava
iulia@eed.usv.ro , alinp@eed.usv.ro, Adrian.Graur@usv.ro

Abstract — The first part of paper discusses a variety of system usually involves complex algorithms or tasks, which
issues regarding finite state machine design using the hardware can be expressed as a sequence of actions based on system
description language. VHDL coding styles and different status and external commands. An FSM can function as the
methodologies are presented. Our study of FSM focuses on the
control circuit that coordinates and governs the operations of
modeling issues such as VHDL coding style, state encoding
schemes and Mealy or Moore machines. Our discussion is other units of the system [4].
limited to the synchronous FSM, in which the transition is
controlled by a clock signal and can occur only at the Figure 1 shows the general structure for a finite state
triggering edge of the clock. machine. The current state of the machine is stored in the
The second part contains a worked example of a model that state memory register, a set of k flip-flops clocked by a
detects a unique pattern from a serial input data stream and single clock signal. The current state is the value currently
generates a ‘1’ value to output whenever the sequence ‘10’
occurs. The string detector is modeled at the RTL level in
stored by the state memory register. The next state logic
VHDL and Verilog, for comparison purposes. circuit of the machine is a function of the state vector and
The last part of this paper presents a view on VHDL and the inputs. Mealy outputs are a function of the state vector
Verilog languages by comparing their similarities and and the inputs, while Moore outputs are a function of the
contrasting their difference. state vector only [5].

Index Terms — VHDL code, Verilog code, finite state

current state
machine, Mealy machine, Moore machine, modeling issues,
state encoding.

I. INTRODUCTION next-state state

logic circuit memory
The automata theory is the basis behind the traditional inputs register
model of computation and is used for many purposes other
than controller circuit design, including computer program
compiler construction, proofs of algorithm complexity, and clock
the specification and classification of computer
programming languages [1].
Because automata are mathematical models that produce
values dependent upon internal state and possibly some
Mealy Moore
dependent input values, they are referred to as state output logic output logic
machines [2]. A state machine may allow for a finite or an circuit circuit
infinite set of possible states and further more, they may
have nondeterministic or deterministic behavior. A
deterministic state machine is one whose outputs are the
same for a given internal state and input values. A finite Mealy outputs Moore outputs
state machine (FSM) is one where all possible state values
made a finite set. The synchronous sequential circuits that Figure 1 State Machine Structure
are the focus of this paper are modeled as deterministic
finite state machines and they are modeled as either Mealy A finite state machine is specified by five entities:
or Moore machines. symbolic states, input signals, output signals, next-state
function and output function [4]. A state specifies a unique
II. OVERVIEW OF FINITE STATE MACHINES internal condition of a system and as time progresses, the
FSM transits from one state to another. The new state is
Finite state machines (FSM) constitute a special modeling determined by the next-state function, which is a function of
technique for sequential logic circuits. Such a model can be the current state and input signals.
very helpful in the design of certain types of systems,
particularly those whose tasks form a well-defined sequence The output function specifies the value of the output
[3]. signals. If it is a function of the state only, the output is
The main application of an FSM is to realize operations known as a Moore output and if it is a function of the
that are performed in a sequence of steps [4]. A large digital

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state and input signals, the output is known as a Mealy TABLE 1. STATE ENCODING OF A 8-STATE FSM
ENCODING
output. An FSM is called a Moore machine or Mealy
STATE BINARY ONE-HOT TWO-HOT
machine if it contains only Moore outputs or Mealy STYLE STYLE STYLE
outputs, but a complex FSM has both types of outputs. STATE1 000 00000001 00011
FSMs are commonly modeled in a variety of ways, STATE2 001 00000010 00101
STATE3 010 00000100 01001
including state diagrams, state equations, state tables, and
STATE4 011 00001000 10001
algorithmic state machine (ASM) charts. STATE5 100 00010000 00110
In synthesis of FSM, we start with a functional STATE6 101 00100000 01010
description of the circuit. From this description, we need STATE7 110 01000000 10010
STATE8 111 10000000 01100
precise operation of the circuit using a state diagram. The
FLIP-FLOPS THREE FLIP- EIGHT FLIP- FIVE FLIP-
state diagram allows us to complete the next-state and NUMBER FLOPS FLOPS FLOPS
output tables and then the circuit can be derived from
these tables. The one-hot style is recommended in applications
During the synthesis process, there are many possible where flip-flops are abundant, like in FPGA circuits.
circuit optimizations in terms of the circuit size, speed, CPLD circuits have fewer flip-flops available to the
and power consumption that can be performed [6]. designer.
While one-hot encoding is sometimes preferred
III. ENCODING STYLE because it is easy, a large state machine will require a
The most important decision to make when describing large number of flip-flops. Therefore, when implementing
a finite state machine is what state encoding to use. To finite state machines on CPLD circuits, in order to
encode the states of a state machine, we can select from conserve available resources, it is recommended that
several styles, the default encoding style being binary. binary or gray encoding be used [7]. That enables the
The advantage in using the binary code to encode state largest number of states to be represented by as few flip-
assignment is that requires the least number of flip-flops flops as possible.
(with n flip-flops can be encoded up to 2n states). The
disadvantage is that it requires more logic and is slower IV. HDL LANGUAGES
than the others. Most hardware designers use hardware description
A highly encoded state assignment will use fewer flip- languages (HDLs) to describe designs at various levels of
flops for the state vector; however, additional logic will abstraction. A hardware description language is a high
be required simply to encode and decode the state [5]. level programming language, with programming
A style that uses one flip-flop per state is one-hot constructs such as assignments, conditions, iterations and
encoded style, because only one bit of the state vector is extensions for timing specification, concurrency and data
asserted for any given state and all other state bits are structure proper for modeling different aspects of
zero. In this case, with n flip-flops can be encoded only n hardware. The most popular hardware description
states. languages are VHDL [8] and Verilog [9].
There are more advantages to using the one-hot style to VHDL (VHSIC (Very High Speed Integrated Circuits)
design a state machine: Hardware Description Language) [8] is an IEEE
Standard since 1987 while Verilog was standardized in
 One-hot state machines are faster. Speed 1995.
depends on the number of transitions into a Both languages are programming language that has
particular state. been designed and optimized for describing the behavior
 It is equally “optimal” for all machines. of digital systems. This HDL languages support the
 One-hot state machines are easy to design and development, verification, synthesis, and testing of
HDL code can be written directly from the state hardware designs.
diagram without coding a state table. In this paper we chose the VHDL language. One
 Adding and deleting states, or changing important aspect related to the FSM approach in VHDL
excitation equations, can be implemented easily code is that, though any sequential circuit can in principle
without affecting the rest of the state machine. be modeled as a state machine, this is not always
 Easily synthesized from HDL languages, VHDL advantageous [3]. The reason is that the code might
or Verilog. become longer, more complex, and more error prone than
 It is easy to debug. in a conventional approach [3].

An style that is in between the two styles above is the The FSM approach is adequate in systems whose tasks
two-hot encoding style, which presents two bits active per constitute a well-structured list so all states can be easily
state and therefore, with n flip-flops can be encoded up to enumerated. That is, in a typical state machine
n(n-1)/2 states. implementation, we will encounter, at the beginning of
The encoding styles and the number of flip-flops the ARCHITECTURE, a user-defined enumerated data
required for a finite state machine with eight states is type, containing a list of all possible system states [3].
shown below:

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V. FSM VHDL DESIGN AND MODELING ISSUES In the following table, are presented the corresponding
A Finite State Machines are an important aspect of parts of the VHDL source code for one process and two
hardware design. A well written model will function processes design for the string detector circuit.
correctly and meet requirements in an optimal manner. TABLE 3.VHDL DESIGN FOR STRING DETECTOR CIRCUIT
Finite state machine VHDL design issues to consider ONE VHDL PROCESS TWO VHDL PROCESS
are: FSM_ONE: PROCESS (CLK, RST) --PROCESS TO HOLD SYNCHRONOUS ELEMENTS
BEGIN FSM_SYNCH: PROCESS (CLK, RST)
 VHDL coding style. IF (RST=’1’) THEN BEGIN
 How many processes we use? CURRENT_STATE <= S0; IF (RST=’1’) THEN
 State encoding. ELSIF CURRENT_STATE <= S0;
(CLK’EVENT AND CLK=’1’) ELSIF (CLK’EVENT AND CLK=’1’)
 Mealy or Moore type outputs. THEN THEN
CASE CURRENT_STATE IS CURRENT_STATE <= NEXT_STATE;
A. VHDL coding style WHEN S0 => END IF;
There are many ways of modeling the same state IF (A=’0’) THEN END PROCESS FSM_SYNCH;
F<=’0’;
machine. Our example of FSM focuses on simple tasks, NEXT_STATE <= S0;
--PROCESS TO HOLD COMBINATIONAL LOGIC
such as detecting a unique pattern from a serial input data FSM_COMB: PROCESS (A, CURRENT_
ELSE
STATE) BEGIN
stream and generating a ‘1’ value to output whenever the F<=’0’;
CASE CURRENT_STATE IS
NEXT_STATE <= S1;
sequence ‘10’ occurs. WHEN S0=>
END IF;
The state diagram of our string detector circuit is IF (A=’0’) THEN
WHEN S1 =>
F<=’0’;
shown in figure 2. There are three states, which we called IF (A=’0’) THEN
NEXT_STATE <=S0;
F<=’01’;
s0, s1, and s2. ELSE
NEXT_STATE <= S2;
F<=’0’;
0/0 1/0 ELSE
NEXT_STATE <= S1;
1/0 F<=’0’;
END IF;
s0 s1 NEXT_STATE <= S1;
WHEN S1=>
END IF;
IF (A=’0’) THEN
WHEN S2 =>
1/0 F<=’1’;
IF (A=’0’) THEN
NEXT_STATE <= S2;
F<=’1’;
0/0 0/1 ELSE
NEXT_STATE <= S0;
F<=’0’;
ELSE
NEXT_STATE <= S1;
s2 F<=’0’;
END IF;
NEXT_STATE <= S1;
WHEN S2=>
END IF;
IF (A=’0’) THEN
WHEN OTHERS =>
Figure 2. FSM State diagram F<=’0’;
CURRENT_STATE <= S0;
NEXT_STATE <= S0;
END CASE;
TABLE 2. TABLE WITH CURRENT STATE, NEXT STATE AND ELSE
END IF;
MEALY/MOORE OUTPUT FOR STRING DETECTOR CIRCUIT F<=’0’;
END PROCESS FSM_ONE;
CURRENT MOORE NEXT_STATE <= S1;
NEXT STATE MEALY OUTPUT END IF;
STATE OUTPUT
A=0 A=1 A=0 A=1 WHEN OTHERS =>
CURRENT_STATE <= S0;
S0 S0 S1 0 0 0
END CASE;
S1 S2 S1 1 0 0
END PROCESS FSM_COMB;
S2 S0 S1 0 0 1

Simulation results are shown in figure 3. As can be In one process version, in the CASE statement which
seen, the data sequence A=”010110110” was applied to models the state transitions, the current state of the string
the circuit, resulting the response F= “001001010” at the detector FSM is detected and it is examined whether
output F. input values are present that lead to a change of the state.
HDL code may be divided into three different parts to The same FSM is used to show an implementation
represent current state logic, next state logic and Mealy or based on two VHDL processes. The VHDL source code
Moore output logic. It may also be structured so that the contains two processes, one process defines synchronous
three different parts are combined in the model. In elements of the design (state registers) and the other
VHDL, it is impossible to synthesize a combined current process defines the combinational part of the design (case
state, next state, and output logic in a single always statement). The result is a clocked process describing the
statement. storing elements and another combinational process
A FSM with n state flip-flops may have 2n binary describing the logic. In the CASE statement, the current
numbers that can encode states and often, all states are state is checked and the input values are examined. If the
not needed. Therefore, next-state logic is best modeled state has to change, then NEXT_STATE and
using the case statement even though this means the state CURRENT_STATE will differ and with the next
machine cannot be modeled in one process. The default appearance of the active clock edge, this new state will be
clause used in a case statement avoids having to define taken over as the current state.
the unused states. There are different advantages and disadvantages of
using one process or two processes and these differences
B. How many processes? are presented below.
Generally every finite state machine can be described 1) Structure and legibility
either by one process or by two separated processes. The one process description is more adequate for

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observing changes of the states of the string detector FSM processes because the combinational elements and
from the outside of the VHDL module. The graphical synchronous elements (state registers) are two different
description resembles more a one process than a two structural elements.
process description. 2) Simulation
The VHDL source code should be split into two For two process version, can be determined
exactly the time and location where the error occurs for
D. MOORE MACHINE VERSUS MEALY MACHINE
the first time and therefore the source of the error.
3) Synthesis The two most popular state machines are referred to as
Several synthesis tools tend to produce better results Moore or Mealy machines, named after researchers who
when two processes are used to describe a finite state published early papers on their structure [10, 11]. There
machine. are different reasons for a designer to use one or other
version of the two different type of finite state machine.
C. State encoding in VHDL The primary difference between these two state machines
A finite state machine is an abstract description of is that the output of a Moore machine depends only upon
digital structure and therefore the synthesis tools requires the state of the circuit whereas the output of a Mealy
states of the automaton to be encoded as binary values or machine depends upon both the state and the inputs of the
the synthesis tool itself will transform the state into a circuit. This has a practical effect in that the output
binary description. The way in which states are assigned signals of a Moore machine only change after output
binary values is called state encoding. logic delays following a clock signal edge whereas the
Some different state encoding schemes frequently used output signals of a Mealy machine may change at any
are presented in table 1. time shortly after an input signal changes value [1].
Most synthesis tools selects a binary code by default, In theoretical computer science, a Moore machine and
except the designer specifies another code explicitly. a Mealy machine are considered to have similar
From all possibilities of state encoding is used frequently efficiency because both can recognize “regular
one-hot code, which is needed for speed optimized expressions” [4]. When the FSM is used as a control
circuits. circuit, the control signals generated by a Moore machine
and a Mealy machine have different timing characteristics
TABLE 4. STATE ENCODING
STATE ENCODING
and for the efficiency of a control circuit the timing
TYPE STATE_TYPE IS ( S0, S1, S2) ; difference is critical. We used a simple edge detection
SIGNAL STATE : STATE_TYPE ; circuit to observe the difference between these two state
BINARY CODE ONE-HOT CODE GRAY CODE machines.
S0 → "00" S0 → "001" S0 → "00"
S1→ "01" S1→ "010" S1→ "01"
There are three major differences between the Moore
S2→ "10" S2→ "100" S2→ "11" machine and Mealy machine. First, a Mealy machine
requires fewer states to perform the same task because its
The circuit requires two flip-flops, which encode the output is a function of states and external inputs, and
three states of the string detector state machine. several possible output values can be specified in one
As the automat consists only of three states and two state.
flip-flops can represent up to four states, there is one Second, a Mealy machine can generate a faster
invalid state which leads to an unsafe state machine response. Since a Mealy output is a function of input, it
where the behavior of the design is not determined. changes whenever the input meets the designated
The best method of state encoding is hand coding in condition and a Moore machine reacts indirectly to input
which case the designer decides by himself what code changes.
will be used. The third difference involves the control of the width
and timing of the output signal. In a Mealy machine, the
TABLE 5. HAND CODING
width of an output signal varies with input and can be
SUBTYPE STATE_TYPE IS STD_LOGIC_VECTOR (1 DOWNTO 0) ;
SIGNAL STATE : STATE_TYPE ; very narrow. A Mealy machine is susceptible to
CONSTANT S0: STATE_TYPE := "00"; disturbances in the input signal and passes to the output.
CONSTANT S1: STATE_TYPE := "10";
The output of a Moore machine is synchronized with the
CONSTANT S2: STATE_TYPE := "11";
clock edge and its width is about the same as a clock
period.
The constants are defined to represent the
From this perspective, selection between a Mealy
corresponding states of the state machine and the code
machine and a Moore machine depends on the need of
can be fixed by the designer. The behavior in case of
control signals. If we divide control signals into two
errors can be verified in a simulation and therefore the
categories: edge-sensitive and level-sensitive, then for the
hand coding alternative is the best method to design a
first case, both the Mealy and the Moore machines can
safe finite state machine and is furthermore portable
generate output signals that meet this requirement.
among different synthesis tools.
However, a Mealy machine is preferred since it uses
This type of state encoding has the advantage of using
fewer states and responds one clock faster than does a
a vector type and the only disadvantage is a little more
Moore machine. A level-sensitive control signal means
effort in writing the VHDL code, when the code is
that a signal has to be asserted for a certain amount of
changed.
time. When asserted, it has to be stable and free of spikes.

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A Moore machine is preferred since it can accurately

control the activation time of its output, and can shield VHDL is also a hardware description language that
the control signal from input glitches. describes the behavior of an electronic circuit or system,
from which the physical circuit can then be implemented
TABLE 6. MEALY AND MOORE VHDL DESIGN FOR A STRING DETECTOR [3]. This language is designed to fill a number of needs in
MEALY VHDL DESIGN MOORE VHDL DESIGN
the design process:
ENTITY MEALY IS ENTITY MOORE IS
PORT(A,CLK,RST: IN BIT; PORT(A,CLK,RST: IN BIT;
F: OUT BIT); END MEALY; F: OUT BIT); END MOORE;  It allows description of the structure of a design
ARCHITECTURE FSM OF MEALY IS ARCHITECTURE FSM OF MOORE IS
that is how it is decomposed into sub-designs,
SUBTYPE STATE_TYPE IS STD_ SUBTYPE STATE_TYPE IS STD_
LOGIC_VECTOR (2 DOWNTO 0); LOGIC_VECTOR (2 DOWNTO 0); and how those sub-designs are interconnected;
SIGNAL STATE : STATE_TYPE; SIGNAL STATE : STATE_TYPE;  It allows the specification of the function of
CONSTANT S0: CONSTANT S0:
designs using familiar programming language
STATE_TYPE:="001"; STATE_TYPE:="001";
CONSTANT S1: CONSTANT S1: forms;
STATE_TYPE:="010"; STATE_TYPE:="010";  It allows a design to be simulated before being
CONSTANT S2: CONSTANT S2:
manufactured, so that designers can test for
STATE_TYPE:="100"; STATE_TYPE:="100";
SIGNAL CURRENT_STATE, SIGNAL CURRENT_STATE, correctness and compare alternatives.
NEXT_STATE : STATE_TYPE; NEXT_STATE : STATE_TYPE;
BEGIN BEGIN
Regarding design reusability in Verilog the functions
FF: PROCESS (CLK, RST) BEGIN FF: PROCESS (CLK, RST) BEGIN
IF (RST=’1’) THEN IF (RST=’1’) THEN and procedures must be placed in a separate file and
CURRENT_STATE <= S0 ; CURRENT_STATE <= S0 ; included using include compiler directive to make them
ELSIF (CLK’EVENT AND CLK='1') ELSIF (CLK’EVENT AND CLK=’1’) accessible from different module statements [12]. In the
THEN THEN
CURRENT_STATE<= NEXT_STATE; CURRENT_STATE<= NEXT_STATE;
VHDL case, the procedures and functions may be placed
END IF ; END IF ; in a package so that they are available to any design-unit
END PROCESS; END PROCESS FF ; that wishes to use them.
LOGIC: PROCESS (A, LOGIC: PROCESS (A,
CURRENT_STATE) BEGIN CURRENT_STATE) BEGIN
Compared to VHDL, Verilog data types are very
CASE CURRENT_STATE IS CASE CURRENT_STATE IS simple, easy to use and unlike VHDL, all data types used
WHEN S0 => IF (A=’0’) THEN WHEN S0=> F <= ’0’; in a Verilog model are not defined by the user but by the
F <= ’0’; IF (A=’0’) THEN
NEXT_STATE <= S0; NEXT_STATE <=S 0;
Verilog language. Objects of type reg hold their value
ELSE F <= ’0’; ELSE over simulation cycles and should not be confused with
NEXT_STATE <= S1; NEXT_STATE <= S1; the modeling of a hardware register. Verilog may be
END IF; END IF;
preferred because of simplicity, but VHDL may be
WHEN S1 => IF (A=’0’) THEN WHEN S1=> F <= ’0’;
F <= ’0’; IF (A=’0’) THEN recomended because it allows a multitude of user defined
NEXT_STATE <= S2; NEXT_STATE <= S2; data types to be used.
ELSE F<=’0’; ELSE
There are more VHDL constructs and features for
NEXT_STATE<=S1; NEXT_STATE <= S1;
END IF; END IF; high-level modeling, compared with Verilog, where is no
WHEN S2 => IF (A=’0’) THEN WHEN S2=> F <= ’1’; equivalent to the high-level VHDL modeling statements.
F<=’1’; IF (A=’0’) THEN In VHDL abstract data types can be used along with the
NEXT_STATE<=S0; NEXT_STATE <= S0;
ELSE F<=’0’; ELSE
following statements: package statements for model
NEXT_STATE<=S1; NEXT_STATE <= S1; reuse, configuration statements for configuring design
END IF; END IF; structure, generate statements for replicating structure and
WHEN OTHERS => WHEN OTHERS =>
CURRENT_STATE <= S0; CURRENT_STATE <= S0;
generic statements for generic models [12].
END CASE; END CASE; There is no concept of library in Verilog and this is
END PROCESS; END PROCESS; due to origins as an interpretive language. In VHDL a
END FSM; END FSM ;
library is a store for compiled entities, architectures,
packages and configurations and they are useful for
managing multiple design projects, compared with
Verilog, where are not statements who manage large
VI. VHDL/VERILOG COMPARED & CONTRASTED designs.
A final specification regarding VHDL is that, contrary
Hardware structures can be modeled equally
to regular computer programs which are sequential, its
effectively in both languages, VHDL and Verilog.
statements are concurrent and only statements placed
Choosing which of these hardware description languages
inside a process, function, or procedure are executed
can use them only depends on personal preferences, EDA
sequentially. For that reason, VHDL is referred to as a
tool availability or commercial and marketing issues.
code rather than a program.
Verilog HDL allows a designer to describe designs at a
Model of a string detector circuit was proposed as
high level of abstraction such as at the structural or
problem for describing a finite state machine using
behavioral level as well as the lower implementation
VHDL and in this last part of paper we include a model
levels leading to Very Large Scale Integration Integrated
written in Verilog in addition to VHDL, for comparison
Circuits layouts and chip fabrication. A basic use of HDL
purposes.
languages is the simulation of designs before the designer
must commit to fabrication.

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TABLE 7. MEALY AND MOORE VERILOG DESIGN FOR A STRING S0 : IF (A = = 0) BEGIN S0 :

DETECTOR CIRCUIT F <= 0; BEGIN
MEALY VERILOG DESIGN MOORE VERILOG DESIGN NEXT_STATE <= S0; F <= 0;
MODULE MODULE END IF (A = = 0)
MEALY_STRING_DETECTOR (F, A, MOORE_STRING_DETECTOR (F, A, ELSE BEGIN NEXT_STATE <= S0;
CLK, RST); CLK, RST); F <= 0; ELSE
OUTPUT F; OUTPUT F; NEXT_STATE <= S1; NEXT_STATE <= S1;
INPUT A, CLK, RST; INPUT A, CLK, RST; END END
REG F; REG F; S1 : IF (A = = 0) BEGIN S1 :
REG [2:0] CURRENT_STATE, REG [2:0] CURRENT_STATE, F <= 0; BEGIN
NEXT_STATE; NEXT_STATE; NEXT_STATE <= S2; F <= 0;
PARAMETER PARAMETER END IF (A = = 0)
S0=3’B001, S0=3’B001, ELSE BEGIN NEXT_STATE <= S2;
S1=3’B010, S1=3’B010, F<= 0; ELSE
S2=3’B100; S2=3’B100; NEXT_STATE <= S1; NEXT_STATE <= S1;
END END
ALWAYS ALWAYS S2 : IF (A = = 0) BEGIN S2 :
@ (POSEDGE CLK AND POSEDGE @ (POSEDGE CLK OR POSEDGE RST) F<=1; BEGIN
RST) BEGIN BEGIN NEXT_STATE <= S0; F <= 1;
IF (RST = = 1) IF (RST = = 1) END IF (A = = 0)
CURRENT_STATE <= S0 ; CURRENT_STATE <= S0 ; ELSE BEGIN NEXT_STATE <= S0;
ELSE ELSE F<=0; ELSE
CURRENT_STATE<= NEXT_STATE; CURRENT_STATE<= NEXT_STATE; NEXT_STATE <= S1; NEXT_STATE <= S1;
END END END END
DEFAULT : DEFAULT :
ALWAYS ALWAYS CURRENT_STATE <= S0; CURRENT_STATE <= S0;
@(CURRENT_STATE OR A) @(CURRENT_STATE OR A) ENDCASE ENDCASE
BEGIN BEGIN END END
CASE (CURRENT_STATE) CASE (CURRENT_STATE) ENDMODULE ENDMODULE

Figure 3. Simulation Results for String Detector circuit

VII. CONCLUSIONS REFERENCES

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