Current Mirrors

Coyright Susanta Sengupta @IIT Jammu

 Current mirrors
• We have seen quite a few circuits by now.
We have solved their small signal model VDD
“intuitively”. Circuit #3
• Next, we would like to start implementing
R1
these circuits in the simulator.
• But, there is one key step that still remains to
be reviewed - DC biasing. Vout

• Let’s look at this circuit #3 that we solved

previously. It had an ideal bias current source VDC
M1
(Ibias). In reality, it has to be implemented on gm, rds
the chip somehow - that’s where we need
vin
current mirrors.... like the one shown.
Ibias

W/L Ibias
W/L

Coyright Susanta Sengupta @IIT Jammu

© Susanta Sengupta
 Current Mirrors
VDD
• Input impedance of the current mirror
should be low
Load
• Output impedance of the current mirror
should be high Iin
Output current
Iout
• We ideally want to match “Vgs and Vds” of
the mirroring devices. Most of the time, we
can not match Vds due to the “load” circuit
causing a variable “Vds” of the mirroring
device.
• Voltage headroom (Vds) is one of the key
challenges in current day technologies with
circuits running at low supply voltages.
• What channel lengths to use for the devices?
Short or Long? Remember, channel length
modulation!!
• Cascode current mirrors
• Current mirrors are sometimes used as
current amplifiers

Coyright Susanta Sengupta @IIT Jammu

© Susanta Sengupta
 Sample Current Mirror Circuit #1,2
• Impedances
• input impedance
• output impedance
• Voltage headroom (min needed at input and output).
• Solve for various node voltages please !! 1.2V

1.2V VDD

Load vout
vin
Output current
Iin 0.7V
vin vout Iout M3 M4 0.2V

M1 M2
0.2V 0.7V

M1 M2

Assume
•VT=0.5V
•Vd(sat) = (Vgs - VT) = 0.2V

• Use Long channel devices for

mirroring transistor
• Use short channel devices for
cascode devices
Coyright Susanta Sengupta @IIT Jammu
© Susanta Sengupta
 Sample Current Mirror Circuit #3
• Impedances 1.2V VDD

• input impedance Iin

• output impedance
• Voltage headroom (min needed at input and vin
Load
output).
R

Iout
0.6V vout

M3 M4 0.2V
Assume L L
•VT=0.5V short short
•Vd(sat) = (Vgs - VT) = 0.1V
•Keep in mind the VTs might
be different for long and short
0.2V M1 M2
channel devices
L L
long long

Coyright Susanta Sengupta @IIT Jammu

© Susanta Sengupta
Coyright Susanta Sengupta @IIT Jammu
General Equations
NMOS

!"# = 0 – cut off Region

23 456 7 9?=>
!"# = 8
9:# − 9< 9"# − @
1 + C9=> - Linear Region

23 456 7 @
!"# = 9:# − 9< 1 + C9=> - Saturation Region
@8

PMOS

!#" = I – cut off Region

23 456 7 9J>=
!#" = 9#: − 9< 9#" − K + C9>= - Linear Region
8 J

23 456 7 J
!#" = 9#: − 9< K + C9>= - - Saturation Region
J8

PQ= 23 456 7 7 J!=

:O = = 9L> − 9< 1 + C9=> = J23 456 != = 9
PRL> 8 8 L> M9<N

SQ= 23 456 7 J K K
:"# = = 9L> − 9< C9=> ≅ C9=> => U"# = =
SR=> 8 :"# C!=

Coyright Susanta Sengupta @IIT Jammu

Considering equation of !45

%& '() * +
!"# = -.# − -0 1 + 3-45 - Saturation Region ,
+,

Let ∆- = -E5 − -0 = -45. #GH

⇒ -E5 = ∆- + -0

Effect of channel length on various parameters

2!4
∆- =
*
%& '()
,
%& '() *
.T = -E5 − -0 1 + 3-45
,

VT does not vary with length for very long channel devices

Below a critical length , VT decreases with decrease in length

Coyright Susanta Sengupta @IIT Jammu

 Analysis made for Load RL = ∞
For ac equivalent In=0
=> open circuit
1.2 V VDD
Iout Rout
Reference Output Rin
current current
Load I G2 D2
Iin 0.7 V out
vin vout G1 D1
gmvgs rds
M1 M2 0.2 V
rds rm
S2

S1

Assume VT = 0.5V
Vd(sat) = (Vgs – Vt) = 0.2V
Coyright Susanta Sengupta @IIT Jammu
 %"#
!"# =
""#

iin %"#
= &' ⁄/ &*+
""#
R=∞ !"# %"# &' &*+
= &' ⁄/ &*+ =
""# &' + &*+

%-./
!-./ = 0
"-./ 1234 567 8 9 :; <67 8 9
%-./ = "-./ − =' %=+ &*+

iout %=+ = 0

%-./ = "-./ &*+

To find Rout when iin =0 (input set to zero) , %-./
current through device M1 is zero , so %-./
voltage at G2 = 0 = &*+
"-./
Coyright Susanta Sengupta @IIT Jammu
 Given ∆" = "$% − "' = "(%. *+, = 0.2 V, "' = 0.5V
1.2 V VDD
Node Voltages

Node A: 0V

Load I Node B: "$% = ∆" + "' = 0.7 V

Iin 0.7 V C ∆" + "' out
vin D Node C: 0.7 V
∆" vout
∆" + "'
B Node D: ∆" = "(%. *+, = 0.2V
M1 M2 0.2 V

Minimum Voltages at input and output

A
At input (c) = 0.7V

At output (D) = 0.2V

Coyright Susanta Sengupta @IIT Jammu

 Rout
1.2 V VDD Rin Iout
Reference Output
G3 D3 G4 D4
current current
Iout
Iin Load
./,0 ./,-
vin vout .)0
()- +(,-

M3 M4 0.2 V
G1 D 1 G2 S4 D
2
0.7 V

M1 M2 rds1 rm1 ./,*

()* +(,*

S2
Long channel devices for mirroring S1
transistor , short channel devices for
cascode devices Coyright Susanta Sengupta @IIT Jammu
 Rin Iout Rout
R =∞
G3 D3 G4 D4

./,0 .)0 ./,-

()- +(,-
!"#
= ('()* //',* ) + ('()/ //',/ )
R =∞ ""#
G1 D 1 G2 S 4 D2 ./,0 .)0 ./,3 .)3
= +
./,0 + .)0 ./,0 + .)3

rds1 rm1 ./,*

()* +(,* ~ .)0 + .)3

S2
S1

Coyright Susanta Sengupta @IIT Jammu

 !"#$ = &'() *"#$ − ,-) !,() + &'(/ *"#$ ……. equation1
iout !,(0 = −*"#$ &'(/

!"#$ !"#$ = &'() *"#$ + ,-) *"#$ &'(/ + &'(1 *"#$

!"#$ = *"#$ &'(/ + ,-/ &'(/ &'() *"#$ + *"#$ &'(0 )

!"#$
3"#$ = = &'(/ + &'(0 + ,-1 &'(0 &'(/
*"#$

,-/ &'() &'(/ ≫> &'(0 + &'(/

!"#$
≅ ,-/ &'() &'(/
*"#$

To find Rout when iin =0 (input set to zero) , current through

device M1 is zero , so voltage at G2 , G4 =0 Coyright Susanta Sengupta @IIT Jammu
 1.2 V VDD
Given ∆" = "$% − "' = "(%. *+, = 0.2 V, "' = 0.5V
Reference Output
current current
Iout Node Voltages
Iin Load
F
vin vout Node A: 0 V
G Node B: "$%(./01) = ∆" + "' = 0.7 V
E Node C: 0.7 V
M3 M4 0.2 V Node D: "$%(./01)
Node E: "$%(./01) + "$%(*4/5,)
0.7 V C Node F: : "$%(./01) + "$%(*4/5,)
D
Node G: "$%(./01) + "(%. *+,(*4/5,)
B
M1 M2 Minimum Voltages at input and output

A At input (F) : "$%(./01) + "$%(*4/5,) = ∆" + "' 6789 + ∆" + "' :;7<=

At output (G) : "$%(./01) + "(%. *+,(*4/5,) = ∆" + "' 6789 + ∆" :;7<=

Long channel devices for mirroring transistor , short channel

Coyright Susanta Sengupta @IIT Jammu
devices for cascode devices
 1.2 V VDD
,-.
,/01
Iin R
vin Load
G3 G4 D4
R Iout D3
()& *(#& ()' *(#'
0.6 V vout !"#& !"#'

M3 M4 0.2 V
S4
Lshort Lshort D1S3 G1 G2 D2

()+ *(#+
!"#% !"#$
0.2 V M1 M2
()% *(#%
Llong Llong S1 S2

Coyright Susanta Sengupta @IIT Jammu

 From the equivalent circuit,
!"# = ""# & + !()* + !()+
!"# = ""# & + ()*+, -""# − /0, !/+, 12 + ()*+3 -""# − /03 !/+3 12

Let " = $$% & , ' = ()*+, -$$% − /0, 1/+, 23 , ! = #$%&' ())* − ,-' .,&' /0
!"# $!%
Also = ""# , !()* = !% , !" = !%& −%%& ( , !"#$ = !'( − !*#+
&

Expanding term B

! = #$%&' ())* − ,-' .,&' /0 = !"#$% &''( − *+% (-'( − -#$. )01

= !"#$% &''( − *+% ,-'( − ."#$/ 0''( − *+/ -*$/ 12345

= #$%&' ())* − ,-' ./)* − 0$%&1 ())* − ,-1 (/)* −))* 3))5678

= "#$% &&' − "#$% )*% +&' + "#$% )*% "#$- &&' − "#$% )*% "#$- )*- +&' +"#$% &'% "#$( &'( ))*

= !!" ($%&' + $%&' )*' $%&+ + $%&' )*' $%&+ )*+ - ) - !"# (%&'( )*( + %&'( )*( %&', )*, )

Coyright Susanta Sengupta @IIT Jammu

 Contin….…

Expanding term C

!"#$ %&&' − )*$ +)#$ , = #$%& ((() − +,& (-() −(() .))

= ""# (%&'( + %&'( *+( , ) - ."# (%&'( *+( )

!"# = % + ' + (

!"# = ""# & + ""# ()*+, + )*+, -., )*+/ + )*+, -., )*+/ -./ & ) - !"# (%&'( )*( + %&'( )*( %&', )*, ) + ""# (%&', + %&', )*, / ) - !"# (%&'( )*( )
!"# (& + ()*+ ,-+ + ()*& ,-& + ()*+ ,-+ ()*& ,-& ) = !!" # + %&'( + %&') + %&'( *+( # + %&') *+) %&'( + %&') *+) %&'( *+( #

,!" #.%&'/ . %&'0 . %&'/ *+/ #.%&'0 *+0 %&'/ . %&'0 *+0 %&'/ *+/ #
Rin = =
!!" (. %&'0 *+0 .%&'/ *+/ .%&'0 *+0 %&'/ *+/

Considering only second order terms

!"# &'() *+) &'(, + &'() *+) &'(, *+, . $%& '
= => = + +
""# &'() *+) &'(, *+, %%& ()'

Coyright Susanta Sengupta @IIT Jammu

 !"#$ = −'()* +,#-

!()* = +,#. '()* + "0. '()* +,#- + +,#1 '()*

!()* = '()* +,#- + "0- +,#- +,#. '()* + '()* +,#$ )

!()*
3()* = = +,#- + +,#$ + "01 +,#$ +,#-
'()*

"0- +,#. +,#- ≫> +,#$ + +,#-

!()*
≅ "0- +,#. +,#-
'()*

To find Rout when iin =0 (input set to zero) , current through

device M1 is zero , so voltage at G2 , G4 =0 Coyright Susanta Sengupta @IIT Jammu
 1.2 V VDD
Given ∆" = "$% − "' = "(%. *+, = 0.1 V, "' = 0.5V

Iin
Node Voltages
vin H Load
Node A: 0 V
R Iout Node B: "$%(./01) = ∆" + "' 4567
F vout Node C: 8"(%. *+,(./01) = 2∆" 4567
0.6 V
G Node D: 2"(%. *+,(./01) = 2∆" 4567
E Node E: "(%. *+,(./01) + "$%(*:/;,) = 2∆" 4567 + ∆" + "' <=5>?
M3 M4 0.2 V
Node F: : "$%(./01) = ∆" + "' 4567
Lshort Lshort Node G: 8"(%.*+,(./01) + "(%. *+,(*:/;,)
Node H: "(%. *+,(./01) + "$%(*:/;,) = 2∆" 4567 + ∆" + "' <=5>?
D
C Node (H-F) – voltage drop across resistor = ∆" + "' 4567 + ∆" + "' <=5>?
B
0.2 V M1 M2
Minimum Voltages at input and output
Llong Llong
A At input (H) : 2∆" + ∆" + "'
4567 <=5>?

At output (G) : 8"(%.*+,(./01) + "(%. *+,(*:/;,)

Coyright Susanta Sengupta @IIT Jammu
 1.2 V VDD
Reference Output
current current !"#
Iin !$%&
0.8 V
Load !"# $%!#
vin Iout 0.4 V

VDC2 vout !"#$

!"# $!%#
VDC1 !"#$
M5 M4
0.2V 0.2 V
0.2V 0.8V
Lshort Lshort
!"#$
!"#$
!"# $!%#
0.6V !"# $!%#
M1 M2 0.2 V
Ibias
Llong Llong

Coyright Susanta Sengupta @IIT Jammu

 From the equivalent circuit
!*+ = ()#, **+ − "&, !"#, … … /0+ 1
!"#$ = "&' !#"' ()#' …..(a)

(iz =0) !#"' = !#' − !"' ⇒ !#' = !*+ (. : !"' = 6) ….(b)

iz
Substituting (a) and (b) in eqn. 1 we have
!*+ = ()#, **+ − "&, ("&9 ()#9 !#"9 8 = ()#$ **+ − "&$ ("&' ()#' !*+ )

!*+ 1 + "&, "&9 ()#, ()#9 = ()#, **+

!*+ ()#,
;*+ = =
**+ 1 + "&, "&9 ()#, ()#9

Coyright Susanta Sengupta @IIT Jammu

 !"#$ = −'()* +,#-

!()* = +,#. '()* + "0. '()* +,#- + +,#1 '()*

!()* = '()* +,#- + "0- +,#- +,#. '()* + '()* +,#$ )

!()*
3()* = = +,#- + +,#$ + "01 +,#$ +,#-
'()*

"0- +,#. +,#- ≫> +,#$ + +,#-

!()*
≅ "0- +,#. +,#-
'()*

To find Rout when iin =0 (input set to zero) , current through

device M1 is zero , so voltage at G2 , G4 =0 Coyright Susanta Sengupta @IIT Jammu
 1.2 V VDD
Reference Output Given ∆" = "$% − "' = "(%. *+, = 0.1 V, "' = 0.5V
current current
Iin
D 0.8 V
Load Node Voltages

vin Iout 0.4 V

Node A: 0 V
E
VDC2 vout Node B: "$%(./01) = ∆" + "' 4567
VDC1 Node C: 8"(%. *+,(./01) = 2∆" 4567
M5 M4
0.2V 0.2 V Node D: "$%(./01) +"(%. *+,(*:/;,) = ∆" + "' 4567+ ∆" <=5>?
0.2V 0.8V
Node E: 2"(%. *+,(./01) + "(%. *+,(*:/;,) = 2∆" 4567 + ∆" <=5>?

C Minimum Voltages at input and output

B 0.6V
At input (D) : "$%(./01) +"(%. *+,(*:/;,) = ∆" + "' 4567 + ∆" <=5>?
M1 M2 0.2 V

At output (E) : 8"(%.*+,(./01) + "(%. *+,(*:/;,) = 2∆" 4567 + ∆" <=5>?

Coyright Susanta Sengupta @IIT Jammu

 1.2 V VDD
Rout
G4 D4
()' *(#'
Iin iin
Load D3
!"#'
G3
Iout 0.7 V
()& *(#&
vout !"#& G2 D2 S4
M4 0.2 V
Lshort vin Rin S3 !"#$
M5 0.5 V ()$ *(#$
0.6V Lshort D1G1
vin S2

M1 M2 !)% !"#%
Llong Llong
S1

Coyright Susanta Sengupta @IIT Jammu

 !"# '() '+,)
= ('() // '+,) ) =
""# '() + '+,)

Coyright Susanta Sengupta @IIT Jammu

 !"#$ = &'() *"#$ − ,-) !,() + *"#$ &'(/

!,(0 = !,0 − !(0 , !(0 = 1

!,) = −,-2 !,(2 &'(2 , !,(2 = !,2 − !(2 , !,2 = *"#$ &'(/
!,) = −,-2 *"#$ &'(/ &'(2

!"#$ = &'() *"#$ − ,-) (−,-2 *"#$ &'(/ &'(2 ) + *"#$ &'(/
!"#$ = *"#$ &'() + *"#$ &'(/ + *"#$ ,-2 ,-) &'(/ &'(2 &'()

!"#$
= &'() + &'(/ + ,-2 ,-) &'(/ &'(2 &'()
*"#$

To find Rout when iin =0 (input set to zero) , current through

device M1 is zero , so voltage at G2 =0 Coyright Susanta Sengupta @IIT Jammu
 Given ∆" = "$% − "' = "(%. *+, = 0.1 V, "' = 0.5V

Node Voltages

Node A: 0 V
Node B: "$%(./01) = ∆" + "' 4567
F Node C: "$%(./01) = ∆" + "' 4567
E Node D:
Node E:
Node F :
C
D
Minimum Voltages at input and output

B At input (C) : "$%(./01) = ∆" + "' 4567

At output (G) : 8"(%.*+,(./01) + "(%. *+,(*9/:,)

Coyright Susanta Sengupta @IIT Jammu

Coyright Susanta Sengupta @IIT Jammu
!" #$%# &'()*(+,$(- .(/$,(- -*&&(' &'01 "#( (&&(," 0& 23'3-$"$,- .

53'3-$"$, 6323,$"3+,(- $+#('(+" "0 "#( 2#7-$,38 .(/$,(- -#09 *2 .*( "0 #$%# &'()*(+,7 (&&(,"-

G 6%.
D

6%- '.
%1 /%-

High-frequency model of a BJT High-frequency model of a MOSFET

Coyright Susanta Sengupta @IIT Jammu

 Effect of
blocking Effect of
Effect of
capacitors / inductors High-frequency
Resistive elements
Used for biasing Parasitic elements
Current / Voltage
Gain in dB

LOW-FREQUENCY MID- BAND FREQUENCY GAIN HIGH-FREQUENCY

GAIN GAIN

frequency

Coyright Susanta Sengupta @IIT Jammu

 Millers Approximation

''( ''(
Z1 Z2=Z-Z1
Z

''( ''(
')/+ ≈ 0 ')/+ ≈ 0
∆"
∆" #$ ∆"
X #$ ∆" X BJT/MOS
BJT/MOS Y
Y
%& %&

Coyright Susanta Sengupta @IIT Jammu

 -./0 123 4#.5#1 62/7$ #$
##$ #%/' ≈ 0
∆) ∆, − +, ∆,
X −+, ∆) ##$ =
BJT/MOS 9
##$ Y ∆,
Z1 ##$ =

Z2=Z-Z1
##$ !" 9:

∆, −+, ∆, −+, ∆,
##$ = = =
9: 9 − 9: 9;
∆, − +, ∆, ∆, −+, ∆, −+, ∆,
= = =
9 9: 9 − 9: 9;

=23.3 +, #6 123 60>?? 6#'$>? '>#$ : − +, : −+, −+,

= = =
%31733$ @/#$16 A >$B C >1 0#B − %>$B D.3E53$4#36 9 9: 9 − 9: 9;

(#3. , 723$ 4/0@/$3$16 ?3>B#$' 1/ ?/7 D.3E53$4I

: − +, : 9 9
>$B 2#'2 D.3E53$4I 3DD3416 = => 9: = 9: =
9 9: : − +, : − +,
>.3 $5??#D#3B.)
: − +, −+, 9 9
= => 9; = 9; =
9 9; : :
:−+ :−
Coyright Susanta Sengupta @IIT Jammu , +,
 Effect of parasitic capacitances on the
performance of basic configurations of BJT and
MOSFET

Coyright Susanta Sengupta @IIT Jammu

 Frequency – domain analysis : Simple filters
!" #$% &'(&)'#* '"+,-+'". &/0/&'#,(* /"1 '"1)&#,(* , ./'" ,( -,** '* / 3)"&#'," ,3 3(%4)%"&5
6, )"1%(*#/"1 #$'*, &,"*'1%( / *'70-% %8/70-% ,3 / -,9 0/** ,( $'.$ 0/** 3'-#%(
Low-pass filter High-pass filter
1
:;C =
:A = B; >?@A
+,)# +,)# ’
1
+'" :; =
>?@; +'" ’ :CA = BA

+,)# ′ BA
+,)# 1⁄> ?@; =
= +'" ′ BA + 1⁄> ?@A
+'" B; + 1⁄> ?@;
+,)# ′ *@A BA
=
+,)# H +'" ′ 1 + *@A BA
=
+'" H + *@; BH +,)# ′ ωSA TA
G+ ′ = =
+,)# 1 +'" ′ 1 + ?@A BA A
G+ = = O
+'" 1 + ?@; B; A , ∅ = − KLMN; ?BH @H ∅′ = − KLMN; ?BQ @Q
2
Coyright Susanta Sengupta @IIT Jammu
 Frequency – domain analysis : Simple filters
Low-pass filter : pole-zero pot High-pass filter : pole - zero plot

)*(+,&-+.&$/) )*(+,&-+.&$/)

× "($%&') × "($%&')

0123 9< ;<

= 0123 ′ 6
0+. 1 =
6+ 0+. ′ 1
9< ;< 6+9 ;
: :
1 1
1.% A1'% &3 − ,0 1.% =%$1 &3 0,0 &.@ 1.% A1'% &3 − ,0
9< ;< 9: ;:

Coyright Susanta Sengupta @IIT Jammu

 Low-pass filter High-pass filter
Amplitude
Amplitude -3dB point
20 #$%&' () 20 #$%&' ()
-3dB point

Frequency (f) Frequency (f)

Phase , ∅ Phase , ∅

*° 90°
-45°
-90° 45°
-135°
-180°
Frequency (f) 1 1 Frequency (f)
/01& 2& /013 23
(4 − 378 9:;<4, >DEF78 GH IH &
1 1
(4 − 378 9:;<4,
H
= √3
= &J >DEF78 2H 1H
1 + >?@78 2& 1& 3 √2
1 1
1 ⇒ >′?@78 = , C′?@78 =
C?@78 = 13 23 2013 23
201& 2
Coyright Susanta Sengupta @IIT Jammu
&
 Low-pass filter High-pass filter
& 1 & 1
!"#$, = )*+,- = !"#$ , = )′*+,- =
' /0 10 '′ /< 1<
⇒ ' = /& 1& , ' 3# ′5367 8$9#5:95; ⇒ ' = /= 1= , '′ 3# ′5367 8$9#5:95;
!$ !$ #
H>:9#A7> AC9853$9 39 57>6# $A ' → 1 + #' H>:9#A7> AC9853$9 39 57>6# $A ' → 1 + #'

!"57>9:57 ?:@ 5$ A39, 5367 8$9#5:95 τ $A : 83>8C35 ∶ (FG79 13>8C35 H367 8$9#5:95)

• O$. $A 5367 8$9#5:9#5# 39 : 83>8C35 = O$. $A >7:853L7 7"76795# (8:G:835$> $> Q9,C85$> 39 5K7 83>8C35)

• H$ A39, ' A$> : N3L79 >7:853L7 7"76795 , 9C""3A@ 5K7 7AA785 $A :"" $5K7> >7:853L7 7"76795#
(1:G:835$> − FG79 83>8C35 :9, Q9,C85$># (#K$>5 83>8C35)

• J39, 5K7 HK7L3939; # >7#3#5:987 , "$$M39N 395$ G$395# ?K7>7 >7:853L7 7"76795 3# 8$997857,
H367 8$9#5:95 ' $A : 1:G:835$> 8$997857, R75?779 G$395# : :9, R 39 5K7 83>8C35 3# N3L79 R@

'1:R = /5K :R 1:R

Coyright Susanta Sengupta @IIT Jammu
 /01 *+2 3&134&* 5+06' )2706 ,

#$
(

%&' !"

#$
=> .!$ = #$ !$
(

#*+" = #"

9&*+ *+&5 :'0672;<2, 62 6&77 ('(7=>2 +&<+ ?12@42'3= 125A0'52

0? BCD ('; EFG (HA7&?&215

Coyright Susanta Sengupta @IIT Jammu

 High –frequency model of BJT

#$
B C

&' ()*
!" #" !%

Coyright Susanta Sengupta @IIT Jammu

 Circuit 1

!""

#%
#%
&'()
&'()

#$ #$
&*+ &*+

Coyright Susanta Sengupta @IIT Jammu

 Current Gain
#$
*-. %+ B C *'/0 B #$ C
#" %+ !" () *+,
!' --. !' -'/0
!"
() *+, %& #"

E E

1!') 02, ,3/-*45,.0 6-(/!,, A#$

-'/0 <(@ − )
()
-'/0 = () *+, − *+, :;#$ =
--. @ + A<!) #" + #$
--.
*+, = 1!') 02, ,3/40-'. 4+'*,,
<!) + :; #" + #$
B-C − D4.C E4-. -A < (F2,. A → H)
() 1
--. (() −:;#$ ) I., J,!' 40 4.C '., K'5, 40
-'/0 = ( #$ !" #" + #$
)
+ :; #" + #$
< 1 ()
A#$ ≪
!" #" + #$ #$
-'/0 <(@ − )
()
=
--. @ + A<!) #" + #$ Coyright Susanta Sengupta @IIT Jammu
 Amplitude Response 1
0%!$1 "( 034 -5!% !6 5$
(. *) + *,

!"#$ 6*,
/(1 − 7 6*,
-.
!!% / = 1 ,1 − ≅1
1 + 6/(. *) + *, -.

1 + 6/(. *) + *, ≅ 6/(. *) + *,
1
/ 1
= = ⇒ &#%!$1 =
6/(. *) + *, (. *) + *,
*,
*) + *,
1 06!%- $B@ 5F"G@ 5DD("H!.5$!"%6,
1 -. &
() *) + *, (. *) + *, *, -. !"#$ *,
5$ ?@(", AB@% 6 → , →
*, !!% *) + *,
1 !"#$
5$ D"E@, AB@% 6 → , →/
() *) + *, !!%

Coyright Susanta Sengupta @IIT Jammu

 Phase response

./01
*+(,-
..+
2°
−56°

−72°

−896°

−8:2°

1 ()
#$ %$ + %' %' !

Coyright Susanta Sengupta @IIT Jammu

 Voltage Gain F!') 0;, ,G/-*75,.0 <-!</-0 ,

%+ #$ #?$ = #$ ? − B*
*-. B C *'/0
?
#C$ = #$ ? −
#" B*
!'
!"
() *+, %& D-= − E7.= F!,G/,.<H (7-. +,0>,,. 8'-.04 E 7.< #
;74 75!,7=H +,,. <75</570,= 8!,*-'/45H
7.= -4 (-*,. +H
E
*'/0
= − () !' ⁄/ %&
*-.
34-.( )-55,!6 4 788!'9-)70-'. ,
0;, <-!</-0 <7. +, !,=!7>. 74 +,5'> -K !' ≫ %& ,
*'/0
= − () %&
*-.
*-. %+ B C *'/0
2
#?$ = #$ ? − B* = #$ ? + () %&
() *+,
#" #1$ !' #$
!" %& ? ?
#C$ = #$ ? − = #$ ? +
B* () %&

E () %& ≫ 1 #2$ ≅ #$

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#/0 ($ B C #'12 A-
1
#'12 − !" + @*,
- !" #$% *., ()
*+ *, &' =
#/0 1
&+ () 1 + ($ + @ *- , + *+
&+

E
#'12 − !"
=
3&'" 24% %51/#67%02 8/&81/2, (0%!7%82/0! &' ) #/0 1 1
1 + ($ + @ *- , + *+ + @*,
A> &+ ()
>
#'12 = − !" #$% + @*,
() (%6&&60!/0! 24% 2%&"@ C% 46#%,

&+
A>
#'12 − !" ()
> &+ + ($
#/0 + @ *> , + *+ =
&+ #/0 &+ ($
#$% = 1 + @ *- , + *+ 1 + @*, ()
A> &+ + ($
>
($ + + @ *> , + *+
&+
6$'#% %5162/'0 /@ 'D 24% D'&",
#/0
#$% = #'12 E'
> =
+ @ *> , + *+ ($ + > #/0 1 + @F- 1 + @F.
&+ Coyright Susanta Sengupta @IIT Jammu
 -.
!"#$ − )* +,
-. + +0
=
!%& -. +0
1 + 2 34 5 + 3. 1 + 235 +,
-. + +0

-.
6-"* $7%2 89#:$%"&, <%= − >:&= ?:%&( A%$7 0:28 -82%2$:&B8 +0 %2 − )* +,
-. + +0
E E
CDE = =
FE - +0
3E 5 + 3. - .+ +
. 0
E E
CDG = =
FG 35 +,

Coyright Susanta Sengupta @IIT Jammu

 !"#$%& ': )*+,-+*#./0 12"/ ,.3,-.# 4.5" ,%/6#*/# &.3",#+7 83%5 #$" ,.3,-.#

B C
?#$:
)E< ?#$'
?B )>
?C )F<
3>
05 DB"

9: *66%,.*#"& ;.#$ ): < + )> 9' *66%,.*#"& ;.#$ )<

?#$: = 3> //?B ?#$' = ?C
9: = 3> //?B ): < + )> 9' = ?C )<

Coyright Susanta Sengupta @IIT Jammu

!"#$% "&'(&') *+ ,'( *- , #%,'/"$% "0'1#&2' 2" #3$ ,456&"&$% 1,' 7$ 8%&##$' ,/

920# !9
=
9&' 1 + /*+ 1 + /*-

!9 &/ #3$ 4&( − 7,'( ),&' (@,&' &' #3$ ,7/$'1$ 2" %$,1#&9$ $6$4$'#/)

A%24 #3$ 5%$9&20/ /6&($/ , *B = %C //E7 FB G + FC , *H = EI FG

%C
!9 = − )4 EI
%C + E7

%C
920# − )4 EI
%C + E7
=
9&' 1 + / %C //E7 FB G + FC 1 + /EI FG

Coyright Susanta Sengupta @IIT Jammu

!"#$% &'($ )#*)+#, ,#-().$",/$, -(,ℎ.1 ,. 2#$1

,*/$"2(* 2+$),#.$" .2 *(", .2 ,ℎ( )#*)+#,"

Coyright Susanta Sengupta @IIT Jammu

 Circuit 2
*++

!) #'( !)
#'(

#$%& #$%&

!"
!"

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 +, ($ +*
#-. ($ B C #-. B E #'/0

&* !" #$%

+* &'
&* +, ()
&'
!" #$%

#'/0 C
E ()

Coyright Susanta Sengupta @IIT Jammu

 /*+0*+! "*0 − $2+0 !2*+ $%.3%%+ 4,*+.5 6 2+0 7(+%!9%:.*+! (, , %<:9-0*+! &$ )

>(*.*+! +,029 %?-2.*,+ 2. #,-.

#,-. #,-. − #*+
− !" #$% + =B
&$ () #,-. &' ()
B #*+ E
#$% = #*+ − #,-.
!" #$% #,-. #,-. − #*+
&' − !" #*+ − #,-. + =B
&' ()
!"
C #,-. !" +
C
=
#*+ D !
+ !" + "
&' C
!"
+%!9%:.*+! .%("
C
#,-. !" &'
=
#*+ D + !" &'

Coyright Susanta Sengupta @IIT Jammu

 #-. &$ B () #/01 E
!" &'
*)2 = *) 1 − 6#7 = *) 1 −
1 + !" &'
*, &'
*)+ !" #$%
1
*)2 = *)
1 + !" &'
C

9:;-<=>>: !" &' ≫ +, A/ 6#/ ≅ + (</""/. </>>%<1/( </.D-!0(=1-/.)

F. A0<G = <=A% . %DD%<1 /D *) -A .0>>-D-%I /. 1G% >%D1 A-I% =.I (-!G1 A-I% /D ;/-.1A J =.I K

()
B E
&%A0>1=.1 <-(<0-1 1/ D-.I /;%. <-(<0-1 1-"% </.A1=.1A -A AG/L. .
&' *'
&$ !" #$%
*, I0% 1/ M.-1: !=-. , 1G%(% -A ./ %DD%<1 /D *) =1 1G% /01;01 =>A/.

F.A1%=I >%1 0A </.A-I%( = </0;>-.! <=;=<-1/( *' =1 1G% /01;01 1/ %#=>0=1% NO

C

Coyright Susanta Sengupta @IIT Jammu

 /'0* 12, ,34!+56,71 8!'84!1,
!& +,
'( = !& + .!& ≅ .!&
B E %-
+"#
!"# .!& !& = − + !"#
%- %&
%& )* +&,
$"# +& − +, +"# − +,
= !& => = !&
'( '(
+"# '(
=> +, = −!& '( + +"# = − !"# '( + +"#
%&
−!& '( + +"#
= .!&
%-
−!& '( + +"# +"#
=− + !"#
.%- %&
@# = %12# A(
+"# '(
@# = %& // .%- + '( A( %& − !"# '( + +"# +"#
=− + !"#
.%- %&
.%- '(
+"# #+ + = !"# .%- + '(
%& %&
+"# %& .%- + '(
= = %& // .%- + '(
!"#
Coyright Susanta Sengupta .%- + '( + %&
@IIT Jammu
 () -+,
E
B
&'
&$ *+,
#+,
!" #$% &./, = &' //
-+,
#+,
-$ =
C () + &$
3 + 4 -$ = -+,
#+, () + &$ 4 &$
= ≅ +
() -+, -+, 3+4 !" 3 + 4
E
B
&$ *+, 1 &$
67 = &' ⁄/ + :
!" #$%
!" 3 + 1 '

Coyright Susanta Sengupta @IIT Jammu

 !"" Circuit 3

#$
#$

!%&'(

#( #(

)(

Coyright Susanta Sengupta @IIT Jammu

 +, E
B C #'./
!" #$%
(-
+* &' &* &'
&* () +*
!" #$% #-
C
E (- B +, #'./
#- ()

Coyright Susanta Sengupta @IIT Jammu

 E

.,- %& '()

#$ !"
',-
+,- /.( + .( + ., = ≅ /.( + .,
#$
C −',-
.( =
B !"

#* - / ',- -
',- + = .,- => = //#$
#$ !" .,- %&

6- = #78- 9"
-
6- = //#$ 9"
%&

Coyright Susanta Sengupta @IIT Jammu

 E
E
',-
#012 = #* //
#$ .,-
#$ !"
!/ !/ ',- = .,- − %& '() !/ + #$ //!" .,-
!" %& '() '() = − #$ //!" .,-
%& '()
',-
= !/ - + %& #$ //!" + #$ //!"
C .,- C .,-
B B
≅ !/ - + %& #$ //!"
.,-
#* +,- #012 = #* //!/ - + %& #$ //!"
+,-
1 #(
89 = #* ⁄/ + =
%& < + 1 "

Coyright Susanta Sengupta @IIT Jammu

 MOS device high –frequency model

G !"$
D

!"# %$
"& '"#

IMPORTANT NOTE : Difference between BJT and MOS models is , replace high frequency
parameters in BJT with the following in MOSFET

%( = ∞ , , = ∞ , !( = !"# , !- = !"$ , './ = "& '"#

We can directly obtain the results for MOS circuits by making these substitutions

Coyright Susanta Sengupta @IIT Jammu

 Circuit 1

!""

#%
#%
&'()
&'()
&*+ #$
&*+ #$

Coyright Susanta Sengupta @IIT Jammu

 After Miller’s approximation
%* !"$ )./ %* G D )+,-
)./ D )+,-
G
!"# !0"$ '$
%&
!"# '$
"( )"# %& "( )"# !1"$

S
S

Gain between points G and D

"( )"# .;1
%& 9) = −"( '$ //%& ≅ −"( %&

'$ %-21 = '$ //%& ≅ %&

); !0"$ = !"$ 1 − 9) = !"$ 1 + "( %&
61 = %& !1 "$
%-2J = %*
6J = %* !"# + !J "$

Coyright Susanta Sengupta @IIT Jammu

 Circuit 2

*++

!"
#$% !" #$%
#'()
#'()

!& !&

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 !"( %+, &' !"# S %-./
%+, &' G
G D

!"( *( &)
!"# *(
"$ %"#
"$ %"#
S %-./
&) D

Coyright Susanta Sengupta @IIT Jammu

 After Miller’s approximation
#*/ ', #012
G S
'(
+-!$ %& +.!$
+!&

!" #!$

#)
'238 = %& //'( //
*)
*) #!$ = −#)
!" #!$ '(
*) = −!" #!$ Gain between points G and S is unity
'234 = ',
%& #) 4
#) = 64 = ', +!& + +4 !$
*) !"
4 4
'238 = %& //'( // ≅
!" !"
Coyright Susanta Sengupta @IIT Jammu
 Circuit 3

!""

#$
#$

!%&'(

#(
#(
)(
)(

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 #$% D S
G '*+, $& '$"
!"
$& '$" #$" (%
#$" (% '"
!) G D '*+,

S !) #$%
!"
'"
S S
'. $& '$" $& '$"
!" !" (%
-.
D
G G -.D
!)
'.

Coyright Susanta Sengupta @IIT Jammu

 ()
!"#3 = !4 //
*)
() = *) !& + 51 *) + +, (+&
(+& = −*) !&
() = *) !& + 51 *) − +, *) !&
() = *) !& + 51 $ + +, !& ≈ *) 51 $ + +, !&
()
= 51 $ + +, !&
*)
()
!"#$ = !& // .8 = !4 08 +&
*)
*) = +, (+&
(+& = () $
9:$ =
.$
() $
=> = $
*) +, 9:3 =
.3
.$ = !/ 0+1 + 0$ +& 1 1
9; = =
.= + .8 .*> + .?@"
Coyright Susanta Sengupta @IIT Jammu
Parasitic Capacitances in MOSFETs

Coyright Susanta Sengupta @IIT Jammu

 Parasitic Capacitances and AC Response

GATE (G)
SUB SOURCE (S) DRAIN (D)
metal
metal metal metal
Poly Silicon gate

Cgs_ov Cox SiO2 Cgd_ov

C_channel
p+ n+ n+

Csb Cdb

p-substrate

• Overlap capacitances - Cgs_ov and Cgd_ov

• Diode capacitances of junctions - Csb and Cdb
• Gate oxide capacitance (Cox). Depending on how much channel is formed, C_channel varies and
we will look at various operating conditions.
Coyright Susanta Sengupta @IIT Jammu
© Susanta Sengupta
 Parasitic Capacitance - Weak Inversion (Vgs<VT)

GATE (G)
SUB SOURCE (S) DRAIN (D)
metal
metal metal metal
Poly Silicon gate

Cgs_ov Cox SiO2 Cgd_ov

C_channel
p+ n+ n+

Csb Cdb

p-substrate

• C_channel = dQ/dVgs. In weak inversion, the channel is barely formed as there isn’t enough charge,
and the change in charge with Vgs yield a small value of C_channel.
• Thus, the series combination of gate oxide (Cox) and C_channel ~ C_channel, which is very small.
• Cgs ~ Cgs_ov and Cgd ~ Cgd_ov. Coyright©Susanta Sengupta @IIT Jammu
Susanta Sengupta
 Parasitic Capacitance - Strong Inversion (linear region)

GATE (G)
SUB SOURCE (S) DRAIN (D)
metal
metal metal metal
Poly Silicon gate
Cox/2 Cgd_ov
Cgs_ov Cox/2

C_channel
p+ n+ n+

Csb Cdb

p-substrate

• In strong inversion and linear region (Vds< Vdsat), the channel is uniformly formed from source to
drain.
• C_channel > Cox and the effective series cap ~ Cox.
• Cgs ~ Cgs_ov + Cox/2 and Cgd ~ Cgd_ov + Cox/2.
Coyright Susanta Sengupta @IIT Jammu
© Susanta Sengupta
 Parasitic Capacitance - Strong Inversion (saturation region)

GATE (G)
SUB SOURCE (S) DRAIN (D)
metal
metal metal metal
Poly Silicon gate

Cgs_ov (2Cox)/3 Cgd_ov

p+ n+ n+

Csb Cdb

p-substrate

• In strong inversion and saturation region (Vds>Vdsat), the channel is pinched off near the drain.
• C_channel > Cox and the effective series cap ~ Cox.
• Cgs ~ Cgs_ov + (2Cox)/3 and Cgd ~ Cgd_ov.
Coyright Susanta Sengupta @IIT Jammu
© Susanta Sengupta
 Parasitic Capacitances

Capacitance

Cgs
Cgs_ov + (2Cox)/3

Cgs_ov + Cox/2

Cgd
Cgs_ov, Cgd_ov

OFF or weak Strong inversion & Strong inversion &

inversion saturation linear

Coyright Susanta Sengupta @IIT Jammu

© Susanta Sengupta
 Extracting Parasitic Capacitance Parameters
For every process, we need to extract two key
parasitic capacitance parameters. The same
circuit used previously can be reused.... we
just need to make sure the device is in
saturation. We can derive these two
parameters by printing DC operating points
1.Cgs0/Cgd0
• These represent the amount of
overlap capacitance in the MOS
devices. They are given in “fF/um
width”.
• For example, if we print Cgd and find
it is 3 fF for a 10um wide device, the
value of Cgs0=Cgd0=0.3fF per um
width
2.Gate oxide capacitance density
• It is given as the density of gate
oxide per unit gate area (W.L)
• For example, if we know Cgs ~ 80fF,
Cgd=3fF, we know that the rest 77fF
corresponds to the 2/3(Cox) term.
• Thus, this gate oxide density ~
12fF/sq-um

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© Susanta Sengupta
Revisit Device Capacitances from Simulator

Coyright Susanta Sengupta @IIT Jammu

© Susanta Sengupta
 Parasitic Capacitances & Small-signal model

G Cgd id D
D

Cgs Cds
G vgs Cgb gm.vgs rds vds
B

S Cdb
S

Csb
B

Coyright Susanta Sengupta @IIT Jammu

© Susanta Sengupta
 Example Circuit #2
• Next, let’s find the AC response of the CS
amplifier’s gain as we did previously. VDD

• Continue for all the rest of the circuits.

R1

Vout

vin M1
gm, rds

Coyright Susanta Sengupta @IIT Jammu

© Susanta Sengupta
 Understanding Miller Effect @ Input
• Let’s take the case for Cgd!
• If we applied a test voltage “Vt” at Gate, it VDD

will get gained up at drain by the term “A”.

In this case, A will have a negative sign. R1

Cgd
Vt A.Vt Vt Vout

Ceff
• If we ask ourselves - what will be the total
effective capacitance looking at node Vt to Cgd
ground, we can draw the above model and A.Vt
try to answer this question
M1
• We know Q = C.V. Charge has to be same Vt gm, rds
in both. In the LHS case, total voltage across
the capacitor is (1-A)Vt.
• In the RHS case, the total voltage is just Vt.
The charge, Q, has to be same in both. R
Vt A.Vt
Q=Cgd(1-A).V t Q=Ceff.V t Vt

Ceff=(1-A).Cgd Reff
Reff = R
(1-A)
Coyright Susanta Sengupta @IIT Jammu
© Susanta Sengupta
 Understanding Miller Effect @ Output
•Let’s consider the case where we need to
find the loading at the output node. VDD
Cgd
Vt Vt
Vt
R1
A

Ceff
Q=Cgd.(1-1/A).Vt Q=Ceff.Vt Vout

Ceff=Cgd.(1-1/A)

Cgd
Vt

R Vt
Vt Vt M1
Vt gm, rds
A A
Reff
Reff = A.R
(A-1)

Coyright Susanta Sengupta @IIT Jammu

© Susanta Sengupta
Example Circuit #3
VDD

R1

Vout

VDC
M1
gm, rds

vin

Ibias

Coyright Susanta Sengupta @IIT Jammu

© Susanta Sengupta
Example Circuit #5

VDD

vin M1
gm, rds
Vout

R1

Coyright Susanta Sengupta @IIT Jammu

© Susanta Sengupta
 Diff Amp example
• Shown is a differential amplifier circuit. VDD

R1 R1

• Find its differential gain Vop Von

gm gm vip
vin
• Find its common-mode gain

Ibias

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© Susanta Sengupta
Coyright Susanta Sengupta @IIT Jammu
Coyright Susanta Sengupta @IIT Jammu