Architecture !

Verilog
An Extended Example

always @(posedge clk) begin

Rc
: <2
5:2
A2
1>
SE
L assign pcinc = pc + 4;
1> 1 R

for (i=0; i < 31; i = i+1) begin

on
cti 15:1 0
ILLP JT tru ry Rb
: < F
dOr 0 Ins emo 2 WD WER
XA 1 A M 6 > RA
2 0:1 ter WE
3 00
D : <2 gis 2
L4 Ra L Re ile RD
SE PC SE RA1 F
PC WA A
WWA 1
1
1> RD JT EL
XP5:2 0 BS
+4 + : <2 0
Rc 1 Wr
Z
:0>)
C: 15 R/W
) XT(< 0 WD
1 ry
X T(C S L e mo
4*S E M
AS ta
+4+ Z B Da
PC RD
IRQ AL
U Adr
gic
Lo A
ol
o ntr L
C SE N
PC SEL UF
2 AL
RA EL
AS L
E
BS SEL L
WD FN +4 WDSE
U
AL r PC 2
W RF 01
WE EL
A S
W

,…
t ,irq
e Inpu
es
c lk,r t [31
:0] m
ta( em_
e be data
l ;
du
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If (done) $finish; e
ul
od
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en

6.371 – Fall 2002 09/11/02 L03 – More Verilog 1

 Reprise: Why use an HDL?
• Want an executable functional specification
– Document exact behavior of all the modules and their interfaces
– Executable models can be tested & refined until they do what you want
• Too much detail at the transistor and mask levels
– Can’t debug 1M transistors as individual analog components
– Abstract away “unnecessary” details
– Play by the rules: don’t break abstraction with clever hacks
• HDL description is first step in a mostly automated process to
build an implementation directly from the behavioral model

Verilog Gate
Logic Synthesis Place & route Mask
netlist
• HDL! logic • create floorplan blocks
• map to target library • place cells in block
• optimize speed, area • route interconnect
• optimize (iterate!)

6.371 – Fall 2002 09/11/02 L03 – More Verilog 2

 Beta redux!
ILL I thought I already did
XAdr OP JT
6.004
PCSEL 4 3 2 1 0

PC 00

A Instruction
Memory
D
+4

Ra: <20:16> Rb: <15:11> Rc: <25:21>

0 1 RA2SEL
+ WASEL

XP 1
RA1
Register RA2
WD
Rc: <25:21> 0 WA
WA
File
RD1 RD2 WE WERF
Z
JT
C: SXT(<15:0>)
PC+4+4*SXT(C)
IRQ Z
ASEL 1 0 1 0 BSEL

Control Logic

PCSEL
RA2SEL A B
ASEL ALU WD R/W Wr
ALUFN
BSEL
WDSEL Data Memory
ALUFN Adr RD
Wr
WERF
WASEL
PC+4

0 1 2 WDSEL

6.371 – Fall 2002 09/11/02 L03 – More Verilog 3

 Goals for the Verilog description
• Readable, correct code that clearly captures the architecture diagram –
“correct by inspection”
• Partition the design into regions appropriate for different implementation
strategies. Big issue: wires are “bad” since they take up area and have
capacitance (impacting speed and power).
– Memories: very dense layouts, structured wires pretty much route themselves,
just a few base cells to design & verify
– Datapaths: each cell contains necessary wiring, so replicating cells (for N bits
of datapath) also replicates wiring. Data flows between columnar functional
units on horizontal busses and control flows vertically.
– Random logic: interconnect is “random” but library of cells can be designed
ahead of time and characterized.
– Think about physical partition: wires that cross boundaries can take lots of
area; blocks have to fit into the floorplan without wasteful gaps.

Themes: draw as few fets as possible; maximize use of design techniques that offer
good wire management strategies; use special tools for each type of layout

6.371 – Fall 2002 09/11/02 L03 – More Verilog 4

 Hey! What happened to abstraction?
Wasn’t the plan to abstract- Because life is short! If you have
away the physical details so the luxury of writing two models
we could concentrate on (the first to experiment with
getting the functionality function, the second to describe
right? Why are we worrying the actual partition you want to
about wires and floorplans at have), by all means! But with a
this stage? little experience you can tackle
both problems at once.

6.371 – Fall 2002 09/11/02 L03 – More Verilog 5

 Helping the Tools*
In an ideal world it shouldn’t matter how you write the Verilog – optimization in the
CAD tools will find the best solution. But the world is not ideal (yet…)

• Tools work best on smaller problems

• Need to partition real problem into pieces for you and the tools (it’s hard to
think about 1M gates at one time). Decompose large problems into smaller
problems and then connect the solutions
• Hierarchy in Verilog " partitions in physical layout

• Tools use your code as a starting point.

• Your structure isn’t completed eliminated (this is good…)
• Little optimization will be done between top-level blocks

• Structure of the problem is often important

• Finding a “good” way to think about the problem is key

Like optimizing compilers for C, tools are good for local optimizations but don’t
expect them to rewrite your code and change your algorithm. With practice you’ll
learn what works and what doesn’t…
*adapted from a Stanford EE271 lecture by Mark Horowitz

6.371 – Fall 2002 09/11/02 L03 – More Verilog 6

 Divide and conquer…
ILL
XAdr OP JT

PCSEL 4 3 2 1 0
Step 1: identify memories
1 Step 2: identify datapaths
PC 00

A Instruction
Memory
What’s left is random logic…
D
+4

Ra: <20:16> Rb: <15:11> Rc: <25:21>

0 1 RA2SEL

2 + WASEL

XP 1
RA1
Register RA2
WD
1
Rc: <25:21> 0 WA
WA
PC Z
RD1
File RD2 WE WERF

JT
C: SXT(<15:0>)
PC+4+4*SXT(C)
IRQ Z
ASEL 1 0 1 0 BSEL

Control Logic

PCSEL
RA2SEL A B
ASEL ALU WD R/W Wr
ALUFN
BSEL
WDSEL Data Memory
ALUFN Adr RD
Wr
WERF
WASEL
PC+4 1
0 1 2 WDSEL
2
Main Datapath
6.371 – Fall 2002 09/11/02 L03 – More Verilog 7
 Choosing the right style…
• Structural Verilog
– Use for hierarchy (instantiating other modules)
– Floorplanning tools often require that modules which include structural
verilog not include other styles. In other words the leafs of the
hierarchy are dataflow/behavioral modules, all other modules are pure
structural verilog.
• Dataflow Verilog: assign target = expression
– Use for (most) combinational logic
– Avoids problems with activation list omissions These two styles
are often mixed in
• Behavioral Verilog: always @(…) begin … end a single module
– Use to model state elements (e.g., registers)
– Sometimes useful for combinational logic expressed using for or case
statements
– Simulates much faster than dataflow statements since no waveforms
are produced for signals internal to behavioral block. Here’s where you
can make the tradeoff between simulation speed and debugability.

6.371 – Fall 2002 09/11/02 L03 – More Verilog 8

 Beta Module Hierarchy
• beta
– control [random logic]
– regfile [memory]
– pc [datapath]
– datapath
• dp_misc [datapath]
• dp_alu
– dp_addsub [datapath]
– dp_boole [datapath]
– dp_shift [datapath]
– dp_cmp [datapath]
– dp_mux [datapath]
• dp_wdata [datapath]

Beta
Betaverilog
verilogcan
canbe
befound
foundinin/mit/6.371/examples/beta.vl
/mit/6.371/examples/beta.vlor
orHandouts
Handoutswebpage
webpage
6.371 – Fall 2002 09/11/02 L03 – More Verilog 9
 Register File
// 2-read, 1-write 32-location register file
module regfile(ra1,rd1,ra2,rd2,clk,werf,wa,wd);
input [4:0] ra1; // address for read port 1 (Reg[RA])
output [31:0] rd1; // read data for port 1
input [4:0] ra2; // address for read port 2 (Reg[RB], Reg[RC] for ST)
output [31:0] rd2; // read data for port 2
input clk;
input werf; // write enable, active high
input [4:0] wa; // address for write port (Reg[RC])
input [31:0] wd; // write data

reg [31:0] registers[31:0]; // the register file itself (local)

// read paths are combinational

// logic to ensure R31 reads as zero is in main datapath
assign rd1 = registers[ra1];
assign rd2 = registers[ra2];

// write port is active only when WERF is asserted

always @(posedge clk)
if (werf) registers[wa] <= wd;
endmodule

6.371 – Fall 2002 09/11/02 L03 – More Verilog 10

 = vs. <= inside begin … end
always
always @(posedge
@(posedge clk)
clk) begin
A begin
aa == b;
b; //
// blocking assignment
blocking assignment
module main; bb == a; // execute sequentially
reg a,b,clk; a; // execute sequentially
end
end
always
always @(posedge
@(posedge clk)
clk) begin
B begin
aa <=
<= b; // non-blocking assignment
b; // non-blocking assignment
bb <=
<= a; // eval all RHSs first
a; // eval all RHSs first
end
end

always
always @(posedge
@(posedge clk)
clk) aa == b;
b;
C always @(posedge clk) b = a;
always @(posedge clk) b = a;
initial begin
always
always @(posedge
@(posedge clk)
clk) aa <=
<= b;
b;
clk = 0; a = 0; b = 1; D always @(posedge clk) b <= a;
#10 clk = 1; always @(posedge clk) b <= a;
#10 $display("a=%d b=%d\n",a,b);
$finish; always
E always @(posedge
@(posedge clk)
clk) begin
begin
end aa <= b;
<= b;
endmodule bb == a;
a; //// urk!
urk! Be
Be consistent!
consistent!
end
end

Rule:
Rule:always
alwayschange
changestate
stateusing <=(e.g.,
using<= (e.g.,inside
insidealways
always @(posedge clk)…))
@(posedge clk)…
6.371 – Fall 2002 09/11/02 L03 – More Verilog 11
 module pc(clk,reset,pcsel,offset,jump_addr,

PC
branch_addr,pc,pc_plus_4);
input clk;
input reset; // forces PC to 0x80000000
input [2:0] pcsel; // selects source of next PC
input [15:0] offset; // inst[15:0]
input [31:0] jump_addr; // from Reg[RA], used in JMP instruction
output [31:0] branch_addr; // send to datapath for LDR instruction
output [31:0] pc; // used as address for instruction fetch
output [31:0] pc_plus_4; // saved in regfile during branches, JMP, traps

reg [31:0] pc;

wire [30:0] pcinc;
wire [31:0] npc;

// the Beta PC increments by 4, but won’t change supervisor bit

assign pcinc = pc + 4;
assign pc_plus_4 = {pc[31],pcinc};

// branch address = PC + 4 + 4*sxt(offset)

assign branch_addr = {0,pcinc + {{13{offset[15]}},offset[15:0],2'b00}};

assign npc = reset ? 32'h80000000 :

(pcsel == 0) ? {pc[31],pcinc} : // normal
(pcsel == 1) ? {pc[31],branch_addr[30:0]} : // branch
(pcsel == 2) ? {pc[31] & jump_addr[31],jump_addr[30:0]} : // jump
(pcsel == 3) ? 32'h80000004 : 32'h80000008; // illop, trap

// pc register, pc[31] is supervisor bit and gets special treatment

always @(posedge clk) pc <= npc;
endmodule
6.371 – Fall 2002 09/11/02 L03 – More Verilog 12
 module datapath(inst,rd1,rd2,pc_plus_4,branch_addr,mem_data,
rd1zero,rd2zero,asel,bsel,wdsel,alufn, Main
Datapath
wdata,mem_addr,mem_wdata,z);
input [15:0] inst; // constant field from instruction
input [31:0] rd1; // Reg[RA] from register file
input [31:0] rd2; // Reg[RB] from register file (Reg[RC] for ST)
input [31:0] pc_plus_4; // incremented PC
input [31:0] branch_addr; // PC + 4 + 4*sxt(inst[15:0])
input [31:0] mem_data; // memory read data (for LD)
input rd1zero; // RA == R31, so treat RD1 as 0
input rd2zero; // RB/RC == R31, so treat RD2 as 0
input asel; // select A operand for ALU
input bsel; // select B operand for ALU
input [1:0] wdsel; // select regfile write data
input [5:0] alufn; // operation to be performed by alu
output [31:0] wdata; // regfile write data (output of WDSEL mux)
output [31:0] mem_addr; // alu output, doubles as data memory address
output [31:0] mem_wdata; // data memory write data
output z; // true if Reg[RA] is zero, used during branches

wire [31:0] alu_a,alu_b; // A and B inputs to ALU

// compute A and B inputs into alu, also Z bit for control logic
dp_misc misc(rd1zero,rd2zero,asel,bsel,inst,rd1,rd2,branch_addr,
alu_a,alu_b,mem_wdata,z);
// where all the heavy-lifting happens
dp_alu alu(alufn,alu_a,alu_b,mem_addr);
// select regfile write data from PC+4, alu output, and memory data
dp_wdata wdata(wdsel,mem_data,mem_addr,pc_plus_4,wdata);
endmodule
6.371 – Fall 2002 09/11/02 L03 – More Verilog 13
 module dp_addsub(fn,alu_a,alu_b,result,n,v,z);
input fn; // 0 for add, 1 for subtract
input [31:0] alu_a;
input [31:0] alu_b;
// A operand
// B operand
Adder
output [31:0] result; // result
output n,v,z; // condition codes computed from result

reg n,v,z; What’s

What’swrong
wrongwith:
with:
reg [31:0] result; assign
assign result == fn
result fn ?? aa –– bb :: aa ++ b;
b;

always @(fn or alu_a or alu_b) begin: ripple

integer i; // FOR loop index, not in hardware
reg cin,p,g; // expanded at compile time into many signals
reg [31:0] xb; // hold's complement of ALU_B during subtract

// simple ripple-carry adder for now

xb = fn ? ~alu_b : alu_b; // a - b == a + ~b + 1
cin = fn; // carry-in is 0 for add, 1 for sub
// remember: this FOR is expanded at *compile* time
for (i = 0; i < 32; i = i + 1) begin
p = alu_a[i] ^ xb[i]; // carry propagate
g = alu_a[i] & xb[i]; // carry generate
result[i] = p ^ cin;
cin = g | (p & cin); // carry into next stage
end

n = result[31]; // negative
z = ~|result; // zero
v = (alu_a[31] & xb[31] & !n) | (~alu_a[31] & ~xb[31] & n); // overflow
end
endmodule
6.371 – Fall 2002 09/11/02 L03 – More Verilog 14
 …
reg [17:0] ctl; // local
always @(inst or interrupt) begin // control rom
Instruction
if (interrupt)
ctl = 16'b0100100000000000; // interrupt decode
(fragment)
else case (inst[31:26])
// ppp aaaaaaww
// bcccw lllllldd
// tsssaabuuuuuuss
// eeeesssffffffeex
// sllleeennnnnnllw
// t210lll54321010r
default: ctl = 16'b0011100000000000; // illegal opcode
6'b011000: ctl = 16'b0000001000000100; // LD
6'b011001: ctl = 16'b0000001000000101; // ST
6'b011011: ctl = 16'b0010000000000000; // JMP
…
6'b111101: ctl = 16'b0000001100001010; // SHRC
6'b111110: ctl = 16'b0000001100011010; // SRAC
endcase
end

assign werf = ~ctl[0];

assign mem_we = !reset & ctl[0];
assign wdsel = ctl[2:1];
assign alufn = ctl[8:3];
assign bsel = ctl[9];
assign asel = ctl[10];
assign wa = ctl[11] ? 5'b11110 : inst[25:21];
assign pcsel = ((ctl[14:12] == 3'b001) & (ctl[15] ^ z)) ? 3'b000 : ctl[14:12];
…
6.371 – Fall 2002 09/11/02 L03 – More Verilog 15
 module main;

Test Jig
reg clk,reset,irq;

wire [31:0] inst_addr,inst_data;

wire [31:0] mem_addr,mem_rd_data,mem_wr_data;
wire mem_we;

reg [31:0] memory[1023:0];

beta beta(clk,reset,irq,inst_addr,inst_data,
mem_addr,mem_rd_data,mem_we,mem_wr_data);

// main memory (2 async read ports, 1 sync write port)

assign inst_data = memory[inst_addr[13:2]];
assign mem_rd_data = memory[mem_addr[13:2]];
always @(posedge clk)
if (mem_we) memory[mem_addr[13:2]] <= mem_wr_data;

always #5 clk = ~clk; About 20 megabytes for 300 cycles!

initial begin
@0
@0 //
// starting
starting address
address
$dumpfile("beta_checkoff.vcd");
77df000a
77df000a
$dumpvars;
77ff0003
77ff0003
$readmemh("beta_checkoff",memory);
6ffe0000
6ffe0000
clk = 0; irq = 0; reset = 1;
c3e00000
c3e00000
#10
77fffffe
77fffffe
reset = 0;
d01e0004
d01e0004
#3000 // 300 cycles
77e00002
77e00002
$finish;
……
end
endmodule
6.371 – Fall 2002 09/11/02 L03 – More Verilog 16